Fin type gallium oxide heterogeneous CMOS (Complementary Metal Oxide Semiconductor) platform with low power consumption and strong driving capability

Abstract

The invention discloses a fin-type gallium oxide heterogeneous CMOS (Complementary Metal Oxide Semiconductor) platform with low power consumption and strong driving capability. The fin-type gallium oxide heterogeneous CMOS platform comprises a semi-insulating gallium oxide substrate layer, an unintentional doped gallium oxide buffer layer, a gallium oxide NMOS (N-channel Metal Oxide Semiconductor) device with a fin-type structure and a gallium oxide PMOS (P-channel Metal Oxide Semiconductor) device with a fin-type structure. According to the fin type gallium oxide CMOS platform, the current capacity of a gallium oxide PMOS device can be greatly improved, and due to the low turn-on voltage of a nickel oxide / gallium oxide heterojunction, the gallium oxide PMOS device and a gallium oxide NMOS device have symmetrical transfer characteristics, so that the fin type gallium oxide CMOS platform has high power density and high static noise margin; in addition, compared with a pseudo CMOS, the gallium oxide heterogeneous CMOS platform has lower power loss, the grid control capability of the gallium oxide heterogeneous CMOS platform is improved, the scattering effect is reduced, and the driving capability of the device is greatly improved under the same threshold voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor devices, in particular to a fin-shaped gallium oxide heterojunction CMOS platform with low power consumption and strong driving capability and a preparation method thereof. BACKGROUND

[0002] Compared with traditional narrow-bandgap semiconductor materials silicon (Si), gallium arsenide (GaAs) and wide-bandgap semiconductor materials gallium nitride (GaN) and silicon carbide (SiC), the ultra-wide-bandgap semiconductor gallium oxide (Ga2O3) material has a larger bandgap width E g (4.5-4.9eV), a higher critical breakdown field E m (8MV / cm) and other excellent characteristics. In theory, the power loss of gallium oxide material is about 1 / 3444 of silicon, 1 / 10 of silicon carbide and 1 / 4 of gallium nitride. This means that under the same withstand voltage, the drift region of the gallium oxide device can be made shorter, and the on-resistance can be further reduced. It has great advantages in terms of high power, low power consumption, miniaturization and reliability, and is expected to play a key role in the fields of energy, military and aviation in China.

[0003] Gallium oxide is limited by its special valence band structure (valence band top dominated by O-2p orbit) and deep acceptor level (>1eV), resulting in a large hole effective mass (m h *≈4.3m0), high ionization energy, making it difficult to achieve stable and reliable P-type doping. Even if P-NiO, P-CuO and other materials commonly used at present are used, the hole mobility is still lower than 10cm 2 / (V·s), which significantly restricts the development of enhancement mode devices and complementary metal oxide semiconductor (CMOS) integrated processes.

[0004] Traditional enhancement mode gallium oxide NMOS devices generally use P-type nickel oxide and N-type gallium oxide to form a heterojunction, and the channel carrier concentration is regulated by depletion effect. When the energy band bending at the heterojunction interface forms a depletion region, the channel layer thickness needs to be less than the width of the depletion region, so that the channel electrons can be completely depleted to obtain a positive threshold voltage. However, although a very thin channel layer can ensure a positive threshold voltage, it significantly limits the on-current density and transconductance value of the device. Increasing the channel layer thickness can improve the current driving capability, but it will cause the depletion region to fail to completely cover the channel region, resulting in a negative shift of the threshold voltage, and finally forming a trade-off relationship between threshold voltage stability and on-current performance. SUMMARY

[0005] In view of the above problems in the actual application of ultra-wide-bandgap semiconductor materials, the present application provides a fin-shaped gallium oxide heterojunction CMOS platform with low power consumption and strong driving capability and a preparation method thereof.

[0006] To achieve the above technical purposes, the technical scheme adopted by the present application is:

[0007] In a first aspect, the present application discloses a fin-shaped gallium oxide hetero-CMOS platform with low power consumption and strong driving capability, which comprises a semi-insulating gallium oxide substrate layer (1), a non-intentionally doped gallium oxide buffer layer (2), a gallium oxide NMOS device (3) with a fin-shaped structure, and a gallium oxide PMOS device (4) with a fin-shaped structure.

[0008] The gallium oxide NMOS device (3) comprises a first gallium oxide channel layer (5a) with a fin-shaped structure, a P-type nickel oxide gate cap layer (6a) provided above the first gallium oxide channel layer (5a), a first metal source electrode (7a), and a first metal drain electrode (8), a first gate dielectric layer (9a) provided above the P-type nickel oxide gate cap layer (6a) and the gallium oxide channel layer (5), and a first metal gate electrode (10) provided above the first gate dielectric layer (9a).

[0009] The gallium oxide PMOS device (4) comprises a second gallium oxide channel layer (5b) with a fin-shaped structure, a P-type nickel oxide channel layer (6b) provided above the second gallium oxide channel layer (5b), a metal collector electrode (11), a second metal source electrode (7b) provided above the P-type nickel oxide channel layer (6b), an N-type gallium oxide dielectric layer (12), a second metal drain electrode (13) provided above the N-type gallium oxide dielectric layer (12), a second gate dielectric layer (9b) provided above the second metal drain electrode (13), the second metal source electrode (7b), the metal collector electrode (11), the P-type nickel oxide channel layer (6b), and a second metal gate electrode (14) provided above the second gate dielectric layer (9b).

[0010] The second metal collector electrode (11) and the first metal drain electrode (8) are electrically interconnected by a first metal layer (15), and the second metal gate electrode (14) and the first metal gate electrode (10) are electrically interconnected by a second metal layer (16), forming a CMOS structure.

[0011] Further, the first gallium oxide channel layer (5a) and the second gallium oxide channel layer (5b) are both in a fin-shaped structure, with a width ranging from 0.01 um to 1.5 um and a thickness ranging from 100 nm to 2 um.

[0012] Further, the gallium oxide PMOS device (4) is provided with an N-type gallium oxide dielectric layer (12) doped with Si on the P-type nickel oxide channel layer (6b) on the drain side by magnetron sputtering, with a donor concentration ranging from 10 17 cm -3 -10 19 cm -3 , with a thickness ranging from 70nm to 90nm; the N-type gallium oxide dielectric layer (12), the P-type nickel oxide channel layer (6b) and the second gallium oxide channel layer (5b) constitute an NPN bipolar stacked triode structure.

[0013] Furthermore, the second metal gate electrode (14) and the first metal gate electrode (10) are one or more combinations of Pd, Ni, Pt, Au, and W metal materials, and have the same work function.

[0014] Furthermore, the first metal source electrode (7a) and the first metal drain electrode (8), the second metal drain electrode (13) and the metal collector (11) are one or more combinations of Ti, In, and Au metal materials, and have the same work function.

[0015] Furthermore, the first gallium oxide channel layer (5a) and the second gallium oxide channel layer (5b) are both N-type doped, with a concentration range of 10 17 cm -3 -10 18 cm -3 The P-type nickel oxide channel layer (6b) is P-type doped with a concentration range of 10 16 cm 3 -10 19 cm 3 .

[0016] Furthermore, the first gallium oxide channel layer (5a) forms an ohmic contact with the first metal source electrode (7a) and the first metal drain electrode (8) above it; the second gallium oxide channel layer (5b) forms an ohmic contact with the metal collector electrode (11) above it; the nickel oxide channel layer (12) forms an ohmic contact with the second metal source electrode (7b) above it; and the first gate dielectric layer (9a) forms a Schottky contact with the first metal gate electrode (10) above it, the second gate dielectric layer (9b) and the second metal gate electrode (14) above it.

[0017] Furthermore, the first gate dielectric layer (9a) and the second gate dielectric layer (9b) are one or more combinations of SiO2, Al2O3, Si3N4 dielectric materials, and have a thickness ranging from 100nm to 1000nm.

[0018] In a second aspect, the present invention discloses a method for preparing a fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability as described above, the method comprising the following steps:

[0019] epitaxially growing a semi-insulating gallium oxide substrate layer (1), an unintentionally doped gallium oxide buffer layer (2), and a gallium oxide channel layer in sequence;

[0020] An inductively coupled plasma etching method is used for mesa isolation, and a Ni / SiO2 mask mode and SF6-ArICP-RIE technology are used to etch the gallium oxide channel layer to form a fin-shaped channel with uniform height, extending from the source end to the drain end, thereby generating a first gallium oxide channel layer (5a) with a fin structure and a second gallium oxide channel layer (5b) with a fin structure, which correspond to a gallium oxide NMOS device and a gallium oxide PMOS device, respectively;

[0021] Wet acid treatment with room temperature diluted HCl and HF is used to restore surface damage caused by etching;

[0022] Magnetron sputtering a P-type nickel oxide medium, and performing debonding and stripping to form a P-type nickel oxide gate cap layer (6a) and a P-type nickel oxide channel layer (6b);

[0023] Magnetron sputtering an N-type gallium oxide dielectric layer (12) at the drain end of the gallium oxide PMOS device;

[0024] Heavy doping is performed on four electrode regions, namely, a first metal source electrode (7a) of the gallium oxide NMOS device, a first metal drain electrode (8) of the gallium oxide NMOS device, a second metal drain electrode (13) of the gallium oxide PMOS device, and a collector (11) of the gallium oxide PMOS device, forming metal electrodes by electron beam evaporation, and thermal annealing is performed in an N2 atmosphere;

[0025] Heavy doping is performed in the second metal source electrode (7b) region of the gallium oxide PMOS device, forming a metal electrode by electron beam evaporation, and thermal annealing is performed in an N2 atmosphere;

[0026] Depositing a first gate dielectric layer (9a) and a second gate dielectric layer (9b) using ALD technology;

[0027] Electron beam evaporation forms a first metal gate electrode (10) of a gallium oxide NMOS device and a second metal gate electrode (14) of a gallium oxide PMOS device;

[0028] The surface is passivated, and a first metal gate electrode (10) of a gallium oxide NMOS device and a second metal gate electrode (14) of a gallium oxide PMOS device, and a first metal drain electrode (8) of the gallium oxide NMOS and a collector (11) of the gallium oxide PMOS device are metal interconnected through open hole contacts.

[0029] Compared with the prior art, the fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability and the preparation method thereof of the present invention have the following advantages:

[0030] First, better gate control capability. The channel layers of the gallium oxide NMOS and gallium oxide PMOS in the fin-type gallium oxide heterogeneous CMOS platform of the present invention are both fin-shaped structures. Combined with the P-type nickel oxide gate cap layer, it is easier to deplete the electrons in the gallium oxide channel layer in the fin column, thereby achieving better gate control capability and enhancement mode devices.

[0031] Second, strong driving capability. The gallium oxide channel layer of the fin-type gallium oxide heterogeneous CMOS platform of the present invention is a fin-shaped structure. Increasing the thickness of the fin column increases the current density. At the same time, controlling the width of the fin column can better adjust the threshold voltage of the gallium oxide NMOS device. The gallium oxide PMOS forms an NPN bipolar stacked triode structure at the drain end to expand the hole current density in the gallium oxide PMOS and amplify the hole current as the base current of the NPN triode. Under the premise of the same threshold voltage, the driving capability of the fin-type structure gallium oxide PMOS device of this patent is greatly improved.

[0032] Third, high reliability: The fin-type gallium oxide heterogeneous CMOS platform of the present invention is composed of gallium oxide ultra-wide bandgap semiconductor materials, which are resistant to high temperatures and radiation, thus achieving high reliability of the entire system.

[0033] Fourth, low turn-on voltage and high noise margin. The present invention's fin-type gallium oxide heterogeneous CMOS platform, thanks to its gallium oxide and nickel oxide heterostructure, achieves a low turn-on voltage of 1-2V. Furthermore, the gallium oxide NMOS and PMOS devices within the gallium oxide CMOS platform have symmetrical threshold voltages and current drive capabilities. This improves static noise margin compared to traditional CMOS structures.

[0034] Fifth, low power loss. The fin-type gallium oxide heterogeneous CMOS platform of the present invention is a traditional CMOS structure, consisting of enhanced NMOS and enhanced PMOS. For semiconductor materials without P-type doping, most of them are composed of enhanced NMOS and depletion NMOS to form a pseudo-CMOS structure. Because of the normally-on NMOS, when the enhanced NMOS is turned on, current will flow through the load, causing power loss. The CMOS platform of the present invention is a traditional CMOS structure with low power loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of the fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability of the present invention;

[0036] Figure 2 Schematic diagram of the cross section of the drain end of gallium oxide NMOS;

[0037] Figure 3 Schematic diagram of the process preparation;

[0038] Figure 4 Prepare flow charts for the processes;

[0039] Figure 5 is a transfer characteristic curve of an enhanced-mode gallium oxide NMOS fin device;

[0040] Figure 6 This is a comparison chart of the output characteristic curves of the enhanced PMOS gallium oxide fin structure power device and the traditional enhanced PMOS gallium oxide power device. DETAILED DESCRIPTION

[0041] The embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

[0042] See also Figure 1 and Figure 2 The present invention discloses a fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability, which includes a semi-insulating gallium oxide substrate layer 1, an unintentionally doped gallium oxide buffer layer 2, a gallium oxide NMOS device 3 with a fin structure, and a gallium oxide PMOS device 4 with a fin structure.

[0043] The gallium oxide NMOS device 3 includes: a first gallium oxide channel layer 5a with a fin structure, a P-type nickel oxide gate cap layer 6a, a first metal source electrode 7a, and a first metal drain electrode 8 are provided above the first gallium oxide channel layer 5a, a first gate dielectric layer 9a is provided above the P-type nickel oxide gate cap layer 6a and the gallium oxide channel layer 5, and a first metal gate electrode 10 is provided above the first gate dielectric layer 9a.

[0044] The gallium oxide PMOS device 4 includes: a second gallium oxide channel layer 5b with a fin structure; a P-type nickel oxide channel layer 6b and a metal collector electrode 11 are provided above the second gallium oxide channel layer 5b; a second metal source electrode 7b and an N-type gallium oxide dielectric layer 12 are provided above the P-type nickel oxide channel layer 6b; a second metal drain electrode 13 is provided above the N-type gallium oxide dielectric layer 12; a second gate dielectric layer 9b is provided above the second metal drain electrode 13, the second metal source electrode 7b, the metal collector 11, and the P-type nickel oxide channel layer 6b; and a second metal gate electrode 14 is provided above the second gate dielectric layer 9b.

[0045] The second metal collector electrode 11 and the first metal drain electrode 8 are electrically interconnected by the first metal layer 15 , and the second metal gate electrode 14 and the first metal gate electrode 10 are electrically interconnected by the second metal layer 16 , forming a CMOS structure.

[0046] In this embodiment, the gallium oxide channel layers (including the first gallium oxide channel layer 5a and the second gallium oxide channel layer 5b) are both fin-shaped structures with a width ranging from 0.01 μm to 1.5 μm. By reducing the width of the gallium oxide channel layer and the nickel oxide gate cap layer, a normally-off device and stronger gate control capability are achieved. The narrow channel layer can reduce trap scattering, improving mobility and current capability. The gallium oxide channel layer has a thickness ranging from 100 nm to 2 μm. Increasing its thickness can increase carrier density and current capability. The gallium oxide channel layer has a narrow and tall fin-shaped channel layer, thereby achieving higher current capability under the same threshold voltage conditions.

[0047] The gallium oxide PMOS device 4 is a P-type nickel oxide channel layer 6b on the drain side of which an N-type gallium oxide dielectric layer 12 doped with Si is magnetron sputtered. The donor concentration range is 10 17 cm -3 -10 19 cm -3 , with a thickness ranging from 70nm to 90nm. The N-type gallium oxide dielectric layer 12, the P-type nickel oxide channel layer 6b, and the second gallium oxide channel layer 5b form an NPN bipolar stacked triode structure, which improves the current density of the gallium oxide PMOS. That is, at the same threshold voltage, the fin-structured gallium oxide PMOS device has a higher current density than the traditional structure gallium oxide PMOS device.

[0048] The first gallium oxide channel layer 5a forms an ohmic contact with the first metal source electrode 7a and the first metal drain electrode 8 above it; the second gallium oxide channel layer 5b forms an ohmic contact with the metal collector electrode 11 above it; the nickel oxide channel layer 12 forms an ohmic contact with the second metal source electrode 7b above it; and the first gate dielectric layer 9a forms a Schottky contact with the first metal gate electrode 10 and the second gate dielectric layer 9b and the second metal gate electrode 14 above it.

[0049] In terms of material selection, the second metal gate electrode 14 and the first metal gate electrode 10 are one or more combinations of Pd, Ni, Pt, Au, and W metal materials, and have the same work function. The first metal source electrode 7a and the first metal drain electrode 8, the second metal drain electrode 13 and the metal collector 11 are one or more combinations of Ti, In, and Au metal materials, and have the same work function. The first gallium oxide channel layer 5a and the second gallium oxide channel layer 5b are both N-type doped with a concentration range of 10 17 cm -3 -10 18 cm -3 ; P-type nickel oxide channel layer 6b is P-type doped, with a concentration range of 10 16 cm 3 -10 19 cm 3Furthermore, the first gate dielectric layer 9a and the second gate dielectric layer 9b are made of one or more combinations of SiO2, Al2O3, and Si3N4 dielectric materials, and have a thickness ranging from 100 nm to 1000 nm.

[0050] like Figure 3 and Figure 4 As shown, the present invention discloses a method for preparing a fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability as described above, the preparation method comprising the following steps:

[0051] epitaxially growing a semi-insulating gallium oxide substrate layer 1, an unintentionally doped gallium oxide buffer layer 2, and a gallium oxide channel layer in sequence;

[0052] Mesa isolation is performed using inductively coupled plasma etching, and the gallium oxide channel layer is etched using a Ni / SiO2 mask pattern and SF6-ArICP-RIE technology to form a fin-shaped channel with uniform height, extending from the source end to the drain end. This generates a first gallium oxide channel layer 5a with a fin structure and a second gallium oxide channel layer 5b with a fin structure, corresponding to the gallium oxide NMOS device and the gallium oxide PMOS device, respectively.

[0053] Wet acid treatment with room temperature diluted HCl and HF is used to restore surface damage caused by etching;

[0054] Magnetron sputtering of P-type nickel oxide dielectric, followed by stripping and peeling to form a P-type nickel oxide gate cap layer 6a and a P-type nickel oxide channel layer 6b;

[0055] Magnetron sputtering an N-type gallium oxide dielectric layer 12 at the drain end of the gallium oxide PMOS device;

[0056] Heavy doping is performed on the four electrode regions of the first metal source electrode 7a of the gallium oxide NMOS device, the first metal drain electrode 8 of the gallium oxide NMOS device, the second metal drain electrode 13 of the gallium oxide PMOS device, and the collector 11 of the gallium oxide PMOS device, and metal electrodes are formed by electron beam evaporation, followed by thermal annealing in an N2 atmosphere;

[0057] The second metal source electrode 7b region of the gallium oxide PMOS device is heavily doped, a metal electrode is formed by electron beam evaporation, and thermal annealing is performed in an N2 atmosphere;

[0058] Depositing a first gate dielectric layer 9a and a second gate dielectric layer 9b using ALD technology;

[0059] Electron beam evaporation is used to form a first metal gate electrode 10 of the gallium oxide NMOS device and a second metal gate electrode 14 of the gallium oxide PMOS device;

[0060] The surface is passivated, and the first metal gate electrode 10 of the gallium oxide NMOS device and the second metal gate electrode 14 of the gallium oxide PMOS device, and the first metal drain electrode 8 of the gallium oxide NMOS and the collector 11 of the gallium oxide PMOS device are metal interconnected through open contacts.

[0061] like Figure 5 As shown, Figure 5 The figure shows the transfer characteristic curve of the fin-shaped GaO NMOS device. The thickness of the fin column of the GaO NMOS device represented by the dotted line is the same as the width of the fin column of the GaO NMOS device represented by the solid line, that is, the threshold voltage of the two devices is the same. The thickness of the fin column of the GaO NMOS device represented by the solid line is 0.18 μm thicker than that of the GaO NMOS device represented by the dotted line. GS When the drain voltage is 1V and the current capability is increased by 51.3%, that is, when the thickness of the fin column is increased (W H ), the current in the GaO NMOS device will increase significantly. Changing the thickness of the fin column can change the current capability of the GaO MOS device, and changing the width of the fin column can change the threshold voltage of the GaO MOS device.

[0062] like Figure 6 As shown, Figure 6 The figure below is a comparison of the output characteristic curves of the enhanced PMOS gallium oxide fin structure power device and the traditional enhanced PMOS gallium oxide power device. The solid line represents the output characteristic curve of the traditional enhanced gallium oxide PMOS device, and the dotted line represents the output characteristic curve of the enhanced gallium oxide PMOS fin structure of this patent. Figure 6 As shown, the enhanced gallium oxide PMOS device with fin structure uses the hole current as the base current of the NPN transistor to turn on the transistor. The final PMOS current is the electron current flowing out of the drain as the emitter. GS When the voltage is -10V and the drain voltage is 1V, the current capability of the fin-structured gallium oxide PMOS device is increased by 2010% compared with the traditional enhancement-mode gallium oxide PMOS device.

[0063] The gallium oxide PMOS device of the present invention benefits from an NPN structure consisting of a gallium oxide channel layer with a fin structure, a P-type nickel oxide channel layer, and an N-type gallium oxide dielectric layer, which greatly increases the current capability of the gallium oxide PMOS device. In addition, thanks to the low turn-on voltage of the nickel oxide / gallium oxide heterojunction, the gallium oxide PMOS device and the gallium oxide NMOS device have symmetrical transfer characteristics, thereby enabling the fin-type gallium oxide CMOS platform to have high power density and high static noise margin. The gallium oxide heterogeneous CMOS platform benefits from the traditional CMOS structure and has a gallium oxide channel layer with a fin structure. Compared with pseudo-CMOS, the gallium oxide heterogeneous CMOS platform has lower power loss, improved its gate control capability, and reduced scattering effects, thereby significantly increasing the device's driving capability at the same threshold voltage.

[0064] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0065] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability, characterized in that: The platform comprises a semi-insulating gallium oxide substrate layer (1), an unintentionally doped gallium oxide buffer layer (2), a gallium oxide NMOS device with a fin structure (3), and a gallium oxide PMOS device with a fin structure (4); The gallium oxide NMOS device (3) comprises: a first gallium oxide channel layer (5a) with a fin structure; a P-type nickel oxide gate cap layer (6a), a first metal source electrode (7a), and a first metal drain electrode (8) are provided above the first gallium oxide channel layer (5a); a first gate dielectric layer (9a) is provided above the P-type nickel oxide gate cap layer (6a) and the gallium oxide channel layer (5a); and a first metal gate electrode (10) is provided above the first gate dielectric layer (9a); The gallium oxide PMOS device (4) comprises: a second gallium oxide channel layer (5b) with a fin structure; a P-type nickel oxide channel layer (6b) and a metal collector electrode (11) are provided above the second gallium oxide channel layer (5b); a second metal source electrode (7b) and an N-type gallium oxide dielectric layer (12) are provided above the P-type nickel oxide channel layer (6b); a second metal drain electrode (13) is provided above the N-type gallium oxide dielectric layer (12); a second gate dielectric layer (9b) is provided above the second metal drain electrode (13), the second metal source electrode (7b), the metal collector electrode (11), and the P-type nickel oxide channel layer (6b); and a second metal gate electrode (14) is provided above the second gate dielectric layer (9b); The second metal collector (11) and the first metal drain electrode (8) are electrically interconnected by a first metal layer (15), and the second metal gate electrode (14) and the first metal gate electrode (10) are electrically interconnected by a second metal layer (16), forming a CMOS structure.

2. The fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability according to claim 1, characterized in that: The first gallium oxide channel layer (5a) and the second gallium oxide channel layer (5b) are both fin-shaped structures with a width ranging from 0.01um to 1.5um and a thickness ranging from 100nm to 2um.

3. The fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability according to claim 1, characterized in that: The gallium oxide PMOS device (4) magnetron sputters an N-type gallium oxide dielectric layer (12) doped with Si on a P-type nickel oxide channel layer (6b) on the drain side, with a donor concentration range of 10 17 cm -3 -10 19 cm -3 , with a thickness ranging from 70nm to 90nm; the N-type gallium oxide dielectric layer (12), the P-type nickel oxide channel layer (6b) and the second gallium oxide channel layer (5b) constitute an NPN bipolar stacked triode structure.

4. The fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability according to claim 1, characterized in that: The second metal gate electrode (14) and the first metal gate electrode (10) are one or more combinations of Pd, Ni, Pt, Au, and W metal materials, and have the same work function.

5. The fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability according to claim 1, characterized in that: The first metal source electrode (7a), the first metal drain electrode (8), the second metal drain electrode (13), and the metal collector (11) are one or more combinations of Ti, In, and Au metal materials, and have the same work function.

6. The fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability according to claim 1, characterized in that: The first gallium oxide channel layer (5a) and the second gallium oxide channel layer (5b) are both N-type doped, with a concentration range of 10 17 cm -3 -10 18 cm -3 The P-type nickel oxide channel layer (6b) is P-type doped with a concentration range of 10 16 cm 3 -10 19 cm 3 .

7. The fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability according to claim 1, characterized in that: The first gallium oxide channel layer (5a) forms an ohmic contact with the first metal source electrode (7a) and the first metal drain electrode (8) above it; the second gallium oxide channel layer (5b) forms an ohmic contact with the metal collector electrode (11) above it; the nickel oxide channel layer (12) forms an ohmic contact with the second metal source electrode (7b) above it; and the first gate dielectric layer (9a) forms a Schottky contact with the first metal gate electrode (10) above it, the second gate dielectric layer (9b) and the second metal gate electrode (14) above it.

8. The fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability according to claim 1, characterized in that: The first gate dielectric layer (9a) and the second gate dielectric layer (9b) are one or more combinations of SiO2, Al2O3, Si3N4 dielectric materials, and have a thickness ranging from 100nm to 1000nm.

9. A method for preparing a fin-type gallium oxide heterogeneous CMOS platform with low power consumption and strong driving capability as claimed in any one of claims 1 to 8, characterized in that: The method comprises the following steps: epitaxially growing a semi-insulating gallium oxide substrate layer (1), an unintentionally doped gallium oxide buffer layer (2), and a gallium oxide channel layer in sequence; An inductively coupled plasma etching method is used for mesa isolation, and a Ni / SiO2 mask mode and SF6-ArICP-RIE technology are used to etch the gallium oxide channel layer to form a fin-shaped channel with uniform height, extending from the source end to the drain end, thereby generating a first gallium oxide channel layer (5a) with a fin structure and a second gallium oxide channel layer (5b) with a fin structure, which correspond to a gallium oxide NMOS device and a gallium oxide PMOS device, respectively; Wet acid treatment with room temperature diluted HCl and HF is used to restore surface damage caused by etching; Magnetron sputtering a P-type nickel oxide medium, and performing debonding and stripping to form a P-type nickel oxide gate cap layer (6a) and a P-type nickel oxide channel layer (6b); Magnetron sputtering an N-type gallium oxide dielectric layer (12) at the drain end of the gallium oxide PMOS device; Heavy doping is performed on four electrode regions, namely, a first metal source electrode (7a) of the gallium oxide NMOS device, a first metal drain electrode (8) of the gallium oxide NMOS device, a second metal drain electrode (13) of the gallium oxide PMOS device, and a collector (11) of the gallium oxide PMOS device, forming metal electrodes by electron beam evaporation, and thermal annealing is performed in an N2 atmosphere; Heavy doping is performed in the second metal source electrode (7b) region of the gallium oxide PMOS device, forming a metal electrode by electron beam evaporation, and thermal annealing is performed in an N2 atmosphere; Depositing a first gate dielectric layer (9a) and a second gate dielectric layer (9b) using ALD technology; Electron beam evaporation forms a first metal gate electrode (10) of a gallium oxide NMOS device and a second metal gate electrode (14) of a gallium oxide PMOS device; The surface is passivated, and a first metal gate electrode (10) of a gallium oxide NMOS device and a second metal gate electrode (14) of a gallium oxide PMOS device, and a first metal drain electrode (8) of the gallium oxide NMOS and a collector (11) of the gallium oxide PMOS device are metal interconnected through open hole contacts.

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