Data output method and device based on fixed-point number extraction and storage medium

Abstract

The invention discloses a data output method and device based on fixed-point number extraction and a storage medium, and relates to the technical field of computers, and the method comprises the steps: carrying out the calculation and normalization processing of a non-zero positive number of an input value through a precision formula, and generating a valid number corresponding to the non-zero positive number; querying in a compression lookup table according to a compression index corresponding to the effective number to obtain a reciprocal square root approximate value corresponding to the effective number; performing iterative optimization, index parity adjustment, remainder feedback correction and boundary specialization processing on the basis of a reciprocal square root approximate value corresponding to the effective number to generate an effective result; and carrying out reverse normalization processing on the effective result, generating a fixed point number corresponding to the effective result, and outputting the fixed point number. According to the invention, through conversion between the fixed-point number form and the effective number form, the technical problem of distributed environment amplification errors in a fixed-point number extraction algorithm in related technologies is solved, and the performance and accuracy of fixed-point number extraction are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a data output method based on fixed-point number square root, device and storage medium. BACKGROUND

[0002] In a distributed computing environment (such as games, simulation, physical engine, etc.), cross-platform data computing consistency is a key problem. In the related art, fixed-point numbers are directly used for square root operation, resulting in errors, which in turn magnifies the error in the distributed environment.

[0003] The above content is only used to assist in understanding the technical solutions of the present application and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0004] The main purpose of the present application is to provide a data output method based on fixed-point number square root, device and storage medium, aiming at solving the technical problem that in the related art, fixed-point numbers are used to replace significant digits, but the fixed-point number square root algorithm is restricted by various factors in implementation, resulting in the technical problem that precision and performance are difficult to balance.

[0005] To achieve the above purpose, the present application provides a data output method based on fixed-point number square root, which comprises:

[0006] The precision formula is used to calculate and normalize the non-zero positive number of the input value, to generate the significant digits corresponding to the non-zero positive number;

[0007] According to the compression index corresponding to the significant digits, the significant digits are queried in the compression lookup table to obtain the square root reciprocal approximation value corresponding to the significant digits;

[0008] Based on the square root reciprocal approximation value corresponding to the significant digits, iterative optimization, exponential parity adjustment, remainder feedback correction and boundary specialization processing are performed to generate effective results;

[0009] The effective results are subjected to inverse normalization processing to generate fixed-point numbers corresponding to the effective results and output.

[0010] In an embodiment, according to a preset number judgment rule, the input value is distinguished to determine the sign of the input value;

[0011] The number of binary leading zeros calculated based on the input value and its corresponding sign is used to determine the most significant bit position corresponding to the binary form input value;

[0012] According to the most significant bit position and the sign of the input value, the non-zero positive number of the input value is determined.

[0013] In one embodiment, an equivalent exponent is calculated for the non-zero positive number using a precision formula to generate an equivalent double-precision exponent corresponding to the non-zero positive number;

[0014] According to the double-precision exponent, a conditional bit shift operation and a normalization process are performed on the non-zero positive number to generate the significant digit corresponding to the non-zero positive number.

[0015] In one embodiment, an approximate value is searched in the compression lookup table based on the compression index corresponding to the significant digit to obtain an initial inverse square root approximation corresponding to the significant digit;

[0016] Calculating and generating a dynamic interpolation weight based on the low-order part corresponding to the effective number;

[0017] According to the dynamic interpolation weight, a linear weighted correction is performed on the initial inverse square root approximation to generate an optimized inverse square root approximation.

[0018] In one embodiment, the compressed index is generated based on the continuous high-order portion of the mantissa field corresponding to the truncated significant digit;

[0019] Generate the initial inverse square root approximation corresponding to the compression index according to the high-order part;

[0020] The compressed lookup table is generated based on the compressed index and the corresponding initial inverse square root approximation value.

[0021] In one embodiment, the reciprocal square root approximation is iteratively processed according to an iterative formula to generate an iterated reciprocal square root approximation;

[0022] performing bit weight compensation and remainder correction on the reciprocal square root approximation based on the parity of the double-precision exponent corresponding to the significant digit to generate a target reciprocal square root approximation;

[0023] Based on a preset boundary specialization condition, the target inverse square root approximation value is subjected to boundary specialization processing to generate a valid result.

[0024] In one embodiment, the valid results are calculated using an exponential formula to generate an index value of the valid results;

[0025] Performing a direction-adaptive shift operation based on the exponential value of the valid result to obtain the fixed-point result after the denormalization processing;

[0026] The sign bit is restored from the effective result to the highest bit of the fixed-point result, and a signed fixed-point number form is generated and output.

[0027] In one embodiment, the displacement is calculated based on the exponent value of the valid result, the decimal width of the fixed-point number, and the exponent offset of the internal floating-point format;

[0028] Based on the displacement amount, a direction-adaptive displacement operation is performed to adjust the effective result to generate the fixed-point result.

[0029] In addition, to achieve the above-mentioned purpose, the present application also proposes a fixed-point number square root device, which includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the computer program is configured to implement the steps of the data output method based on fixed-point number square root as described above.

[0030] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by the processor, the steps of the data output method based on fixed-point number square root as described above are implemented.

[0031] The present application provides a data output method based on fixed-point square root, including calculating and normalizing the non-zero positive number of the input value through a precision formula to generate a valid number corresponding to the non-zero positive number; querying the compressed lookup table according to the compression index corresponding to the valid number to obtain the square root reciprocal approximation corresponding to the valid number; performing iterative optimization, exponent parity adjustment, remainder feedback correction and boundary specialization based on the square root reciprocal approximation corresponding to the valid number to generate a valid result; performing denormalization on the valid result to generate a fixed-point number corresponding to the valid result and output it. The present application improves the accuracy and performance of the fixed-point square root operation by converting the input value into floating-point format for square root calculation, then making the open result more accurate through multi-dimensional processing, and finally converting it back to fixed-point number form.

[0032] In summary, this application achieves completely consistent fixed-point square root operations on different platforms by converting between fixed-point number form and effective digital form, combined with a series of methods to ensure high precision and high efficiency, while ensuring high precision and high performance. It overcomes the technical problem in related technologies of using fixed-point numbers to directly perform square root operations, resulting in errors, and then causing errors to be amplified in distributed environments, and improves the performance and accuracy of fixed-point square root operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those skilled in the art, the other drawings can also be obtained based on these drawings without any creative work.

[0035] Figure 1 Flowchart of a first embodiment of the data output method based on fixed-point number square root of the present application;

[0036] Figure 2 Flowchart of a second embodiment of the data output method based on fixed-point number square root of the present application;

[0037] Figure 3 Flowchart of a fifth embodiment of the data output method based on fixed-point number square root of the present application;

[0038] Figure 4 Flowchart of a sixth embodiment of the data output method based on fixed-point number square root of the present application;

[0039] Figure 5 Flowchart of a seventh embodiment of the data output method based on fixed-point number square root of the present application;

[0040] Figure 6 Structure diagram of the fixed-point number square root device of the present application.

[0041] The object implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0042] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application, and are not used to limit the present application.

[0043] In the related art, the fixed-point number is directly used for square root operation, which leads to error, and further leads to the problem of amplifying error in a distributed environment.

[0044] The present application provides a solution: first, the precision formula is used to calculate and normalize the non-zero positive input value, to generate the valid digits corresponding to the non-zero positive number, then, according to the compression index corresponding to the valid digits, the compressed lookup table is queried to obtain the square root reciprocal approximation value corresponding to the valid digits, then, based on the square root reciprocal approximation value corresponding to the valid digits, the iteration optimization, the index parity adjustment, the remainder feedback correction and the boundary specialization processing are performed to generate the effective result, finally, the effective result is normalized to generate the fixed-point number corresponding to the effective result and output.

[0045] It should be noted that the execution subject of the embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, or an electronic device capable of realizing the above functions, a fixed-point number square root device, etc. The following will take the fixed-point number square root device as an example to describe the embodiment and the following embodiments.

[0046] In order to better understand the technical solutions of the present application, the following will be described in detail in combination with the drawings of the specification and the specific embodiments.

[0047] The embodiment of the present application provides a data output method based on fixed-point number square root, referring to Figure 1 , Figure 1 The flowchart of the first embodiment of the data output method based on fixed-point number square root of the present application.

[0048] In the embodiment, the data output method based on fixed-point number square root includes steps S10-S40:

[0049] Step S10, calculating and normalizing the non-zero positive number of the input value by the precision formula, to generate the significant digits corresponding to the non-zero positive number.

[0050] In the embodiment, the non-zero positive number of the input value refers to the non-zero positive number filtered out by the user-provided input value according to the constraint condition of being greater than zero and not being zero. The precision formula refers to a mathematical expression used to determine the significant digits of the floating-point format mantissa and the rounding rule. The normalization processing refers to the operation of eliminating the leading "1" in binary representation and adjusting the value to the interval [1, 2). The significant digits refer to the 52-bit mantissa field (including the decimal part after rounding) after the leading "1" is hidden.

[0051] As an optional implementation, the input non-zero positive number is converted to binary format by presetting the precision bit width parameter of the double-precision floating-point format. First, the binary bit sequence of the input value is scanned to locate the position index of the most significant bit. The normalization displacement is calculated according to the difference between the position and the standard bit width of the mantissa field. The leading bit "1" of the integer part of the value is eliminated by shifting operation to adjust the value to the scientific notation interval. The leading preset number of significant digits of the decimal part in the bit sequence after shifting is taken as the base mantissa. The rounding decision is made based on the discarded low bit value to determine whether to adjust the last digit of the base mantissa. When mantissa overflow occurs, the bit displacement compensation mechanism is reactivated to correct the temporary exponent value synchronously. Finally, the preset number of significant digits of the hidden leading integer bit "1" is generated as the mantissa field output.

[0052] As an optional implementation, the non-zero positive number of the input value is converted into an absolute value binary original code representation, and the mantissa containing the protection bit in the non-zero positive number is truncated in combination with the precision formula. If the first digit of the truncated mantissa is zero, the mantissa is right-shifted and the exponent is incremented to complete normalization. The mantissa is rounded based on the precision formula. If the mantissa overflows after rounding, it is rolled back and right-shifted and the exponent is adjusted. Finally, the sign bit corresponding to the fixed-point number is fixed to zero to obtain the target sign bit. The target exponent field is obtained by adding a preset offset to the adjusted exponent, and the mantissa is truncated to the target number of bits to obtain the target mantissa field. The target sign bit, target exponent field and target mantissa field are combined according to the internal floating-point format to generate a valid number corresponding to the non-zero positive number.

[0053] As an optional input implementation method, an operator inputs the numerical value to be squared into the client or server, or transmits the numerical value to the client or server via data.

[0054] Step S20 , searching a compression lookup table according to the compression index corresponding to the valid number, and obtaining an approximate inverse square root value corresponding to the valid number.

[0055] In this embodiment, a compressed index is a condensed index generated by truncating the high-order bits of the mantissa of a significant number, with a bit width smaller than the full mantissa. A compressed lookup table is an optimized lookup table that stores precomputed reciprocal square root approximations, with the number of entries exponentially reduced due to index compression. The reciprocal square root approximation is a value generated through table lookup and compensation calculation, used as an initial estimate for subsequent iterative optimization.

[0056] As an optional implementation, based on the significant digit, the high-order part of the mantissa field corresponding to the significant digit is truncated as the initial compression index, the compression index offset is adjusted according to the parity of the exponent field corresponding to the significant digit to obtain the compression index, the stored compression lookup table is accessed according to the compression index, the initial square root inverse approximation is obtained, the interpolation compensation coefficient is calculated by truncating the low-order mantissa corresponding to the significant digit, the interpolation compensation coefficient is linearly superimposed with the initial square root inverse approximation to generate an optimized initial square root inverse approximation, and the initial square root inverse approximation is shifted and scaled according to the parity of the exponent corresponding to the significant digit, and finally the square root inverse approximation matching the significant digit is output.

[0057] Step S30 , performing iterative optimization, exponent parity adjustment, remainder feedback correction, and boundary specialization processing based on the reciprocal square root approximation corresponding to the effective digit to generate a valid result.

[0058] In this embodiment, iterative optimization refers to the process of repeatedly correcting approximate values ​​to improve computational accuracy using mathematical optimization methods such as the Newton-Raphson method. Exponent parity adjustment refers to shifting the mantissa based on the parity of the significand exponent and simultaneously correcting the exponent to ensure that the mantissa range meets normalization constraints. Residual feedback correction refers to calculating a compensation term using the residual error of the previous iteration result to dynamically correct the current iteration value. Boundary specialization refers to rounding compensation or bit width expansion for values ​​close to the boundaries of the floating-point representation range to avoid overflow or loss of precision.

[0059] As an optional implementation, iterative optimization is performed based on the initial inverse square root approximation corresponding to the significant digit, and a single Newton iteration formula is executed to obtain the inverse square root approximation after the iteration. Based on the inverse square root approximation after the iteration and combined with the exponent parity of the original significant digit, a bit weight compensation is generated. The mantissa of the iterative result is shifted right by one position or kept in place and the exponent corresponding to the significant digit is adjusted synchronously through the bit weight compensation. The remainder term of the significant digit is calculated and a compensation coefficient is generated through a right shift operation. The compensation coefficient is superimposed on the iterative result, and it is detected whether the corrected value is close to the minimum normalized value or the maximum range of the floating-point format. If it is in the boundary interval, additional rounding bit compensation is applied or the mantissa bit width is extended, and finally a valid result that meets the target accuracy is output.

[0060] As an implementation method for applying additional rounding bit compensation, the additional rounding bit is calculated based on the weight of the lowest bit of the mantissa corresponding to the current significant digit, the last bit of the mantissa is extended by one bit, and whether to carry is determined based on the mid-point threshold of the remainder. If the absolute value of the remainder exceeds the threshold or is equal to the threshold and the last bit is an odd number, the last bit is added by one. The step of extending the mantissa bit width is achieved by temporarily increasing the mantissa storage bit width, truncating it back to the target bit width after completing all arithmetic operations, and retaining the extended bit for dynamic precision compensation. Finally, an unbiased mantissa result is generated according to the rounding rules.

[0061] Step S40: Denormalize the valid result to generate a fixed-point number corresponding to the valid result and output it.

[0062] In this embodiment, the denormalization process refers to an inverse operation of restoring the normalized valid result to the original fixed-point representation.

[0063] As an optional implementation, based on the input valid result, the actual order parameter is calculated by analyzing the index domain to extract the offset exponent value, and after determining the positive and negative signs, the mantissa domain binary sequence is left shifted by a preset number of bits to restore the leading "1" to generate a preset bit complete mantissa base sequence. According to the actual exponent value, the bit shift compensation operation is performed on the base sequence: if the actual order parameter is greater than the order threshold, the integer part is expanded by left shifting the corresponding number of bits, and if the actual order parameter is less than the order threshold, the decimal point bit is calibrated by right shifting, and the rounding error correction value is compensated synchronously. Finally, the fixed-point number is output.

[0064] As an optional implementation, based on the significant digits, the sign bit of the valid result is extracted, the bit shift amount is calculated according to the exponent value of the significant digits and the index offset of the internal format, if the bit shift amount is greater than or equal to zero, the mantissa of the significant digits is left shifted by one bit shift amount to generate an integer part, if the bit shift amount is less than zero, the mantissa of the significant digits is right shifted by one bit shift amount, and the remainder of the significant digits after bit shift is extracted. According to the rounding to the nearest even rule, the fixed-point decimal number with low bit alignment is generated. Based on the significant digits after bit shift, it is detected whether the value after bit shift exceeds the fixed-point number bit width range, and when overflow occurs, the maximum value 2 or the minimum value -2 is returned, and when no overflow occurs, the fixed-point number highest bit sign flag is set according to the floating point sign bit, and the fixed-point number conforming to the internal representation form is output. The internal representation form refers to the storage format defined by the system, which includes the sign bit, the offset index domain, and the implicit highest bit mantissa domain.

[0065] Exemplarily, after receiving the input non-zero positive number, the binary most significant bit position is determined by leading zero counting, and the mantissa containing the guard bit is intercepted and normalized according to the precision formula to generate the internal significant digits with zero sign bit, offset exponent calibrated, and truncated mantissa to the target bit width. Based on the exponent parity and high bit mantissa of the significant digits, a compression index is generated, an initial reciprocal square root approximation value is obtained by accessing a pre-stored interpolation compensation optimized lookup table, a correction value is calculated by a single Newton iteration formula, the mantissa bit shift is adjusted according to the original exponent parity and the residue feedback compensation term is superimposed, an additional rounding bit compensation or bit width expansion is applied to the values close to the normalization boundary, and the corrected valid result is generated. The exponent of the valid result is extracted and the bit shift amount is calculated, the mantissa of the valid result is aligned to the decimal bit width of the target fixed-point number by left or right shift operation, the rounding to the nearest even rule is applied according to the residue value, and the saturation extreme value or the sign bit is injected after overflow detection. Finally, the signed fixed-point number conforming to the bit width constraint is output.

[0066] By converting between fixed-point number form and effective digital form, combined with a series of methods to ensure high precision and high efficiency, completely consistent fixed-point square root operations can be achieved on different platforms while ensuring high precision and performance. This overcomes the technical problem in related technologies of using fixed-point numbers directly for square root operations, which leads to errors and then causes errors to be amplified in distributed environments, thereby improving the performance and accuracy of the fixed-point square root method.

[0067] Based on any of the above embodiments, in the second embodiment of the present application, refer to Figure 2 , Figure 2 This is a flow chart of the second embodiment of the data output method based on fixed-point square root of this application. Before step S10, steps A11 to A13 are also included:

[0068] Step A11: Differentiate the input value according to a preset digital judgment rule and determine the sign of the input value.

[0069] In this embodiment, the preset numerical judgment rule refers to the system's predefined sign judgment logic used to determine whether a value is positive, negative, or zero. Discrimination refers to the process of classifying input values ​​based on numerical value size or specific conditions. The sign of an input value refers to an identifier for a value that is positive (+), negative (-), or zero (0).

[0070] As an optional implementation, after reading the original data of the input value, according to the symbol judgment logic in the preset digital judgment rule, if the input value is greater than zero, the sign is set to a positive number; if the input value is less than zero, the sign is set to a negative number; if the input value is zero, it is marked as a zero value or exception processing is triggered according to the rule, and finally the sign corresponding to the input value is output.

[0071] Step A12: determining the most significant bit position corresponding to the binary input value by calculating the number of binary leading zeros based on the input value and its corresponding sign.

[0072] In this embodiment, the number of leading zeros in binary refers to the number of consecutive zeros before the most significant bit of the input value after conversion to binary. The most significant bit position refers to the position sequence of the first non-zero bit in the binary value, counting from the most significant bit.

[0073] As an optional implementation, according to the sign corresponding to the input value, the absolute value of the input value is obtained, the absolute value of the input value is converted into a two's complement form, and the absolute value in the two's complement form is scanned from the highest binary bit to the first non-zero bit through a leading zero counting function, and the number of zeros before the first non-zero bit is counted as the number of leading zeros. If the input value is zero, the number of leading zeros is directly marked as the data bit width, otherwise its position is calculated according to the formula for the most significant bit position to obtain the most significant bit position corresponding to the binary input value, wherein the leading zero counting function refers to an algorithm for counting the number of consecutive zeros before the first non-zero bit of a binary value from the left.

[0074] Step A13: Determine whether the input value is a non-zero positive number according to the most significant bit position and the sign of the input value.

[0075] In this embodiment, the input value is judged based on a mathematical judgment method, and a corresponding operation is generated according to whether the input value is a positive number, a negative number, or zero.

[0076] As an optional implementation, if the sign identifier of the input value is zero and the most significant bit position of the input value exists, then the input value is determined to be a non-zero positive number.

[0077] As an implementation method with an optional input value of zero or a negative number, if the sign is a negative number identifier or the most significant bit position does not exist, the input value is determined to be negative or zero, triggering exception handling or terminating the process, and finally outputting a confirmation mark of a non-zero positive number and a binary normalized value.

[0078] Exemplarily, after reading the original data of the input value, its sign is determined according to a preset digital judgment rule: if the input value is greater than zero, the sign identifier is set to positive (0); if it is less than zero, it is negative (1); if it is zero, it is marked as zero and the process is terminated. After retaining the sign identifier, the absolute value of the input value is converted into a binary complement form, and the leading zero counting function is used to scan from the highest binary bit to the first non-zero bit, and the number of consecutive zeros before it is counted as the number of leading zeros. Its position is determined according to the formula: most significant bit position = total bit width - 1 - number of leading zeros. If the sign identifier is positive and the most significant bit position is valid (not all zero), the input value is determined to be a non-zero positive number and its binary normalized value is output. Otherwise, an exception is triggered or an error state is returned.

[0079] By pre-setting digital judgment rules and generating symbolic identifiers, the efficiency of input value legitimacy detection and exception handling is ensured, preventing invalid negative numbers or zero values ​​from entering the subsequent calculation process. Combined with the leading zero counting function and binary conversion mechanism, the most significant bit position is accurately located, thereby improving the performance and accuracy of the fixed-point square root method.

[0080] Based on any of the above embodiments, in the third embodiment of the present application, step S10 includes steps B11 to B12:

[0081] Step B11, calculating the equivalent exponent of the non-zero positive number using a precision formula to generate an equivalent double-precision exponent corresponding to the non-zero positive number.

[0082] In this embodiment, the double-precision exponent refers to an 11-bit unsigned integer generated by adding an offset to the actual exponent value of the significant digit based on the IEEE-754 standard.

[0083] As an optional implementation, the non-zero positive number is converted into binary form, the most significant bit position corresponding to the non-zero positive number in binary form is determined by counting leading zeros, the most significant bit position of the exponent corresponding to the non-zero positive number is calculated according to the precision formula, the double-precision offset is superimposed to generate a double-precision exponent, the lowest binary bit is checked, if the lowest binary bit is 1, the parity is marked and the corrected exponent is stored, if the lowest binary bit is 0, the even mark and the exponent corresponding to the non-zero positive number are retained, and a parity marker is bound to the double-precision exponent, wherein the parity marker refers to a logical operation of performing parity judgment on the lowest binary bit of the double-precision exponent and generating a marker.

[0084] Step B12: Perform a conditional shift operation and normalization processing on the non-zero positive number according to the double-precision exponent to generate the valid digit corresponding to the non-zero positive number.

[0085] In this embodiment, the conditional bit shift operation refers to a bit operation of shifting the mantissa left or right according to the parity of the double-precision exponent.

[0086] As an optional implementation, a normalized shift parameter is parsed based on the double-precision exponent value calculated in the previous step, and an exponent-driven conditional shift operation is performed on the input non-zero positive number: when the exponent indicates that the leading "1" needs to be eliminated, the left shift logic is started, and when the exponent underflow is detected, the right shift compensation path is switched. After the shift is completed, a preset number of bits is truncated, the highest bit "1" of the integer is removed from the intermediate bit sequence, and the preset number of bits after the decimal point is taken as the basic mantissa field. The rounding decision maker is called based on the discarded low-order bit value. If the most significant bit of the discarded bit is 1, the last bit of the mantissa is triggered to carry 1. When the carry causes overflow, the mantissa is synchronously shifted right by 1 and the exponent value is incremented, and finally a preset number of significant digits after rounding adjustment is generated as output.

[0087] As an optional implementation, based on the parity mark of the double-precision exponent, if the double-precision exponent is an odd number, the binary mantissa of the non-zero positive number is shifted right by 1 bit and the exponent value is updated; if the double-precision exponent is an even number, the original mantissa and exponent are directly retained, the double-precision offset is subtracted from the adjusted double-precision exponent, the actual exponent is restored, the high bit of the mantissa is truncated as the valid mantissa field; if the mantissa overflows after truncation, it is shifted right by one bit and the actual exponent is incremented; the sign bit is fixed to zero, the internal format offset is superimposed on the actual exponent to generate the exponent field; the mantissa field removes the implicit highest bit and is filled to the target bit width; the sign bit, the exponent field, and the mantissa field are combined to form the valid digits corresponding to the non-zero positive number.

[0088] Exemplarily, after the non-zero positive number is converted into binary form, its most significant bit position is determined by counting leading zeros, the original exponent = most significant bit position - 1 is calculated based on the precision formula, the double-precision offset is superimposed to generate a double-precision exponent = original exponent + 1023, and the lowest binary bit of the double-precision exponent is detected to mark the parity; if the mark is odd, the binary mantissa is shifted right by 1 bit and the exponent is updated to the updated exponent = double-precision exponent - 1, otherwise the original mantissa and exponent are retained; the adjusted exponent is restored to the actual exponent = updated exponent - 1023, the upper 23 bits of the mantissa are truncated and overflow is processed, and the sign bit (fixed to 0), the exponent field (actual exponent + internal offset) and the mantissa field are combined to generate an internal valid number.

[0089] Since the mantissa normalization process is optimized by dynamically adjusting the parity of the double-precision exponent, the resource waste of traditional bit shift operations is avoided, and the performance of the fixed-point square root method is improved.

[0090] Based on any of the above embodiments, in the fourth embodiment of the present application, step S20 includes steps C11 to C13:

[0091] Step C11 , searching for an approximate value in the compression lookup table based on the compression index corresponding to the significant digit, and obtaining an initial inverse square root approximate value corresponding to the significant digit.

[0092] In this embodiment, the initial inverse square root approximation associated with the compressed index is filtered out from the compressed lookup table through the compressed index.

[0093] As an optional implementation, a compression index is generated by truncating the continuous high-bit part starting from the most significant bit from the mantissa field of the valid number, and an approximate value is queried in the compression table based on the compression index, and the initial inverse square root approximation stored in the table is read to determine and obtain the initial inverse square root approximation corresponding to the compression index.

[0094] Step C12: Calculate and generate dynamic interpolation weights based on the low-order portion corresponding to the effective number.

[0095] In this embodiment, the low-order portion corresponding to the significant digit refers to the remaining low-order data in the floating-point mantissa field that is not covered by the compressed index and is used for dynamic error compensation. The dynamic interpolation weight refers to the linear interpolation coefficient calculated in real time based on the numerical range of the low-order portion.

[0096] As an optional implementation, the low-order data in the significant digit mantissa field that is not covered by the compressed index is extracted, and the normalized ratio value of the low-order data relative to the total low-order bit width is calculated as the dynamic interpolation weight.

[0097] Step C13: performing a linear weighted correction on the initial inverse square root approximation according to the dynamic interpolation weight to generate an optimized inverse square root approximation.

[0098] In this embodiment, the initial inverse square root approximation refers to the uncorrected inverse square root estimate directly obtained from the compressed lookup table. Linear weighted correction refers to an error compensation operation that linearly combines the initial approximation with the differences between adjacent table entries according to weights. The optimized inverse square root approximation refers to the final approximation that meets the target accuracy requirements after correction.

[0099] As an optional implementation, the dynamic interpolation weight is used as a coefficient, and the differences between adjacent table items in the compressed lookup table are linearly combined to generate a compensation increment value, which is superimposed on the initial inverse square root approximation. If the superimposed initial inverse square root approximation exceeds a preset accuracy threshold, saturation truncation is performed. If the final output error is less than the preset error threshold, the superimposed initial inverse square root approximation is used as the optimized inverse square root approximation.

[0100] Exemplarily, continuous high bits are truncated from the mantissa field of the significant digit to generate a compressed index (such as taking the first 12 bits as the index address), and a pre-compression lookup table is accessed to obtain an initial inverse square root approximation. The lookup table optimizes storage space by pre-calculating interpolation compensation, and each table entry stores a 32-bit approximation compensated for low-bit errors; the low-bit portion of the mantissa field not covered by the index is extracted, and its value is normalized to the interval [0, 1) to generate a dynamic interpolation weight. The weight is used as a coefficient to perform a multiplication and addition operation on the difference between adjacent table entries in the lookup table to generate a compensation value. After the compensation value is superimposed on the initial approximation, the result is overflow detected and saturated truncation is performed, and an optimized inverse square root approximation with an error less than 1ULPs (least precision unit) is output.

[0101] Because the storage size is exponentially compressed through compressed indexes and pre-compensated lookup tables while retaining the original precision characteristics, dynamic interpolation weights combined with the difference between adjacent table entries achieve real-time error compensation, converging the approximate error to within 1ULPs without expanding the number of table entries. The normalized weight calculation and multiplication and addition operations are adapted to the hardware single-cycle instruction set, meeting high-throughput computing requirements and improving the performance of the fixed-point square root.

[0102] Based on any of the above embodiments, in the fifth embodiment of the present application, refer to Figure 3 , Figure 3 This is a flow chart of the fifth embodiment of the data output method based on fixed-point square root of this application. Before step S30, it also includes steps D11 to D13:

[0103] Step D11: Generate the compressed index based on the continuous high-order portion of the mantissa field corresponding to the truncated significant digit.

[0104] In this embodiment, the mantissa field refers to a binary bit segment storing a significant digit in the significant digit. The continuous high-order portion refers to a number of consecutive binary bits starting from the most significant bit in the mantissa field.

[0105] As an optional implementation, based on the mantissa field of the valid digit, the implicit most significant bit is removed from the mantissa field, the highest bit of the remaining mantissa in the mantissa field is truncated to a continuous preset number of bits, and a compressed index is generated based on the truncated continuous preset number of bits.

[0106] Step D12: Generate the initial inverse square root approximation corresponding to the compression index based on the high-order portion.

[0107] In this embodiment, the high-order portion refers to a continuous binary bit segment starting from the most significant bit in the significand mantissa field.

[0108] As an optional implementation, the high-order part is left-shifted to align to the target bit width of the compressed index. If the high-order part width is insufficient, the low-order zeros are filled to the target bit width. The generated compressed index is used to access the compressed lookup table, and the initial inverse square root approximation stored in the table is directly read. The compressed lookup table pre-corrects the index truncation error through a linear interpolation compensation algorithm of adjacent indexes to generate a corrected initial inverse square root approximation.

[0109] Step D13: Generate the compression lookup table based on the compression index and its corresponding initial inverse square root approximation.

[0110] In this embodiment, association generation refers to a pre-calculation process of constructing a lookup table according to the correspondence between indexes and approximate values.

[0111] As an optional implementation, all compressed indexes are traversed, and the exact square root inverse average value is calculated for the complete mantissa interval corresponding to each index value. Linear interpolation compensation is performed based on the exact results of adjacent index values ​​to generate a pre-compensated approximation. The initial square root inverse approximation is compensated according to the compensated approximation, and the compensated initial square root inverse approximation is associated and stored according to the compressed index, and finally a compressed lookup table of the initial square root inverse approximation corresponding to the compressed index is output.

[0112] Exemplarily, after removing the implicit most significant bit from the mantissa field of the valid number, N consecutive bits (such as N=12) starting from the most significant bit are intercepted as the high-order part, left-shifted and filled with low-order zeros to the target bit width to generate a compressed index, all possible compressed index values ​​are traversed, and the exact inverse square root of the complete mantissa interval corresponding to each index (such as the index covers the high-order 12 bits and the remaining low-order 20 bits) is calculated. Linear interpolation compensation is performed based on the exact result difference of adjacent indexes to generate a pre-compensated approximation, and the compensated 32-bit approximation is stored in the compressed lookup table according to the index address to generate a pre-compensated optimized lookup table with a table number of 2^N entries.

[0113] By compressing the lookup table size from the exponential level through high-bit truncation and pre-compensation interpolation mechanisms, and using interpolation pre-compensation to eliminate position errors caused by index truncation, the accuracy of the initial approximation value can be strictly controlled, thereby improving the accuracy of the fixed-point square root method.

[0114] Based on any of the above embodiments, in the sixth embodiment of the present application, refer to Figure 4 , Figure 4 This is a flow chart of the sixth embodiment of the data output method based on fixed-point square root of this application. Step S30 includes steps E11 to E13:

[0115] Step E11 : performing iterative processing on the inverse square root approximation value according to an iterative formula to generate an iterated inverse square root approximation value.

[0116] In this embodiment, the iterative formula refers to a mathematical expression based on Newton's method or an improved numerical approximation method. Iterative processing refers to a calculation process that gradually approaches higher precision through multiple iterations and corrections. Intermediate values ​​refer to temporary approximate values ​​generated during each iteration. The reciprocal square root approximation after iteration refers to the final result that meets the target precision requirement after multiple corrections.

[0117] As an optional implementation, the initial inverse square root approximation is input into the iterative formula, and a single or multiple iterations are performed. The intermediate result retaining the double precision exponent is calculated to generate a corrected intermediate value. If the target precision error is greater than the precision error threshold, the iteration is repeated until it meets the precision error threshold. Otherwise, the inverse square root approximation after a single iteration is directly output to generate the inverse square root approximation after iteration, wherein correction refers to the error compensation operation of updating the intermediate value according to the iterative formula.

[0118] Step E12: performing bit weight compensation and remainder correction on the reciprocal square root approximation based on the parity of the double-precision exponent corresponding to the significant digit to generate a target reciprocal square root approximation.

[0119] In this embodiment, the remainder correction refers to using the remainder to perform incremental compensation on the approximation value. The target inverse square root approximation value refers to the final result that meets the preset accuracy requirement after error compensation.

[0120] As an optional implementation, by extracting the double-precision exponent of the significant digit and determining the parity of the double-precision exponent, if it is odd, the mantissa is shifted right by one position and the exponent is decremented to maintain numerical equivalence, a corrected intermediate value is generated, the square of the intermediate value is calculated and multiplied by the original number to obtain the remainder, and the compensation weight coefficient is dynamically adjusted according to the positive and negative and size of the remainder value. The intermediate value and the compensation term are added to generate the target reciprocal square root approximation. If the absolute value of the remainder is greater than a threshold, the compensation operation is repeated until convergence, and finally the target reciprocal square root approximation is output, wherein the square remainder of the intermediate value refers to the error remainder generated by squaring the current reciprocal square root approximation and multiplying it by the original number.

[0121] In step E13 , based on a preset boundary specialization condition, the target inverse square root approximation value is subjected to boundary specialization processing to generate a valid result.

[0122] In this embodiment, the preset boundary specialization condition refers to a special processing rule triggered when the input value approaches zero, infinity, or a specific threshold. Boundary specialization processing refers to operations such as bit width expansion, saturation truncation, or sign correction on the approximate value under boundary conditions. The valid result refers to the final output value that conforms to the internal floating-point format.

[0123] As an optional implementation, whether the target reciprocal square root approximation is in a minimum, maximum, or special numerical interval is determined according to a preset boundary specialization condition. If the target reciprocal square root approximation is in a minimum interval, the target reciprocal square root approximation is shifted left by the mantissa bits and the exponent is decremented to avoid underflow. If the target reciprocal square root approximation is in a maximum interval, the target reciprocal square root approximation is shifted right by the mantissa bits and the exponent is incremented to prevent overflow. If it is detected that the input original number of the target reciprocal square root approximation is zero, the target reciprocal square root approximation is directly marked as infinite. If the target reciprocal square root approximation is a special numerical value, the identifier of the target reciprocal square root approximation is inherited, and the normalized bit width is adjusted according to the exponent and mantissa corresponding to the corrected target reciprocal square root approximation, the overflow bit is saturated and truncated to the target floating-point format bit width, the sign bit is fixed to non-negative, and finally a valid result that conforms to the internal floating-point representation is synthesized.

[0124] Exemplarily, the initial inverse square root approximation is input into the Newton iteration formula for single iterative optimization, the square of the intermediate value is calculated and multiplied by the original significant digit to generate a remainder, the compensation weight is dynamically adjusted according to the remainder and the intermediate value is updated, and the parity of the double-precision exponent of the significant digit is taken into consideration. If the exponent is odd, the mantissa is shifted right by 1 bit and the exponent is decreased to eliminate the parity deviation, the remainder is calculated again for the corrected intermediate value and linear weighted compensation is performed to generate a target inverse square root approximation with an error less than 0.5ULPs; for the target approximation, it is determined whether it is in a minimum value (close to zero), a maximum value (close to infinity) or a special value. If it is in a minimum value range, the mantissa is shifted left and the exponent is adjusted to prevent underflow. If it is in a maximum value range, the mantissa is shifted right and the exponent is increased to avoid overflow. If the input original number is zero, an infinity flag is returned. Finally, the adjusted exponent is superimposed on the internal format offset, the mantissa is truncated to the target bit width, and a sign bit is injected to generate a final result that meets the internal floating-point representation specifications.

[0125] Thanks to the dual correction mechanism of Newton iteration and dynamic compensation of the remainder, the initial approximation error is reduced to meet the needs of high-precision calculations. The parity-driven mantissa shift and exponent adjustment are combined to eliminate normalization deviations and ensure the numerical stability of intermediate value corrections. Boundary specialization is then used to effectively avoid floating-point overflow and underflow exceptions, ensuring output compliance for extreme input values ​​and improving the accuracy of the fixed-point square root method.

[0126] Based on any of the above embodiments, in the seventh embodiment of the present application, refer to Figure 5 , Figure 5 This is a flow chart of the seventh embodiment of the data output method based on fixed-point square root of this application. Step S40 includes steps F11 to F13:

[0127] Step F11, calculating the valid result using an exponential formula to generate an exponential value of the valid result.

[0128] In this embodiment, the exponent formula refers to the rule for calculating the actual exponent based on the exponent offset defined in the floating-point format. The exponent value refers to the actual exponent in the scientific notation of the significant digits, which determines the magnitude of the value.

[0129] As an optional implementation, the stored binary exponent value is extracted according to the exponent field of the valid result, and the actual exponent value is calculated by the exponential formula according to the exponent offset of the internal floating-point format. If the valid result is a non-normalized number, the actual exponent is forced to be set to a preset format to adapt to the special representation rules. If the valid result is infinity or a non-numeric value, the exponent calculation is skipped, and the original identifier is directly inherited, and finally the exponent value that matches the actual numeric value is output.

[0130] Step F12: performing a direction-adaptive shift operation based on the exponential value of the valid result to obtain the fixed-point result after the denormalization processing.

[0131] In this embodiment, the direction-adaptive bit shift operation refers to a binary bit shift operation that dynamically selects left or right shift based on the difference between the exponent value and the target fixed-point number bit width. A fixed-point result refers to a numerical format with fixed bit widths for the integer and fractional parts.

[0132] As an optional implementation, the actual order parameter is calculated based on the exponent value parsed from the valid result, and the preset number of digits in the mantissa field is combined to restore the implicit leading "1" to form a complete mantissa sequence of the preset number of digits. The direction adaptive shift is performed according to the positive and negative signs of the actual order parameter: when the actual exponent is greater than or equal to the exponent threshold, a left shift operation is performed to move the binary decimal point right to the end of the mantissa; when the actual exponent is less than the exponent threshold, the right shift path is switched to shift the decimal point left. Rounding compensation is synchronously processed during the shifting process, and a preset correction value is injected into the least significant bit according to the rounding direction of the original floating-point conversion, and finally a fixed-point result matching the target bit width is generated.

[0133] As an optional implementation, the exponent value of the valid result is extracted, combined with the decimal width of the target fixed-point number and the exponent offset of the floating-point format, to calculate the displacement. If the displacement is greater than or equal to zero, the floating-point mantissa is left-shifted by the absolute value of the displacement to generate a high-bit aligned fixed-point integer part. If the displacement is less than zero, the mantissa is right-shifted by the absolute value of the displacement and the remainder is retained. The round-to-nearest-even rule is applied to the remainder after the right shift. It is detected whether the shifted or rounded value exceeds the target fixed-point number bit width range. In case of overflow, the corresponding extreme value is returned. Otherwise, the floating-point sign bit is injected into the highest bit of the fixed-point number to generate the final signed fixed-point result.

[0134] Step F13, restore the sign bit from the valid result to the highest bit of the fixed point result, generate and output the signed fixed point number form.

[0135] In the embodiment, the sign bit refers to the binary bit in the significant digit that identifies the positive or negative. The fixed point result refers to the intermediate value with the fixed bit width of the integer and the decimal part. The signed fixed point number refers to the positive or negative value in the two's complement form, including the sign bit, the integer bit and the decimal bit.

[0136] As an optional implementation, according to the sign bit of the valid result, the binary identifier is extracted, if the sign bit is 1, the absolute value of the fixed point result is converted to the two's complement form, otherwise the original code form is retained, the sign bit is written to the highest bit of the fixed point number, the value after the sign injection is detected whether it exceeds the target fixed point number bit width range, if it overflows, the corresponding extreme value is returned, otherwise the signed fixed point number combined by the sign bit and the value bit is directly output.

[0137] Exemplarily, first, the exponent value corresponding to the valid result is extracted, the actual exponent is calculated according to the exponent offset of the internal floating point format, if the valid result is a non-normalized number, the exponent is forced to be 1-B, if the valid result is a special value, the identifier is directly inherited, based on the actual exponent and the decimal bit width of the target fixed point number, the bit shift s is calculated, if s≥0, the floating point mantissa is left shifted by s bits to generate the high bit aligned integer part, if s<0, the mantissa is right shifted by ∣s∣ bits and the remainder is applied to the round to nearest even rule, the overflow is detected and the extreme value is returned, the floating point sign bit (0 or 1) is extracted and injected to the highest bit of the fixed point result, if the sign bit is 1, the fixed point value is converted to the two's complement form, the value after the sign bit injection is detected whether it exceeds the target fixed point number bit width range, if it overflows, the saturated extreme value is returned, otherwise the signed fixed point number combined by the sign bit and the value bit is output.

[0138] Since the high-precision conversion from floating point to fixed point is realized by the dynamic bit shift direction and the rounding rule, the error can be strictly controlled, the format compatibility is guaranteed by the calculation of the exponent offset and the bit shift, the calculation chain error diffusion is effectively prevented by the sign bit restoration, the two's complement conversion mechanism, the overflow detection and the extreme value truncation, the system robustness is enhanced, and the precision and efficiency of the fixed point square root method are improved.

[0139] Based on any of the above embodiments, in the eighth embodiment of the present application, step F12 includes steps G11-G12:

[0140] Step G11, calculate the bit shift s according to the exponent value of the valid result, the decimal bit width of the fixed point number and the exponent offset of the internal floating point format.

[0141] In this embodiment, the decimal width of a fixed-point number refers to the number of binary bits allocated to the decimal portion of the target fixed-point number format. The exponent offset of the internal floating-point format refers to the difference between the stored exponent value and the actual exponent value as defined by the floating-point standard. The displacement refers to the number of binary bits used to shift the mantissa left or right, determined by the difference between the exponent and decimal widths.

[0142] As an optional implementation, the stored binary exponent value is extracted from the exponent field of the valid result, and the actual exponent is calculated based on the offset of the internal floating-point format. If the valid result is a non-normalized number, it is forced to be corrected. If the valid result is a special value, the calculation is skipped and the identifier is inherited. Combined with the decimal place width of the target fixed-point number, the displacement is calculated and output through the displacement formula.

[0143] Step G12: performing a direction-adaptive displacement operation based on the displacement amount, adjusting the effective result, and generating the fixed-point result.

[0144] In this embodiment, generating a fixed-point result is a process of adjusting the floating-point mantissa to a target fixed-point format through a bit shift operation.

[0145] As an optional implementation, the shift direction is dynamically selected according to the sign of the shift amount. If the shift amount is greater than or equal to zero, the floating-point mantissa is shifted left by the shift amount to expand the integer part, and the overflow high bits that exceed the target fixed-point integer bit width are truncated. If the shift amount is less than zero, the mantissa is shifted right by the absolute value of the shift amount to adapt to the decimal bit width, retaining the integer part after the right shift, and the low-order remainder discarded by the right shift is processed according to the rounding to the nearest even number rule. It is checked whether the shifted value exceeds the target fixed-point bit width range. In case of overflow, the corresponding extreme value is returned, otherwise the adjusted fixed-point result is output.

[0146] Exemplarily, the storage exponent value of the valid result is extracted, and the actual exponent Eactual = EStored - B is calculated according to the exponent offset B of the internal floating-point format. If the valid result is a denormalized number (EStored = 0), the actual exponent is forcibly corrected to 1-B. Special values ​​(such as Inf / NaN) are skipped and the identifier is inherited. The displacement is calculated by combining the fractional bit width fraction_bits of the target fixed-point number through the formula s = Eactual + B-fraction_bits. If s≥0, the floating-point mantissa is shifted left by s bits and the high-order overflow part is truncated. If s<0, the mantissa is shifted right by |s| bits and the discarded low-order remainder is rounded to the nearest even rule (carry when the remainder is greater than 2|s|-1 or equal to the value and the least significant bit is an odd number). It is detected whether the value after the shift exceeds the bit width range of the target fixed-point number (such as the maximum value of a 32-bit fixed-point number is 2 to the thirty-first power -1). If there is overflow, the corresponding extreme value is returned, otherwise the adjusted fixed-point result is output.

[0147] Since high-precision conversion from floating-point to fixed-point is achieved through dynamic displacement direction and remainder rounding rules, errors are reduced. At the same time, the loss of precision of minimum values ​​is avoided through denormalized exponent correction, ensuring full-scale numerical coverage. Combined with the displacement formula, it is compatible with different floating-point formats and arbitrary fixed-point bit width configurations. The overflow truncation and extreme value return mechanisms prevent the propagation of calculation chain errors, enhance system robustness, and improve the accuracy and efficiency of the fixed-point square root method.

[0148] Based on any of the above embodiments, in Embodiment 9 of the present application, the square root verification method between the client and the server is as follows:

[0149] As an optional implementation method, in the scenario where the client and the server perform square root verification, by receiving the input value, the input value information is synchronized between the client and the server, and the client and the server both perform square root calculations on the input value at the same time. By reading the original data of the input value, the input value is sign-judged based on the sign judgment logic in the preset digital judgment rule, and the input value is divided into positive, negative and zero values. The non-zero positive numbers are filtered out and converted into the corresponding binary form. The most significant bit position of the non-zero positive number in binary form is determined by counting the leading zeros. The mantissa of the non-zero positive number including the protection bit is truncated by the precision formula and normalized. An internal valid digit is generated with a sign bit of zero, an exponent calibrated by an offset, and a mantissa truncated to a target bit width. The correction value is calculated according to the single Newton iteration formula to obtain the reciprocal square root approximation after the iteration. Based on the reciprocal square root approximation after the iteration and combined with the exponent parity of the original valid digit, a bit weight compensation is generated. The bit weight compensation is used to The mantissa of the iterative result is shifted right by one position or remains in place, and the exponent corresponding to the significant digit is synchronously adjusted. The remainder of the significant digit is calculated and a compensation coefficient is generated by a right shift operation. The compensation coefficient is added to the iterative result. The corrected value is checked to see if it is close to the minimum normalized value or maximum range of the floating-point format. If it is in the boundary interval, additional rounding bit compensation is applied or the mantissa bit width is expanded. Finally, a valid result that meets the target precision is output. The exponent of the valid result is extracted and the displacement is calculated. The floating-point mantissa is aligned to the decimal bit width of the target fixed-point number through a left shift or a right shift operation. The round-to-nearest-even rule is applied based on the remainder value. After detecting overflow, the saturated extreme value is returned or a sign bit is injected. Finally, a signed fixed-point number that meets the bit width constraint is output. Finally, the output results obtained by taking the square root of the same input value by the client and the server are verified. If the output results of the client and the server are the same, the verification result is passed. If the output results of the client and the server are different, the verification result is failed.

[0150] The application provides a fixed-point number square root device, which comprises at least one processor and a memory connected with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the fixed-point number square root-based data output method in the first embodiment.

[0151] Reference will be made to the following Figure 6 which shows a structural diagram of the fixed-point number square root device suitable for being used to implement the embodiments of the application. The fixed-point number square root device in the embodiments of the application can include, but is not limited to, mobile terminals such as mobile phones, notebook computers, smart calculators, personal digital assistants (PDA), tablet computers (PAD), portable multimedia players (PMP), fixed-point number square root devices, and the like, and fixed terminals such as portable calculators, desktop computers, and the like. Figure 6 The fixed-point number square root device shown is only an example, and should not bring any limitation to the functions and use range of the embodiments of the application.

[0152] As Figure 6As shown, the fixed-point number square root device may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes based on a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. Various programs and data required for the operation of the fixed-point number square root device are also stored in the random access memory 1004. The processing device 1001, the read-only memory 1002, and the random access memory 1004 are connected to each other via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input device 1007 including, for example, a touch screen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output device 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage device 1003 including, for example, a magnetic tape, hard disk, etc.; and communication device 1009. Communication device 1009 can allow the fixed-point number square root device to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows a fixed-point number square root device with various systems, it should be understood that it is not required to implement or have all of the systems shown. More or fewer systems may be implemented or have alternatively.

[0153] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program comprising program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device 1003, or installed from a read-only memory 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are performed.

[0154] The fixed-point number square root device provided in this application utilizes the data output method based on fixed-point number square root in the above-mentioned embodiment, resolving the technical issue in related art where direct square root calculations using fixed-point numbers result in errors, which in turn leads to amplified errors in distributed environments. Compared to the prior art, the fixed-point number square root device provided in this application achieves the same beneficial effects as the data output method based on fixed-point number square root in the above-mentioned embodiment. Other technical features of this fixed-point number square root device are the same as those disclosed in the above-mentioned embodiment and are not further elaborated here.

[0155] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0156] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

[0157] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, a computer program) stored thereon, wherein the computer-readable program instructions are used to execute the data output method based on fixed-point number square root in the above embodiment.

[0158] The computer-readable storage medium provided in this application can be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination thereof. More specific examples of computer-readable storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM, Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM, CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, radio frequency (RF, Radio Frequency), etc., or any suitable combination thereof.

[0159] The computer-readable storage medium may be included in the fixed-point number square root device; or may exist independently without being assembled into the fixed-point number square root device.

[0160] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by a fixed-point number square root device, the fixed-point number square root device: calculates and normalizes the non-zero positive number of the input value through a precision formula to generate a valid digit corresponding to the non-zero positive number; queries a compressed lookup table according to the compression index corresponding to the valid digit to obtain the square root reciprocal approximation corresponding to the valid digit; based on the square root reciprocal approximation corresponding to the valid digit, performs iterative optimization, exponent parity adjustment, remainder feedback correction and boundary specialization processing to generate a valid result; denormalizes the valid result to generate a fixed-point number corresponding to the valid result and outputs it.

[0161] Computer program code for performing the operations of the present application can be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0162] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0163] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0164] The computer-readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the aforementioned data output method based on fixed-point square root calculations. This computer-readable storage medium can address the technical issues in related art where direct square root calculations using fixed-point numbers can lead to errors, which in turn can lead to amplified errors in distributed environments. Compared to the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the data output method based on fixed-point square root calculations provided in the aforementioned embodiments, and are not further elaborated here.

[0165] The above description is only part of the embodiments of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made by using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A data output method based on fixed-point number square root, characterized in that: The method comprises: Calculate and normalize the non-zero positive number of the input value using the precision formula to generate a valid number corresponding to the non-zero positive number; According to the compression index corresponding to the effective number, query the compression lookup table to obtain the inverse square root approximation corresponding to the effective number; Based on the reciprocal square root approximation corresponding to the significant digit, iterative optimization, exponent parity adjustment, remainder feedback correction, and boundary specialization processing are performed to generate a valid result; The valid result is denormalized to generate a fixed-point number corresponding to the valid result and output it.

2. The data output method based on fixed-point number square root according to claim 1, wherein: Before the step of calculating and normalizing the non-zero positive number of the input value using the precision formula to generate a valid digit corresponding to the non-zero positive number, the method further includes: Differentiate the input value according to a preset digital judgment rule and determine the sign of the input value; determining a most significant bit position corresponding to the input value in binary form by calculating the number of leading binary zeros based on the input value and its corresponding sign; A non-zero positive number of the input value is determined based on the most significant bit position and the sign of the input value.

3. The data output method based on fixed-point number square root according to claim 1, wherein: The step of calculating and normalizing the non-zero positive number of the input value by using the precision formula to generate a valid number corresponding to the non-zero positive number includes: Calculating an equivalent exponent of the non-zero positive number using a precision formula to generate an equivalent double-precision exponent corresponding to the non-zero positive number; According to the double-precision exponent, a conditional bit shift operation and a normalization process are performed on the non-zero positive number to generate the significant digit corresponding to the non-zero positive number.

4. The data output method based on fixed-point square root as claimed in claim 1, wherein: The step of querying a compression lookup table according to the compression index corresponding to the effective number to obtain the inverse square root approximation corresponding to the effective number includes: Searching for an approximate value in the compression lookup table based on the compression index corresponding to the significant digit, and obtaining an initial inverse square root approximation corresponding to the significant digit; Calculating and generating a dynamic interpolation weight based on the low-order part corresponding to the effective number; According to the dynamic interpolation weight, a linear weighted correction is performed on the initial inverse square root approximation to generate an optimized inverse square root approximation.

5. The data output method based on fixed-point number square root according to claim 4, characterized in that: Before the step of searching for an approximate value in the compression lookup table based on the compression index corresponding to the significant digit to obtain the initial inverse square root approximate value corresponding to the significant digit, the method further includes: Generate the compressed index based on the continuous high-bit portion of the mantissa field corresponding to the intercepted significant number; Generate the initial inverse square root approximation corresponding to the compression index according to the high-order part; The compressed lookup table is generated based on the compressed index and the corresponding initial inverse square root approximation value.

6. The data output method based on fixed-point number square root according to claim 1, wherein: The step of performing iterative optimization, exponent parity adjustment, remainder feedback correction, and boundary specialization processing based on the reciprocal square root approximation corresponding to the valid digit to generate a valid result includes: Iteratively processing the reciprocal square root approximation value according to an iterative formula to generate an iterated reciprocal square root approximation value; performing bit weight compensation and remainder correction on the reciprocal square root approximation based on the parity of the double-precision exponent corresponding to the significant digit to generate a target reciprocal square root approximation; Based on a preset boundary specialization condition, the target inverse square root approximation value is subjected to boundary specialization processing to generate a valid result.

7. The data output method based on fixed-point number square root according to claim 1, wherein: The step of performing denormalization processing on the valid result, generating a fixed-point number corresponding to the valid result and outputting the same comprises: Calculating the valid results using an exponential formula to generate an exponential value of the valid results; Performing a direction-adaptive shift operation based on the exponential value of the valid result to obtain the fixed-point result after the denormalization processing; The sign bit is restored from the effective result to the highest bit of the fixed-point result, and a signed fixed-point number form is generated and output.

8. The data output method based on fixed-point number square root according to claim 7, characterized in that: The step of performing a direction-adaptive shift operation based on the exponential value of the valid result to obtain the fixed-point result after the denormalization processing includes: Calculating a displacement according to the exponent value of the valid result, the decimal width of the fixed-point number, and the exponent offset of the internal floating-point format; Based on the displacement amount, a direction-adaptive displacement operation is performed to adjust the effective result to generate the fixed-point result.

9. A fixed-point number square root device, characterized in that: The fixed-point number square root device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the data output method based on fixed-point number square root according to any one of claims 1 to 8.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the data output method based on fixed-point number square root according to any one of claims 1 to 8 are implemented.

Images