Dynamic reconfigurable chip configuration management structure for data cycle processing

Abstract

The invention discloses a dynamic reconfigurable chip configuration management structure oriented to data cycle processing. Automatic cycle configuration of a plurality of configuration indexes is supported. The configuration index can be operated according to a certain sequence rule in each cycle process; an end signal of the address generator integrated in the structure is used as a trigger signal of the next configuration, so that the automation of the configuration is realized; automatic link configuration among a plurality of configuration indexes is supported, and any specified configuration index can be automatically started after the current configuration index is executed. The method is suitable for the dynamic reconfigurable chip, especially for the dynamic reconfigurable chip in the field of data encryption and decryption and graphic image processing, and by means of the design, the function configuration time can be shortened, the complexity of function configuration management can be reduced, and the overall performance of the dynamic reconfigurable chip can be improved.

Description

Technical Field

[0001] The present invention relates to a configuration management structure for a dynamically reconfigurable chip, in particular to a configuration management structure which needs to cyclically configure chip structure and function, reduce configuration delay, and reduce external module intervention during encryption and decryption data calculations. Background Art

[0002] Dynamically reconfigurable chips have two key characteristics: first, the functional units of the chip are reconfigurable after manufacturing; second, they can map algorithms to the processing units within the chip. Unlike fine-grained reconfigurable processors like field-programmable gate arrays (FPGAs), dynamically reconfigurable chips utilize coarse-grained ALUs (arithmetic logic units) as processing units and a streamlined interconnect structure. Consequently, they offer significant advantages over FPGAs in terms of configuration information volume, configuration latency, and chip power consumption. Dynamically reconfigurable chips consist of a data path and a control path. The data path uses an array of processing units to perform calculations on data; the control path receives and caches configuration data, which is then transmitted to the data path by a configuration manager to complete the configuration of the data path. This process of transmitting configuration data to the data path is called configuration. The control path of current dynamically reconfigurable chips generally utilizes multiple configuration boards. Each board stores the configuration information required to reconfigure the processing unit's functionality, allowing for rapid switching of configuration information between boards. To distinguish these boards, they are numbered, and these numbered boards are called configuration indexes. The configuration manager is responsible for assigning different configuration indexes to the data path. Current research focuses on the design of configuration information and the pipeline configuration of dynamically reconfigurable chips in rows / columns on the time axis. The configuration manager, currently commonly performed by the processor, is responsible for configuring and controlling the dynamically reconfigurable chip.

[0003] In the paper "Research on Key Configuration Technologies for High Energy Efficiency in Coarse-Grained Dynamically Reconfigurable Processors," Wang Yansheng, Tsinghua University, 2014, the concept of iterative configuration is proposed. This paper considers the operation of a dynamically reconfigurable chip as a multi-iterative configuration process, dividing each iteration into three steps: inputting internal data, performing calculations on the processing unit array, and outputting internal data. These three steps are repeated to form the entire iterative configuration information. This configuration concept is essentially a first-in, first-out sequential configuration method, where the size of the iterative configuration information is proportional to the number of configurations. The paper only distributes the complete configuration information locally. Through hierarchical, row-based, and three-dimensional configuration techniques, the configuration delay is hidden within the runtime of the reconfigurable processing unit, reducing configuration latency.

[0004] Patent CN113129961B, "A Configuration Circuit for Local Dynamic Reconfiguration of a Cryptographic Logic Array," describes a configuration circuit comprising a register stack, a configuration parsing circuit, a reconfigurable computing unit, and a global configuration storage unit. The register stack stores configuration information, and the configuration parsing circuit parses the configuration information output by the register stack to generate a configuration signal, which is then sent to the reconfiguration computing unit. The global configuration storage unit stores non-real-time configuration index numbers and the configuration information to be reconfigured, and is responsible for generating the control signals required for dynamic reconfiguration.

[0005] Patent CN117201297A, "A fast and flexible slice-based dynamic reconstruction configuration system for CGRA", the configuration system is mainly a slice-based control unit, which is connected to each processing element (PE) unit in the chip architecture, provides address input for the configuration generator corresponding to the PE unit, and determines the functional switching of the PE unit in each business cycle through the input address. It can also configure the address of the configuration generator of the PE unit used for another business when performing business calculations.

[0006] In the patent "Hybrid and Efficient Approach to Accelerate Complicated Loopson CGRA Accelerators, publication number 20200133672, application number 16 / 172,254," a coarse-grained reconfigurable array includes a processing unit array, an instruction memory circuit, a data memory circuit, and an instruction fetch unit. The instruction fetch unit is coupled to the processing unit array and the instruction memory circuit and is configured to receive the conditional instruction execution result of a processing unit and output a corresponding instruction fetch signal based on the received execution result, thereby providing the instruction associated with the conditional instruction branch execution result to the corresponding processing unit.

[0007] Patent "Tightly Coupled Processor Arrays Using CGRA with Iteration LevelCommits, patent number10120685, Application number

[0008] 14 / 932,672, IBM” in which, to support the configuration management structure of the multiple iteration (SMI) design, the state signals of all processing units are connected to a load storage unit and a control unit. The load storage unit can track which compiled program code iterations have been completed, which are in progress, and which have not yet started; the control unit includes hardware structures for maintaining synchronization and starting and terminating the loops within the processing units. If instructions from multiple iterations are ready for execution, the hardware selects the instructions that are ready for execution, the lowest iteration number.

[0009] The design of the control path in the dynamically reconfigurable chip includes how to effectively organize the configuration information of the underlying hardware modules of the reconfigurable processor, and the design of the configuration management structure to reduce the number of times that the main controller in the system participates in configuration and support for mapping of tasks with high computational complexity to the reconfigurable processing units. Among them, the configuration management structure is increasingly important and gradually becomes the key to enabling the dynamically reconfigurable chip to dynamically reconfigure and adapt to complex task mapping.

[0010] Current research on the configuration management structure in the dynamically reconfigurable chip focuses on reducing configuration delay and achieving reading and caching of the next configuration information while computing. It does not focus on the fact that in the execution of data encryption and decryption algorithms and other data loop processing tasks, the data processing process often needs to be continuously looped for tens of times, and multiple configuration indexes need to be coordinated to complete one loop operation. The existing designs have four obvious shortcomings:

[0011] 1) Current research on the configuration management structure generally focuses on the fast switching of configuration functions and the mapping of conditional branch execution in the chip, and rarely focuses on simplifying loop configuration and shortening the delay of loop configuration.

[0012] 2) The configuration manager often uses a processor that needs to constantly determine whether the function of each configuration index is complete, which consumes a lot of query and processing time and reduces the performance of the chip.

[0013] 3) If the sequential configuration control mode is continued in the face of multiple loop configurations, the amount of configuration data will be very large.

[0014] 4) The configuration manager is not combined with loop data reading and writing, and a special circuit is needed to manage the configuration information of the loop data reading and writing addresses, increasing the complexity of the control path implementation. SUMMARY

[0015] The technical solution of the present application is: overcome the shortcomings of the prior art, and provide a dynamic reconfigurable chip configuration management structure for data loop processing, which replaces the traditional processor used for configuration management, simplifies configuration management, quickly completes the judgment and operation on the next configuration index, significantly shortens the reconfiguration time, and is suitable for data loop processing.

[0016] The technical solution of the present application is:

[0017] The dynamic reconfigurable chip configuration management structure for data loop processing comprises a loop configuration control unit, an address generator, a configuration index and an interface control unit.

[0018] The configuration index comprises a plurality of configuration data, the address generator is used for quickly generating loop data read / write addresses, and the interface control unit is responsible for setting the configuration index and internal registers of the loop configuration control unit.

[0019] The loop configuration control unit internally comprises two control registers and three state registers, uses combination logic to analyze and judge the control registers and the state registers, supports two modes of loop configuration and linked automatic configuration, and sends correct configuration commands to the configuration index in a single clock cycle; the configuration index receives the configuration commands, outputs correct configuration data to the address generator according to configuration index number information contained in the configuration commands, and configures the address generation rule of the address generator; and the address generator outputs address data as the read / write address of data in loop processing according to the configuration rule under the joint action of the configuration data and the configuration commands.

[0020] Further, the two control registers in the loop configuration control unit are a loop configuration control register and a configuration link control register; and the three state registers are an effective configuration index number register, a loop configuration number register and a to-be-configured index number register.

[0021] The input of the loop configuration control unit is an interface control signal provided by the interface control unit and an address generator end signal provided by the address generator, the loop configuration control unit uses combination logic to analyze and judge the control registers and the state registers, and outputs the configuration commands to the address generator and the configuration index in a single clock cycle.

[0022] Further, the input of the address generator is configuration data provided by the configuration commands and the configuration index, and the output is an address generator end signal and address data; the address generator is a timing logic unit, generates address information according to a setting rule, and the setting rule is derived from configuration data output by the configuration index and comprises an initial address, a step length and a step number.

[0023] The input configuration command is the start signal of the address generator, when the configuration command is valid, the address generator starts to generate and output address data according to the setting rule.

[0024] Further, the multiple configuration indexes, input as the interface control signal provided by the configuration command and the interface control unit, output the configuration data to the address generator; when the input configuration command is valid, the configuration data of a configuration index is selected from the multiple configuration indexes according to the configuration index number selection signal in the configuration command.

[0025] Further, the interface control signal output by the interface control unit is used for initializing and setting the loop configuration control unit and the multiple configuration indexes; the interface control signal is composed of 32-bit control data lines, 8-bit control address lines and a write signal.

[0026] Further, the configuration command includes a configuration command valid flag line and an N-bit configuration index number selection line; the configuration command valid flag line is set high, indicating that the configuration command is valid; if the configuration indexes have M in total, N=log2M;

[0027] The address generator end signal is set high, indicating that the address generator generates an address end;

[0028] The address data output by the address generator includes an address data valid flag line and bit address signal lines, and the address data valid flag line is set high to indicate that the address data is valid.

[0029] Further, the loop configuration control register includes three fields, namely a loop configuration times control field, a loop configuration start index number control field and a loop valid bit control field;

[0030] The loop valid bit control field defines whether the loop configuration function is valid, when the field is set to '1' and valid, the loop configuration function is valid, and a group of configuration indexes is allowed to configure the chip function multiple times according to a certain order;

[0031] The loop configuration start index number control field defines the start configuration index number of each loop, and specifies the start configuration index of the loop configuration; when a group of configuration indexes as the loop configuration completes the configuration of the chip function according to a certain order, the next loop configuration will start from the start configuration index number;

[0032] The loop configuration times control field defines the loop times of the configuration of the chip function by a group of configuration indexes as the loop configuration.

[0033] Furthermore, in the configuration link control register, each configuration index number corresponds to two fields, namely the automatic link enable control field and the automatic link index number control field; only when the automatic link enable control field is valid, after this configuration index function ends, in the configuration command issued by the cyclic configuration control unit, except for the configuration command valid flag line, the N-bit configuration index number selection line is consistent with the value of the automatic link index number control field.

[0034] Furthermore, the valid configuration index number register records the configuration index number of the address generator function currently being configured. The valid configuration index number register has an initial value of 0 after power-on reset.

[0035] The loop configuration times register records the number of loop configurations that have been completed. After power-on reset, the initial value of the loop configuration times register is 0;

[0036] The index number register to be configured records the configuration index number to be started next. The initial value of the index number register to be configured is 0 after power-on reset.

[0037] Furthermore, the loop configuration control unit uses combinational logic to analyze and judge the control register and status register, specifically:

[0038] (1) After power-on reset, initialize the index number register to be configured, and the initial value is 0;

[0039] (2) Output configuration command signal according to the index number register to be configured;

[0040] (3) Determine whether the address end signal input by the loop configuration control unit is at a high level. If it is at a high level, execute step (4); if it is at a low level, continue the loop determination at this step;

[0041] (4) Determine whether the automatic link enable field corresponding to the current configuration index in the configuration link control register is valid. If valid, jump to step (7); if invalid, execute step (5);

[0042] (5) The loop configuration value recorded in the loop configuration times register is increased by 1;

[0043] (6) Determine whether the loop configuration times register is equal to the loop configuration times field setting value. If they are equal, the configuration management function ends; if they are not equal, jump to step (8);

[0044] (7) Update the index number register to be configured according to the value in the automatic link index number control field, and jump to step (2);

[0045] (8) Update the index number register to be configured according to the value in the loop configuration start index number control field, and jump to step (2).

[0046] Furthermore, the loop configuration refers to: according to the definition of the loop configuration control register, a set of configuration indexes, each configuration index can configure the function of the chip, this set of configuration indexes configures the chip in sequence, and the chip completes data processing according to the configured functions. When all the configuration indexes are configured, the configuration indexes will be executed again from the loop configuration starting index number. This set of configuration indexes will continue to loop until the number of loop executions reaches the loop configuration number requirement;

[0047] The automatic link configuration means that according to the definition of the configuration link control register, when the configuration index configures the chip function, the chip executes data processing according to the configured function until the data execution is completed and the configuration function corresponding to the current configuration index number ends. At this time, the configuration index number corresponding to the next configuration function that the chip needs to start is no longer necessarily in a sequential relationship with the current configuration index number that completed the configuration function. Instead, it is directly specified by the current configuration index number through the control register. Through this configuration order specification relationship, multiple configuration indexes can be linked to form a configuration order in any order.

[0048] The beneficial effects of the present invention compared with the prior art are:

[0049] (1) The configuration management structure of the present invention is completely implemented by dedicated hardware circuits. Compared with the traditional method of using a processor to complete the configuration management function, the processor does not need to constantly query the control path status and then run the program to perform configuration management, which can significantly shorten the dynamic configuration time;

[0050] (2) The configuration management structure of the present invention supports loop configuration between two configuration indexes, linked automatic configuration of multiple configuration indexes, and a combination of these two configuration modes. The combination of the two configuration modes is similar to a for loop. The loop condition of the for loop is determined by the loop configuration, defining the number of times the loop configuration is repeated; the loop body of the for loop is determined by the linked automatic configuration, defining which configuration indexes are executed in sequence for each loop configuration. This design can significantly simplify configuration management and meet the needs of complex computing tasks in data loop processing.

[0051] (3) The configuration management structure of the present invention integrates an address generator and uses the address end signal of the address generator as a trigger signal for the loop configuration control unit to analyze and judge. Instead of using the signal output by the processing unit array in the data path as the trigger signal for the loop configuration control unit to analyze and judge, the configuration management structure is fully functional and is particularly suitable for a configuration structure for data loop processing.

[0052] (4) The configuration management structure of the present invention can be integrated with each reconstruction unit in the dynamically reconfigurable chip and is responsible for the management of the configuration data of a single reconstruction unit; the cyclic configuration control unit in the configuration management structure can also be integrated outside the reconstruction unit array to perform configuration management on the reconstruction unit array in the dynamically reconfigurable chip separately. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 This is a diagram of the configuration management structure;

[0054] Figure 2 Schematic diagram of the structure of the loop configuration control register 200;

[0055] Figure 3 Schematic diagram of the link control register with two configuration indexes;

[0056] Figure 4 This is a functional flow chart of the combinational logic unit in the loop configuration control unit 101. DETAILED DESCRIPTION

[0057] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0058] The dynamic reconfigurable chip control structure designed by the present invention is a dedicated hardware circuit that supports automatic cyclic configuration management of multiple configuration indexes, and supports running the configuration index according to a certain order rule during each cycle. The control structure includes an address generator, a configuration index and a cyclic configuration control module, which adapts to the requirements for different data read and write addresses during the data cyclic processing. This control structure replaces the traditional processor used for configuration management, simplifies configuration management, quickly completes the judgment and operation of the next configuration index, and significantly shortens the reconfiguration time; this control structure, combined with the address generator, directly realizes the requirements for different data read and write addresses during the cyclic process, and can quickly start the next configuration index and generate a new address at the same time after the address generator finishes generating the address. This method of using the address generator state as a trigger for configuration index transformation is suitable for cyclic processing of data.

[0059] The present invention implements a configuration manager using a dedicated hardware circuit. The structure includes multiple configuration indexes that store configuration information, an address generator capable of rapidly generating cyclic data read and write addresses, a cyclic configuration control unit suitable for data cyclic processing, and an interface control unit responsible for configuring the configuration indexes and internal registers of the cyclic configuration control unit. The cyclic configuration control unit internally contains two control registers: a cyclic configuration control register and a configuration link control register (which automatically activates the next configuration index after the current configuration index function ends); and three status registers: a valid configuration index number register, a cyclic configuration count register, and a pending configuration index number register. Combinatorial logic is used to analyze and determine the control registers and status registers, supporting both cyclic configuration and link automatic configuration modes, and issuing the correct configuration command to the configuration index within a single clock cycle. Upon receiving the configuration command, the configuration index outputs the correct configuration data to the address generator based on the configuration index number information contained in the configuration command, thereby configuring the address generator's address generation rules. Under the combined action of the re-entered configuration data and the configuration command, the address generator outputs an address according to a certain rule, which serves as the read and write address for the data in the cyclic processing.

[0060] Configuration management structure such as Figure 1 shown. Figure 1 It mainly includes a loop configuration control unit 101, an address generator 102, a configuration index 103, and an interface control unit 104.

[0061] The configuration index 103 contains multiple configuration data, the address generator 102 is used to quickly generate the cyclic data read and write address, and the interface control unit 104 is responsible for setting the configuration index 103 and the internal register of the cyclic configuration control unit 101;

[0062] The loop configuration control unit 101 internally contains two control registers and three status registers, and uses combinational logic to analyze and judge the control registers and status registers. It supports two modes: loop configuration and link automatic configuration, and issues the correct configuration command to the configuration index 103 within a single clock cycle; the configuration index 103 receives the configuration command and outputs the correct configuration data to the address generator 102 based on the configuration index number information contained in the configuration command, and configures the address generation rules of the address generator 102; under the joint action of the configuration data and the configuration command, the address generator 102 outputs the address data according to the configuration rules as the read and write address of the data in the loop processing.

[0063] The loop configuration control unit 101 takes as input the interface control signal 105 and the address generator end signal 108, and outputs the configuration command 106. The unit contains two control registers: loop configuration control register 200 and configuration link control register 210; three status registers: valid configuration index number register 220, loop configuration count register 230, and pending configuration index number register 240; it uses combinational logic, and the logic function flow chart is as follows: Figure 4 As shown, the control register and the status register are analyzed and judged, and a configuration command 106 is issued to the configuration index 103 and the address generator 102 within a single clock cycle.

[0064] Address generator 102 receives configuration command 106 and configuration data 107 as inputs, and outputs address generator end signal 108 and address data 109. The address generator is a sequential logic unit that generates address information according to certain rules. These rules include settings such as the initial address, step size, and number of steps. These settings are derived from configuration data 107 output by configuration index 103. Input configuration command 106 serves as the start signal for the address generator. When configuration command 106 is valid, the address generator begins generating and outputting address data 109 according to the set rules.

[0065] Multiple configuration indexes 103 are input as interface control signals 105 and configuration commands 106, and are output as configuration data 107. When the input configuration command 106 is valid, a signal is selected according to the configuration index number in the configuration command to select and output configuration data 107 of a configuration index from the multiple configuration indexes.

[0066] The interface control signal 105 output by the interface control unit 104 is used to initialize the loop configuration control unit 101 and the multiple configuration indexes 103; the interface control signal 105 consists of a 32-bit control data line, an 8-bit control address line and a write signal.

[0067] The interface control signal 105 is output by the interface control unit 104 and consists of a 32-bit control data line, an 8-bit control address line and a write signal.

[0068] The configuration command 106 is output by the cyclic configuration control unit 101 and consists of a configuration command valid flag line (this signal line is set high to indicate that the configuration command is valid) and an N-bit configuration index number selection line (if there are 8 configuration indexes, then N is 3; if there are 16 configuration indexes, then N is 4; that is, if there are M configuration indexes, then N = log2M).

[0069] Configuration data 107 is output by configuration index 103 and includes information such as initial address, step length, and number of steps.

[0070] The address generator end signal 108 is output by the address generator 102. This signal line is set high, indicating that the address generator has finished generating the address.

[0071] The address data 109 is output by the address generator 102 and is composed of a 32-bit address signal line and a valid address flag line. This signal line is set high to indicate that the address data is valid.

[0072] The loop configuration control register 200 is an internal control register of the loop configuration control unit 101 and is composed of three fields, such as Figure 2 As shown, they are the loop configuration times control field 201, the loop configuration start index number control field 202, and the loop valid bit control field 203.

[0073] The configuration link control register 210 is an internal control register of the cyclic configuration control unit 101 and is composed of multiple fields. Each configuration index number corresponds to two fields, namely, an automatic link enable control field and an automatic link index number control field. Figure 3 The figure shows two link control registers for configuration indexes, namely, the index number control field 211 for automatic linking of configuration index 0, the automatic link enable control field 212 for configuration index 0, the configuration index number control field 213 for automatic linking of configuration index 1, and the automatic link enable control field 214 for configuration index 1. Only when the automatic link enable control field is valid, after the configuration index function is completed, in the configuration command issued by the cyclic configuration control unit 101, the N-bit configuration index number selection line, excluding the configuration command valid flag line, will be consistent with the value of the automatic link index number control field.

[0074] The valid configuration index number register 220 records the configuration index number of the address generator function currently being configured. It is an internal status register of the cyclic configuration control unit 101. After power-on reset, the initial value of this status register is 0.

[0075] The loop configuration times register 230 records the completed loop configuration times and is an internal status register of the loop configuration control unit 101. The initial value of this status register is 0 after power-on reset.

[0076] The to-be-configured index number register 240 records the configuration index number to be started next and is an internal status register of the cyclic configuration control unit 101. The initial value of this status register is 0 after power-on reset.

[0077] Figure 4This is a functional flow chart of the combinational logic unit in the loop configuration control unit 101. The control register and status register inside the unit are analyzed, and combined with the input address end signal 108, a logical judgment is completed according to the process in the figure to determine the configuration index number to be configured next and output it through the configuration command 106. In the flow chart,

[0078] (41) After power-on reset, initialize the index number register 240 to be configured, and the initial value is 0;

[0079] (42) Outputting a configuration command signal 106 according to the to-be-configured index number register 240;

[0080] (43) Determine whether the address end signal 108 input by the loop configuration control unit is at a high level. If it is at a high level, execute step (44); if it is at a low level, continue the loop determination at this step;

[0081] (44) Determine whether the automatic link enable field corresponding to the current configuration index in the configuration link control register 210 is valid. If valid, jump to step (47); if not, execute step (45);

[0082] (45) The loop configuration value recorded in the loop configuration times register 230 + 1;

[0083] (46) Determine whether the loop configuration times register 230 is equal to the value set in the loop configuration times field 201. If they are equal, the configuration management function ends; if they are not equal, jump to step (48);

[0084] (47) Update the to-be-configured index number register 240 according to the value in the automatic link index number control field, and jump to step (42);

[0085] (48) Update the index number register to be configured 240 according to the value in the loop configuration start index number control field 202, and jump to step (42).

[0086] Parts of the present invention that are not described in detail belong to common knowledge among those skilled in the art.

Claims

1. A dynamic reconfigurable chip configuration management structure for data cycle processing, characterized by include: Looping through a configuration control unit (101), an address generator (102), a configuration index (103), and an interface control unit (104); The configuration index (103) includes a plurality of configuration data, the address generator (102) is used to quickly generate a cyclic data read and write address, and the interface control unit (104) is responsible for setting the configuration index (103) and the internal register of the cyclic configuration control unit (101); The loop configuration control unit (101) internally contains two control registers and three status registers, adopts combinational logic to analyze and judge the control registers and status registers, supports two modes of loop configuration and link automatic configuration, and sends a correct configuration command to the configuration index (103) within a single clock cycle; the configuration index (103) receives the configuration command, outputs the correct configuration data to the address generator (102) according to the configuration index number information contained in the configuration command, and configures the address generation rule of the address generator (102); under the joint action of the configuration data and the configuration command, the address generator (102) outputs the address data according to the configuration rule as the read and write address of the data in the loop processing.

2. The dynamic reconfigurable chip configuration management structure for data cycle processing according to claim 1, characterized in that: The two control registers inside the loop configuration control unit (101) are: a loop configuration control register (200) and a configuration link control register (210); the three status registers are: a valid configuration index number register (220), a loop configuration times register (230) and a to-be-configured index number register (240); The inputs of the loop configuration control unit (101) are an interface control signal (105) provided by the interface control unit (104) and an address generator end signal (108) provided by the address generator (102). The loop configuration control unit (101) uses combinational logic to analyze and judge the control register and the status register, and outputs a configuration command (106) to the address generator (102) and a configuration index (103) within a single clock cycle.

3. The dynamic reconfigurable chip configuration management structure for data cycle processing according to claim 1, characterized in that: The input of the address generator (102) is the configuration command (106) and the configuration data (107) provided by the configuration index (103), and the output is the address generator end signal (108) and the address data (109); the address generator is a sequential logic unit that generates address information according to a setting rule, wherein the setting rule is derived from the configuration data (107) output by the configuration index (103), including an initial address, a step length, and a number of steps; The input configuration command (106) is a start signal for the address generator. When the configuration command (106) is valid, the address generator (102) starts to generate and output address data (109) according to the setting rules.

4. The dynamic reconfigurable chip configuration management structure for data cycle processing according to claim 1, characterized in that: A plurality of configuration indexes (103) are input as a configuration command (106) and an interface control signal (105) provided by an interface control unit (104), and configuration data (107) are output to an address generator (102); when the input configuration command (106) is valid, a configuration index number selection signal in the configuration command is selected and configuration data (107) of a configuration index is selected and output from the plurality of configuration indexes.

5. The dynamic reconfigurable chip configuration management structure for data cycle processing according to claim 1, characterized in that: The interface control signal (105) output by the interface control unit (104) is used to initialize the loop configuration control unit (101) and multiple configuration indexes (103); the interface control signal (105) is composed of a 32-bit control data line, an 8-bit control address line and a write signal.

6. The dynamic reconfigurable chip configuration management structure for data cycle processing according to claim 2, characterized in that: The configuration command (106) includes a configuration command valid flag line and an N-bit configuration index number selection line; the configuration command valid flag line is set high, indicating that the configuration command is valid; if there are M configuration indexes in total, then N=log2M; The address generator end signal (108) is set high, indicating that the address generator has finished generating the address; The address data (109) is output by the address generator (102), and comprises an address data valid flag line and a 32-bit address signal line. When the address data valid flag line is set high, it indicates that the address data is valid.

7. The dynamic reconfigurable chip configuration management structure for data cycle processing according to claim 2, characterized in that: The loop configuration control register (200) includes three fields, namely a loop configuration times control field (201), a loop configuration start index number control field (202) and a loop valid bit control field (203); The loop valid bit control field (203) defines whether the loop configuration function is valid. When this field is set to '1', the loop configuration function is valid, allowing a group of configuration indexes to configure the chip function multiple times according to a certain order rule; The loop configuration start index number control field (202) defines the start configuration index number of each loop, specifies the start configuration index of the loop configuration, and when a group of configuration indexes as the loop configuration completes the chip function configuration according to a certain sequence rule, the next loop configuration will be restarted from the start configuration index number; The loop configuration times control field (201) defines the loop times for configuring chip functions using a set of configuration indexes as loop configuration.

8. The dynamic reconfigurable chip configuration management structure for data cycle processing according to claim 6, characterized in that: In the configuration link control register (210), each configuration index number corresponds to two fields, namely, an automatic link enable control field and an automatic link index number control field; only when the automatic link enable control field is valid, after the configuration index function is completed, in the configuration command issued by the cyclic configuration control unit (101), in addition to the configuration command valid flag line, the N-bit configuration index number selection line is consistent with the value of the automatic link index number control field.

9. The dynamic reconfigurable chip configuration management structure for data cycle processing according to claim 2, characterized in that: An effective configuration index number register (220) records the configuration index number of the address generator function currently being configured. After power-on reset, the effective configuration index number register (220) has an initial value of 0; A loop configuration times register (230) records the number of loop configurations that have been completed. After power-on reset, the loop configuration times register (230) has an initial value of 0; The index number register to be configured (240) records the configuration index number to be started next. After power-on reset, the initial value of the index number register to be configured (240) is 0.

10. The dynamic reconfigurable chip configuration management structure for data cycle processing according to claim 2, characterized in that: The loop configuration control unit (101) uses combinational logic to analyze and judge the control register and the status register, specifically: (1) After power-on reset, initialize the index number register to be configured (240) with an initial value of 0; (2) outputting a configuration command signal (106) according to the index number register to be configured (240); (3) Determine whether the address end signal (108) input by the loop configuration control unit is at a high level. If it is at a high level, execute step (4); if it is at a low level, continue the loop determination at this step; (4) determining whether the automatic link enable field corresponding to the current configuration index in the configuration link control register (210) is valid; if valid, skipping to step (7); if invalid, executing step (5); (5) The loop configuration value recorded in the loop configuration times register (230) is increased by 1; (6) Determine whether the loop configuration times register (230) is equal to the value set in the loop configuration times field (201). If they are equal, the configuration management function ends; if they are not equal, jump to step (8); (7) Update the to-be-configured index number register (240) according to the value in the automatic link index number control field, and jump to step (2); (8) Update the index number register to be configured (240) according to the value in the loop configuration start index number control field (202), and jump to step (2).

11. The dynamic reconfigurable chip configuration management structure for data cycle processing according to claim 2, characterized in that: The loop configuration means: according to the definition of the loop configuration control register, a set of configuration indexes, each configuration index can configure the function of the chip, this set of configuration indexes configures the chip in sequence, and the chip completes data processing according to the configured functions. When all the configuration indexes are configured, the configuration indexes will be executed again from the loop configuration starting index number. This set of configuration indexes will continue to loop until the number of loop executions reaches the loop configuration number requirement; The automatic link configuration means that according to the definition of the configuration link control register, when the configuration index configures the chip function, the chip executes data processing according to the configured function until the data execution is completed and the configuration function corresponding to the current configuration index number ends. At this time, the configuration index number corresponding to the next configuration function that the chip needs to start is no longer necessarily in a sequential relationship with the current configuration index number that completed the configuration function. Instead, it is directly specified by the current configuration index number through the control register. Through this configuration order specification relationship, multiple configuration indexes can be linked to form a configuration order in any order.

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