Memory access method and device, electronic equipment and storage medium

Abstract

The invention discloses a memory access method and device, electronic equipment and a storage medium. The memory comprises a plurality of memory channels, the plurality of memory channels comprise N memory channels to be accessed, and N is an integer greater than 1. The memory access method comprises the steps that a first address field in a system memory address is selected, and each memory channel corresponds to at least one value of the first address field; based on the number N of the memory channels to be accessed, first address processing is carried out on the first address field to obtain a target address field, and the target address field comprises N first values; and accessing the N memory channels to be accessed based on the N first values. According to the memory access method, the number of the memory channels to be accessed can be flexibly adjusted, so that the chip design can be flexibly compatible with multiple memory channel numbers, the flexibility of the chip design is improved, unnecessary cost waste is reduced, and the memory access method has relatively high practical value.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory access method and device, an electronic device, and a storage medium. Background Art

[0002] With the widespread adoption of technologies like artificial intelligence (AI), the computing power of processors and chips continues to increase, raising the demand for memory access bandwidth. In systems on a chip (SoC), multi-channel memory control technology can be used for memory access, effectively increasing total memory bandwidth to meet the data transmission and processing needs of high-speed processors. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a memory access method, wherein the multiple memory channels include N memory channels to be accessed, wherein N is an integer greater than 1, and the memory access method includes: selecting a first address segment in a system memory address, wherein each memory channel in the multiple memory channels corresponds to at least one value of the first address segment; based on the number N of the memory channels to be accessed, performing first address processing on the first address segment to obtain a target address segment, wherein the target address segment includes N first values; and accessing the N memory channels to be accessed based on the N first values.

[0004] At least one embodiment of the present disclosure further provides a memory access device, wherein the memory corresponds to multiple memory channels, and the multiple memory channels include N memory channels to be accessed, wherein N is an integer greater than 1, and the memory access device includes: a first selection module, configured to select a first address segment in a system memory address, wherein each memory channel in the multiple memory channels corresponds to at least one value of the first address segment; an address processing module, configured to perform first address processing on the first address segment based on the number N of memory channels to be accessed to obtain a target address segment, wherein the target address segment includes N first values; and an access module, configured to access the N memory channels to be accessed based on the N first values.

[0005] At least one embodiment of the present disclosure further provides an electronic device. The electronic device includes: a processor; and a memory including one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules are used to implement the memory access method provided in any embodiment of the present disclosure.

[0006] The memory access method provided in any one of the embodiments of the present disclosure can be implemented by a computer directly reading the computer program in a tangible storage medium, or by a computer readable program code in a tangible storage medium. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only related to some embodiments of the present disclosure, and not limit the present disclosure.

[0008] Figure 1 A schematic diagram of memory access of a system on chip;

[0009] Figure 2 An exemplary flowchart of the memory access method provided in at least one of the embodiments of the present disclosure;

[0010] Figure 3A A schematic diagram of one example of the first address segment provided in at least one of the embodiments of the present disclosure;

[0011] Figure 3B A schematic diagram of another example of the first address segment provided in at least one of the embodiments of the present disclosure;

[0012] Figure 4 A schematic diagram of one example of the memory access method provided in at least one of the embodiments of the present disclosure;

[0013] Figure 5 A schematic diagram of one example of the first address processing and the second address processing provided in at least one of the embodiments of the present disclosure;

[0014] Figure 6 Another exemplary flowchart of the memory access method provided in at least one of the embodiments of the present disclosure;

[0015] Figure 7 A schematic diagram of another example of the memory access method provided in at least one of the embodiments of the present disclosure;

[0016] Figure 8A A schematic diagram of yet another example of the memory access method provided in at least one of the embodiments of the present disclosure;

[0017] Figure 8B A schematic diagram of still another example of the memory access method provided in at least one of the embodiments of the present disclosure;

[0018] Figure 9 A schematic block diagram of a memory access device provided in at least one of the embodiments of the present disclosure;

[0019] Figure 10A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure;

[0020] Figure 11 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure; and

[0021] Figure 12 A schematic diagram of a storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0023] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0024] The present disclosure is described below using several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numeral in each drawing.

[0025] For capacity and bandwidth considerations, systems on a chip (SoC) typically have multiple memory channels. Each memory channel has a fixed physical address space and independently limited available bandwidth. If the SoC's master wishes to simultaneously access the combined available bandwidth of multiple memory channels, it must interleave access to each memory channel. This access method is known as memory interleaving.

[0026] With the development of high-speed chips such as CPUs, NPUs, GPUs, and video processors, the demand for memory access bandwidth is increasing, and the use of double-data-rate synchronous dynamic random access memory (DDR SDRAM) is becoming increasingly widespread. DDR is equipped with multi-channel memory control technology, and each DDR channel can independently transmit data. Each DDR channel can correspond to one or more dynamic random access memories (DRAM). DDR's multi-channel memory control technology effectively increases the total memory bandwidth, thereby meeting the data transmission and processing needs of high-speed processors.

[0027] Figure 1 A schematic diagram of memory access in a system on a chip.

[0028] For example, Figure 1 As shown, there are multiple hosts in the SoC subsystem (host 1, host 2...host X, where X is a positive integer), and each host accesses the memory through the on-chip bus (Fabric). For example, the memory includes multiple memory units (memory unit 1, memory unit 2...memory unit Y, where Y is a positive integer). In some examples, each memory unit can be DDR DRAM, etc. Since data is stored in different memory units, the host can interleave access to multiple memory channels (memory channel 1, memory channel 2...memory channel Y) according to a specific interleaving granularity (256B, 512B, 1KB, 2KB, etc.) to interleave access to data in each memory unit, thereby improving the total bandwidth of memory access.

[0029] For example, memory interleaving methods use fixed address bits to select memory channels (e.g., DDR channels). Depending on the number of memory channels to be interleaved, multiple bits are used for memory channel selection; each bit can take two values ​​(e.g., 0 or 1) and can be used to determine which of the two memory channels is selected. For example, two memory channels typically use a single address bit as the channel selection bit, while four memory channels typically use a two-bit address bit as the channel selection bit, and so on.

[0030] In order to fully utilize the state corresponding to each bit address bit, so as to balance the access to each memory channel, when a fixed number of bit address bits are selected, the number of memory channels is restricted. For example, if 1 bit address bit is selected, the number of memory channels is limited to 2; if 2 bit address bits are selected, the number of memory channels is limited to 4; if 3 bit address bits are selected, the number of memory channels is limited to 8. As can be seen, the fixed number of bit address bits limits the number of memory channels used for memory interleaving to 2n.

[0031] In the design of a chip, under the condition of meeting the bandwidth and capacity requirements, it is necessary to avoid redundant memory channels as much as possible. However, when using the memory interleaving method, the number of memory channels is limited to 2n, resulting in the memory channels required to exceed the bandwidth, causing waste of cost resources.

[0032] On the one hand, in the actual design and manufacture of a chip (for example, a SoC), the power consumption and cost of the chip are strongly related to the number of memory channels. The increase of the number of memory channels will bring a large area overhead and an overhead of chip pad IO, reduce the chip yield, increase the chip power consumption, and increase the design difficulty of the back end, packaging, board level, etc.

[0033] On the other hand, the bandwidth requirement of the memory channel is not necessarily 2n, and forcibly supplementing the number of memory channels will also cause resource waste. For example, when the number of memory channels required is small, such as only 3 memory channels are required, increasing one memory channel can meet the requirement of 2n, which is still within an acceptable range. When the required bandwidth is slightly higher than 4 or 8 memory channels, the number of memory channels needs to be doubled to 8 or even 16 to meet the requirement of 2n, resulting in redundancy of memory channels.

[0034] In addition, the memory interleaving limits the number of memory channels to 2n, which limits the chip grouping (binning) strategy in many aspects such as chip testing and application.

[0035] For example, in one case, the chip will be binned after the chip is manufactured; for the chip with non-fatal defects, part of the functions will be cut accordingly for use. When the manufacturing defects cause part of the memory channels to be unavailable, due to the fixed interleaving relationship between multiple memory channels, if the available memory channels in the chip are not 2n, the chip cannot normally interleave access to the memory, and the chip will be classified as a scrap chip, resulting in waste of cost resources.

[0036] For example, in another case, during the binning process of the chip, when a manufacturing defect causes part of the master on the chip to be unavailable, the chip can still be used after being functionally trimmed, but the bandwidth demand of the memory of the trimmed chip will decrease accordingly; if the original number of memory channels is continued to be used, it will also cause waste of cost and power consumption. For example, the chip has 4 memory channels, and after binning, some chips only need 3 memory channels to meet the demand; and the memory interleaving limits the number of memory channels to 4, causing a waste of 1 extra memory channel resource.

[0037] At least one embodiment of the present disclosure provides a memory access method, wherein the memory corresponds to a plurality of memory channels, and the plurality of memory channels includes N memory channels to be accessed, where N is an integer greater than 1. The memory access method includes: selecting a first address segment in a system memory address, wherein each memory channel corresponds to at least one value of the first address segment; performing first address processing on the first address segment based on the number N of memory channels to be accessed, to obtain a target address segment, wherein the target address segment includes N first values; and accessing the N memory channels to be accessed based on the N first values.

[0038] At least one embodiment of the present disclosure also provides a memory access device, an electronic device and a storage medium for implementing the memory access method of the above-mentioned embodiments.

[0039] The method, device, electronic device and storage medium provided by at least one embodiment of the present disclosure can flexibly adjust the number of memory channels to be accessed by performing first address processing on a first address segment in a system memory address to obtain a target address segment and accessing a specific number of memory channels based on the first values of the target address segment, so that the chip design can be flexibly compatible with multiple numbers of memory channels, improving the flexibility of chip design and reducing unnecessary cost waste, and having high practical value.

[0040] In the following, at least one embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements that have been described.

[0041] In at least one embodiment of the present disclosure, the memory corresponds to a plurality of memory channels, and the plurality of memory channels includes N memory channels to be accessed, where N is an integer greater than 1. In some examples, N is not a power of 2. For example, the memory can include a plurality of memory units, each of which can be a DDR DRAM or the like, and the memory channel can be a DDR channel or the like, or other types of memory units and memory channels can be selected according to actual needs, and the embodiments of the present disclosure do not limit this.

[0042] Figure 2An exemplary flowchart of a memory access method provided for at least one embodiment of the present disclosure.

[0043] For example, Figure 2 As shown, the memory access method may include the following steps S110 to S130.

[0044] Step S110: selecting the first address segment in the system memory address;

[0045] Step S120: performing first address processing on the first address segment based on the number N of memory channels to be accessed to obtain a target address segment;

[0046] Step S130: Based on the N first values, access N memory channels to be accessed.

[0047] For example, in step S110, the system memory address is used to access multiple memory channels. The selected first address segment includes at least one address bit, and each address bit (e.g., each bit) corresponds to two values ​​(e.g., 0 or 1). When the first address segment includes n address bits (e.g., n bits), then the address corresponds to a power of 2. For example, each memory channel corresponds to one or more values ​​of the first address segment, that is, the value of the first address segment can be used to access the corresponding memory channel.

[0048] For example, in step S120, the number N of memory channels to be accessed does not necessarily satisfy the n-th power of 2 (for example, N may not be the n-th power of 2). After performing the first address processing on the first address segment, the obtained target address segment includes N first values, that is, the number N of first values ​​included in the target address segment is the same as the number N of memory channels to be accessed.

[0049] For example, in step S130 , since the number N of first values ​​included in the target address segment is the same as the number N of memory channels to be accessed, the N memory channels to be accessed can be accessed based on the N first values.

[0050] In some examples, the first address segment includes the n1th address bit to the n2th address bit of the system memory address, where n2 is an integer greater than 1, n1 is an integer greater than 1 and less than n2, and the bit width of the first address segment, n2-n1+1, is greater than log2N. For example, the bit width of the first address segment can be selected based on actual needs, as long as it is greater than log2N, and embodiments of the present disclosure are not limited thereto.

[0051] Figure 3A A schematic diagram of an example of a first address segment provided in at least one embodiment of the present disclosure; Figure 3B A schematic diagram of another example of a first address segment provided in at least one embodiment of the present disclosure. For example, Figure 3Aand Figure 3B for Figure 2 Two specific examples of the first address segment are provided in .

[0052] For example, Figure 3A As shown, the 8th to 9th address bits of the system memory address are selected as the first address segment addr_in[9:8]. Since the bit width of the first address segment is 9-8+1=2, that is, the first address segment contains 2 address bits (for example, 2 bits), at this time, the first address segment includes 4 values, namely 00, 01, 10 and 11.

[0053] For example, Figure 3A As shown, memory channel 1 corresponds to the first address segment value 00, memory channel 2 corresponds to the first address segment value 01, memory channel 3 corresponds to the first address segment value 10, and memory channel 4 corresponds to the first address segment value 11. For example, the on-chip bus can allocate access requests to corresponding memory channels based on the value of the first address segment.

[0054] For example, Figure 3B As shown, the 8th to 10th address bits of the system memory address are selected as the first address segment addr_in[10:8]. Since the bit width of the first address segment is 10-8+1=3, that is, the first address segment contains 3 address bits (for example, 3 bits), at this time, the first address segment includes 8 values, namely 000, 001, 010, 011, 100, 101, 110 and 111.

[0055] For example, Figure 3B As shown, memory channel 1 corresponds to the first address segment values ​​000 and 100, memory channel 2 corresponds to the first address segment values ​​001 and 101, memory channel 3 corresponds to the first address segment values ​​010 and 110, and memory channel 4 corresponds to the first address segment values ​​011 and 111. For example, the on-chip bus can allocate access requests to corresponding memory channels based on the value of the first address segment.

[0056] In some examples, Figure 2 The step S120 may further include a step S121.

[0057] Step S121: taking the remainder of the first address segment and the number N of memory channels to be accessed to obtain a target address segment.

[0058] For example, in step S121, the first address segment is represented as addr_in[n2:n1], and the target address segment Address_M[n2-n1:0]=addr_in[n2:n1]%N, where % represents a modulo operator.

[0059] It should be noted that, in addition to the remainder operation in step S121, the first address processing can also select other processing modes according to actual needs, and embodiments of the present disclosure do not limit this.

[0060] Figure 4 A schematic diagram of one example of the memory access method provided by at least one embodiment of the present disclosure is shown in FIG. 1. Figure 4 For example, as shown in FIG. 1, the first address segment in the memory access request is addr_in[9:8], and the memory corresponds to four memory channels (i.e., memory channel 1, memory channel 2, memory channel 3, and memory channel 4). If the number of memory channels to be accessed is 3, that is, the number N of memory channels to be accessed does not satisfy 2 raised to the power of n, the step S120 of performing first address processing on the first address segment addr_in[9:8] based on the number N of memory channels to be accessed (here N = 3) is required to obtain the target address segment Address_M[1:0]. Figure 2 One specific example of steps S120-S130 is provided.

[0061] For example, as shown in FIG. 1, the first address segment in the memory access request is addr_in[9:8], and the memory corresponds to four memory channels (i.e., memory channel 1, memory channel 2, memory channel 3, and memory channel 4). If the number of memory channels to be accessed is 3, that is, the number N of memory channels to be accessed does not satisfy 2 raised to the power of n, the step S120 of performing first address processing on the first address segment addr_in[9:8] based on the number N of memory channels to be accessed (here N = 3) is required to obtain the target address segment Address_M[1:0]. Figure 4 Figure 3A For example, as shown in FIG. 1, the first address segment in the memory access request is addr_in[9:8], and the memory corresponds to four memory channels (i.e., memory channel 1, memory channel 2, memory channel 3, and memory channel 4). If the number of memory channels to be accessed is 3, that is, the number N of memory channels to be accessed does not satisfy 2 raised to the power of n, the step S120 of performing first address processing on the first address segment addr_in[9:8] based on the number N of memory channels to be accessed (here N = 3) is required to obtain the target address segment Address_M[1:0]. Figure 2 For example, as shown in FIG. 1, the first address segment in the memory access request is addr_in[9:8], and the memory corresponds to four memory channels (i.e., memory channel 1, memory channel 2, memory channel 3, and memory channel 4). If the number of memory channels to be accessed is 3, that is, the number N of memory channels to be accessed does not satisfy 2 raised to the power of n, the step S120 of performing first address processing on the first address segment addr_in[9:8] based on the number N of memory channels to be accessed (here N = 3) is required to obtain the target address segment Address_M[1:0].

[0062] Figure 4 For example, as shown in FIG. 1, the first address segment in the memory access request is addr_in[9:8], and the memory corresponds to four memory channels (i.e., memory channel 1, memory channel 2, memory channel 3, and memory channel 4). If the number of memory channels to be accessed is 3, that is, the number N of memory channels to be accessed does not satisfy 2 raised to the power of n, the step S120 of performing first address processing on the first address segment addr_in[9:8] based on the number N of memory channels to be accessed (here N = 3) is required to obtain the target address segment Address_M[1:0]. Figure 2 For example, as shown in FIG. 1, the first address segment in the memory access request is addr_in[9:8], and the memory corresponds to four memory channels (i.e., memory channel 1, memory channel 2, memory channel 3, and memory channel 4). If the number of memory channels to be accessed is 3, that is, the number N of memory channels to be accessed does not satisfy 2 raised to the power of n, the step S120 of performing first address processing on the first address segment addr_in[9:8] based on the number N of memory channels to be accessed (here N = 3) is required to obtain the target address segment Address_M[1:0].

[0063] Figures 3A to 4 For example, as shown in FIG. 1, the first address segment in the memory access request is addr_in[9:8], and the memory corresponds to four memory channels (i.e., memory channel 1, memory channel 2, memory channel 3, and memory channel 4). If the number of memory channels to be accessed is 3, that is, the number N of memory channels to be accessed does not satisfy 2 raised to the power of n, the step S120 of performing first address processing on the first address segment addr_in[9:8] based on the number N of memory channels to be accessed (here N = 3) is required to obtain the target address segment Address_M[1:0].

[0064] ​​​The memory access method provided by at least one embodiment of the present disclosure can obtain a target address segment by performing first address processing on a first address segment in a system memory address, access a specific number of memory channels based on a first value of the target address segment, thereby flexibly adjusting the number of memory channels to be accessed, making the chip design compatible with a plurality of memory channel numbers, improving the flexibility of chip design, reducing unnecessary cost waste, and having high practical value.

[0065] In some examples, the system memory address further includes a second address segment and a third address segment, a plurality of address bits in the second address segment are higher than a plurality of address bits in the first address segment, and a plurality of address bits in the third address segment are lower than the plurality of address bits in the first address segment.

[0066] For example, the second address segment can be a high bit part of the system memory address, and correspond to a unique address of each memory channel; and the third address segment can be a low bit part of the system memory address, and the bit width thereof depends on an interleaving granularity, that is, a basic granularity (for example, 256B, 512B, 1KB, 2KB, etc.) for accessing the memory channel.

[0067] For example, since the first address processing is performed on the first address segment, the second address segment of the high bit part needs to be processed accordingly to avoid access errors caused by the values of two addresses being mapped to the same memory channel; and the third address segment of the low bit part can be directly processed in a transparent manner, that is, no other operation processing is performed on the third address segment.

[0068] In some examples, in order to perform corresponding processing on the second address segment of the high bit part, before accessing N memory channels to be accessed, the memory access method provided by at least one embodiment of the present disclosure further includes steps S140-S150 (not shown in the figure):

[0069] Step S140: dividing values of a plurality of address bits of the target address segment into M groups;

[0070] Step S150: performing second address processing on the second address segment based on the number N of the memory channels to be accessed and the first address segment, so that the values of the plurality of address bits of the second address segment jump by M as a granularity, to obtain a fourth address segment.

[0071] For example, in step S140, since the values of the plurality of address bits of the target address segment have changed compared with the first address segment, the changed values and the unchanged values can be grouped, for example, divided into M groups, where M is an integer greater than 1.

[0072] For example, in step S150, in order to make the values ​​of multiple address bits in the high-order address segment correspond to the values ​​of multiple address bits in the target address segment and avoid mapping the values ​​of the two addresses to the same memory channel, the second address segment is subjected to second address processing so that the values ​​of the multiple address bits in the second address segment jump with a granularity of M to obtain a fourth address segment. For example, the values ​​of the multiple address bits in the fourth address segment correspond to the values ​​of the multiple address bits in the target address segment.

[0073] For example, the system memory address includes n3+1 address bits, the second address segment addr_in[n3:n2+1] includes the n2+1th address bit to the n3th address bit of the system memory address, and the first address segment addr_in[n2:n1] includes the n1th address bit to the n2th address bit of the system memory address, where n3 is an integer greater than 2, n2 is an integer greater than 1 and less than n3-1, and n1 is an integer greater than 1 and less than n2. For example, step S150 can be further expressed by the following formula (1):

[0074] Address_H[n3-n2:0]=addr_in[n3:n2+1]×((2 m -1) / N+1)+addr_in[n2:n1] / N

[0075] Formula (1)

[0076] Wherein, Address_H[n3-n2:0] represents the fourth address segment, and the maximum possible number of groups of values ​​of multiple address bits of the target address segment is M=(2 m -1) / N+1, m represents the bit width of the target address segment and m=n2-n1+1. For example, the first half of formula (1) is addr_in[n3:n2+1]×((2 m -1) / N+1) indicates that the values ​​of multiple address bits of the second address segment addr_in[n3:n2+1] jump with a granularity of M. The second half of formula (1), addr_in[n2:n1] / N, indicates the specific group to which the jump occurs.

[0077] Figure 5 A schematic diagram of an example of first address processing and second address processing provided in at least one embodiment of the present disclosure. For example, Figure 5 for Figure 2 A specific example of step S120 and steps S140 to S150 described above is provided.

[0078] For example, in Figure 5In the example, assuming that the number of memory channels to be accessed is N=3 (in this case, N is not a power of 2), the first address segment addr_in[9:8] with a bit width of 2 bits is selected. For example, the system memory address addr_in[31:0] includes 32 address bits (i.e., n3=31), the second address segment addr_in[31:10] includes the 10th to 31st address bits of the system memory address, and the first address segment addr_in[9:8] includes the 8th to 9th address bits of the system memory address (i.e., n1=8, n2=9).

[0079] For example, Figure 5 As shown, the values ​​of the first address segment and the second address segment are intercepted, and the values ​​of the first address segment and the second address segment are dynamically changed in sequence starting from 0. For example, for the sake of simplicity, Figure 5 In the partial values ​​of the second address segment shown, the previously omitted parts are all 0.

[0080] For example, Figure 5 As shown on the left, the first address segment addr_in[9:8] includes 4 values ​​and changes dynamically in the order of 00, 01, 10 and 11; when every 4 values ​​of the first address segment complete a change, the value of the second address segment addr_in[31:10] changes once.

[0081] For example, Figure 5 As shown, after execution Figure 2 In step S120, the first address segment addr_in[9:8] is subjected to first address processing, and the resulting target address segment Address_M[1:0] includes three values: 00, 01, and 10. The portion of the first address segment originally having a value of 11 is replaced by the target address segment value 00. For example, further, step S140 is executed to divide the values ​​of the multiple address bits of the target address segment into two groups (i.e., M=2), where 00, 01, and 10 are group 0, and the repeated 00 is group 1. The values ​​of the multiple address bits of the target address segment dynamically change in the order of group 0, group 1, and so on.

[0082] For example, Figure 5 As shown, when executing Figure 2After step S120, if the second address segment is not processed, the value of group 1 will overlap with the first value of the corresponding group 0, causing the two address values ​​to be mapped to the same memory channel, thereby causing an access error. For example, to avoid the above situation, step S150 is executed to perform second address processing on the second address segment addr_in[31:10] so that the values ​​of multiple address bits of the second address segment jump with a granularity of 2 (i.e., the number of groups M of the values ​​of the target address segment), thereby obtaining a fourth address segment Address_H[21:0].

[0083] For example, for Figure 5 For example, the fourth address segment Address_H[21:0] is expressed by formula (1):

[0084] Address_H[21:0]=addr_in[31:10]×((2 2 -1) / 3+1)+addr_in[9:8] / 3

[0085] Wherein, Address_H[21:0] represents the fourth address segment, the bit width of the target address segment is 2, and the maximum possible number of groups of values ​​of multiple address bits of the target address segment is M=(2 2 -1) / 3+1=2. For example, the first half of formula (1) is addr_in[31:10]×((2 2 -1) / 3+1) indicates that the values ​​of multiple address bits of the second address segment addr_in[31:10] jump with a granularity of 2. The second half of formula (1), addr_in[9:8] / 3, indicates the specific group to which the change occurs.

[0086] For example, Figure 5 As shown, in the process of executing the second address processing of step S150, the values ​​of multiple address bits of the second address segment addr_in[31:10] jump with the granularity of 2, which is the number of groups divided by the values ​​of multiple address bits of the target address segment; specifically, when the value of the target address segment changes from the first 0th group to the first 1st group, the value of the second address segment jumps from...000 to...001; when the value of the target address segment changes from the first 1st group to the second 0th group, the value of the second address segment jumps from...001 to...010; when the value of the target address segment changes from the second 0th group to the second 1st group, the value of the second address segment jumps from...001 to...011, and so on.

[0087] For example, after executing step S150, the values ​​of the multiple address bits of the fourth address segment Address_H[21:0] obtained correspond to the values ​​of the multiple address bits of the target address segment; that is, the values ​​of the multiple address bits of the fourth address segment also dynamically change in the order of group 0, group 1..., avoiding the situation where the values ​​of two addresses are mapped to the same memory channel.

[0088] It should be noted that Figure 5 The first address segment, second address segment, target address segment and fourth address segment are only exemplary. The address bits, values, value change order, grouping method and jump form contained in each address segment are not limited to the above examples. They can be selected according to actual needs. The embodiments of the present disclosure do not impose any restrictions on this.

[0089] Figure 6 Another exemplary flowchart of a memory access method provided by at least one embodiment of the present disclosure.

[0090] For example, Figure 6 As shown, when executing Figure 2 Before step S130, the memory access method provided by at least one embodiment of the present disclosure may further include steps S160 to S170.

[0091] Step S160: selecting N target memory channels to be accessed from the plurality of memory channels;

[0092] Step S170: Based on the correspondence between each target memory channel in the N target memory channels and at least one value of the first address segment, a remapping operation is performed on the N first values ​​of the target address segment to obtain N target values ​​of the target address segment.

[0093] For example, after executing steps S160 to S170, Figure 2 The step S130 may further include a step S131: accessing N target memory channels based on the N target values.

[0094] For example, specifically, step S131 may further include: allocating the access request corresponding to each target memory channel to the corresponding target memory channel based on the N target values.

[0095] For example, in step S160, when the N memory channels to be accessed need to be specific N target memory channels, N target memory channels can be selected from multiple memory channels; in this case, the N first values ​​of the target address segment do not necessarily correspond one-to-one to the selected N target memory channels.

[0096] For example, further, in step S170, based on the correspondence between each target memory channel and the value of the first address segment, the N first values of the target address segment are remapped, that is, the first values not corresponding to the target memory channel are remapped to the target values corresponding to the corresponding target memory channel; at this time, the N target values of the target address segment obtained are one-to-one corresponding to the N target memory channels.

[0097] For example, further, in step S131, based on the N target values, the access request corresponding to each target memory channel is allocated to the corresponding target memory channel to access the N target memory channels.

[0098] Figure 7 Another example of the memory access method provided by at least one embodiment of the present disclosure is shown in the schematic diagram. For example, Figure 7 For example, the steps S160-S170 provided by Figure 6 are shown in the schematic diagram.

[0099] For example, as shown in Figure 7 , taking the target address segment and the memory channel in Figure 4 as an example, the memory corresponds to 4 memory channels (i.e. memory channel 1, memory channel 2, memory channel 3, and memory channel 4); when 3 memory channels to be accessed need to be specific 3 target memory channels, step S160 of Figure 6 needs to be performed to select 3 target memory channels, i.e. memory channel 1, memory channel 2, and memory channel 4, from the 4 memory channels.

[0100] For example, as shown in Figure 7 , the 3 first values 00, 01, and 10 of the target address segment are not in one-to-one correspondence with the 3 target memory channels (memory channel 1, memory channel 2, and memory channel 4) selected. For example, the first value 10 corresponds to the memory channel 3 which does not belong to the target memory channel; the target memory channel 4 corresponds to the value 11 of the target address segment, but 11 is not included in the 3 first values of the target address segment; therefore, the first value 10 needs to be remapped to the target value 11.

[0101] For example, as shown in Figure 7 , after performing Figure 6In step S170, based on the correspondence between the target memory channels (memory channel 1, memory channel 2, and memory channel 4) and the values ​​00, 01, and 11 of the first address segment, a remapping operation is performed on the three first values ​​00, 01, and 10 of the target address segment. That is, the first value 10 that does not correspond to the three target memory channels is remapped to a target value 11 corresponding to the target memory channel 4. At this time, the three target values ​​00, 01, and 11 of the target address segment respectively correspond one-to-one with the three target memory channels (memory channel 1, memory channel 2, and memory channel 4).

[0102] For example, Figure 7 As shown, step S131 is executed. Based on the three target values ​​00, 01 and 11, the on-chip bus distributes the access request corresponding to each target memory channel to the corresponding target memory channel to access the three target memory channels (memory channel 1, memory channel 2 and memory channel 4); and memory channel 3, which does not belong to the target memory channel, is no longer accessed.

[0103] It should be noted that Figure 7 The target address segments and memory channels are merely exemplary. The types and numbers of address bits and values ​​contained in the target address segments, the number and form of memory channels, the correspondence between address segment values ​​and memory channels, etc. are not limited to the above examples. Specific selections can be made based on actual needs, and the embodiments of the present disclosure do not impose any restrictions on this.

[0104] At least one embodiment of the present disclosure provides a memory access method that performs a remapping operation on a target address segment and accesses a specific target memory channel based on a target value obtained by the remapping operation, thereby flexibly configuring the memory channels to be accessed and improving the flexibility of chip design. In particular, in applications such as chip binning, memory channels with manufacturing defects can be flexibly avoided, thereby significantly reducing costs.

[0105] In some examples, Figure 6 The step S160 may further include a step S161.

[0106] Step S161: using a first configuration signal to configure N target memory channels to be accessed among a plurality of memory channels.

[0107] For example, multiple bits of the first configuration signal correspond one-to-one to multiple memory channels, and step S161 may further include: in response to N bits of the multiple bits of the first configuration signal being valid values, selecting N memory channels corresponding to the N bits as N target memory channels. In some examples, the first configuration signal is a one-hot code.

[0108] In some examples, at least one embodiment of the present disclosure further includes step S180.

[0109] Step S180: Use the second configuration signal to configure the number N of memory channels to be accessed.

[0110] For example, the first configuration signal and the second configuration signal may be generated by a specific register, the second configuration signal is used to flexibly configure the number N of memory channels to be accessed, and the first configuration signal is used to flexibly configure the N target memory channels to be accessed.

[0111] In some examples, after the allocation of access requests is completed, the target address segment needs to be deleted; this is because the main function of the target address segment is to allocate access requests to the memory channel to be accessed, and the target values ​​contained in the target address segment are not continuous (for example, see Figure 5 , the values ​​of group 1 and group 0 are not continuous), which will cause the memory addresses accessed to the memory channel to be discontinuous. For example, Figure 2 Step S130 further includes steps S132 to S133.

[0112] Step S132: for each of the N memory channels to be accessed, allocating an access request corresponding to each memory channel to be accessed to the corresponding memory channel based on the N first values;

[0113] Step S133: Delete the target address segment.

[0114] For example, in step S132, based on the N first values, the access request is allocated to the memory channel to be accessed; in step S133, the target address segment is deleted to obtain a continuous memory address.

[0115] Figure 8A A schematic diagram of another example of a memory access method provided by at least one embodiment of the present disclosure. For example, Figure 8A This is a specific example of steps S110 to S180 provided in at least one embodiment of the present disclosure.

[0116] For example, Figure 8AAs shown, the host (master) in the chip (e.g., SoC) initiates a read and write access request, and interleaves access to multiple memory channels according to a specific interleaving granularity. For example, the memory corresponds to 4 memory channels (i.e., memory channel 1, memory channel 2, memory channel 3, and memory channel 4), including 3 memory channels to be accessed (i.e., N=3), where N is not a power of 2. For example, first, step S110 is executed to select the first address segment addr_in[9:8] in the system memory address. For example, each memory channel corresponds to at least one value of the first address segment, i.e., memory channel 1 corresponds to the value 00 of the first address segment, memory channel 2 corresponds to the value 01 of the first address segment, memory channel 3 corresponds to the value 10 of the first address segment, and memory channel 4 corresponds to the value 11 of the first address segment.

[0117] For example, in Figure 8A In the example, the system memory address addr_in[31:0] used for memory access includes 32 address bits. After executing step S110, the selected first address segment addr_in[9:8] includes the 8th address bit to the 9th address bit of the system memory address, the second address segment addr_in[31:10] of the high-order part includes the 10th address bit to the 31st address bit of the system memory address, and the third address segment addr_in[7:0] of the low-order part includes the 7th address bit to the 0th address bit of the system memory address.

[0118] For example, Figure 8A As shown, since the number of memory channels to be accessed is 3 (i.e., it does not satisfy the n-th power of 2), step S120 is executed to perform first address processing on the first address segment addr_in[9:8] based on the number N of memory channels to be accessed (here, N=3) to obtain the target address segment Address_M[1:0]. Specifically, step S121 is executed to obtain the target address segment Address_M[1:0] by taking the remainder of 3 from the first address segment addr_in[9:8], i.e., Address_M[1:0]=addr_in[9:8]%3. For example, after the first address processing, the target address segment Address_M[1:0] only includes three first values ​​00, 01, and 10.

[0119] For example, since the first address segment addr_in[9:8] is subjected to the first address processing, the second address segment addr_in[31:10] of the high-order portion needs to be processed accordingly to avoid access errors caused by mapping the values ​​of the two addresses to the same memory channel. For example, step S140 is executed to divide the values ​​of the multiple address bits of the target address segment into 2 groups (i.e., M=2); step S150 is executed to perform the second address processing on the second address segment addr_in[31:10] so that the values ​​of the multiple address bits of the second address segment jump with a granularity of 2 to obtain the fourth address segment Address_H[21:0]. For example, the specific method of the second address processing is detailed in the description of steps S140 to S150 in at least one embodiment of the present disclosure, and will not be repeated here.

[0120] For example, Figure 8A As shown, the address processing operation of step S120 (for example, including the first processing operation and the second processing operation) can be performed by an address processing module, and the address processing module receives the second configuration signal interleave_n[1:0] generated by the first register; in step S180, the second configuration signal is used to configure the number N of memory channels to be accessed, for example, N=interleave_n+1.

[0121] For example, Figure 8A As shown, after the address processing operation of step S120 is performed on the system memory address addr_in[31:0], the first memory address addr_cal[31:0] is obtained. For example, the first memory address addr_cal[31:0] includes the target address segment Address_M[1:0] obtained by the first address processing, the fourth address segment Address_H[21:0] obtained by the second address processing, and the third address segment addr_in[7:0] directly transmitted.

[0122] For example, Figure 8AAs shown, when the three memory channels to be accessed need to be specific three target memory channels, the target address segment needs to be remapped. For example, step S160 is executed to select three target memory channels from the four memory channels, namely memory channel 1, memory channel 2, and memory channel 4. For example, specifically, step S161 can be executed to use the first configuration signal ddr_en[3:0] generated by the first register to configure the three target memory channels to be accessed. For example, the first configuration signal ddr_en[3:0] can be a one-hot code, and the four bits of ddr_en[3:0] correspond one-to-one to the four memory channels; if memory channel 3 is not desired to be used, the ddr_en[3:0] signal takes the value 4'b1011 according to the one-hot code. For example, specifically, in response to the 0th, 1st, and 3rd bits of the first configuration signal ddr_en[3:0] being valid values, memory channel 1, memory channel 2, and memory channel 4 corresponding to the 0th, 1st, and 3rd bits are selected as the three target memory channels.

[0123] For example, further, step S170 is executed to perform a remapping operation on the three first values ​​00, 01, and 10 of the target address segment based on the correspondence between the target memory channels (memory channel 1, memory channel 2, and memory channel 4) and the values ​​00, 01, and 11 of the first address segment. That is, the first value 10 that does not correspond to the three target memory channels is remapped to the target value 11 corresponding to the target memory channel 4. At this time, the three target values ​​00, 01, and 11 of the target address segment respectively correspond one-to-one to the three target memory channels (memory channel 1, memory channel 2, and memory channel 4).

[0124] For example, Figure 8A As shown, the remapping operation of steps S160 to S170 can be performed by a remapping module. For example, the remapping module receives a first configuration signal ddr_en[3:0] generated by a first register; in step S161, all available memory channels are traversed according to the state of the first configuration signal ddr_en[3:0] to configure the three target memory channels to be accessed (memory channel 1, memory channel 2, and memory channel 4) using the first configuration signal ddr_en[3:0]; in step S170, the three first values ​​00, 01, and 10 of the target address segment are remapped to obtain three target values ​​00, 01, and 11 of the target address segment corresponding one-to-one to the three target memory channels.

[0125] For example, Figure 8AAs shown, after the remapping operation of step S170 is performed on the first memory address addr_cal[31:0], the second memory address addr_map[31:0] is obtained. For example, the second memory address addr_map[31:0] includes the remapped target address segment Address_M[1:0], the second address segment Address_H[21:0], and the directly transparent third address segment addr_in[7:0].

[0126] For example, Figure 8A As shown, step S130 is executed to access the three memory channels to be accessed. For example, specifically, steps S131 / S132 are executed, and the on-chip bus allocates the access request to the corresponding target memory channel based on the target value of the target address segment Address_M[1:0]. That is, based on the target value 00, the access request is allocated to memory channel 1, based on the target value 01, the access request is allocated to memory channel 2, and based on the target value 11, the access request is allocated to memory channel 4. Memory channel 3, which is not a target memory channel, is not allocated an access request.

[0127] For example, Figure 8A As shown, further, after the allocation of the access request is completed, the deletion operation of step S133 is performed, that is, the target address segment Address_M[1:0] in the second memory address addr_map[31:0] is deleted to obtain a continuous third memory address addr_cut[31:0]. For example, the third memory address addr_cut[31:0] is obtained by splicing the second address segment Address_H[21:0] and the directly transparently transmitted third address segment addr_in[7:0].

[0128] Figure 8B A schematic diagram of another example of a memory access method provided by at least one embodiment of the present disclosure. For example, Figure 8B for Figure 8A A specific example of the system memory address, the first memory address, the second memory address and the third memory address.

[0129] For example, Figure 8BAs shown in the figure, the system memory address addr_in[31:0] includes the second address segment addr_in[31:10] of the high-order portion, the first address segment addr_in[9:8] of the middle portion, and the third address segment addr_in[7:0] of the low-order portion. For example, the first address segment addr_in[9:8] is used to select the memory channel to be accessed; the second address segment addr_in[31:10] corresponds to the unique address of each memory channel; and the third address segment addr_in[7:0] corresponds to the data volume of the host read / write operation. Its bit width depends on the interleaving granularity and can be directly transparently transmitted during the memory access process.

[0130] For example, Figure 8B As shown, after the system memory address addr_in[31:0] is Figure 8A The address processing operation is performed to obtain the first memory address addr_cal[31:0]. For example, the first memory address addr_cal[31:0] includes the target address segment Address_M[1:0] obtained by the first address processing, the fourth address segment Address_H[21:0] obtained by the second address processing, and the third address segment addr_in[7:0] directly transmitted.

[0131] For example, Figure 8B As shown, after the first memory address addr_cal[31:0] is Figure 8A The remapping operation is performed to obtain the second memory address addr_map[31:0]. For example, the second memory address addr_map[31:0] includes the remapped target address segment Address_M[1:0], the second address segment Address_H[21:0], and the directly transmitted third address segment addr_in[7:0].

[0132] For example, Figure 8B As shown, after the first memory address and the second memory address addr_map[31:0] are Figure 8A The target address segment Address_M[1:0] is deleted to obtain the third continuous memory address addr_cut[31:0]. For example, the third memory address addr_cut[31:0] is obtained by concatenating the second address segment Address_H[21:0] and the directly transparently transmitted third address segment addr_in[7:0].

[0133] It should be noted that Figure 8A and Figure 8BThe memory addresses, operation modes, configuration signals and memory channels are only exemplary. The specific number, form and specific operation mode of each address, signal and memory channel are not limited to the above examples. They can be selected according to actual needs. The embodiments of the present disclosure do not limit this.

[0134] The memory access method provided by at least one embodiment of the present disclosure can be designed, adjusted, and used accordingly according to different application scenarios, thereby improving the flexibility of chip design and significantly reducing costs.

[0135] For example, in a chip binning application scenario, the memory access method provided by at least one embodiment of the present disclosure can improve the chip binning strategy, and adjust the first configuration signal and the second configuration signal by adjusting the value of the first register, so that the target memory channel to be accessed and the number of target memory channels can be flexibly configured. For example, specifically, when a manufacturing defect causes some hosts and / or some memory channels on a chip to be unavailable, if the remaining hosts and / or memory channels can still work normally and the bandwidth is available, the memory access method provided by at least one embodiment of the present disclosure can be used to match the remaining hosts and / or memory channels, so that the chip can still be used after functional tailoring, thereby reducing the number of waste chips, improving the chip yield, and saving production costs.

[0136] For example, in low-power application scenarios, the memory access method provided by at least one embodiment of the present disclosure can reduce power consumption by flexibly shutting down some memory channels. Specifically, for certain scenarios with low bandwidth requirements, the memory access method provided by at least one embodiment of the present disclosure can flexibly adjust the number of interleaved memory channels based on bandwidth requirements and perform clock or power-down operations on unused memory channels, thereby saving computing resources.

[0137] Figure 9 A schematic block diagram of a memory access device provided in at least one embodiment of the present disclosure.

[0138] For example, Figure 9 As shown, the memory access device 200 includes a first selection module 210, an address processing module 220, and an access module 230. For example, the memory corresponds to multiple memory channels, and the multiple memory channels include N memory channels to be accessed, where N is an integer greater than 1.

[0139] For example, the first selection module 210 is configured to select a first address segment in the system memory address. For example, each memory channel in the plurality of memory channels corresponds to at least one value of the first address segment. That is, the first selection module 210 can be configured to perform, for example Figure 2 Step S110 is shown.

[0140] For example, the address processing module 220 is configured to perform first address processing on the first address segment based on the number N of memory channels to be accessed to obtain a target address segment. For example, the target address segment includes N first values. That is, the address processing module 220 can be configured to perform, for example Figure 2 Step S120 is shown.

[0141] For example, the access module 230 is configured to access N memory channels to be accessed based on N first values. That is, the determination module 230 can be configured to perform, for example Figure 2 Step S130 is shown.

[0142] In some examples, the first address segment includes the n1th address bit to the n2th address bit of the system memory address, where n2 is an integer greater than 1, n1 is an integer greater than 1 and less than n2, and where n2-n1+1>log2N.

[0143] In some examples, the address processing module 220 is further configured to obtain a target address segment by taking a remainder of the first address segment and the number N of memory channels to be accessed.

[0144] In some examples, the system memory address further includes a second address segment and a third address segment, wherein multiple address bits in the second address segment are higher than multiple address bits in the first address segment, and multiple address bits in the third address segment are lower than multiple address bits in the first address segment.

[0145] For example, the address processing module 220 is further configured to: divide the values ​​of multiple address bits of the target address segment into M groups, where M is an integer greater than 1; and based on the number N of memory channels to be accessed and the first address segment, perform second address processing on the second address segment so that the values ​​of multiple address bits of the second address segment jump with a granularity of M, to obtain a fourth address segment. In other words, the address processing module 220 can also be configured to execute steps S140 to S150 provided in at least one embodiment of the present disclosure.

[0146] For example, the system memory address includes n3+1 address bits, the second address segment addr_in[n3:n2+1] includes the n2+1th address bit to the n3th address bit of the system memory address, and the first address segment addr_in[n2:n1] includes the n1th address bit to the n2th address bit of the system memory address, where n3 is an integer greater than 2, n2 is an integer greater than 1 and less than n3-1, and n1 is an integer greater than 1 and less than n2. For example, the address processing module 220 is further configured to execute formula (1) described above:

[0147] Address_H[n3-n2:0]=addr_in[n3:n2+1]×((2 m-1) / N+1)+addr_in[n2:n1] / N

[0148] Among them, Address_H[n3-n2:0] is the fourth address segment, M=(2 m -1) / N+1, m=n2-n1+1.

[0149] In some examples, such as Figure 9 As shown, the memory access device 200 further includes a second selection module 240 and a remapping module 250 .

[0150] For example, the second selection module 240 is configured to select N target memory channels to be accessed from a plurality of memory channels. That is, the second selection module 240 can be configured to perform, for example Figure 6 Step S160 is shown.

[0151] For example, the remapping module 250 is configured to perform a remapping operation on the N first values ​​of the target address segment based on the correspondence between each target memory channel in the N target memory channels and at least one value of the first address segment, to obtain N target values ​​of the target address segment. For example, the N target values ​​correspond one-to-one to the N target memory channels. That is, the remapping module 250 can be configured to perform, for example Figure 6 Step S170 is shown.

[0152] For example, the access module 230 is further configured to access N target memory channels based on the N target values.

[0153] For example, the access module 230 is further configured to distribute the access request corresponding to each target memory channel to the corresponding target memory channel based on the N target values.

[0154] In some examples, such as Figure 9 As shown, the memory access device 200 further includes a first register 270 configured to generate a first configuration signal and a second configuration signal.

[0155] In some examples, the first register 270 is configured to configure N target memory channels to be accessed among the plurality of memory channels using a first configuration signal.

[0156] For example, the multiple bits of the first configuration signal correspond one-to-one to the multiple memory channels, and the first register 270 is further configured to, in response to N bits of the multiple bits of the first configuration signal being valid values, select N memory channels corresponding to the N bits as the N target memory channels. In some examples, the first configuration signal is a one-hot code.

[0157] In some examples, the first register 270 is further configured to use the second configuration signal to configure the number N of memory channels to be accessed. That is, the first register 270 can also be configured to execute step S180 provided in at least one embodiment of the present disclosure.

[0158] In some examples, the access module 230 includes an allocation submodule 231 and a deletion submodule 232 (not shown). For example, the allocation submodule 231 is configured to, for each of the N memory channels to be accessed, allocate an access request corresponding to each memory channel to the corresponding memory channel based on the N first values. For example, the deletion submodule 232 is configured to delete the target address segment.

[0159] Since in the above description Figure 2 In the process of the memory access method shown in FIG, the details of the operation of the memory access device 200 have been introduced, so for the sake of brevity, they will not be repeated here. For relevant details, please refer to the above Figures 1 to 8B Description.

[0160] It should be noted that Figure 9 The modules in the memory access device 200 can be configured as software, hardware, firmware, or any combination thereof to perform specific functions. For example, these modules can correspond to dedicated integrated circuits, pure software codes, or modules that combine software and hardware. Figure 9 The device described may be a PC computer, a tablet device, a personal digital assistant, a smartphone, a web application, or other device capable of executing program instructions, but is not limited thereto.

[0161] In addition, although the memory access device 200 is divided into modules for respectively performing corresponding processing in the above description, it is clear to those skilled in the art that the processing performed by each module can also be performed without any specific module division in the device or without clear boundaries between the modules. Figure 9 The memory access device 200 is not limited to include the modules described above, but may also include some other modules (eg, storage module, control module, etc.) as needed, or the above modules may also be combined.

[0162] At least one embodiment of the present disclosure further provides an electronic device, comprising a processor and a memory; the memory comprising one or more computer program modules; the one or more computer program modules being stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising computer-executable instructions for implementing the memory access method provided by the embodiments of the present disclosure described above. For example, the processor may be a single-core processor or a multi-core processor.

[0163] Figure 10 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0164] For example, Figure 10 As shown, the electronic device 300 includes a processor 310 and a memory 320. For example, the memory 320 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 310 is used to execute the non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by the processor 310, one or more steps of the memory access method described above can be performed. The memory 320 and the processor 310 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0165] For example, the processor 310 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a digital signal processor (DSP), or other processing units with memory access capabilities and / or program execution capabilities, such as a field programmable gate array (FPGA). For example, the central processing unit (CPU) may be an X86, RISC-V, or ARM architecture. The processor 310 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 300 to perform desired functions.

[0166] For example, the memory 320 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disc read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 310 may execute one or more computer program modules to implement various functions of the electronic device 300. Various applications and various data, as well as various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.

[0167] It should be noted that, in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 300 can be referred to the above description of the memory access method provided in at least one embodiment of the present disclosure, and will not be repeated here.

[0168] Figure 11 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0169] For example, Figure 11 As shown, the electronic device 400 is suitable for implementing the memory access method provided by the embodiment of the present disclosure. It should be noted that, Figure 11 The electronic device 400 shown is only an example and does not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0170] For example, Figure 11 As shown, electronic device 400 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 41, which can perform various appropriate actions and processes according to programs stored in read-only memory (ROM) 42 or programs loaded from storage device 48 into random access memory (RAM) 43. Various programs and data required for the operation of electronic device 400 are also stored in RAM 43. Processing device 41, ROM 42, and RAM 43 are connected to each other via bus 44. Input / output (I / O) interface 45 is also connected to bus 44. Generally, the following devices can be connected to I / O interface 45: input device 46 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output device 47 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage device 48 including, for example, a magnetic tape, hard disk, etc.; and communication device 49. Communication device 49 can allow electronic device 400 to communicate with other electronic devices wirelessly or by wire to exchange data.

[0171] Although Figure 11 The electronic device 400 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 400 may alternatively implement or possess more or fewer devices.

[0172] For a detailed description and technical effects of the electronic device 400, please refer to the above description of the memory access method, which will not be repeated here.

[0173] Figure 12 A schematic diagram of a storage medium provided for at least one embodiment of the present disclosure.

[0174] For example, Figure 12As shown, the storage medium 500 stores non-transitory computer-readable instructions 510. For example, when the non-transitory computer-readable instructions 510 are executed by a computer, one or more steps in the memory access method described above are performed.

[0175] For example, the storage medium 500 can be applied to Figure 10 For example, the storage medium 500 may be the memory 320 in the electronic device 300. For example, the description of the storage medium 500 may refer to Figure 10 The corresponding description of the memory 320 in the electronic device 300 is not repeated here.

[0176] Regarding this disclosure, the following points need to be explained:

[0177] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0178] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0179] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory access method, wherein: The memory corresponds to a plurality of memory channels, and the plurality of memory channels include N memory channels to be accessed, wherein N is an integer greater than 1. The memory access method includes: Selecting a first address segment in a system memory address, wherein each memory channel in the plurality of memory channels corresponds to at least one value of the first address segment; Based on the number N of memory channels to be accessed, performing first address processing on the first address segment to obtain a target address segment, wherein the target address segment includes N first values; Based on the N first values, the N memory channels to be accessed are accessed.

2. The memory access method according to claim 1, wherein: The first address segment includes the n1th address bit to the n2th address bit of the system memory address, wherein n2 is an integer greater than 1, n1 is an integer greater than 1 and less than n2, and wherein n2-n1+1>log2N.

3. The memory access method according to claim 1, wherein: The performing first address processing on the first address segment based on the number N of memory channels to be accessed to obtain a target address segment includes: The target address segment is obtained by taking the remainder of the first address segment and the number N of the memory channels to be accessed.

4. The memory access method according to claim 1, wherein: The system memory address further includes a second address segment and a third address segment, wherein multiple address bits in the second address segment are higher than multiple address bits in the first address segment, and multiple address bits in the third address segment are lower than multiple address bits in the first address segment.

5. The memory access method according to claim 4, wherein: Before accessing the N memory channels to be accessed, the memory access method further includes: Dividing the values ​​of multiple address bits of the target address segment into M groups, where M is an integer greater than 1; Based on the number N of memory channels to be accessed and the first address segment, second address processing is performed on the second address segment, so that the values ​​of multiple address bits of the second address segment jump with M as a granularity, to obtain a fourth address segment.

6. The memory access method according to claim 5, wherein: The system memory address includes n3+1 address bits, the second address segment addr_in[n3:n2+1] includes the n2+1th address bit to the n3th address bit of the system memory address, and the first address segment addr_in[n2:n1] includes the n1th address bit to the n2th address bit of the system memory address, wherein n3 is an integer greater than 2, n2 is an integer greater than 1 and less than n3-1, and n1 is an integer greater than 1 and less than n2. The step of performing second address processing on the second address segment based on the number N of memory channels to be accessed and the first address segment, so that values ​​of multiple address bits of the second address segment jump with a granularity of M to obtain a fourth address segment, includes: Address_H[n3-n2:0]=addr_in[n3:n2+1]×((2 m -1) / N+1)+addr_in[n2:n1] / N Among them, Address_H[n3-n2:0] is the fourth address segment, M=(2 m -1) / N+1, m=n2-n1+1.

7. The memory access method according to claim 1, wherein: Before accessing the N memory channels to be accessed, the memory access method further includes: Selecting N target memory channels to be accessed from the plurality of memory channels; Based on a correspondence between each target memory channel in the N target memory channels and at least one value of the first address segment, a remapping operation is performed on the N first values ​​of the target address segment to obtain N target values ​​of the target address segment, wherein the N target values ​​correspond one-to-one to the N target memory channels, The step of accessing the N memory channels to be accessed based on the N first values ​​includes: Based on the N target values, the N target memory channels are accessed.

8. The memory access method according to claim 7, wherein: The accessing the N target memory channels based on the N target values ​​includes: Based on the N target values, the access request corresponding to each target memory channel is allocated to the corresponding target memory channel.

9. The memory access method according to claim 7, wherein: The selecting N target memory channels to be accessed from the multiple memory channels includes: The first configuration signal is used to configure N target memory channels to be accessed among the plurality of memory channels.

10. The memory access method according to claim 9, wherein: The multiple bits of the first configuration signal correspond one-to-one to the multiple memory channels. The configuring N target memory channels to be accessed among the plurality of memory channels using the first configuration signal includes: In response to N bits among the plurality of bits of the first configuration signal being valid values, N memory channels corresponding to the N bits are selected as the N target memory channels.

11. The memory access method according to claim 10, wherein: The first configuration signal is a one-hot code.

12. The memory access method according to claim 1, further comprising: The second configuration signal is used to configure the number N of memory channels to be accessed.

13. The memory access method according to claim 1, wherein: The step of accessing the N memory channels to be accessed based on the N first values ​​includes: For each of the N memory channels to be accessed, allocating an access request corresponding to each memory channel to be accessed to a corresponding memory channel based on the N first values; Delete the target address segment.

14. The memory access method according to any one of claims 1 to 13, wherein: N is not a power of 2.

15. A memory access device, wherein: The memory corresponds to a plurality of memory channels, and the plurality of memory channels include N memory channels to be accessed, wherein N is an integer greater than 1. The memory access device comprises: a first selection module configured to select a first address segment in a system memory address, wherein each memory channel in the plurality of memory channels corresponds to at least one value of the first address segment; an address processing module configured to perform first address processing on the first address segment based on the number N of memory channels to be accessed to obtain a target address segment, wherein the target address segment includes N first values; An access module is configured to access the N memory channels to be accessed based on the N first values.

16. The memory access device according to claim 15, further comprising: A second selection module is configured to select N target memory channels to be accessed from the multiple memory channels; a remapping module configured to perform a remapping operation on the N first values ​​of the target address segment based on a correspondence between each target memory channel in the N target memory channels and at least one value of the first address segment, to obtain N target values ​​of the target address segment, wherein the N target values ​​correspond one-to-one to the N target memory channels, The access module is further configured to access the N target memory channels based on the N target values.

17. The memory access device according to claim 15, further comprising: The first register is configured to generate a first configuration signal and a second configuration signal.

18. The memory access device according to claim 15, wherein: The access module includes an allocation submodule and a deletion submodule. The allocation submodule is configured to allocate, for each of the N memory channels to be accessed, an access request corresponding to each memory channel to be accessed to a corresponding memory channel based on the N first values; The deletion submodule is configured to delete the target address segment.

19. An electronic device comprising: processor; a memory comprising one or more computer program modules; The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules are used to implement the memory access method according to any one of claims 1 to 14.

20. A storage medium storing non-transitory computer-readable instructions, wherein when the non-transitory computer-readable instructions are executed by a computer, the memory access method according to any one of claims 1 to 14 is implemented.

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