Chip layout quality inspection method and device in circuit design

Abstract

The invention provides a chip layout quality inspection method and device in circuit design, and the method comprises the steps: receiving chip design information and quality inspection options inputted by a user, the chip design information comprises the shapes of a plurality of blocks in a chip, the positions of the blocks, the connection relation among the blocks, the shapes of a plurality of units and the connection relation among the units, and each block comprises at least one unit. The quality inspection option comprises any one or more of data flow inspection, unit layout evaluation, congestion estimation and static time sequence analysis; according to the chip design information, the layout result of the chip is determined, and the layout result comprises the positions of the units; and obtaining a layout quality inspection result of the chip according to the layout result and an inspection rule corresponding to the quality inspection option. According to the method provided by the invention, the chip design efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a chip layout quality checking method and device in circuit design. BACKGROUND

[0002] As an early step of integrated circuit physical design, integrated circuit layout planning (floorplan) has a significant impact on subsequent macro placement, clock tree synthesis (CTS), and place and route (PnR). Therefore, the repair cost of layout planning problems increases as the physical design process progresses. With increasingly complex design and manufacturing constraints, early checking of the quality of chip layout planning and reporting of potential problems can positively impact the efficiency of the physical design process.

[0003] Currently, the quality of chip layout planning is checked mainly by manual work, which is inefficient. Therefore, there is an urgent need for a chip layout quality checking method to improve the efficiency of chip design in integrated circuits. SUMMARY

[0004] The present application provides a chip layout quality checking method and device in circuit design, which can improve the efficiency of chip design.

[0005] In a first aspect, a chip layout quality checking method in circuit design is provided. The method includes: receiving user input chip design information and quality checking options, the chip design information including shapes of a plurality of blocks in a chip, positions of the plurality of blocks, connection relationships between the plurality of blocks, shapes of a plurality of units, and connection relationships between the plurality of units, the block including at least one unit, the quality checking options including any one or more of data flow checking, unit layout evaluation, congestion estimation, and static timing analysis (STA), the data flow checking being used to indicate checking of wire distances between a plurality of elements in a layout result of the chip, the element including the block or the unit, the unit layout evaluation being used to indicate checking of regularity of the plurality of units in the layout result, the congestion estimation being used to indicate estimation of congestion degrees of wire routing in the layout result, and the STA being used to indicate analysis of timing paths in the layout result; determining the layout result of the chip according to the chip design information, the layout result including positions of the plurality of units; and obtaining a layout quality checking result of the chip according to checking rules corresponding to the layout result and the quality checking options.

[0006] The application provides a chip layout quality checking method, which includes a quality checking option for automatically early evaluating power, performance and area (PPA) of elements in a chip, and presents a layout quality checking result, so that deficiencies of the chip layout can be found early, iteration overhead is reduced, and chip design efficiency is improved.

[0007] In a possible implementation, the chip design information includes a design exchange format (DEF) file, a library exchange format (LEF) file and a netlist file of a current level of the chip input by a user, and optionally, the chip design information can further include lib information, a Verilog file, etc. The DEF file can be used to describe positions of blocks, the LEF file can be used to describe shapes of blocks and cells, and the netlist file can be used to describe connection relationships between blocks and cells.

[0008] The element described in the application can be a block, a macro cell or a standard cell. The block can include any one or more of the macro cell and the standard cell, and the block can further include a port.

[0009] Optionally, the layout result can further include any one or more of a connection relationship between a plurality of cells, positions of a plurality of blocks, and a connection relationship between a plurality of blocks.

[0010] In a possible implementation, the layout quality checking result of the chip can include any one or more of the following: evaluation of a wire distance between elements, regularity of a macro cell, regularity of a standard cell, a congestion map, a congestion value, a critical path of a circuit, and a timing value.

[0011] With reference to the first aspect, in some implementations of the first aspect, the method further includes: displaying any one or more of the layout result, the layout quality checking result, and an optimization suggestion corresponding to the layout quality checking result on a graphical user interface (GUI) or in a report.

[0012] The chip layout quality inspection method provided in the application can display any one or more of the layout result, the layout quality inspection result, and the optimization suggestion corresponding to the layout quality inspection result in a GUI or a report. The user can conveniently check the quality of the chip layout in the current design, the user experience is improved, the manual or automatic layout tool is guided to further layout iteration optimization, and the efficiency of the chip layout is improved.

[0013] In some implementation forms of the first aspect, the quality inspection options further include any one or more of shape and position inspection of the plurality of blocks, pin placement inspection, feedthrough inspection, and pin grouping inspection.

[0014] The chip layout quality inspection method provided in the application includes an integrated quality inspection command or user interface (UI), which facilitates the user to use and check the quality of the chip layout in the current design, and improves the user experience.

[0015] In some implementation forms of the first aspect, the rules corresponding to the shape and position inspection of the plurality of blocks include any one or more of the following: the shape vertex of the block needs to be on a grid point determined by a process, the length of an edge of the block under an advanced process node is a multiple of a preset value, a reused or flipped instantiation object of the block meets the constraint of a corresponding process, the blocks are placed without overlapping each other, and the blocks are placed within the outer frame of the chip.

[0016] Exemplarily, under a fin field-effect transistor (FinFET) process, the shape vertex of the block needs to be on a grid point determined by a process.

[0017] The chip layout quality inspection method provided in the application can set different inspection rules to inspect the shape and position of the blocks, supports function expansion, and can add new quality inspection options or inspection rules according to the user demand, thereby improving the chip design efficiency.

[0018] In some implementation forms of the first aspect, the rules corresponding to the pin placement inspection include any one or more of the following: the pins directly connected between the plurality of blocks need to be aligned in a direction parallel to a horizontal plane or a direction perpendicular to the horizontal plane, the pin arrangement of a reused block needs to be consistent, the wire winding direction of the metal layer where the pin is located needs to be perpendicular to the direction of the edge where the pin is located, the pin needs to be aligned to a process corresponding wire, and the metal layer where the pin is located meets the requirement of a manufacturing process.

[0019] It should be understood that the reused block is a same block that is reused.

[0020] The chip layout quality checking method provided in the application can set different checking rules to check pin placement, supports function expansion, and can add new quality checking options or checking rules according to user requirements, thereby improving chip design efficiency.

[0021] In some implementation forms of the first aspect, the rules corresponding to the feedthrough checking include any one or more of the following: all connections that need to establish a feedthrough have established a corresponding feedthrough, all feedthroughs are in the layout result.

[0022] A feedthrough refers to, in the process of obtaining a layout, if two blocks have a connection but the blocks are not placed adjacently or the length of the adjacent common edge cannot place all pins, a feedthrough technology is needed to connect two blocks that have a connection relationship but are not placed adjacently, and the connection added on this basis is referred to as a feedthrough.

[0023] The chip layout quality checking method provided in the application can set different checking rules to check feedthroughs, supports function expansion, and can add new quality checking options or checking rules according to user requirements, thereby improving chip design efficiency.

[0024] In some implementation forms of the first aspect, the rules corresponding to the pin grouping checking include any one or more of the following: pins of a bus need to be grouped in the same group, pins connected to the same block need to be grouped in the same group, and pins connected to different blocks need to be grouped in different groups.

[0025] The chip layout quality checking method provided in the application can set different checking rules to check pin grouping, supports function expansion, and can add new quality checking options or checking rules according to user requirements, thereby improving chip design efficiency.

[0026] In some implementation forms of the first aspect, the determining the layout result of the chip according to the chip design information includes: determining a placement position of a macro cell in the layout result according to a connection relationship between the plurality of cells and a weight corresponding to the connection relationship between the plurality of cells; and determining a placement position of a standard cell in the layout result according to a preset placement density constraint condition and the connection relationship between the plurality of cells.

[0027] In a possible implementation form, the weight corresponding to the connection relationship between the plurality of cells can be extracted according to the chip design information, and a macro cell placement condition that minimizes an overall weight loss value when the chip is laid out can be solved to determine the placement position of the macro cell in the chip.

[0028] In a possible implementation, the placement density constraint condition comprises that a placement density of some local standard cells in the chip cannot exceed a preset threshold. In the case of satisfying the density constraint condition, a placement of the standard cells is determined, in which a total length of the wires between the standard cells is minimized when the chip layout is solved.

[0029] The application provides a chip layout quality checking method, which can automatically perform layout according to chip design information, complete placement of macro cells and standard cells, and improve chip design efficiency.

[0030] With reference to the first aspect, in some implementations of the first aspect, the quality checking option comprises the data flow checking, and the obtaining of the layout quality checking result of the chip according to the layout result and the checking rule corresponding to the quality checking option comprises: checking a wire distance between the plurality of elements in the layout result according to a weight corresponding to a connection relationship between the plurality of elements to obtain the layout quality checking result.

[0031] The connection relationship between the plurality of elements comprises any one or more of a connection relationship between a plurality of blocks and a connection relationship between a plurality of cells.

[0032] In the chip layout quality checking method provided by the application, the connection relationship between the plurality of elements is extracted and analyzed, and a weight corresponding to the connection relationship is obtained to represent a connection tightness between different elements. The checking of the wire distance between the plurality of elements in the layout result according to the weight corresponding to the connection relationship between the plurality of elements comprises checking whether the weight of the connection relationship between the elements and the wire length between the elements satisfy a mapping relationship, for example, setting the weight range of the connection relationship between the elements to be one-to-one corresponding to the wire length range.

[0033] The application provides a chip layout quality checking method, which can set different checking rules to check data flow, supports function expansion, and can add new quality checking options or checking rules according to user demand, thereby improving chip design efficiency.

[0034] With reference to the first aspect, in some implementations of the first aspect, the quality checking option comprises the unit layout evaluation, and the obtaining of the layout quality checking result of the chip according to the layout result and the checking rule corresponding to the quality checking option comprises: performing any one or more of the following on the positions of the plurality of units in the layout result to obtain the layout quality checking result: a layout symmetry degree in the layout result, an alignment in a horizontal or vertical direction, a layout uniformity degree in the layout result, and a layout density degree of a plurality of units having a correlation.

[0035] The cell layout evaluation includes macro cell layout evaluation and / or standard cell layout evaluation, for example, regularity of macro cells and / or standard cells can be evaluated. The regularity can be checked by any one or more of the following aspects: 1, symmetry, a regular layout usually has symmetry, that is, macro cells or standard cells have symmetrical positions and shapes relative to the center of the chip or other reference points, a symmetrical layout can improve the balance of signal transmission, reduce signal transmission delay and power consumption; 2, alignment, a regular layout usually aligns macro cells or standard cells on a specific grid or boundary of the chip, so that they have consistent positions in horizontal and vertical directions, an aligned layout helps to simplify routing and timing optimization, and reduce signal transmission distance across macro cells or standard cells; 3, uniformity, a regular layout tries to maintain uniform spacing between macro cells or standard cells, so that they are evenly distributed on the chip, which helps to balance circuit load and signal transmission, and avoid hot spot areas and electrical noise problems; 4, cluster group, a regular layout may organize related macro cells or standard cells into cluster groups or clusters, so that they are physically close and connected to each other, a cluster group layout can promote local communication and data sharing, and reduce long-distance signal transmission.

[0036] The layout quality check result of the chip can include layout regularity of macro cells and / or layout regularity of standard cells.

[0037] The application provides a chip layout quality check method, which can set different check rules to evaluate cell layout, supports function expansion, and can add new quality check options or check rules according to user needs, thereby improving chip design efficiency.

[0038] With reference to the first aspect, in some implementations of the first aspect, the quality check option includes the congestion estimation, and the layout quality check result of the chip is obtained according to the layout result and the check rule corresponding to the quality check option, including: performing any one or more of the following checks on the layout result to obtain the layout quality check result: wire density, channel narrowness, and signal integrity.

[0039] The congestion degree can be estimated in the following aspects: 1. trace density, which refers to the number of traces in a unit area or the proportion of space occupied by traces. When the trace density of some areas is too high, it may cause crossing and interference between traces, making wiring more difficult and possibly affecting signal transmission performance; 2. channel narrowness, which means that the width of the horizontal and vertical channels available for wiring is limited, resulting in smaller spacing between traces, making wiring more difficult, and channel narrowness can also cause increased signal transmission delay and increased power consumption; 3. signal integrity, congestion of wiring can affect signal integrity. When the trace density is too high or the channel is narrow, signal coupling, crosstalk, and electrical noise may be introduced, resulting in a decrease in signal integrity.

[0040] The layout quality inspection result of the chip can include display of relevant congestion maps and / or congestion values.

[0041] The present application provides a chip layout quality inspection method, which can set different inspection rules to estimate the wiring congestion degree in the chip layout, and supports function expansion, so that new quality inspection options or inspection rules can be added according to user needs, improving chip design efficiency.

[0042] In combination with the first aspect, in some implementations of the first aspect, the quality inspection options include the STA, and the layout quality inspection result of the chip is obtained according to the layout result and the inspection rule corresponding to the quality inspection option, including: performing any one or more of the following analyses on the layout result to obtain the layout quality inspection result: circuit critical path, transmission delay, clock boundary, and data arrival time at the receiving end.

[0043] In combination with the connection relationship between elements in the chip design information, the present application can complete the STA task in the chip, that is, by analyzing parameters such as critical path, transmission delay, clock boundary, and data arrival time in the circuit, to determine whether the circuit meets the timing requirements and check potential timing violation problems.

[0044] The layout quality inspection result of the chip can include display of relevant critical paths and / or timing values.

[0045] The present application provides a chip layout quality inspection method, which can set different inspection rules to perform STA, and supports function expansion, so that new quality inspection options or inspection rules can be added according to user needs, improving chip design efficiency.

[0046] In some embodiments of the first aspect, the receiving the chip design information and the quality check option input by the user comprises receiving the chip design information and the quality check option input by the user through a GUI or a tool command language (TCL).

[0047] In a second aspect, a computer device is provided, comprising: a receiving module configured to receive chip design information and a quality check option input by a user, the chip design information comprising shapes of a plurality of blocks in a chip, positions of the plurality of blocks, connection relationships between the plurality of blocks, shapes of a plurality of cells, and connection relationships between the plurality of cells, the block comprising at least one of the cells, the quality check option comprising any one or more of a data flow check, a cell layout evaluation, a congestion estimation, and a static timing analysis (STA), the data flow check being configured to check wire distances between a plurality of elements in a layout result of the chip, the element comprising the block or the cell, the cell layout evaluation being configured to check regularity of the plurality of cells in the layout result, the congestion estimation being configured to estimate a congestion degree of routing in the layout result, and the STA being configured to analyze timing paths in the layout result; and a processing module configured to determine the layout result of the chip according to the chip design information, the layout result comprising positions of the plurality of cells, and configured to obtain a layout quality check result of the chip according to an inspection rule corresponding to the quality check option and the layout result.

[0048] In some embodiments of the second aspect, the device further comprises a display module configured to display any one or more of the layout result, the layout quality check result, and an optimization suggestion corresponding to the layout quality check result on a GUI or in a report.

[0049] In some embodiments of the second aspect, the quality check option further comprises any one or more of shape and position inspection of the plurality of blocks, pin placement inspection, feedthrough inspection, and pin grouping inspection.

[0050] In some embodiments of the second aspect, the rule corresponding to the shape and position inspection of the plurality of blocks comprises any one or more of the following: a shape vertex of the block needs to be on a grid point determined by a process, a length of an edge of the block at an advanced process node is a multiple of a preset value, an object of reuse or flip instantiation of the block satisfies a constraint of a corresponding process, placements of the plurality of blocks do not overlap with each other, and the placements of the block are within an outer frame of the chip.

[0051] With reference to the second aspect, in some implementations of the second aspect, the pin placement checking corresponds to a rule that includes any one or more of the following: pins that are directly connected to each other between the plurality of blocks need to be aligned in a direction parallel to a horizontal plane or in a direction perpendicular to the horizontal plane, pin arrangements of a multiplex block need to be consistent, a wire winding direction of a metal layer on which the pins are located needs to be perpendicular to a direction of an edge on which the pins are located, the pins need to be aligned to a process corresponding trace, and a metal layer on which the pins are located meets a manufacturing process requirement.

[0052] With reference to the second aspect, in some implementations of the second aspect, the feedthrough checking corresponds to a rule that includes any one or more of the following: all connections that need to establish a feedthrough have established a corresponding feedthrough, and all feedthroughs are in the layout result.

[0053] With reference to the second aspect, in some implementations of the second aspect, the pin grouping checking corresponds to a rule that includes any one or more of the following: pins of a bus need to be grouped in a same group, pins that are connected to a same block need to be grouped in a same group, and pins that are connected to different blocks need to be grouped in different groups.

[0054] With reference to the second aspect, in some implementations of the second aspect, the processing module is specifically configured to: determine, according to a connection relationship between the plurality of elements and a weight corresponding to the connection relationship between the plurality of elements, a placement position of a macro element in the layout result; and determine, according to a preset placement density constraint condition and the connection relationship between the plurality of elements, a placement position of a standard element in the layout result.

[0055] With reference to the second aspect, in some implementations of the second aspect, the quality checking option includes the data flow checking, and the processing module is specifically configured to: check, according to a weight corresponding to a connection relationship between the plurality of elements, a trace distance between the plurality of elements in the layout result to obtain the layout quality checking result.

[0056] With reference to the second aspect, in some implementations of the second aspect, the quality checking option includes the element layout evaluation, and the processing module is specifically configured to: perform any one or more of the following on a position of the plurality of elements in the layout result to obtain the layout quality checking result: a layout symmetry degree in the layout result, an alignment in a horizontal or vertical direction, a layout uniformity degree in the layout result, and a layout density degree of a plurality of elements that have a correlation.

[0057] With reference to the second aspect, in some implementations of the second aspect, the quality checking option includes the congestion estimation, and the processing module is specifically configured to: perform any one or more of the following on the layout result to obtain the layout quality checking result: a trace density, a channel narrowness degree, and a signal integrity degree.

[0058] With reference to the second aspect, in some implementations of the second aspect, the quality check option includes the STA, and the processing module is specifically configured to analyze the layout result in any one or more of the following: a circuit critical path, a transmission delay, a clock boundary, and a data arrival time at a receiving end, to obtain the layout quality check result.

[0059] With reference to the second aspect, in some implementations of the second aspect, the receiving module is specifically configured to receive the chip design information and the quality check option input by the user through a GUI or TCL.

[0060] The beneficial effects of the second aspect and any one of the possible implementations of the second aspect are corresponding to those of the first aspect and any one of the possible implementations of the first aspect, and thus are not described herein again.

[0061] In a third aspect, an embodiment of the present application provides a computer device, which includes a processor configured to be coupled with a memory, read and execute instructions and / or program codes in the memory, to execute the first aspect or any one of the possible implementations of the first aspect.

[0062] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores program codes, and when the computer storage medium is run on a computer, causes the computer to execute the first aspect or any one of the possible implementations of the first aspect.

[0063] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes computer program codes, and when the computer program codes are run on a computer, causes the computer to execute the first aspect or any one of the possible implementations of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0064] Figure 1 is a schematic diagram of a chip layout planning provided by an embodiment of the present application.

[0065] Figure 2 is a schematic diagram of an application scenario of a chip layout quality check method provided by an embodiment of the present application.

[0066] Figure 3 is an exemplary flowchart of a chip layout quality check method provided by an embodiment of the present application.

[0067] Figure 4 is a schematic diagram of an application architecture of a chip layout quality check provided by an embodiment of the present application.

[0068] Figure 5is a schematic diagram of a feedthrough provided by an embodiment of the present application.

[0069] Figure 6 is a schematic diagram of a chip layout result provided by an embodiment of the present application.

[0070] Figure 7 is a schematic diagram of another chip layout result provided by an embodiment of the present application.

[0071] Figure 8 is an exemplary flowchart of another chip layout quality checking method provided by an embodiment of the present application.

[0072] Figure 9 is a structural example diagram of a computer device provided by an embodiment of the present application.

[0073] Figure 10 is a structural example diagram of another computer device provided by an embodiment of the present application.

[0074] Figure 11 is an example diagram of a computer program product provided by an embodiment of the present application. DETAILED DESCRIPTION

[0075] The technical solutions in the embodiments of the present application will be described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work should fall within the protection scope of the present application.

[0076] In the embodiments of the present application, the words such as "example", "for example" are used to represent an example, illustration or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the word "example" is intended to present the concept in a specific manner.

[0077] The business scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those of ordinary skill in the art can know that, as new business scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0078] Reference in the specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" or "in some embodiments" in various places in the specification are not necessarily all referring to the same embodiment, although it can. The terms "including," "comprising," "having," and variations thereof are meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

[0079] In this application, "at least one" means one or more, "multiple" means two or more. "And / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the cases of A alone, A and B together, and B alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c, can represent a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0080] In order to facilitate the understanding of the embodiments of the present application, first, some definitions involved in the present application are simply explained.

[0081] 1. Electronic design automation (EDA): refers to the use of computer-aided design software to complete the functional design, synthesis, verification, physical design (including layout, routing, layout, design rule checking, etc.) of very large scale integrated circuit chips and other processes.

[0082] 2. Static timing analysis (STA): or static timing verification, is a work flow in electronic engineering to calculate and predict the timing of digital circuits. By analyzing the logic circuit and physical layout of the chip, the maximum operating frequency of the circuit, timing violations and potential timing problems can be determined.

[0083] 3. Advanced process node: represents a new manufacturing technology and process standard, usually with smaller transistor size, higher integration and lower power consumption. Common advanced process nodes currently include 7 nanometers (7nm), 5 nanometers (5nm) and 3 nanometers (3nm).

[0084] The integrated circuit floorplan, as an early step of integrated circuit physical design, has a significant impact on subsequent macro placement, clock tree synthesis (CTS), place and route (PnR), and thus the repair cost of a problem in the floorplan is increasingly large as the physical design process progresses. With increasingly complex design and manufacturing constraints, early checking of the quality of the floorplan of a chip and reporting of potential problems are of positive significance to improving the efficiency of the physical design process.

[0085] The floorplan refers to a reasonable arrangement of elements with a given interconnection relationship in a given chip area, so as to minimize the total bus length, the data flow length and / or the feedthrough between the elements. The floorplan is an important part of chip physical design, and mainly includes determining the shape and position of elements in the chip within a given chip frame, and making the layout of each element meet the chip design constraints, which is conducive to chip routing and timing convergence. The elements in the chip include blocks, cells and the like, wherein the cell refers to a standard cell or a macro cell, and the block includes at least one cell. Figure 1 is a schematic diagram of a chip floorplan provided by an embodiment of the present application. Among them, the interface dispatch unit (IDU), the bus exchange unit (BXU), the load-store unit (LSU), the integer execution unit (ISU), the floating-point execution unit (FXU) and the floating-point unit (FPU) are blocks of the chip.

[0086] Figure 2 is a schematic diagram of an application scenario of a chip floorplan quality checking method provided by an embodiment of the present application.

[0087] The chip floorplan quality checking method provided by the present application can be applied in EDA, and the automatic design of the chip floorplan in the chip physical design stage is performed by using the chip floorplan quality checking method provided by the present application. By reading in the chip design information, the layout result, the quality checking result and / or the optimization suggestion of the chip can be output.

[0088] Specifically, the chip layout quality checking method provided by the present application can be located in the layout planning step of the EDA tool. The layout planning is an initial step in physical design, which is used to receive the data of logic synthesis. The logic synthesis is a process of converting the high abstract level description of the designed digital circuit to the logic gate level circuit connection netlist after Boolean function simplification and optimization. The layout planning arranges the elements according to the element information and the netlist connection relationship in the chip to realize the optimal element layout and make the final power, performance and area (PPA) of the chip optimal under the condition of ensuring that all physical design constraints are met.

[0089] Figure 3 is an exemplary flowchart of a chip layout quality checking method provided by an embodiment of the present application.

[0090] 310, receiving the chip design information and the quality checking option input by a user.

[0091] The chip design information includes the shape of a plurality of blocks in the chip, the positions of the plurality of blocks, the connection relationship between the plurality of blocks, the shape of a plurality of cells and the connection relationship between the plurality of cells. The cell refers to a standard cell or a macro cell, and the block includes at least one cell.

[0092] The quality checking option includes any one or more of data flow checking, cell layout evaluation, congestion estimation and STA. The data flow checking is used to check the wire distance between a plurality of elements in the layout result of the chip, and the element includes a block or a cell. The cell layout evaluation is used to check the regularity of a plurality of cells in the layout result. The congestion estimation is used to estimate the congestion degree of the wire in the layout result. The STA is used to analyze the timing path in the layout result.

[0093] 320, determining the layout result of the chip according to the chip design information.

[0094] The layout result includes the positions of the plurality of cells, specifically, the positions of the macro cells and the standard cells. Exemplarily, the layout result can include the positions of the macro cells and / or the standard cells in each block.

[0095] Exemplarily, the layout result can be obtained according to the chip design information in an automated layout. In a possible implementation, weights corresponding to connection relationships between units can be extracted according to the chip design information, and a macro unit placement condition that minimizes an overall weight loss value when the chip is laid out can be solved to determine the placement position of the macro unit in the chip. In a possible implementation, the placement position of a standard unit in the chip can be determined according to a preset placement density constraint condition and connection relationships between a plurality of units. The placement density constraint condition includes that the placement density of some local standard units in the chip cannot exceed a preset threshold. In the case of satisfying the density constraint condition, a standard unit placement condition that minimizes the overall length of the routing between the standard units when the chip is laid out can be solved to determine the placement position of the standard unit in the chip.

[0096] 330, a layout quality inspection result of the chip is obtained according to the layout result and the inspection rule corresponding to the quality inspection option.

[0097] When the quality inspection option includes data flow inspection, the corresponding inspection rule includes checking the routing distance between a plurality of elements in the layout result according to weights corresponding to connection relationships between the plurality of elements.

[0098] When the quality inspection option includes unit layout evaluation, the corresponding inspection rule includes any one or more of the following: checking the layout symmetry degree of the macro unit or the standard unit in the layout result, checking the alignment of the macro unit or the standard unit in the horizontal or vertical direction, checking the layout uniformity degree of the macro unit or the standard unit in the layout result, and checking the layout density of the related plurality of macro units or the related plurality of standard units.

[0099] When the quality inspection option includes congestion estimation, the corresponding inspection rule includes any one or more of the following: checking the routing density, checking the channel narrowness degree, and checking the signal integrity degree.

[0100] When the quality inspection option includes STA, the corresponding inspection rule includes any one or more of the following: analyzing the circuit critical path, analyzing the transmission delay, analyzing the clock boundary, and analyzing the data arrival time at the receiving end.

[0101] In a possible implementation, the layout quality inspection result of the chip can include any one or more of the following: evaluation of the routing distance between elements, regularity of the macro unit, regularity of the standard unit, congestion map, congestion value, circuit critical path, and timing value.

[0102] Figure 4 FIG. 1 is a schematic diagram of an application architecture of chip layout quality inspection provided by an embodiment of the present application.

[0103] Exemplarily, the chip layout quality checking method provided in the application can be implemented in a systematic manner. A user can input chip design information and layout quality checking options to be performed in a layout quality checking user interface, and complete chip layout quality checking. The system background can call corresponding quality checking engines according to the user input. After quality checking, the layout quality checking result can be displayed on the interface, facilitating the user to view the quality of the current layout and improving the user experience.

[0104] The quality checking engine provided in the embodiments of the application includes but is not limited to a block shape and position checking engine, a pin placement checking engine, a feedthrough checking engine, a pin grouping checking engine, a data flow checking engine, a cell layout checking engine, a congestion estimation engine and a STA engine. The following is a specific description of the implementation manners of different quality checking engines:

[0105] (1) Block shape and position checking engine:

[0106] In the manufacturing process of a chip, the positions and shapes of various blocks in the chip are all subject to actual manufacturing process constraints, including but not limited to: 1. Under a fin field-effect transistor (FinFET) process, the shape vertex of a block needs to be on a grid point determined by the process; 2. Under an advanced process node, the length of a certain edge of a block needs to be a multiple of a preset value; 3. In block reuse and flipping, the instantiated object must meet the constraints 1 and 2; 4. The placement of all blocks must not overlap with each other; 5. The placement of a block must be within the range of a die.

[0107] In the chip layout quality checking method provided in the application, any one or more of the above constraints will be specifically modeled, and whether the corresponding constraint is met is checked based on the actual shape and position of each block, and whether reuse, flipping and other actual conditions are met. The related parameters of the corresponding manufacturing process can be preset by the system or manually configured by a person to realize customized checking. The final checking result can be displayed on the GUI and / or output a report file for the user to view.

[0108] (2) Pin placement checking engine:

[0109] In the actual layout planning in the chip manufacturing process, the positions of the pins of each block are subject to constraints caused by actual processes, including but not limited to: 1, the pins directly connected between blocks need to be aligned in a direction parallel to the horizontal plane or a direction perpendicular to the horizontal plane; 2, the pin arrangement of a multiplexing block needs to be consistent; 3, the wire winding direction of the metal layer where the pin is located needs to be perpendicular to the direction of the edge where the pin is located; 4, the pin needs to be aligned to the track of the process; 5, the metal layer where the pin is located meets the requirements of the manufacturing process.

[0110] The chip layout quality checking method provided in the present application specifically models any one or more of the above constraints and checks whether the corresponding constraints are met based on the placement of the pins. The relevant parameters of the manufacturing process can be preset by the system or manually customized for configuration to achieve customized checking. The final checking result can be displayed on the GUI and / or output to a report file for the user to view.

[0111] (3) Feedthrough checking engine:

[0112] Figure 5 is a schematic diagram of a feedthrough provided by an embodiment of the present application. Feedthrough refers to the process of obtaining a layout, if two blocks have a connection, but the blocks are not placed adjacent to each other or the length of the adjacent common edge cannot place all the pins, then the feedthrough technology needs to be used to connect the two blocks with a connection relationship but not adjacent to each other, and the additional connection is called a feedthrough. Assuming that BXU and ISU have 100 connection grids (nets), each grid is connected by a group of pins, but BXU and ISU are not placed adjacent to each other, so a feedthrough needs to be used to start from BXU, pass through the central processing unit (CPU), and reach ISU, which is usually represented as 100 feedthroughs from BXU to ISU.

[0113] The checks made by the embodiment of the present application on the feedthrough include but are not limited to: 1, checking whether all connections that need to establish a feedthrough have established the corresponding feedthrough; 2, checking whether all feedthroughs are in the layout result.

[0114] In the chip layout quality checking method provided in the present application, any one or more of the above constraints are specifically modeled, and it is checked whether the corresponding constraints are met. The final checking result can be displayed on the GUI and / or output to a report file for the user to view.

[0115] (4) Pin grouping checking engine:

[0116] In the chip physical design process, the grouping of pins has an important influence on the quality of the layout result. By arranging closely related pins in a group, the distance between them can be shortened, making their related logic more compact and improving PPA. In the embodiments of the present application, in combination with the actual physical location of the pins, the inspection of pin grouping includes but is not limited to: 1. The pins of a bus need to be grouped in the same group; 2. The pins connecting the same block need to be grouped in the same group; 3. The pins connecting different blocks need to be grouped in different groups.

[0117] The chip layout quality inspection method provided in the present application specifically models any one or more of the above constraints and checks whether the corresponding constraints are met. The final inspection result can be displayed on the GUI and / or output a report file for the user to view.

[0118] (5) Data flow inspection engine:

[0119] In the chip physical design process, the connection relationship between different elements largely determines the physical location of the elements. In the chip layout quality inspection method provided in the present application, by extracting and analyzing the connection relationship between elements in the chip design information, the weight corresponding to the connection relationship can be obtained to represent the connection tightness between different elements.

[0120] The chip layout result corresponding to the chip design information can be obtained through automatic layout, and the chip layout result includes the positions of the macro cells and the standard cells. The steps of automatic layout can refer to the description of step 320 in Figure 3 The embodiments of the present application will not be repeated. In combination with the weight and the distribution of different elements in the chip layout result, the quality of the current chip layout can be evaluated. In the embodiments of the present application, the design rule check (DRC) includes that the weight corresponding to the connection relationship between elements and the wire length between elements satisfy a mapping relationship, for example, the weight range and the wire length range are one-to-one corresponding.

[0121] Figure 6It is a schematic diagram of a chip layout result provided by an embodiment of the present application. Macrocell B3 is connected to macrocell B1 and macrocell B2. The weight of the connection relationship between macrocell B3 and macrocell B1 is 50, and the weight of the connection relationship between macrocell B3 and macrocell B2 is 80. For example, in the chip layout result, the length of the connection between macrocell B3 and macrocell B1 is 600 millimeters (mil), and the length of the connection between macrocell B3 and macrocell B2 is 510 mil. In the data flow DRC, the routing length corresponding to the weights of 45 to 55 is 400 to 500 mil, and the routing length corresponding to the weights of 75 to 85 is 100 to 200 mil. Since the routing length between B3 and B1 and B2 in the chip layout result exceeds the corresponding range, the data flow inspection result may be "the routing distance between B3 and B1 and B2 is too long."

[0122] Figure 6 Placing B3 away from B1 and B2 will result in a long routing distance, affecting chip performance. In the chip layout quality inspection method provided in this application, the data flow inspection results can be displayed in the GUI and / or report file. Optionally, the corresponding chip layout results and / or optimization suggestions can also be displayed to provide a layout reference for the user or the automated layout device. The user can modify the chip design information based on the inspection results, and the automated layout tool can adjust the layout plan based on the inspection results to minimize the connection cost between elements.

[0123] (6) Cell Layout Evaluation Engine:

[0124] The cell layout check engine includes a macro cell layout check engine and a standard cell layout check engine. Through automated layout, the chip layout result corresponding to the chip design information can be obtained. The chip layout result includes the location of macro cells and standard cells. The steps of automated layout can be found in Figure 3 The description of step 320 will not be repeated in this application. Figure 7 This is a schematic diagram of another chip layout result provided by an embodiment of the present application. It should be understood that the elements described in this application can be blocks, macro cells, or standard cells. A block can include any one or more macro cells or standard cells, and can also include ports.

[0125] In the embodiments of the present application, the macro cell layout checking engine can check the regularity of the macro cells in the chip layout result, and the standard cell layout checking engine can check the regularity of the standard cells in the chip layout result. The regularity can be checked in the following aspects: 1. symmetry, a regular layout usually has symmetry, that is, the macro cells or standard cells have symmetric positions and shapes relative to the center of the chip or other reference points, and the symmetric layout can improve the balance of signal transmission, reduce signal transmission delay and power consumption; 2. alignment, a regular layout usually aligns the macro cells or standard cells on a specific grid or boundary of the chip, so that they have consistent positions in the horizontal and vertical directions, and the aligned layout helps to simplify routing and timing optimization and reduce the signal transmission distance across macro cells or standard cells; 3. uniformity, a regular layout tries to maintain uniform spacing between macro cells or standard cells, so that they are evenly distributed on the chip, which helps to balance circuit load and signal transmission and avoid hot spot areas and electrical noise problems; 4. cluster group, a regular layout may organize related macro cells or standard cells into a cluster group or cluster, so that they are physically close and connected to each other, and the cluster group layout can promote local communication and data sharing and reduce long-distance signal transmission.

[0126] In the chip layout quality checking method provided by the present application, the regularity of the chip cell layout can be evaluated in any one or more of the above aspects. The final checking result can be displayed on the GUI and / or output a report file for the user to view.

[0127] (7) Congestion estimation engine:

[0128] The chip layout result corresponding to the chip design information can be obtained through automatic layout, and the chip layout result includes the positions of the macro cells and the standard cells. The steps of automatic layout can refer to the description of step 320 in the Figure 3 On the basis of the chip layout result, in combination with the connection relationship between the elements in the chip design information, the embodiments of the present application can complete the task of estimating the congestion degree of the wire in the chip, and display the related congestion map and / or congestion value in the GUI and / or output report.

[0129] The congestion degree can be estimated in the following aspects: 1. trace density, which refers to the number of traces in a unit area or the proportion of space occupied by traces. When the trace density of some areas is too high, it can cause crossing and interference between traces, making wiring more difficult and possibly affecting signal transmission performance; 2. channel narrowness, which means that the width of the horizontal and vertical channels available for wiring is limited, resulting in smaller spacing between traces, making wiring more difficult, and channel narrowness can also cause increased signal transmission delay and increased power consumption; 3. signal integrity, congestion of wiring can affect signal integrity. When the trace density is too high or the channel is narrow, signal coupling, crosstalk and electrical noise problems can be introduced, resulting in a decrease in signal integrity.

[0130] (8) STA engine:

[0131] The chip layout result corresponding to the chip design information can be obtained through automatic layout, and the chip layout result includes the positions of the macro cells and the standard cells. The steps of automatic layout can refer to the description of step 320 in Figure 3 The steps of automatic layout can refer to the description of step 320 in

[0132] Optionally, the user can also customize the quality check rules. The system supports function extension, and new check engines can be added according to user needs, for example, adding check functions integrating expert experience to improve chip design efficiency.

[0133] In a possible implementation manner, the embodiments of the present application can also provide optimization suggestions corresponding to the quality check results to guide manual or automatic layout devices to perform further layout iteration optimization and improve the efficiency of chip design.

[0134] Figure 8 is an exemplary flowchart of another chip layout quality checking method provided by the embodiments of the present application.

[0135] 810, obtaining chip design information.

[0136] The chip design information includes shapes of a plurality of blocks in the chip, positions of the plurality of blocks, connection relationships between the plurality of blocks, shapes of a plurality of cells, and connection relationships between the plurality of cells. A cell refers to a standard cell or a macro cell, and a block includes at least one cell. Exemplarily, the user can input the chip design information through a graphical user interface (GUI) or a tool command language (TCL).

[0137] In a possible implementation, the chip design information includes a design exchange format (DEF) file, a library exchange format (LEF) file, and a netlist file of a current level of the chip input by the user. Optionally, the chip design information can further include lib information, a Verilog file, and the like. The DEF file can be used to describe positions of blocks, the LEF file can be used to describe shapes of blocks and cells, and the netlist file can be used to describe connection relationships between blocks and cells.

[0138] 820, layout quality check.

[0139] The user can input layout quality check options to be performed through a GUI or a TCL command, and complete the chip layout quality check. After the quality check, the layout quality check result can be displayed on the interface.

[0140] Exemplarily, the user can inform the system to perform any one or more of the following checks through a GUI button or a TCL command: block shape and position check, pin placement check, feedthrough check, pin grouping check, data flow check, cell layout check, congestion estimation, and STA. The system calls corresponding quality check engines to complete the above quality check tasks, and the check result can be displayed on the GUI and / or an output report. For details of the specific check process, refer to the description in Figure 4 , which will not be repeated here.

[0141] 830, verify the check result.

[0142] The check result can include any one or more of a block shape and position check result, a pin placement check result, a feedthrough check result, a pin grouping check result, a data flow check result, a cell layout check result, a congestion estimation result, and a STA.

[0143] Optionally, the user can verify the check result, or the system can automatically verify the check result according to a pre-set program.

[0144] 840, determine whether the checking result meets the requirement.

[0145] If the checking result meets the requirement, perform step 850; if the checking result does not meet the requirement, perform step 860.

[0146] 850, output the chip layout result.

[0147] The chip layout result includes the positions of the macro cells and the standard cells. Optionally, the chip layout result can also include any one or more of the following: the connection relationship between the plurality of cells, the positions of the plurality of blocks, and the connection relationship between the plurality of blocks.

[0148] In a possible implementation, any one or more of the following can be displayed on the GUI or in the report: the chip layout result, the layout quality checking result, and the optimization suggestion corresponding to the layout quality checking result.

[0149] 860, design optimization.

[0150] In a possible implementation, the user can modify the chip design information according to the checking result, and repeat the iteration of the checking step until the chip layout result that meets the checking requirement is obtained.

[0151] In a possible implementation, the automatic layout device can modify the chip design information according to the checking result, and repeat the iteration of the checking step until the chip layout result that meets the checking requirement is obtained.

[0152] In a possible implementation, the embodiments of the present application can also provide the optimization suggestion corresponding to the quality checking result, to guide the manual or automatic layout device to perform further layout iteration optimization, and improve the efficiency of the chip design.

[0153] The above describes the chip layout quality checking method in the circuit design according to the embodiments of the present application. The apparatus and the device according to the embodiments of the present application are described below respectively in combination with Figure 9 and Figure 10 .

[0154] The embodiments of the present application also provide a computer storage medium, which stores program instructions. When the program is executed, the program can include some or all steps of the chip layout quality checking method in the circuit design according to the corresponding embodiments. Figure 3 , Figure 4 and Figure 8 .

[0155] Figure 9This is a diagram illustrating the structure of a computer device 1000 provided in an embodiment of the present application. The computer device 1000 includes a receiving module 1010 and a processing module 1020, and optionally, a display module 1030. The receiving module 1010, processing module 1020, and display module 1030 can be implemented in software, hardware, or a combination of both. Therefore, the computer device 1000 can be a computer simulation tool for chip layout quality inspection, such as an EDA software tool or related modules or devices equipped with such a tool.

[0156] The receiving module 1010 is used to receive chip design information and quality check options input by the user to perform Figure 3 310 and Figure 8 810 and 820 in the method.

[0157] The processing module 1020 is used to determine the layout result of the chip according to the chip design information, and obtain the layout quality inspection result of the chip according to the inspection rules corresponding to the layout result and the quality inspection options, and execute Figure 3 、 Figure 4 and Figure 8 Some or all of the steps in the method.

[0158] Figure 10 This is a diagram illustrating another example of the structure of a computer device 1300 provided in an embodiment of the present application. The computer device 1300 includes a processor 1302, a communication interface 1303, and a memory 1304. An example of the computer device 1300 is a computing device, such as a server for performing EDA simulation.

[0159] The method disclosed in the embodiments of the present application can be applied to the processor 1302 or implemented by the processor 1302. The processor 1302 can be a central processing unit (CPU), and can also be other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. In the implementation process, each step of the above method can be completed by the integrated logic circuit of hardware in the processor 1302 or the instruction in the form of software. The disclosed methods, steps and logic block diagrams in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware coding processor for execution, or a combination of hardware and software modules in the coding processor for execution.

[0160] The memory 1304 can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the nonvolatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct rambus RAM (DRRAM). Note that the memory of the methods described herein is intended to include, but not be limited to, these and any other suitable types of memory.

[0161] The processor 1302, the memory 1304, and the communication interface 1303 can communicate through a bus. The memory 1304 stores executable code, and the processor 1302 reads the executable code in the memory 1304 to execute the corresponding method. The memory 1304 can also include software modules required by other running processes such as an operating system. The operating system can be LINUX TM , UNIX TM , WINDOWS TM , etc.

[0162] For example, the executable code in the memory 1304 is used to implement the method shown in Figure 3 , Figure 4 and Figure 8 , and the processor 1302 reads the executable code in the memory 1304 to execute the method shown in Figure 3 , Figure 4 and Figure 8 .

[0163] In some embodiments of the application, the disclosed methods can be implemented as computer program instructions encoded on a computer-readable storage medium in machine-readable format or on other non-transitory media or articles of manufacture. Figure 11 A conceptual partial view of an example computer program product arranged in accordance with at least some embodiments presented herein is shown schematically, the example computer program product including a computer program for executing a computer process on a computing device. In one embodiment, the example computer program product 1400 is provided using a signal-bearing medium 1401. The signal-bearing medium 1401 can include one or more program instructions 1402, which, when executed by one or more processors, can provide the functionality or some portion of the functionality described in the methods shown above with respect to Figure 3 、 Figure 4 and Figure 8 Thus, for example, one or more features of the embodiments shown in Figure 3 、 Figure 4 and Figure 8 may be assumed by one or more instructions associated with the signal-bearing medium 1401.

[0164] In some examples, the signal bearing medium 1401 can comprise a computer- readable medium 1403, such as, but not limited to, a hard disk drive, a compact disk (CD), a digital video disk (DVD), a memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electronically erasable programmable read-only memory (EEPROM), a floppy disk, a zip disk, a magnetic tape, other forms of magnetic, semiconductor, or optical media, or any other medium appropriate for storing and / or communicating instructions and / or data. In some embodiments, the signal bearing medium 1401 can comprise a computer recordable medium 1404, such as, but not limited to, a floppy disk, a zip disk, a magnetic tape, a floppy disk drive, a zip disk drive, a magnetic tape drive, or other appropriate medium appropriate for recording and / or communicating instructions and / or data. In some embodiments, the signal bearing medium 1401 can comprise a communication medium 1405, such as, but not limited to, a floppy disk, a zip disk, a magnetic tape, a floppy disk drive, a zip disk drive, a magnetic tape drive, or other appropriate medium appropriate for recording and / or communicating instructions and / or data. Thus, for example, the signal bearing medium 1401 can embody the program instructions 1402 by being wirelessly communicated, for example, according to an IEEE 802.11 standard or other transmission protocol. The program instructions 1402 can be, for example, computer executable instructions or logic-implementing instructions. In some examples, the aforementioned computing device can be configured to provide various operations, functions, or acts, in response to program instructions 1402 conveyed to the computing device by one or more of the computer readable medium 1403, the computer recordable medium 1404, and / or the communication medium 1405. It should be understood that the arrangements described herein are for illustrative purposes only. As such, those skilled in the art will appreciate that other arrangements and other elements (e.g., machines, interfaces, functions, orders, and groupings of functions, etc.) can be used instead, and some elements can be omitted altogether according to the desired results. Additionally, many of the described elements can be implemented as functional entities that can be realized as discrete or distributed components, or in conjunction with other components, in any suitable combination and location.

[0165] Those skilled in the art can clearly understand that the units and method steps of various examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0166] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the devices and units described above can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0167] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented by other manners. For example, the apparatus embodiments described above are merely illustrative, for example, the division of the units is merely a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, apparatuses or units, and can be electrical, mechanical or other forms.

[0168] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e., can be located in one place or can be distributed to a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0169] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0170] The functions, if realized in the form of software functional units and sold or used as independent products, can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts of the prior art or the parts of the technical solutions can be embodied in the form of software products, and the computer software products are stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk, and various program code storage media.

[0171] The above is merely a specific implementation manner of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip layout quality inspection method in circuit design, characterized in that: include: Receive chip design information and quality check options input by a user, wherein the chip design information includes shapes of multiple blocks in the chip, positions of the multiple blocks, connection relationships between the multiple blocks, shapes of multiple cells, and connection relationships between the multiple cells, wherein the blocks include at least one cell, and the quality check options include any one or more of data flow check, cell layout evaluation, congestion estimation, and static timing analysis (STA). The data flow check is used to instruct to check the routing distances between multiple elements in the layout result of the chip, wherein the elements include the blocks or the cells. The cell layout evaluation is used to instruct to check the regularity of the multiple cells in the layout result. The congestion estimation is used to instruct to estimate the congestion level of the routing in the layout result. The STA is used to instruct to analyze the timing paths in the layout result. Determining the layout result of the chip according to the chip design information, wherein the layout result includes positions of the plurality of units; A layout quality inspection result of the chip is obtained according to the layout result and the inspection rules corresponding to the quality inspection options.

2. The method according to claim 1, characterized in that The method further comprises: Any one or more of the layout result, the layout quality check result, and the optimization suggestions corresponding to the layout quality check result are displayed on a graphical user interface (GUI) or in a report.

3. The method according to claim 1 or 2, characterized in that The quality inspection options further include any one or more of shape and position inspection of the plurality of blocks, pin placement inspection, feedthrough inspection, and pin grouping inspection.

4. The method according to claim 3, characterized in that The rules corresponding to the shape and position checks of the multiple blocks include any one or more of the following: the shape vertices of the blocks need to be on the grid points determined by the process, the lengths of the sides of the blocks at advanced process nodes are multiples of preset values, the reused or flipped instantiated objects of the blocks meet the constraints of the corresponding process, the placement of the multiple blocks does not overlap with each other, and the placement of the blocks is within the outer frame of the chip.

5. The method according to claim 3 or 4, characterized in that The rules corresponding to the pin placement check include any one or more of the following: the pins directly connected between the multiple blocks need to be aligned in a direction parallel to the horizontal plane or perpendicular to the horizontal plane, the pin arrangement of the multiplexing blocks needs to be consistent, the winding direction of the metal layer where the pins are located needs to be perpendicular to the direction of the edge where the pins are located, the pins need to be aligned to the routing corresponding to the process, and the metal layer where the pins are located meets the requirements of the manufacturing process.

6. The method according to any one of claims 3 to 5, characterized in that The rules corresponding to the feedthrough check include any one or more of the following: all connections requiring feedthroughs have corresponding feedthroughs established, and all feedthroughs are in the layout result.

7. The method according to any one of claims 3 to 6, characterized in that The rules corresponding to the pin grouping check include any one or more of the following: the pins of the bus need to be grouped in the same group, the pins connected to the same block need to be grouped in the same group, and the pins connected to different blocks need to be grouped in different groups.

8. The method according to any one of claims 1 to 7, characterized in that Determining the layout result of the chip according to the chip design information includes: determining placement positions of macro units in the layout result according to connection relationships between the multiple units and weights corresponding to the connection relationships between the multiple units; The placement positions of the standard cells in the layout result are determined according to the preset placement density constraint conditions and the connection relationship between the multiple cells.

9. The method according to any one of claims 1 to 8, characterized in that The quality check options include the data flow check, Obtaining a layout quality inspection result of the chip according to the layout result and the inspection rules corresponding to the quality inspection options includes: The routing distances between the multiple elements in the layout result are checked according to the weights corresponding to the connection relationships between the multiple elements to obtain the layout quality check result.

10. The method according to any one of claims 1 to 9, characterized in that The quality checking options include the cell layout evaluation, Obtaining a layout quality inspection result of the chip according to the layout result and the inspection rules corresponding to the quality inspection options includes: Perform any one or more of the following checks on the positions of the multiple units in the layout result to obtain the layout quality check result: the degree of layout symmetry in the layout result, the alignment in the horizontal or vertical direction, the uniformity of the layout in the layout result, and the layout density of the multiple associated units.

11. The method according to any one of claims 1 to 10, characterized in that The quality check options include the congestion estimate, Obtaining a layout quality inspection result of the chip according to the layout result and the inspection rules corresponding to the quality inspection options includes: Perform any one or more of the following checks on the layout result to obtain the layout quality check result: routing density, channel narrowness, and signal integrity.

12. The method according to any one of claims 1 to 11, characterized in that The quality check options include the STA, Obtaining a layout quality inspection result of the chip according to the layout result and the inspection rules corresponding to the quality inspection options includes: Perform any one or more of the following analyses on the layout results to obtain the layout quality inspection results: circuit critical path, transmission delay, clock boundary, and data arrival time at the receiving end.

13. The method according to any one of claims 1 to 12, characterized in that The receiving chip design information and quality check options input by the user includes: The chip design information and the quality check options input by the user through the GUI or the tool command language TCL are received.

14. A computer device, characterized in that: include: A receiving module, configured to receive chip design information and quality check options input by a user, wherein the chip design information includes shapes of multiple blocks in a chip, positions of the multiple blocks, connection relationships between the multiple blocks, shapes of multiple cells, and connection relationships between the multiple cells, wherein the blocks include at least one cell, and the quality check options include any one or more of data flow check, cell layout assessment, congestion estimation, and static timing analysis (STA). The data flow check is configured to instruct to check routing distances between multiple elements in a layout result of the chip, wherein the elements include the blocks or the cells. The cell layout assessment is configured to instruct to check the regularity of the multiple cells in the layout result. The congestion estimation is configured to instruct to estimate the congestion level of the routing in the layout result. The STA is configured to instruct to analyze the timing paths in the layout result. a processing module, configured to determine a layout result of the chip according to the chip design information, wherein the layout result includes positions of the plurality of units; The processing module is further configured to obtain a layout quality inspection result of the chip according to the layout result and inspection rules corresponding to the quality inspection options.

15. The device according to claim 14, characterized in that It also includes a display module for displaying any one or more of the layout results, the layout quality inspection results, and the optimization suggestions corresponding to the layout quality inspection results on a graphical user interface (GUI) or in a report.

16. The device according to claim 14 or 15, characterized in that The quality inspection options further include any one or more of shape and position inspection of the plurality of blocks, pin placement inspection, feedthrough inspection, and pin grouping inspection.

17. The device according to claim 16, characterized in that The rules corresponding to the shape and position checks of the multiple blocks include any one or more of the following: the shape vertices of the blocks need to be on the grid points determined by the process, the lengths of the sides of the blocks at advanced process nodes are multiples of preset values, the reused or flipped instantiated objects of the blocks meet the constraints of the corresponding process, the placement of the multiple blocks does not overlap with each other, and the placement of the blocks is within the outer frame of the chip.

18. The device according to claim 16 or 17, characterized in that The rules corresponding to the pin placement check include any one or more of the following: the pins directly connected between the multiple blocks need to be aligned in a direction parallel to the horizontal plane or perpendicular to the horizontal plane, the pin arrangement of the multiplexing blocks needs to be consistent, the winding direction of the metal layer where the pins are located needs to be perpendicular to the direction of the edge where the pins are located, the pins need to be aligned to the routing corresponding to the process, and the metal layer where the pins are located meets the requirements of the manufacturing process.

19. The device according to any one of claims 16 to 18, characterized in that The rules corresponding to the feedthrough check include any one or more of the following: all connections requiring feedthroughs have corresponding feedthroughs established, and all feedthroughs are in the layout result.

20. The device according to any one of claims 16 to 19, characterized in that The rules corresponding to the pin grouping check include any one or more of the following: the pins of the bus need to be grouped in the same group, the pins connected to the same block need to be grouped in the same group, and the pins connected to different blocks need to be grouped in different groups.

21. The device according to any one of claims 14 to 20, characterized in that The processing module is specifically used to: determining placement positions of macro units in the layout result according to connection relationships between the multiple units and weights corresponding to the connection relationships between the multiple units; The placement positions of the standard cells in the layout result are determined according to the preset placement density constraint conditions and the connection relationship between the multiple cells.

22. The device according to any one of claims 14 to 21, characterized in that The quality inspection option includes the data flow inspection, and the processing module is specifically configured to: The routing distances between the multiple elements in the layout result are checked according to the weights corresponding to the connection relationships between the multiple elements to obtain the layout quality check result.

23. The device according to any one of claims 14 to 22, characterized in that The quality check option includes the cell layout evaluation, and the processing module is specifically configured to: Perform any one or more of the following checks on the positions of the multiple units in the layout result to obtain the layout quality check result: the degree of layout symmetry in the layout result, the alignment in the horizontal or vertical direction, the uniformity of the layout in the layout result, and the layout density of the multiple associated units.

24. The device according to any one of claims 14 to 23, characterized in that The quality check option includes the congestion prediction, and the processing module is specifically configured to: Perform any one or more of the following checks on the layout result to obtain the layout quality check result: routing density, channel narrowness, and signal integrity.

25. The device according to any one of claims 14 to 24, characterized in that The quality check option includes the STA and the processing module, which are specifically configured to: Perform any one or more of the following analyses on the layout results to obtain the layout quality inspection results: circuit critical path, transmission delay, clock boundary, and data arrival time at the receiving end.

26. The device according to any one of claims 14 to 25, characterized in that The receiving module is specifically configured to receive the chip design information and the quality check options input by the user through the GUI or the tool command language TCL.

27. A computer device, characterized in that: include: A processor, wherein the processor is coupled to a memory, and is configured to read and execute instructions and / or program codes in the memory to perform the method according to any one of claims 1 to 13.

28. A computer-readable medium, characterized in that The computer-readable medium stores a computer program code, and when the computer program code is run on a computer, the computer is caused to perform the method according to any one of claims 1 to 13.

29. A computer program product, characterized in that The computer program product comprises a computer program code, which, when run on a computer, causes the computer to perform the method according to any one of claims 1 to 13.

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