Semiconductor device including two-dimensional material and method of manufacturing same

Abstract

Semiconductor devices including two-dimensional materials and methods of making the same are disclosed. The semiconductor device may include: a channel layer including a two-dimensional material layer and a molecular crystal layer on the two-dimensional material layer, the two-dimensional material layer including a two-dimensional semiconductor material; a source electrode and a drain electrode, which may be on both sides of the channel layer, respectively; and a gate insulating layer and a gate electrode, respectively, on the channel layer between the source electrode and the drain electrode. The molecular crystal layer may include a C20-C40 sheet aromatic compound, and may have a thickness of 1 to 5 molecular layers.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority from U.S. Provisional Application No. 63 / 575,973 filed in the U.S. Patent and Trademark Office on April 8, 2024, and Korean Patent Application No. 10-2024-0077756 filed in the Korean Intellectual Property Office on June 14, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices including two-dimensional materials and / or methods of fabricating the same. Background Art

[0004] As miniaturization progresses to increase the integration density of semiconductor devices, performance limitations due to scaling of 3D bulk materials may emerge. For example, in the case of a silicon channel, as the channel thickness decreases, mobility may decrease and the drift of the threshold voltage (Vth) may increase. As the channel length decreases, performance degradation due to short channel effects may increase.

[0005] To overcome these scaling limitations, research is underway using two-dimensional semiconductor materials. Channels made of two-dimensional semiconductor materials not only exhibit improved performance even at thicknesses of 1 nm or less, but can also have smaller short channel effects than silicon, thereby overcoming silicon's scaling limitations. Summary of the Invention

[0006] Provided are semiconductor devices including two-dimensional semiconductor materials and / or methods for manufacturing the same.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0008] According to example embodiments, a semiconductor device may include: a channel layer including a two-dimensional material layer and a molecular crystal layer on the two-dimensional material layer, the two-dimensional material layer including a two-dimensional semiconductor material; a source electrode and a drain electrode that may be on both sides of the channel layer, respectively; and a gate insulating layer and a gate electrode between the source electrode and the drain electrode on the channel layer. The molecular crystal layer may include C 20 -C 40 The plate-shaped aromatic compound may be a plate-shaped aromatic compound, and the thickness of the molecular crystal layer may be 1 to 5 molecular layers. The source electrode and the drain electrode may be on the channel layer. The source electrode and the drain electrode may be on the molecular crystal layer.

[0009] In some embodiments, the sheet-like aromatic compound may have semiconductor properties.

[0010] In some embodiments, the flaky aromatic compound may include a tetracene-based compound, a A compound based on benzo[9,10]phenanthrene, a pyrene, a perylene, a pentacene, a benzopyrene, a benzoperylene, or a coronene-based compound.

[0011] In some embodiments, the flaky aromatic compound may include at least one of a hydroxyl group, a carboxyl group, a carboxylic acid metal salt (metal carboxylate) group, an imide group, an amide group, and a carboxylic anhydride group.

[0012] In some embodiments, the molecular crystal layer may have a thickness of 1 to 3 molecular layers, for example, 1 to 2 molecular layers.

[0013] In some embodiments, the two-dimensional semiconductor material may have a band gap of 0.1 eV to 3.0 eV.

[0014] In some embodiments, the two-dimensional semiconductor material may include a transition metal dichalcogenide (TMD) or black phosphorus.

[0015] In some embodiments, the transition metal dichalcogenide (TMD) may include a metal element and a chalcogen element. The metal element may include at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, and Re. The chalcogen element may include at least one of S, Se, and Te.

[0016] In some embodiments, the transition metal dichalcogenide (TMD) may include MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReSe2, or any combination thereof.

[0017] In some embodiments, the two-dimensional material layer may include 1 to 10 molecular layers, such as 2 to 8 molecular layers, 3 to 7 molecular layers, or 4 to 6 molecular layers.

[0018] In some embodiments, the molecular crystal layer may have van der Waals interactions with the two-dimensional material layer.

[0019] In some embodiments, the molecular crystal layer may have crystallinity due to the crystal structure of the two-dimensional material layer.

[0020] In some embodiments, the two-dimensional material layer may have a polycrystalline structure.

[0021] In some embodiments, the channel layer may include a first region overlapping the gate electrode and second region(s) overlapping the source electrode and the drain electrode.

[0022] In some embodiments, the material of the two-dimensional material layer in the first region of the channel layer may be different from the material of the two-dimensional material layer in the second region of the channel layer.

[0023] In some embodiments, the electrical conductivity (electrical conductivity) of the two-dimensional material layer in the second region of the channel layer may be greater than or equal to the electrical conductivity of the two-dimensional material layer in the first region of the channel layer.

[0024] In some embodiments, the two-dimensional material layer in the second region of the channel layer may further include a p-type dopant or an n-type dopant.

[0025] In some embodiments, the molecular crystal layer of the second region of the channel layer may include a material configured to provide a p-type dopant or an n-type dopant to the two-dimensional material layer of the second region of the channel layer.

[0026] In some embodiments, the material configured to provide a p-type dopant or an n-type dopant may include a sheet-like aromatic compound including metal ions.

[0027] In some embodiments, the semiconductor device may have a planar FET structure, a fin FET (FinFET) structure, a gate-all-around FET (GAA FET) structure, or a complementary FET (CFET) structure.

[0028] According to an embodiment, an electronic device may include the semiconductor device.

[0029] According to example embodiments, a method of manufacturing a semiconductor device may include forming a channel layer on a substrate, the forming the channel layer including forming a two-dimensional material layer including a two-dimensional semiconductor material on the substrate, and forming a C 20 -C 40 a molecular crystal layer of a sheet-like aromatic compound; forming a gate insulating layer and a gate electrode on the channel layer; and forming a source electrode and a drain electrode on both sides of the channel layer, respectively.

[0030] In some embodiments, the sheet-like aromatic compound may have semiconductor properties.

[0031] In some embodiments, the flaky aromatic compound may include a tetracene-based compound, a A compound based on benzo[9,10]phenanthrene, a pyrene, a perylene, a pentacene, a benzopyrene, a benzoperylene, or a coronene-based compound.

[0032] In some embodiments, the flaky aromatic compound may include at least one of a hydroxyl group, a carboxyl group, a metal carboxylate group, an imide group, an amide group, and a carboxylic anhydride group (eg, an acetic anhydride group).

[0033] In some embodiments, the molecular crystal layer may have a thickness of 1 to 3 molecular layers.

[0034] In some embodiments, the two-dimensional semiconductor material may include a transition metal dichalcogenide (TMD) or black phosphorus.

[0035] In some embodiments, the two-dimensional material layer may include 1 to 10 molecular layers.

[0036] In some embodiments, the molecular crystal layer can be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or evaporation.

[0037] In some embodiments, the channel layer may include a first region and a second region. The first region of the channel layer may overlap with the gate electrode, and the second region of the channel layer may overlap with the source electrode and the drain electrode, respectively.

[0038] In some embodiments, the material of the two-dimensional material layer in the first region of the channel layer may be different from the material of the two-dimensional material layer in the second region of the channel layer.

[0039] In some embodiments, a material of the molecular crystal layer of the first region of the channel layer may be different from a material of the molecular crystal layer of the second region of the channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other aspects, features and advantages of example embodiments of the present disclosure will become more apparent from the following description considered in conjunction with the accompanying drawings, in which:

[0041] Figure 1 is a cross-sectional view of a semiconductor device 100 according to one embodiment.

[0042] Figure 2 is a conceptual diagram of the channel layer 130 according to one embodiment.

[0043] Figure 3 Molecular model diagrams of PDI, Me-PDI, and PTCDA are shown, which are examples of compounds having a phenylene body among sheet-like aromatic compounds capable of forming the molecular crystal layer 120 .

[0044] Figures 4A to 4CScanning tunneling microscopy (STM) images of PDI, Me-PDI, and PTCDA layers deposited on MoS2 layers on Si / SiO2 substrates (left) and molecular arrangement (placement) maps inferred from the STM images (right).

[0045] Figure 5A shows a scanning electron microscope (SEM) image of the upper surface of a MoS2 / HfO2 stacked structure on a Si / SiO2 substrate, and Figure 5B SEM image showing the top surface of the MoS2 / PDI / HfO2 stacked structure on a Si / SiO2 substrate.

[0046] Figures 6A to 6D Atomic force microscopy (AFM) images of MoS2 layer structure, MoS2 / HfO2 layer structure, MoS2 / PTCDA layer structure and MoS2 / PTCDA / HfO2 layer structure on Si / SiO2 substrate are shown respectively.

[0047] Figures 7A to 7E is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment.

[0048] Figure 8 is a schematic cross-sectional view of a semiconductor device 200 according to another embodiment.

[0049] Figure 9 is a schematic cross-sectional view of a semiconductor device 300 according to another embodiment.

[0050] Figure 10A is a perspective view schematically showing a semiconductor device (FinFET, 500) according to another embodiment, and Figure 10B It is along Figure 10A A cross-sectional view taken along line AA'.

[0051] Figure 11A is a perspective view schematically showing a semiconductor device (MBCFET, 600) according to another embodiment, and Figure 11B It is along Figure 11A A cross-sectional view taken along line BB'.

[0052] Figure 12 is a conceptual diagram of a channel layer 630 ′ according to another embodiment.

[0053] Figure 13 and 14 FIG. 1 is a conceptual diagram schematically illustrating an electronic device architecture applicable to an electronic apparatus according to an embodiment. DETAILED DESCRIPTION

[0054] Embodiment will now be described in detail, and its example is shown in the accompanying drawings, wherein similar reference numerals refer to similar elements from time to time. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the following description of the embodiment is to illustrate aspects only by reference to the accompanying drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. When stating, for example, "at least one (individual) of" before or after the list of elements, the entire list of elements is modified and the individual elements of the list are not modified. For example, "at least one (individual) of A, B and C" and similar language (for example, "at least one (individual) selected from A, B and C" and "at least one (individual) of A, B or C") can be interpreted as only A, only B, only C, or any combination of two (individual) or more (individual) of A, B and C, such as ABC, AB, BC and AC.

[0055] When the terms "about" or "substantially" are used in this specification with respect to a numerical value, it is intended that the relevant numerical value include a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words "substantially" and "substantially" are used with respect to a geometric shape, it is intended that the precision of the geometric shape is not required, but rather that the tolerance for the shape is within the scope of the present disclosure. Furthermore, regardless of whether a numerical value or shape is modified with "about" or "substantially," it will be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value or shape. When a range is specified, the range includes all values ​​therebetween, for example, in increments of 0.1%.

[0056] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the following figures, like reference numerals refer to like components, and the dimensions of the components in the drawings may be exaggerated for clarity and ease of description. The embodiments described below are presented as non-limiting examples only, and various modifications are possible from these embodiments.

[0057] Hereinafter, the term "above" or "on" may include not only things that are directly above, below, on the left, or on the right in contact, but also things that are indirectly above, below, on the left, or on the right without contact. In addition, unless the context clearly dictates otherwise, a singular expression includes a plural expression. Furthermore, when a part (part) is said to "include" a component (component), this does not mean that it excludes other components (components), but rather that it may include other components (components), unless otherwise specifically stated.

[0058] The use of the term "above" and similar reference terms in the description may refer to both the singular and the plural. Unless the steps constituting the method are explicitly described in order or described to the contrary, the steps may be performed in any suitable order and are not necessarily limited to the order described.

[0059] In addition, terms such as “part (section)”, “module” and the like described in the specification mean a unit that performs at least one function or operation, which can be implemented by hardware or software or by a combination of hardware and software.

[0060] The line connections or connecting members between components shown in the drawings illustratively represent functional connections and / or physical or circuit connections, and may represent alternative or additional various functional connections, physical connections or circuit connections in an actual device.

[0061] Herein, when the term "monolayer" is used to describe a molecular crystal layer, it means a "mono-molecular layer."

[0062] Any use of examples is intended only to describe the technical ideas in detail and is not intended to limit the scope of the present disclosure unless otherwise defined by the claims.

[0063] Figure 1 is a cross-sectional view of a semiconductor device 100 according to one embodiment. Figure 1 The semiconductor device 100 shown in FIG. 1 may be, for example, a field effect transistor (FET).

[0064] refer to Figure 1 The channel layer 130 is provided on the substrate 101. The substrate 101 may include various materials such as semiconductor materials, insulating materials, and metal materials. The substrate 101 may also be a substrate for growing a two-dimensional semiconductor material of the channel layer 130 to be described later.

[0065] The channel layer 130 may include a two-dimensional material layer 110 and a molecular crystal layer 120. The two-dimensional material layer 110 may include a two-dimensional semiconductor material. A two-dimensional semiconductor material refers to a semiconductor material having a two-dimensional crystal structure and may have a layered structure. Each layer constituting the two-dimensional semiconductor material may have a thickness at the atomic level. For example, the two-dimensional semiconductor material may include 1 to 3 atomic layers. The two-dimensional semiconductor material may have excellent electrical properties in the horizontal direction and may maintain high mobility without significant changes in its properties even when its thickness is reduced to the nanoscale.

[0066] The two-dimensional semiconductor material may include a material having a band gap of approximately 0.1 eV or greater and 3.0 eV or less. For example, the two-dimensional semiconductor material may include, but is not limited to, transition metal dichalcogenides (TMDs).

[0067] TMDs are two-dimensional materials with semiconductor properties and are compounds of transition metals and chalcogens. Here, the transition metal may include, for example, at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Co, Tc, and Re, and the chalcogen may include, for example, at least one of S, Se, and Te. As specific examples, TMDs may include, but are not limited to, MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReSe2, and the like.

[0068] The two-dimensional material layer 110 may include (or consist of), for example, 1 to 10 layers or 1 to 5 layers of two-dimensional semiconductor material, but the present disclosure is not limited thereto. The two-dimensional material layer 110 may have a thickness of, for example, about 0.1 nm to about 1 nm.

[0069] The molecular crystal layer 120 is a layer including molecular crystals and is provided on the two-dimensional material layer 110. The molecular crystals may be made of a sheet-like aromatic compound. A sheet-like aromatic compound refers to an aromatic compound having a two-dimensional structure. The sheet-like aromatic compound of this embodiment may be, for example, C 20 -C 40 The flaky aromatic compound may include, for example, a tetracene-based compound, a The flaky aromatic compound may contain, for example, a hydroxyl group, a carboxyl group, a metal carboxylate group, an imide group, an amide group, or a carboxylic anhydride group.

[0070] Examples of the flaky aromatic compound may include, but are not limited to, PDI (perylene diimide), Me-PDI (N,N′-dimethyl-3,4,9,10-perylenetetracarboxylic diimide), or PTCDA (perylenetetracarboxylic dianhydride).

[0071] The molecular crystal layer 120 may have a thickness of, for example, 1 to 5 molecular layers, or 1 to 3 molecular layers. The molecular crystal layer 120 may have a thickness of, for example, about 0.1 nm to about 0.5 nm.

[0072] Figure 2 FIG is a conceptual diagram of a channel layer 130 according to an embodiment. Figure 2 , the molecular crystal layer 120 is formed on the two-dimensional material layer 110, and both the two-dimensional material layer 110 and the molecular crystal layer 120 are formed as a single layer. Figure 2In the figure, each spherical shape represents an element constituting the two-dimensional semiconductor material and the sheet-like aromatic compound. Since molecular crystal layer 120 is made of the sheet-like aromatic compound according to the embodiment, it can have crystallinity on two-dimensional material layer 110 due to the crystal structure of two-dimensional material layer 110. Molecular crystal layer 120 has a crystal structure in which the sheet-like aromatic compound is regularly arranged (e.g., in a specific pattern), and its crystal size can be smaller than or equal to the crystal size of two-dimensional material layer 110.

[0073] Figure 3 The molecular model diagrams of PDI, Me-PDI, and PTCDA are shown. PDI, Me-PDI, and PTCDA are examples of compounds having a phenylene main body among the sheet-like aromatic compounds capable of forming the molecular crystal layer 120. Figure 3 From the molecular model diagram, it can be expected that PDI, Me-PDI and PTCDA molecules each have an overall sheet-like shape and are stacked in layers. The difference between PDI, Me-PDI and PTCDA is that the ends of the molecules (circled) have an imide group, a methylimide group and a carboxylic anhydride group, respectively.

[0074] Figures 4A to 4C STM images (left) and molecular arrangements inferred from the STM images (right) of PDI, Me-PDI, and PTCDA layers on a MoS2 layer deposited on a Si / SiO2 substrate. The MoS2 layer was deposited as a single layer by MOCVD on a 2-inch silicon (Si) wafer substrate with a silicon insulating layer (SiO2) formed thereon, and the PDI, Me-PDI, and PTCDA layers were each deposited as single layers on the MoS2 layer by evaporation.

[0075] refer to Figures 4A to 4C It seems that the molecules of PDI, Me-PDI and PTCDA layers are regularly arranged on the MoS2 layer. This confirms that the PDI, Me-PDI and PTCDA layers are crystalline. Figures 4A to 4C As shown in Figure 1, the PDI layer has a brick-wall arrangement, the Me-PDI layer has a canted arrangement, and the PTCDA layer has a herringbone arrangement. The differences in the molecular arrangements of the PDI, Me-PDI, and PTCDA layers are believed to be due to differences in the shapes of the ends of these molecules.

[0076] Compared to silicon channels, channels made of two-dimensional semiconductor materials can scale better, but due to their atomic-level thickness (e.g., three-atom-thick layers in the case of transition metal dichalcogenides), they can be damaged during device fabrication processes. Furthermore, since dangling bonds may not exist on the surface of a two-dimensional semiconductor material, it can be difficult to deposit additional materials as a thin, uniform layer on a channel made of a two-dimensional semiconductor material via a dangling bond pathway. When metal for source / drain contacts is deposited on a two-dimensional semiconductor material channel, damage to the channel can increase contact resistance. Furthermore, it may be desirable to deposit a thinner and more uniform high-dielectric gate insulator between the channel and the gate electrode, but non-uniform deposition of the gate insulator can limit scaling of the equivalent oxide thickness (EOT). Furthermore, due to damage that can occur in the channel during formation of the gate insulator, the interface trap density can increase.

[0077] The molecular crystal layer of the present embodiment can be deposited thinner and more uniformly as a layer (e.g., a monolayer) having crystallinity on a two-dimensional semiconductor material layer due to its structural characteristics of a molecular crystal. Therefore, in the transistor manufacturing process, the presence of the molecular crystal layer on the two-dimensional semiconductor material layer enables the source / drain metal structure or the gate stack structure to be formed thinner and more uniformly. In addition, the molecular crystal layer may have improved chemical and thermal stability, so that when a structure is formed on the two-dimensional semiconductor material layer, the two-dimensional semiconductor material layer can be protected. Due to the small thickness of the molecular crystal layer, even when it is used as an insertion layer on the two-dimensional semiconductor material layer, there may be no deterioration in device characteristics.

[0078] Reference again Figure 1 The source electrode 151 and the drain electrode 152 may be disposed on both sides of the channel layer 130. The gate insulating layer 140 may be disposed on the channel layer 130 between the source electrode 151 and the drain electrode 152. The gate electrode 160 may be disposed on the gate insulating layer 140.

[0079] The gate insulating layer 140 may include silicon oxide (SiO 2 ), silicon nitride (SiN), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), and / or lanthanum oxide (La 2 O 3 ), but the present disclosure is not limited thereto. The gate insulating layer 140 may have a thickness of, for example, about 2 nm to about 20 nm, or, for example, about 2 nm to about 10 nm.

[0080] The gate electrode 160 may include a metal material or a conductive oxide. Here, the metal material may include at least one selected from Au, Ti, TiN, TaN, W, Mo, WN, Pt, and Ni. The conductive oxide may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), etc. However, this is merely illustrative.

[0081] The source electrode 151 and the drain electrode 152 may be respectively disposed at both sides of the gate electrode 160. The source electrode 151 and the drain electrode 152 are respectively disposed in the source region and the drain region of the channel layer 130. Here, the source electrode 151 may be disposed to contact the source region of the channel layer 130, and the drain electrode 152 may be disposed to contact the drain region of the channel layer 130. The source electrode 151 and the drain electrode 152 may include a metal material having excellent conductivity, such as Ag, Au, Pt, or Cu, but the present disclosure is not limited thereto.

[0082] Figure 5A shows an SEM image of the upper surface of a MoS2 / HfO2 stacked structure on a Si / SiO2 substrate, and Figure 5B The SEM image of the upper surface of the MoS2 / PDI / HfO2 stacked structure on the Si / SiO2 substrate is shown. Figure 5A In the stacked structure, the MoS2 layer is deposited as a single layer, and the HfO2 layer is deposited with a thickness of 10 nm. Figure 5B In the stacked structure, the MoS2 layer and the PDI layer are each deposited as a single layer, and the HfO2 layer is deposited with a thickness of 10 nm. In this case, the MoS2 layer has a thickness of about 1 nm, and the PDI layer has a thickness of about 0.5 nm.

[0083] refer to Figure 5A , in the MoS2 / HfO2 stacked structure in which the HfO2 layer is deposited on the MoS2 layer with a thickness of 10 nm, there are portions where HfO2 is not deposited (black portions) and portions where HfO2 is thickly deposited (white portions), thus indicating that HfO2 is not uniformly deposited on the MoS2 layer. Figure 5B , in the MoS2 / PDI / HfO2 stacked structure in which a PDI layer is formed on a MoS2 layer, the SEM image shows an overall uniform color distribution, thus indicating that HfO2 is more uniformly deposited.

[0084] Figures 6A to 6D AFM images of MoS2 layer structure, MoS2 / HfO2 layer structure, MoS2 / PTCDA layer structure and MoS2 / PTCDA / HfO2 layer structure on Si / SiO2 substrate are shown respectively. 6A to 6D In each of the structures, a MoS2 layer is formed as a single layer, an HfO2 layer is deposited with a thickness of 3 nm, and PTCDA is formed as a single layer. Figures 6A to 6D In the figure, the images on the left and right are images of the same object, wherein the image on the left is an image based on the difference in surface height, and the image on the right is an image based on the difference in surface material (difference in phase). Figures 6A to 6D, it can be seen that the differences in surface height and phase of the MoS2 / PTCDA / HfO2 layer structure are smaller than those of the MoS2 / HfO2 layer structure, and therefore the surface height and phase appear more uniform.

[0085] Table 1 shows the area capacitance values ​​(μF / cm2) measured for the HfO2 layer, MoS2+HfO2 layer, and MoS2+PDI+HfO2 layer according to the thickness of HfO2. 2 ). The area capacitance was measured by placing the structures in Table 1 between metal electrodes (gold). In Table 1, the effective oxide thickness indicates the thickness of SiO2 that has the same capacitance as HfO2.

[0086] In the MoS2+HfO2 layer and the MoS2+PDI+HfO2 layer, MoS2 and PDI are each formed as a single layer, and HfO2 is formed with the thickness values ​​shown in Table 1. Referring to Table 1, in the structure of MoS2+HfO2, capacitance was measured only when HfO2 was formed to a maximum thickness of 34nm, and capacitance was not measured due to short circuit when HfO2 was formed to a thickness of 13nm, 7nm, and 3nm. This means that as the thinner the HfO2 layer is formed on the MoS2 layer, the more parts where HfO2 is not formed are present. On the other hand, in the structure of MoS2+PDI+HfO2, when PDI is formed on the MoS2 layer, capacitance is measured for HfO2 of all thicknesses, and they are almost the same as the capacitance values ​​of a single HfO2 layer. This shows that thinner HfO2 can be more reliably formed in the structure of MoS2+PDI+HfO2.

[0087] [Table 1]

[0088]

[0089] Hereinafter, a method of manufacturing the above-described semiconductor device 100 according to an embodiment will be described. Figure 7A 1 to 2 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment.

[0090] refer to Figure 7A , a two-dimensional material layer 110 may be formed on a substrate 101. The substrate 101 may include various materials such as a semiconductor material, an insulating material, and / or a metal material. Here, the two-dimensional material layer 110 may be formed by depositing and growing a two-dimensional semiconductor material on the surface of the substrate 101. The deposition of the two-dimensional semiconductor material may be performed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., but example embodiments are not limited thereto.

[0091] TMDs are two-dimensional materials with semiconductor properties and are compounds of transition metals and chalcogens. Here, the transition metal may include, for example, at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Co, Tc, and Re, and the chalcogen may include, for example, at least one of S, Se, and Te. Specific examples of TMDs may include MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReSe2, and the like. However, example embodiments are not limited thereto.

[0092] The two-dimensional material layer 110 may have a single layer or a multilayer structure, wherein each layer may have a thickness at the atomic level. The two-dimensional material layer 110 may include, for example, 1 to 10 layers. For example, the two-dimensional material layer 110 may include 1 to 5 layers. However, example embodiments are not limited thereto.

[0093] refer to Figure 7B , a molecular crystal layer 120 is deposited on the two-dimensional material layer 110 to form a channel layer 130. The molecular crystal layer 120 may be made of C 20 -C 40 The sheet-like aromatic compound may include, for example, a tetracene-based compound, a The flaky aromatic compound may include, for example, a hydroxyl group, a carboxyl group, a metal carboxylate group, an imide group, an amide group, or a carboxylic anhydride group. Examples of the flaky aromatic compound include, but are not limited to, PDI (perylene diimide), Me-PDI (N,N'-dimethyl-3,4,9,10-perylenetetracarboxylic diimide), or PTCDA (perylenetetracarboxylic dianhydride).

[0094] The molecular crystal layer 120 may be formed to a thickness of, for example, 1 to 5 molecular layers or 1 to 3 molecular layers. The molecular crystal layer 120 may have a thickness of, for example, about 0.1 nm to about 0.5 nm.

[0095] refer to Figure 7C , a gate insulating layer 140 is deposited on the molecular crystal layer 120. The gate insulating layer 140 may be formed of at least one of silicon oxide (SiO2), silicon nitride (SiN), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), and lanthanum oxide (La2O3), for example, but the present disclosure is not limited thereto. The gate insulating layer 140 may be formed to a thickness of, for example, about 2 nm to about 20 nm, or about 2 nm to about 10 nm.

[0096] refer to Figure 7D , a gate electrode 160 is formed on the gate insulating layer 140. The gate electrode 160 may be formed of a metal material or a conductive oxide. The metal material may include at least one selected from Au, Ti, TiN, TaN, W, Mo, WN, Pt, and Ni. The conductive oxide may include, for example, at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and the like. However, this is merely illustrative.

[0097] refer to Figure 7E , a source electrode 151 and a drain electrode 152 are formed on both sides of the channel layer 130. The source electrode 151 and the drain electrode 152 are respectively disposed in the source region and the drain region of the channel layer 130. The source electrode 151 may be disposed to contact the source region of the channel layer 130, and the drain electrode 152 may be disposed to contact the drain region of the channel layer 130.

[0098] Figure 8 2 is a schematic cross-sectional view of a semiconductor device 200 according to another embodiment. Hereinafter, differences from the above-described embodiment will be mainly described.

[0099] refer to Figure 8 The two-dimensional material layer 210 may include a first region 210a and second regions 210b disposed on both sides of the first region 210a. The first region 210a of the two-dimensional material layer 210 may be located at the center of the two-dimensional material layer 210. The first region 210a of the two-dimensional material layer 210 may be a channel region corresponding to the gate electrode 160. The second region 210b of the two-dimensional material layer 210 may be a source region and a drain region corresponding to the source electrode 151 and the drain electrode 152.

[0100] In the present embodiment, the first region 210a of the two-dimensional material layer 210 and the second region 210b of the two-dimensional material layer 210 can be made of different materials from each other. For example, the two-dimensional semiconductor material of the second region 210b of the two-dimensional material layer 210 can have higher conductivity (electrical conductivity) than the two-dimensional semiconductor material of the first region 210a of the two-dimensional material layer 210. For example, the two-dimensional semiconductor material of the second region 210b of the two-dimensional material layer 210 can be a two-dimensional semiconductor material doped with an n-type dopant or a p-type dopant. As the p-type dopant and the n-type dopant, for example, a p-type dopant and an n-type dopant used in graphene or a carbon nanotube (CNT) can be used. Nb can be used as the p-type dopant, but the present disclosure is not limited thereto. Re can be used as the n-type dopant, but the present disclosure is not limited thereto. The p-type dopant or the n-type dopant can be doped by ion implantation or chemical doping. Alternatively, the two-dimensional semiconductor material of the second region 210b of the two-dimensional material layer 210 can be, for example, graphene or a metallic two-dimensional material. 1T-MoS2 or PtSe2 can be used as the metallic two-dimensional material, but the present disclosure is not limited thereto. The contact resistance can be improved by increasing the conductivity of the second region 210b, thereby improving the device performance.

[0101] Figure 9 is a schematic cross-sectional view of a semiconductor device 300 according to another embodiment. In the following, differences from the above-described embodiments will mainly be described.

[0102] Reference Figure 9 The molecular crystal layer 320 can include a first region 320a and second regions 320b provided at both sides of the first region 320a. The first region 320a of the molecular crystal layer 320 can be located at a central portion of the molecular crystal layer 320. The first region 320a of the molecular crystal layer 320 can be a channel region corresponding to the gate electrode 160. The second regions 320b of the molecular crystal layer 320 can be source and drain regions corresponding to the source electrode 151 and the drain electrode 152.

[0103] In the present embodiment, the first region 320a of the molecular crystal layer 320 and the second regions 320b of the molecular crystal layer 320 can be made of different materials from each other. In the embodiment, the sheet-like aromatic compound of the second regions 320b of the molecular crystal layer 320 can include a compound capable of modulating the second regions 210b of the doped two-dimensional material layer 210. For example, to modulate the doping, the second regions 320b can include a sheet-like aromatic compound including a metal ion. Examples of the metal ion can include Al 3+ , Mg 2 + , Mn 2+ , Zn 2+ , Co 2+ , Fe 3+ , Ni2+ and the like.

[0104] The conductivity of the second region 210b of the two-dimensional material layer 210 can be increased by modulating the doping, thereby improving the contact resistance and thus improving the device performance. In an embodiment, the first region 320a of the molecular crystal layer 320 can not be doped.

[0105] In the above-described embodiments, the semiconductor devices 100 to 300 having a planar structure are described as examples. However, the present disclosure is not limited thereto, and for example, a semiconductor device having a fin field effect transistor (FinFET) structure, or a semiconductor device having a gate-all-around FET (GAA FET) (e.g., a multi-bridge channel FET (MBCFET)) or a complementary field effect transistor (CFET) (e.g., a vertical CFET) structure can be provided.

[0106] Figure 10A is a perspective view schematically showing a semiconductor device (FinFET, 500) according to another embodiment, and Figure 10B is a cross-sectional view taken along the line A-A' of Figure 10A .

[0107] Referring to Figure 10A and 10B , the insulator 505 is provided on the substrate 501 and can be perpendicular to the substrate 501, and the channel layer 530 can be provided to cover the insulator 505. Here, the channel layer 530 can have a fin shape.

[0108] The channel layer 530 can include a two-dimensional material layer 510 and a molecular crystal layer 520. For the two-dimensional material layer 510 and the molecular crystal layer 520, reference is made to the above-described two-dimensional material layer 110 and the molecular crystal layer 120.

[0109] The two-dimensional material layer 510 can include a first region 510a and second regions 510b provided at both sides of the first region 510a. Similarly, the molecular crystal layer 520 can include a first region 520a and second regions 520b provided at both sides of the first region 520a.

[0110] Three sides of the first region 510a of the two-dimensional material layer 510 and three sides of the first region 520a of the molecular crystal layer 520 are surrounded by the gate electrode 560, and can become a channel region. The second regions 510b of the two-dimensional material layer 510 and the second regions 520b of the molecular crystal layer 520 are located outside the gate electrode 560, and can become a source / drain region.

[0111] The gate insulating layer 540 is provided between the gate electrode 560 and the first region 520a of the molecular crystal layer 520. The gate insulating layer 540 is provided to surround three sides of the channel layer 530, specifically, the first region 520a of the molecular crystal layer 520, and the gate electrode 560 may be provided to surround three sides of the gate insulating layer 540. Although not shown in the figure, the source electrode and the drain electrode may be provided in the second region 520b of the molecular crystal layer 520.

[0112] In one embodiment, the first region 510a of the two-dimensional material layer 510 and the second region 510b of the two-dimensional material layer 510 may be made of different materials. For example, the two-dimensional semiconductor material of the second region 510b of the two-dimensional material layer 510 may have a higher conductivity than the two-dimensional semiconductor material of the first region 510a of the two-dimensional material layer 510. In this regard, reference is made to the above description of the two-dimensional semiconductor material. Figure 8 The channel layer 230 is similar to those described above.

[0113] In another embodiment, the first region 520a of the molecular crystal layer 520 and the second region 520b of the molecular crystal layer 520 may be made of different materials. For example, the sheet-like aromatic compound of the second region 520b of the molecular crystal layer 520 may include a compound capable of modulation-doping the second region 510b of the two-dimensional material layer 510. The first region 520a of the molecular crystal layer 520 may not be doped. In this regard, reference is made to the above description of Figure 9 The channel layer 330 is as described above.

[0114] Figure 11A is a perspective view schematically showing a semiconductor device (MBCFET, 600) according to another embodiment, and Figure 11B It is along Figure 11A A cross-sectional view taken along line BB'.

[0115] refer to Figure 11A and 11B , one or more channel layers 630 are arranged over the substrate 601 to be spaced apart from the substrate 601. Here, the channel layers 630 each may have a sheet shape arranged parallel to the substrate 601. Figure 11A and 11B A case is shown in which two channel layers 630 are vertically arranged above a substrate 630 .

[0116] The channel layers 630 each can include the two-dimensional material layer 610 and the molecular crystal layer 620. For the two-dimensional material layer 610 and the molecular crystal layer 620, refer to the above-described two-dimensional material layer 110 and the molecular crystal layer 120. In the present embodiment, since both the upper surface and the lower surface of the channel layer 630 are in contact with the gate insulating layer 640, the molecular crystal layer 620 can be formed on both the upper surface and the lower surface of the two-dimensional material layer 610.

[0117] Figure 12 is a conceptual diagram of a channel layer 630' according to another embodiment. Refer to Figure 12 , the molecular crystal layer 620 is formed on the two-dimensional material layer 610 and under the two-dimensional material layer 610, and both the two-dimensional material layer 610 and the molecular crystal layer 620 are formed as a single layer. In Figure 12 , each spherical shape indicates an element constituting the two-dimensional semiconductor material and the sheet-like aromatic compound. Since the molecular crystal layer 620 is made of the sheet-like aromatic compound according to the embodiment, it can have crystallinity due to the crystal structure of the two-dimensional material layer 610. In other words, Figure 12 The channel layer 630' in Figure 12 may include the two-dimensional material layer 610 sandwiched between a pair of the molecular crystal layers 620. Figure 8 The channel layer 630' in Figure 9 may replace any one of the channel layers 130, 230, 330, 530, and 630 of the semiconductor devices 100 to 600 described above. Although not shown in the drawing, the channel layer 630' can include a first region between second regions, and in the first region and the second regions of the channel layer 630', the material of the two-dimensional material layer 610, or the materials of the two-dimensional material layer 610 and the molecular crystal layer 620 each, respectively, can be different materials. In this regard, refer to those described above with respect to the channel layer 230 of

[0118] Again refer to Figure 11A and 11B The two-dimensional material layer 610 each can include a first region 610a and second regions 610b provided at both sides of the first region 610a. Similarly, the molecular crystal layer 620 each can include a first region 620a and second regions 620b provided at both sides of the first region 620a.

[0119] Four sides of the first region 610a of the two-dimensional material layer 610 and four sides of the first region 620a of the molecular crystal layer 620 are surrounded by the gate electrode 660, and can become a channel region. The second regions 610b of the two-dimensional material layer 610 and the second regions 620b of the molecular crystal layer 620 are located outside the gate electrode 660, and can become source / drain regions.

[0120] A gate insulating layer 640 is provided between the gate electrode 660 and the first region 620a of the molecular crystal layer 620. The gate insulating layer 640 is provided so as to surround four sides of the channel layer 630, specifically, the first region 620a of the molecular crystal layer 620, and the gate electrode 660 can be provided so as to surround four sides of the gate insulating layer 640. Although not shown in the figure, a source electrode and a drain electrode can be provided in the second region 620b of the molecular crystal layer 620. An insulator (not shown) can also be disposed on the substrate 601 parallel to the substrate 601 and the channel layer 630 is provided so as to surround the insulator.

[0121] The semiconductor devices 100 to 600 described above can be applied to a memory device such as a DRAM. The memory device can have a structure in which the semiconductor devices 100 to 600 described above are electrically connected with a capacitor. In addition, the semiconductor devices 100 to 600 can be applied to various electronic devices. For example, the semiconductor devices 100 to 600 described above can be used for arithmetic operation, program execution, temporary data retention, and the like in electronic devices such as mobile devices, computers, laptop computers, sensors, network devices, neuromorphic devices, and the like.

[0122] Figure 13 and 14 is a conceptual diagram schematically showing an electronic device architecture that can be applied to an electronic device according to an embodiment.

[0123] Referring to Figure 13 , the electronic device architecture 1000 can include a memory unit 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030. The memory unit 1010, the arithmetic logic unit (ALU) 1020, and the control unit 1030 can be electrically connected to each other. For example, the electronic device architecture 1000 can be implemented as a single chip including the memory unit 1010, the ALU 1020, and the control unit 1030.

[0124] Specifically, the memory unit 1010, the ALU 1020, and the control unit 1030 can communicate directly through on-die interconnects. The memory unit 1010, the ALU 1020, and the control unit 1030 can be monolithically integrated on one substrate to form one chip. The electronic device architecture (chip) 1000 can be connected to an input / output device 2000 (e.g., a keyboard, a display, or a mouse).

[0125] The ALU 1020 and the control unit 1030 can each independently include the semiconductor devices 100 to 600 described above, and the memory unit 1010 can include the semiconductor devices 100 to 600, a capacitor, or a combination thereof. The memory unit 1010 can include both a main memory and a cache memory. The electronic device architecture (chip) 1000 can be a processing unit on a chip.

[0126] refer to Figure 14 , the cache memory 1510, the ALU 1520, and the control unit 1530 may be part of a central processing unit (CPU) 1500. The cache memory 1510 may be formed of a static random access memory (SRAM) and may include the semiconductor devices 100 to 600 described above. In addition to the CPU 1500, a main memory 1600 and an auxiliary memory 1700 may be provided. The main memory 1600 may include a dynamic random access memory (DRAM) device.

[0127] In some cases, the electronic device architecture may be implemented in a form where computing unit devices and memory unit devices are adjacent to each other on a single chip without distinction between sub-units. Although embodiments have been described above, they are merely exemplary and various variations therefrom may be made by those skilled in the art.

[0128] In semiconductor devices according to embodiments, the presence of a molecular crystal layer on a two-dimensional material layer can enable thinner and / or more uniform formation of source / drain metal structures or gate stack structures. Furthermore, because the molecular crystal layer has improved or excellent chemical and / or thermal stability, it can better protect the two-dimensional material layer, thereby preventing device performance degradation due to damage to the two-dimensional material layer.

[0129] One or more of the elements disclosed above may include or be implemented as follows: a processing circuit system, such as hardware including logic circuits; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuit system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0130] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects in each embodiment should typically be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. Semiconductor devices, including: a channel layer, the channel layer comprising a two-dimensional material layer and a molecular crystal layer on the two-dimensional material layer, the two-dimensional material layer comprising a two-dimensional semiconductor material; a source electrode and a drain electrode respectively on both sides of the channel layer; as well as A gate insulating layer and a gate electrode are provided on the channel layer between the source electrode and the drain electrode, wherein The molecular crystal layer includes C 20 -C 40 of flaky aromatic compounds, and The thickness of the molecular crystal layer is 1 to 5 molecular layers.

2. The semiconductor device according to claim 1, wherein The sheet-like aromatic compound has semiconductor properties.

3. The semiconductor device according to claim 1, wherein The flaky aromatic compounds include compounds based on tetracene, compounds based on A compound based on benzo[9,10]phenanthrene, a pyrene, a perylene, a pentacene, a benzopyrene, a benzoperylene, or a coronene-based compound.

4. The semiconductor device according to claim 2, wherein The flaky aromatic compound includes at least one of a hydroxyl group, a carboxyl group, a carboxylic acid metal salt group, an imide group, an amide group, and a carboxylic anhydride group. The semiconductor device according to claim 1 , wherein The thickness of the molecular crystal layer is 1 to 3 molecular layers. The semiconductor device according to claim 1 , wherein The two-dimensional semiconductor material includes transition metal dichalcogenides or black phosphorus.

7. The semiconductor device according to claim 6, wherein The transition metal dichalcogenide comprises a metal element and a chalcogen element, The metal element includes at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc and Re, and The chalcogen element includes at least one of S, Se, and Te. The semiconductor device according to claim 6 , wherein The transition metal dichalcogenide includes MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReSe2, or any combination thereof.

9. The semiconductor device according to claim 1, wherein The molecular crystal layer has crystallinity due to the crystal structure of the two-dimensional material layer.

10. The semiconductor device according to claim 1, wherein The two-dimensional material layer has a polycrystalline structure.

11. The semiconductor device according to claim 1, wherein The channel layer includes a first region and a second region, The first region of the channel layer overlaps with the gate electrode, and The second region of the channel layer overlaps with the source electrode and the drain electrode, respectively.

12. The semiconductor device according to claim 11, wherein A material of the two-dimensional material layer in the first region of the channel layer is different from a material of the two-dimensional material layer in the second region of the channel layer.

13. The semiconductor device according to claim 11, wherein The two-dimensional material layer in the second region of the channel layer further includes a p-type dopant or an n-type dopant.

14. The semiconductor device according to claim 11, wherein The molecular crystal layer of the second region of the channel layer includes a material configured to provide a p-type dopant or an n-type dopant to the two-dimensional material layer of the second region of the channel layer.

15. The semiconductor device according to claim 14, wherein The material configured to provide a p-type dopant or an n-type dopant includes a plate-like aromatic compound containing metal ions.

16. The semiconductor device according to claim 11, wherein A material of the molecular crystal layer in the first region of the channel layer is different from a material of the molecular crystal layer in the second region of the channel layer.

17. The semiconductor device according to claim 1, wherein The semiconductor device has a planar FET structure, a fin FET structure, a gate-all-around FET structure, or a complementary FET structure.

18. Electronic devices, including: A semiconductor device according to any one of claims 1 to 17.

19. A method for manufacturing a semiconductor device according to any one of claims 1 to 17, the method comprising: Forming a channel layer on a substrate, wherein forming the channel layer comprises forming a two-dimensional material layer comprising a two-dimensional semiconductor material on the substrate, and forming a C 20 -C 40 Molecular crystal layers of sheet-like aromatic compounds; forming a gate insulating layer and a gate electrode on the channel layer; and A source electrode and a drain electrode are formed on both sides of the channel layer, respectively.

20. The method according to claim 19, wherein The molecular crystal layer is deposited by atomic layer deposition, chemical vapor deposition, or evaporation.

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