Vertical channel oxide semiconductor field effect transistor and manufacturing method

Abstract

A vertical channel oxide semiconductor field effect transistor and a manufacturing method, relating to the technical field of information materials and devices. In the oxide semiconductor field effect transistor, a trench-shaped oxide semiconductor channel layer is used, the trench is then filled with an oxide semiconductor material, and an oxygen vacancy concentration of a material of an oxide semiconductor filling layer is less than an oxygen vacancy concentration of a material of the oxide semiconductor channel layer; and by using an oxide semiconductor having a low carrier concentration as an internal filling material, a threshold regulation capability of the vertical channel oxide semiconductor field effect transistor can be effectively improved, and the impacts of interface damage and unnecessary doping can be avoided, thereby achieving a vertical channel oxide semiconductor field effect transistor of which a threshold can be accurately regulated.

Description

Vertical channel oxide semiconductor field effect transistor and preparation method TECHNICAL FIELD

[0001] The present application relates to a vertical channel oxide semiconductor field effect transistor with precisely regulated threshold value and a preparation method, belonging to the technical field of information materials and devices. BACKGROUND

[0002] Oxide semiconductors show great potential in high retention and high density three-dimensional integrated dynamic random access memory (DRAM) applications due to their suitable mobility (10~100 cm 2 / V·s), extremely low leakage current (<10 -22 A / μm) and back-compatible thermal budget. Among them, vertical channel field effect transistors based on oxide semiconductors not only can reduce the channel length to within 10 nanometers, but also can reduce the feature size of the storage unit, greatly improving the density of the storage array.

[0003] Due to the opposite change trend of the threshold voltage and the mobility of the oxide semiconductor with the change of the carrier concentration, the enhancement mode oxide transistor usually shows low mobility and high contact resistance, which leads to a significant reduction in the on-state current, greatly affecting the working speed of the storage unit. Although the use of high carrier concentration channel can effectively improve the on-state performance, it will also reduce the stability of the device, and the large negative bias gate voltage during the off state will also lead to the increase of the gate leakage, thereby degrading the retention characteristics of the DRAM. In the vertical channel structure, the contact area of the source and drain region is smaller, and the degradation of the contact resistance will be more obvious. And with the increase of the channel thickness, the gate control ability of the center region channel is reduced, which leads to the deterioration of the device switching characteristics. Therefore, generally, silicon oxide, silicon nitride and other insulating materials are used to fill the holes in the channel to improve the gate control ability, but the deposition process of these filling materials often causes interface damage and unnecessary doping to the oxide semiconductor channel layer, affecting the electrical performance and reliability of the transistor device, etc. SUMMARY

[0004] In order to solve the problem that the existing conventional filling layer has limited performance regulation on the device, the present application provides a vertical channel oxide semiconductor field effect transistor with precisely regulated threshold value and a preparation method.

[0005] To achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0006] An oxide semiconductor field effect transistor, characterized by comprising a substrate, a source metal electrode layer, a gate metal electrode layer, an oxide semiconductor channel layer and a drain metal electrode layer, the gate metal electrode layer is located between the source metal electrode layer and the oxide semiconductor channel layer, an insulating layer is provided between the gate metal electrode layer and the source metal electrode layer and the oxide semiconductor channel layer, the oxide semiconductor channel layer is in a groove shape, the groove bottom of the oxide semiconductor channel layer is in contact with the source metal electrode layer, a gate dielectric layer is provided outside the groove of the oxide semiconductor channel layer, the gate dielectric layer is located between the gate metal electrode layer and the oxide semiconductor channel layer, an oxide semiconductor filling layer is provided in the groove of the oxide semiconductor channel layer, the oxygen vacancy concentration of the oxide semiconductor filling layer is smaller than that of the oxide semiconductor channel layer.

[0007] Further, the substrate includes but is not limited to a glass substrate, a sapphire substrate, a silicon substrate, a silicon carbide substrate, a diamond substrate, a diamond-like carbon film substrate or a flexible substrate such as PI, PET, etc.

[0008] Further, the source / drain electrode layer is composed of a conductive metal or the like, and the metal electrode material includes but is not limited to Ti, Ni, Au, Pt, Pd, W, Al, Y, Sc, Mo and alloys thereof, TiN, metallic oxide ITO, IZO, etc., and is prepared by using an electron beam evaporation, a magnetron sputtering, an ion beam sputtering, a thermal evaporation or an atomic layer deposition process, etc., and the recommended thickness of the source / drain electrode layer is 3-300 nm.

[0009] Further, the insulating layer includes but is not limited to SiO2, SiN x , SiON x , etc., and a multi-element doped low dielectric constant medium, etc., and is prepared by using a plasma enhanced chemical vapor deposition, an inductively coupled plasma chemical vapor deposition, a magnetron sputtering, an electron beam evaporation, a pulsed vapor deposition or an atomic layer deposition process, etc., and the thickness of the insulating layer is 3-500 nm.

[0010] Further, the gate metal electrode layer is formed of a conductive metal, and the metal electrode material includes but is not limited to Ti, Ni, Au, Pt, Pd, Al, W, Y, Sc, Mo and alloys thereof, TiN, metallic oxide ITO, IZO, etc., and is prepared by using an electron beam evaporation, a magnetron sputtering, an ion beam sputtering, a thermal evaporation or an atomic layer deposition process, etc., and the thickness of the gate metal electrode layer is 5-300 nm.

[0011] Further, the gate dielectric material includes but is not limited to SiO2, SiN x , Al2O3, HfO2, HfSiOx, HfLaO x , HfAlOx HfZrO x and the like, and the gate dielectric layer has a thickness of 2-300 nm.

[0012] Further, the oxide semiconductor channel layer includes, but is not limited to, In2O3, SnO2, Ga2O3, ZnO, ITO, IGO, IZO, IGZO, IAZO, ITZO, IWO, ITWO and the like, and all oxide semiconductor thin films and composite materials of multilayer oxide film stacks with various doping components and proportions, and the oxide semiconductor channel layer has a thickness of 0.5-50 nm.

[0013] Further, the oxide semiconductor filling layer is an oxide semiconductor material with low carrier concentration. It includes, but is not limited to, Ga2O3, ZnO, SnO2, IGZO, IAZO, ITZO, IWO, ITWO and the like, and all oxide semiconductor thin films and composite materials of multilayer oxide film stacks with various doping components and proportions, and the oxide semiconductor filling layer has a thickness of 0.5-500 nm.

[0014] The application further provides a preparation method of a vertical channel oxide semiconductor field effect transistor, including the following process steps:

[0015] Step 1.1, cleaning the substrate;

[0016] Step 1.2, preparing a source metal electrode layer by using an electron beam evaporation, magnetron sputtering, ion beam sputtering, thermal evaporation or atomic layer deposition process;

[0017] Step 1.3, preparing an insulating layer by using a plasma enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, electron beam evaporation, pulsed vapor deposition or atomic layer deposition process;

[0018] Step 1.4, preparing a gate metal electrode layer by using an electron beam evaporation, magnetron sputtering, thermal evaporation or atomic layer deposition process;

[0019] Step 1.5, preparing an insulating layer by using the same method as in step 1.3;

[0020] Step 1.6, define the channel region by using optical lithography, electron beam lithography process or laser direct writing process, and complete the trench of the channel region by using dry etching or wet etching process;

[0021] Step 1.7, prepare the gate dielectric layer around the trench by using plasma enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, electron beam evaporation, pulsed vapor deposition or atomic layer deposition process;

[0022] Step 1.8, prepare the oxide semiconductor channel layer by using magnetron sputtering, chemical vapor deposition, molecular beam epitaxy or atomic layer deposition process, the oxide semiconductor channel layer is in a trench shape, and the bottom of the trench of the oxide semiconductor channel layer is in contact with the source end metal electrode layer;

[0023] Step 1.9, fill the oxide semiconductor material in the trench by using magnetron sputtering, chemical vapor deposition, molecular beam epitaxy or atomic layer deposition process, and the oxygen vacancy concentration of the oxide semiconductor filling layer material is less than that of the oxide semiconductor channel layer material;

[0024] Step 1.10, prepare the drain end metal electrode layer by using electron beam evaporation, magnetron sputtering, ion beam sputtering, thermal evaporation or atomic layer deposition process.

[0025] The technical effects of the present application are as follows:

[0026] The present application provides a method for precisely regulating the threshold value of a vertical channel oxide semiconductor field effect transistor. The present application uses a trench-shaped oxide semiconductor channel layer, and fills the oxide semiconductor material in the trench, and the oxygen vacancy concentration of the oxide semiconductor filling layer material is less than that of the oxide semiconductor channel layer material. By using the oxide semiconductor with low carrier concentration as the internal filling material, the threshold regulation ability of the vertical channel oxide semiconductor field effect transistor can be effectively improved, and the influence of interface damage and unnecessary doping can be avoided, thereby realizing the vertical channel oxide semiconductor field effect transistor with precisely regulated threshold value. BRIEF DESCRIPTION OF DRAWINGS

[0027] Fig. 1 is a structural schematic diagram of the vertical channel oxide semiconductor field effect transistor of the present application;

[0028] Fig. 2 is a flow chart of the manufacturing method of the vertical channel oxide semiconductor field effect transistor with precisely regulated threshold value in the present application.

[0029] Fig. 3 is an illustration of Figs. 1-2. DETAILED DESCRIPTION

[0030] Embodiments of the present application are described in detail below with reference to the attached drawing figures, wherein the embodiments described are by way of illustration only and should not be construed in any way to restrict the present application. The drawings are not to scale and are as follows:

[0031] The present application provides a vertical channel oxide semiconductor field effect transistor with precisely regulated threshold value and a preparation method thereof.

[0032] Fig. 1 is a schematic diagram of a vertical channel oxide semiconductor field effect transistor structure, which comprises, from bottom to top, a substrate, a source metal electrode layer, a gate metal electrode layer, an oxide semiconductor channel layer and a drain metal electrode layer, an insulating layer is arranged between the source metal electrode layer and the gate metal electrode layer, a gate dielectric layer is arranged between the gate metal electrode layer and the oxide semiconductor channel layer, the oxide semiconductor channel layer is in a trench shape, the bottom of the trench of the oxide semiconductor channel layer is in contact with the source metal electrode layer, a gate dielectric layer is arranged around the trench of the oxide semiconductor channel layer, and an oxide semiconductor filling layer is arranged in the trench of the oxide semiconductor channel layer, the oxygen vacancy concentration of the oxide semiconductor filling layer is smaller than that of the oxide semiconductor channel layer.

[0033] The specific preparation method of the oxide semiconductor field effect transistor of the present application comprises the following steps:

[0034] S001: Obtain and use a cleaned substrate. RCA1 is used to clean the particles and organic matter on the substrate, and high-purity nitrogen is used to dry the substrate after cleaning. The substrate can be a glass substrate, a sapphire substrate, a silicon substrate, a silicon carbide substrate, a diamond substrate, a diamond-like carbon film substrate or a flexible substrate such as PI, PET, etc. In this embodiment, the substrate is a high-resistance silicon substrate with a resistivity of >10000 Ω·cm.

[0035] S002: After cleaning the substrate, the preparation of the source metal electrode layer is completed by using the processes of uniform coating, baking, photolithography, development, electron beam evaporation, magnetron sputtering, stripping, etc., and the thickness is 5-300 nm. In this embodiment, 20 nm of Au is used as the source metal electrode by electron beam evaporation.

[0036] S003: SiO2 insulating layer is grown by plasma-enhanced chemical vapor deposition or atomic layer deposition process, and the thickness of the insulating layer is 3-500 nm.

[0037] S004: The gate metal electrode layer is prepared by electron beam evaporation process, and the thickness of the insulating layer is 3-500 nm. In this embodiment, 20 nm of Au is used as the gate metal electrode by electron beam evaporation.

[0038] S005, growing a SiO2 insulating layer by a plasma enhanced chemical vapor deposition or atomic layer deposition process, the thickness of the insulating layer being 3-500 nm.

[0039] S006, completing opening of the channel region by using process steps such as uniform coating, baking, photolithography, development, etching, and peeling, and forming a groove.

[0040] S007, preparing a gate dielectric layer around the groove by using an atomic layer deposition process, in the embodiment, the gate dielectric layer is 5 nm HfLaO x .

[0041] S008, preparing an oxide semiconductor channel layer ITO by using process steps such as atomic layer deposition, uniform coating, baking, photolithography, development, etching, and peeling, the oxide semiconductor channel layer being in a groove shape, and the thickness of the oxide semiconductor channel layer being 0.5-50 nm.

[0042] S009, filling a low-oxygen-vacancy-concentration Ga2O3 oxide semiconductor material in the groove by using a process such as magnetron sputtering, chemical vapor deposition, molecular beam epitaxy, or atomic layer deposition, the oxygen vacancy concentration of the oxide semiconductor filling layer material being lower than that of the oxide semiconductor channel layer material, and completing preparation of the oxide filling layer with a low carrier concentration.

[0043] S010, completing preparation of a drain metal electrode layer by using process steps such as uniform coating, baking, photolithography, development, electron beam evaporation, magnetron sputtering, and peeling, in the embodiment, 20 nm Au evaporated by an electron beam is used as the drain metal electrode.

[0044] Compared with the prior art, the technical scheme of the present application changes the hole filling material in the channel layer, and the oxygen vacancy concentration of the oxide semiconductor filling layer material is lower than that of the oxide semiconductor channel layer material. By using the good performance adjustability of the oxide semiconductor material, the threshold control capability of the vertical channel oxide semiconductor field effect transistor can be effectively improved by changing the oxide semiconductor element and component in the channel, and a vertical channel oxide semiconductor field effect transistor with precisely controlled threshold can be realized. Meanwhile, the process difficulty of filling the hole in the channel layer is reduced, and problems such as interface damage or unnecessary doping of the semiconductor channel caused by conventional filling materials such as silicon oxide and silicon nitride in the filling process are solved.

[0045] The present application has various embodiments, and all technical schemes formed by equivalent transformation or equivalent conversion fall within the protection scope of the present application.

[0046] It should be noted that the foregoing examples have been provided merely for the purpose of explanation and are in no way to be construed as limiting of the present application.

Claims

1. An oxide semiconductor field-effect transistor, characterized in that, The device includes a substrate, a source metal electrode layer, a gate metal electrode layer, an oxide semiconductor channel layer, and a drain metal electrode layer. The gate metal electrode layer is located between the source metal electrode layer and the oxide semiconductor channel layer. An insulating layer is provided between the gate metal electrode layer and the source metal electrode layer and the oxide semiconductor channel layer. The oxide semiconductor channel layer is trench-shaped, and the bottom of the trench of the oxide semiconductor channel layer is in contact with the source metal electrode layer. A gate dielectric layer is provided outside the trench of the oxide semiconductor channel layer, and the gate dielectric layer is located between the gate metal electrode layer and the oxide semiconductor channel layer. An oxide semiconductor filling layer is provided in the trench of the oxide semiconductor channel layer, and the oxygen vacancy concentration of the oxide semiconductor filling layer material is lower than that of the oxide semiconductor channel layer material.

2. The oxide semiconductor field-effect transistor as described in claim 1, characterized in that, The substrate is a glass substrate, sapphire substrate, silicon substrate, silicon carbide substrate, diamond substrate, diamond-like carbon film substrate, or PI or PET flexible substrate.

3. The oxide semiconductor field-effect transistor as described in claim 1, characterized in that, The source metal electrode layer, gate metal electrode layer, or drain metal electrode layer shall be made of Ti, Ni, Au, Pt, Pd, W, Al, Y, Sc, Mo and their alloys, TiN, metallic oxides ITO, and IZO.

4. The oxide semiconductor field-effect transistor as described in claim 3, characterized in that, The thicknesses of the source metal electrode layer and the drain metal electrode layer range from 3 to 300 nanometers, respectively.

5. The oxide semiconductor field-effect transistor as described in claim 3, characterized in that, The thickness of the gate metal electrode layer ranges from 5 to 300 nanometers.

6. The oxide semiconductor field-effect transistor as claimed in claim 1, characterized in that, The insulating layer is made of SiO2 and SiN. x SiON x It also includes low dielectric constant dielectrics with multi-doped substrates, with a thickness of 3–500 nanometers.

7. The oxide semiconductor field-effect transistor as claimed in claim 1, characterized in that, The gate dielectric material is SiO2 or SiN. x , Al2O3, HfO2, HfSiOx, HfLaO x HfAlO x HfZrO x It and its multi-doped combination medium, with a thickness of 2 to 300 nanometers.

8. The oxide semiconductor field-effect transistor as described in claim 1, characterized in that, The oxide semiconductor channel layer is made of In2O3, SnO2, Ga2O3, ZnO, ITO, IGO, IZO, IGZO, IAZO, ITZO, IWO, ITWO oxide semiconductor thin films and multilayer oxide thin film stacks, with a thickness of 0.5 to 50 nanometers.

9. The oxide semiconductor field-effect transistor as claimed in claim 1, characterized in that, The oxide semiconductor filling layer is a composite material of Ga2O3, ZnO, SnO2, IGZO, IAZO, ITZO, IWO, ITWO oxide semiconductor thin films and multilayer oxide thin films, with a thickness of 0.5 to 500 nanometers; the oxygen vacancy concentration of the oxide semiconductor filling layer material is lower than that of the oxide semiconductor channel layer material.

10. The method for fabricating the vertical channel oxide semiconductor field-effect transistor according to claim 1, comprising the following process steps: Step 1.1, Clean the substrate; Step 1.2: Prepare the source metal electrode layer using electron beam evaporation, magnetron sputtering, ion beam sputtering, thermal evaporation, or atomic layer deposition. Step 1.3: Prepare the insulating layer using plasma-enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, electron beam evaporation, pulsed vapor deposition, or atomic layer deposition. Step 1.4: Prepare the gate metal electrode layer using electron beam evaporation, magnetron sputtering, thermal evaporation, or atomic layer deposition processes; Step 1.5: Prepare the insulating layer using the same method as in Step 1.3; Step 1.6: Define the trench area using optical lithography, electron beam lithography, or laser direct writing, and complete the trench area using dry or wet etching. Step 1.7: Prepare a gate dielectric layer around the trench using plasma-enhanced chemical vapor deposition, inductively coupled plasma chemical vapor deposition, magnetron sputtering, electron beam evaporation, pulsed vapor deposition, or atomic layer deposition. Step 1.8: An oxide semiconductor channel layer is prepared using magnetron sputtering, chemical vapor deposition, molecular beam epitaxy, or atomic layer deposition. The oxide semiconductor channel layer is trench-shaped, and the bottom of the trench of the oxide semiconductor channel layer is in contact with the source metal electrode layer. Step 1.9: Fill the trench with oxide semiconductor material using magnetron sputtering, chemical vapor deposition, molecular beam epitaxy or atomic layer deposition. The oxygen vacancy concentration of the oxide semiconductor filling layer material is lower than that of the oxide semiconductor channel layer material. Step 1.10: Prepare the drain metal electrode layer using electron beam evaporation, magnetron sputtering, ion beam sputtering, thermal evaporation, or atomic layer deposition.

Images