Interrupt control circuit and method, chip and electronic equipment

Abstract

The invention provides an interrupt control circuit and method, a chip and electronic equipment. When an interrupt event occurs at the same time, the plurality of sub-modules generate interrupt requests corresponding to respective interrupt events, and send the interrupt requests and interrupt priorities to the arbiter. And the arbiter obtains an arbitration result according to the plurality of interrupt priorities and the plurality of interrupt requests, and sends the arbitration result to the interrupt processor. And the interrupt processor determines target in-band interrupt data according to the arbitration result, and sends the target in-band interrupt data and the initiating signal to the I3C slave controller, so that the I3C slave controller sends the target in-band interrupt data to the I3C host. And after the sending is finished, the plurality of sub-modules send other interrupt requests except the interrupt request with the highest priority in the plurality of interrupt requests or the interrupt request of the target in-band interrupt data which is not successfully sent to the arbiter again so as to apply for arbitration again. Therefore, the interruption event which is not successfully sent and the interruption event which fails in arbitration can be prevented from being lost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to an interrupt control circuit, method, chip and electronic device. BACKGROUND

[0002] Improved inter integrated circuit (I3C) is a widely used communication protocol, which realizes signal transmission between a host and a slave through a clock line SCL and a data line SDA. The communication rate of the I3C protocol is high, and the fastest communication rate can reach 12.5 MHz. When the I3C slave needs to send an interrupt, the I3C slave can actively send the interrupt through the clock line SCL and the data line SDA.

[0003] Inside the I3C slave, different sub-modules each have a situation of triggering an interrupt, and these interrupts can be generated at the same time. In this way, a large amount of interrupt information is generated inside the I3C slave and needs to be reported to the I3C host. Since the in-band interrupt is the only channel for reporting interrupt information, the I3C slave can only send the interrupt information inside the I3C slave to the I3C host in turn through time division multiplexing and interrupt priority arbitration. The time division multiplexing refers to dividing in time, so that each interrupt information is allocated to a specific time for transmission through the in-band interrupt. The interrupt priority arbitration refers to the priority ordering of multiple in-band interrupt requests of the I3C slave.

[0004] However, when the rate at which these interrupts are generated is greater than the processing capability of the time division multiplexing and the interrupt priority arbitration, the I3C slave cannot send part of the interrupt information in time, resulting in part of the interrupt information being overwritten by new interrupts, so that interrupt events are lost. SUMMARY

[0005] The present application provides an interrupt control circuit, method, chip and electronic device, which can avoid the loss of interrupt events.

[0006] In a first aspect, the present application provides an interrupt control circuit, which comprises a plurality of sub-modules, an arbitrator, an interrupt processor and an I3C slave controller.

[0007] The plurality of sub-modules are connected with the arbitrator and the interrupt processor respectively, the interrupt processor is further connected with the I3C slave controller, and the I3C slave controller is further connected with an I3C host through an I3C bus.

[0008] The plurality of sub-modules are configured to generate an interrupt request corresponding to each of the interrupt events and send the interrupt request and an interrupt priority corresponding to each of the plurality of sub-modules to the arbitrator and send in-band interrupt data corresponding to the interrupt event to the interrupt processor when the interrupt events occur at the same time.

[0009] The arbitrator is configured to arbitrate the plurality of interrupt requests according to a plurality of interrupt priorities to obtain an arbitration result and send the arbitration result to the plurality of sub-modules and the interrupt processor, wherein the arbitration result is used to represent a sub-module corresponding to an interrupt request with the highest priority among the plurality of interrupt requests.

[0010] The interrupt processor is configured to determine target in-band interrupt data from the plurality of in-band interrupt data according to the arbitration result and send the target in-band interrupt data and an initiation signal to the I3C slave controller, wherein the initiation signal is used to indicate that the target in-band interrupt data has been determined.

[0011] The I3C slave controller is configured to send the target in-band interrupt data to the I3C master according to the initiation signal.

[0012] The plurality of sub-modules are further configured to send, after the target in-band interrupt data is sent, other interrupt requests in the plurality of interrupt requests except the interrupt request with the highest priority or an interrupt request corresponding to the target in-band interrupt data that fails to be sent successfully to the arbitrator again to re-apply for arbitration according to the arbitration result.

[0013] The interrupt control circuit provided by the first aspect can generate interrupt requests corresponding to respective interrupt events, send the interrupt requests and interrupt priorities corresponding to respective sub-modules to the arbitrator, and send in-band interrupt data corresponding to the interrupt events to the interrupt processor when interrupt events occur at the same time, so that the arbitrator obtains the interrupt requests and interrupt priorities corresponding to respective sub-modules, and the interrupt processor obtains the in-band interrupt data corresponding to the interrupt events. In this way, the arbitrator can arbitrate the multiple interrupt requests according to the multiple interrupt priorities, obtain an arbitration result, and send the arbitration result to the multiple sub-modules and the interrupt processor to indicate the sub-module corresponding to the interrupt request with the highest priority among the multiple interrupt requests, so that the multiple sub-modules obtain the arbitration result. In this way, the interrupt processor can determine target in-band interrupt data from the multiple in-band interrupt data according to the arbitration result, and send the target in-band interrupt data and an initiation signal indicating that the target in-band interrupt data has been determined to the I3C slave controller, so that the I3C slave controller obtains the target in-band interrupt data and the initiation signal. Furthermore, the I3C slave controller can send the target in-band interrupt data to the I3C master according to the initiation signal, so that the I3C master can obtain the target in-band interrupt data. Furthermore, after the target in-band interrupt data is sent, the multiple sub-modules can send, according to the arbitration result, interrupt requests other than the interrupt request with the highest priority among the multiple interrupt requests or the interrupt request corresponding to the target in-band interrupt data that is not successfully sent to the arbitrator again to reapply for arbitration. In this way, the interrupt events corresponding to the target in-band interrupt data that is not successfully sent and the interrupt events corresponding to the interrupt requests other than the interrupt request with the highest priority among the multiple interrupt requests can be avoided.

[0014] In a possible design, the arbitrator includes a first grouping circuit, a second grouping circuit, an obtaining circuit, and an arbitration circuit.

[0015] The first grouping circuit, the arbitration circuit, and the second grouping circuit are connected with the multiple sub-modules, and the second grouping circuit is further connected with the obtaining circuit.

[0016] The first grouping circuit is configured to receive the multiple interrupt priorities, group the multiple interrupt priorities, obtain multiple first priority groups, and send the multiple first priority groups to the second grouping circuit. Each first priority group contains a plurality of interrupt priorities with the same configurable priority, and the interrupt priorities in each first priority group are sorted according to a default priority. The default priority is negatively correlated with the number corresponding to the respective sub-modules.

[0017] The second grouping circuit is configured to receive the plurality of interrupt requests, distribute the plurality of interrupt requests into the plurality of first priority groups to obtain a plurality of second priority groups, and send the plurality of second priority groups to the obtaining circuit and the arbitration circuit respectively, each of the second priority groups containing a plurality of interrupt requests with the same configurable priority.

[0018] The obtaining circuit is configured to determine whether there is an interrupt request in each of the plurality of second priority groups to obtain a plurality of third priority groups, and send the plurality of third priority groups to the arbitration circuit.

[0019] The arbitration circuit is configured to arbitrate the interrupt requests in the plurality of second priority groups according to the plurality of third priority groups to obtain the arbitration result.

[0020] In summary, the first grouping circuit can receive a plurality of interrupt priorities, group the plurality of interrupt priorities to obtain a plurality of first priority groups, and send the plurality of first priority groups to the second grouping circuit, so that the second grouping circuit can obtain the plurality of first priority groups. Each of the first priority groups contains a plurality of interrupt priorities with the same configurable priority, and is sorted according to a default priority, which is negatively correlated with the number corresponding to each of the plurality of sub-modules. The second grouping circuit can receive a plurality of interrupt requests, distribute the plurality of interrupt requests into the plurality of first priority groups to obtain a plurality of second priority groups, and send the plurality of second priority groups to the obtaining circuit and the arbitration circuit respectively, so that the obtaining circuit and the arbitration circuit can obtain the plurality of second priority groups. Each of the second priority groups contains a plurality of interrupt requests with the same configurable priority. In this way, the obtaining circuit can determine whether there is an interrupt request in each of the plurality of second priority groups to obtain a plurality of third priority groups, and send the plurality of third priority groups to the arbitration circuit, so that the arbitration circuit can obtain the plurality of third priority groups. Further, the arbitration circuit can arbitrate the interrupt requests in the plurality of second priority groups according to the plurality of third priority groups to obtain the arbitration result. Thus, the arbitrator can arbitrate the plurality of interrupt requests according to the plurality of interrupt priorities to obtain the arbitration result.

[0021] In a possible design, the first grouping circuit includes an encoding conversion circuit and a first sub-grouping circuit.

[0022] The encoding conversion circuit is connected with the plurality of sub-modules and the first sub-grouping circuit respectively.

[0023] The encoding conversion circuit is configured to convert the encoding form of the plurality of interrupt priorities from binary code to one-hot code to obtain a plurality of converted interrupt priorities, and send the plurality of converted interrupt priorities to the first sub-grouping circuit.

[0024] The first sub-grouping circuit is configured to group the plurality of converted interrupt priorities according to the configurable priorities, to obtain a plurality of first priority groups.

[0025] In summary, the encoding conversion circuit can convert the encoding form of the plurality of interrupt priorities from binary code to one-hot code, to obtain a plurality of converted interrupt priorities, and send the plurality of converted interrupt priorities to the first sub-grouping circuit, so that the first sub-grouping circuit can obtain the plurality of converted interrupt priorities. In this way, the first sub-grouping circuit can group the plurality of converted interrupt priorities according to the configurable priorities, to obtain a plurality of first priority groups. Thus, the first grouping circuit can group the plurality of interrupt priorities, to obtain a plurality of first priority groups.

[0026] In a possible design, the second grouping circuit is specifically configured to perform a bitwise AND operation on the plurality of interrupt requests and the plurality of first priority groups, to distribute the plurality of interrupt requests to the plurality of first priority groups.

[0027] In a possible design, the obtaining circuit is specifically configured to perform a bitwise OR operation on the plurality of second priority groups, to determine whether there is an interrupt request in each second priority group in the plurality of second priority groups.

[0028] In a possible design, the arbitration circuit includes a first arbitration circuit and a second arbitration circuit.

[0029] The first arbitration circuit is connected with the plurality of sub-modules, the second grouping circuit, and the second arbitration circuit respectively.

[0030] The first arbitration circuit is configured to select, according to the plurality of third priority groups, a second priority group with the highest configurable priority and having an interrupt request from the plurality of second priority groups, to obtain a target second priority group, and send the target second priority group to the second arbitration circuit.

[0031] The second arbitration circuit is configured to select, from the target second priority group, a number corresponding to a sub-module with the highest default priority, and take the number corresponding to the sub-module with the highest default priority as the arbitration result.

[0032] In conclusion, the first arbitration circuit can select, according to the plurality of third priority groups, a second priority group with the highest configurable priority and an interrupt request from the plurality of second priority groups to obtain a target second priority group, and send the target second priority group to the second arbitration circuit, so that the second arbitration circuit can obtain the target second priority group. In this way, the second arbitration circuit selects, in the target second priority group, a number corresponding to a sub-module with the highest default priority, and takes the number corresponding to the sub-module with the highest default priority as an arbitration result. Thus, the arbitration circuit can arbitrate interrupt requests in the plurality of second priority groups according to the plurality of third priority groups to obtain an arbitration result.

[0033] In a possible design, the plurality of sub-modules are specifically configured to generate an interrupt flag corresponding to the respective interrupt event when the interrupt event occurs at the same time.

[0034] The plurality of sub-modules are further specifically configured to generate the interrupt request corresponding to the interrupt flag if the respective corresponding interrupt enable is turned on, and store the corresponding interrupt flag if the respective corresponding interrupt enable is not turned on.

[0035] In a possible design, the in-band interrupt data includes I3C slave address information, information of a sub-module where the interrupt event occurs, and interrupt information.

[0036] In a possible design, each interrupt priority in the plurality of interrupt priorities is a 4-bit binary array, and correspondingly, the configurable priority includes 16 gears; the number of sub-modules in the plurality of sub-modules is a preset number, and correspondingly, the default priority includes a preset number of gears.

[0037] In a second aspect, the present application provides an interrupt control method, which is executed by the interrupt control circuit in the first aspect and each possible design of the first aspect. The interrupt control circuit includes a plurality of sub-modules, an arbitrator, an interrupt handler, and an I3C slave controller. The plurality of sub-modules are connected with the arbitrator and the interrupt handler respectively, the interrupt handler is further connected with the I3C slave controller, and the I3C slave controller is further connected with an I3C master through an I3C bus. The method includes:

[0038] The plurality of sub-modules generate an interrupt request corresponding to the respective interrupt event when the interrupt event occurs at the same time, and send the interrupt request and the respective corresponding interrupt priority of the plurality of sub-modules to the arbitrator, and send in-band interrupt data corresponding to the interrupt event to the interrupt handler.

[0039] The arbiter arbitrates the plurality of interrupt requests according to a plurality of interrupt priorities, obtains an arbitration result, and sends the arbitration result to the plurality of sub-modules and the interrupt processor, where the arbitration result is used to represent a sub-module corresponding to an interrupt request with the highest priority in the plurality of interrupt requests;

[0040] The interrupt processor determines target in-band interrupt data from a plurality of in-band interrupt data according to the arbitration result, and sends the target in-band interrupt data and an initiation signal to the I3C slave controller, where the initiation signal is used to indicate that the target in-band interrupt data has been determined.

[0041] The I3C slave controller sends the target in-band interrupt data to the I3C master according to the initiation signal.

[0042] The plurality of sub-modules further send, after the target in-band interrupt data is sent, interrupt requests other than the interrupt request with the highest priority in the plurality of interrupt requests or the interrupt request corresponding to the target in-band interrupt data that fails to be successfully sent to the arbiter again to reapply for arbitration according to the arbitration result.

[0043] The method provided in the second aspect and each possible design of the second aspect has the beneficial effects of the first aspect and each possible implementation of the first aspect, which will not be repeated here.

[0044] In a third aspect, the present application provides a chip comprising the interrupt control circuit in the first aspect and each possible design of the first aspect.

[0045] In a fourth aspect, the present application provides an electronic device comprising the chip in the third aspect.

[0046] The above description is only a summary of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, the embodiments of the present application can be implemented according to the content of the specification, and in order to make the above and other purposes, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0048] Figure 1 A structural schematic diagram of an interrupt control circuit provided by the embodiments of the present application;

[0049] Figure 2 A flowchart of an interrupt control method provided for an embodiment of the present application is shown in FIG. 1.

[0050] Figure 3 A timing diagram of the operation of an interrupt control circuit provided for an embodiment of the present application is shown in FIG. 2.

[0051] Figure 4 A structure diagram of an arbiter in an interrupt control circuit provided for an embodiment of the present application is shown in FIG. 3.

[0052] Figure 5 A flowchart of the operation of an interrupt control circuit provided for an embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0053] In the present application, “at least one” means one or more, and “multiple” means two or more. “And / or” describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, B exists alone, where A and B can be singular or plural. The character “ / ” generally represents an “or” relationship between the associated objects before and after it. “At least one of the following” or the like means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c alone, can represent: a alone, b alone, c alone, combination of a and b, combination of a and c, combination of b and c, or combination of a, b, and c, where a, b, and c can be single or multiple. In addition, the terms “first”, “second” are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0054] The terms “center”, “longitudinal”, “transverse”, “upper”, “lower”, “left”, “right”, “front”, “back”, and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0055] The terms "connected" and "connection" should be interpreted broadly, for example, the "connection" of a circuit structure can refer to not only a physical connection, but also an electrical connection or a signal connection. For example, the connection can be a direct connection, that is, a physical connection, or an indirect connection through at least one intermediate element, as long as the circuit is connected. The signal connection can be a signal connection through a circuit, or a signal connection through a medium, such as a radio wave.

[0056] First, the professional terms involved in the embodiments of the present application are explained.

[0057] An interrupt is a reaction of a central processing unit (CPU) to a certain event occurring in a system, and an interrupt request can be sent without additional pins.

[0058] An interrupt event is a specific event or situation that triggers an interrupt. An interrupt event can be triggered by a specific state change or a specific operation of an interrupt source. For example, the event represented by the action of pressing a key on a keyboard is an interrupt event, which is generated by the keyboard as an interrupt source.

[0059] An interrupt source is a source or device that can trigger an interrupt. The interrupt source is the source of an interrupt request, which can be a hardware device, such as an external input device or an output device (e.g., a keyboard, a mouse, and a sensor), or a specific instruction or condition in a software program. For example, in a computer system, when a user presses a key on a keyboard, the keyboard as a hardware device is an interrupt source, which sends an interrupt request to the CPU.

[0060] An in-band interrupt is a specific implementation or type of interrupt in a specific communication protocol (e.g., I3C).

[0061] Interrupt information is a collection of information about the details and related data of an interrupt after the interrupt occurs. For example, the interrupt information includes the interrupt type (e.g., sensor data update interrupt and device failure interrupt), the device identifier that generates the interrupt, the time of the interrupt, and specific data related to the interrupt (e.g., new data collected by a sensor).

[0062] An interrupt request is a request sent by an interrupt source to a CPU.

[0063] An in-band interrupt request is a request signal sent by an I3C slave to an I3C master to inform the I3C master that an event has occurred and needs to be handled by the I3C master.

[0064] Time division multiplexing refers to dividing in time, so that each interrupt information is allocated to a specific time for transmission through in-band interrupt.

[0065] Interrupt priority arbitration refers to the priority ordering of multiple in-band interrupt requests of an I3C slave. This priority ordering is a natural consequence of the address arbitration behavior of the I3C bus, in which address bits with value 0 are prioritized over bits with value 1. For example, if I3C slave A has an address of 0x10 (binary 00010000) and I3C slave B has an address of 0x20 (binary 00100000), then during address arbitration, I3C slave A will have more 0s in the front of its address bits than I3C slave B, so I3C slave A will have priority over I3C slave B in gaining control of the bus, and the interrupt of I3C slave A will be processed faster.

[0066] Priority refers to the order in which multiple in-band interrupt requests of an I3C slave are processed. In the I3C bus, the priority of each I3C slave is determined by the I3C slave address, and slaves with lower address values have higher priority. That is, the in-band interrupts of slaves with lower address values will be processed faster by the I3C master than the in-band interrupts of slaves with higher address values.

[0067] Next, the content of the in-band interrupt information reported by the I3C slave to the I3C master in the related art is introduced.

[0068] In the related art, the interrupt information corresponding to each module in the I3C slave is stored in a register, and when it is necessary to report in-band interrupt (IBI) information to the I3C master, the I3C slave sends all IBI information to the I3C master without arbitration, so that the I3C master receives IBI information sent by each module at the same time. In this way, the I3C master needs to process these IBI information to prioritize the processing of interrupts with higher priority.

[0069] The above related art has the following problems.

[0070] First, since the I3C master cannot determine the order of occurrence of the corresponding interrupts from the IBI information, the I3C master can only process the interrupts corresponding to the IBI information according to the priority of the I3C master, which lacks real-time performance.

[0071] Secondly, when there are many modules in the I3C slave, that is, when the I3C slave has many functions, the data amount of the I3C slave when reporting IBI information through in-band interrupts each time will be large, and the number of times of sending will be large when each function frequently sends corresponding interrupts. Therefore, the time consumed by the I3C slave for reporting IBI information to the I3C master is long, and the reporting efficiency is reduced.

[0072] Thirdly, when the interrupt enable of the I3C slave is not turned on, some occurred interrupt events will be lost due to being covered by new interrupt events, so that the I3C master cannot accurately obtain the interrupt events occurring before the new interrupt event.

[0073] Based on the above problems, the I3C slave usually adopts a time division multiplexing and interrupt priority arbitration manner to sequentially send the interrupt information in the I3C slave to the I3C master. However, when the rate of these interrupts is greater than the processing capability of the time division multiplexing and interrupt priority arbitration, part of the interrupt information cannot be sent by the I3C slave in time, so that part of the interrupt information will be covered by new interrupts, causing the loss of interrupt events.

[0074] Therefore, the present application provides an interrupt control circuit, method, chip and electronic device.

[0075] The interrupt control circuit can be a chip or a circuit module. When the interrupt control circuit is a chip, the chip is an I3C slave chip.

[0076] In the present application, the electronic device can include but is not limited to a mobile phone, a router, a vehicle-mounted device and a smart home device.

[0077] Reference Figure 1 , Figure 1 The present application provides a structure schematic diagram of an interrupt control circuit. As shown in Figure 1 , the interrupt control circuit 100 can include a plurality of sub-modules 110, an arbitrator 120, an interrupt processor 130 and an I3C slave controller 140.

[0078] The plurality of sub-modules 110 are respectively connected with the arbitrator 120 and the interrupt processor 130, the interrupt processor 130 is further connected with the I3C slave controller 140, and the I3C slave controller 140 is further connected with an I3C master 200 through an I3C bus.

[0079] The plurality of sub-modules 110, the arbitrator 120, the interrupt processor 130 and the I3C slave controller 140 can be separately arranged or integrally arranged, and the present application does not make a specific limitation on this.

[0080] The I3C master 200 can be an application process (AP) or a microcontroller unit (MCU), and the embodiments of the present application do not make specific limitations in this regard.

[0081] The plurality of sub-modules 110 can include a sub-module 1, a sub-module 2, and a sub-module n, where 1-n represents the number of the sub-module. For ease of illustration, the embodiments of the present application are described by taking an example in which the plurality of sub-modules 110 includes 40 sub-modules. The 40 sub-modules are the sub-module 1, the sub-module 2, and the sub-module 40.

[0082] The sub-module in the plurality of sub-modules 110 refers to a module inside the I3C slave chip for generating an interrupt event, that is, a module for generating an interrupt source. Generally, the interrupt event is triggered by the sub-module. For example, when the timer counts reach a set value, the timer module can generate a timer overflow interrupt, and at this time, the sub-module is the timer module. For another example, when the conversion of the analog signal module is completed or a threshold interrupt is generated, the analog signal module can generate an ADC / DAC interrupt, and at this time, the sub-module is the analog signal module.

[0083] The following refers to Figure 2 , Figure 2 FIG. 1 is a flowchart of an interrupt control method according to an embodiment of the present application.

[0084] S101, when the plurality of sub-modules generate interrupt events at the same time, the plurality of sub-modules generate interrupt requests corresponding to the respective interrupt events, send the interrupt requests and the respective interrupt priorities of the plurality of sub-modules to an arbitrator, and send in-band interrupt data corresponding to the interrupt events to an interrupt processor.

[0085] S102, the arbitrator arbitrates the plurality of interrupt requests according to the plurality of interrupt priorities, obtains an arbitration result, and sends the arbitration result to the plurality of sub-modules and the interrupt processor.

[0086] The arbitration result is used to represent the sub-module corresponding to the interrupt request with the highest priority in the plurality of interrupt requests.

[0087] S103, the interrupt processor determines target in-band interrupt data from the plurality of in-band interrupt data according to the arbitration result, and sends the target in-band interrupt data and a start signal to an I3C slave controller.

[0088] The start signal is used to indicate that the target in-band interrupt data has been determined.

[0089] S104, the I3C slave controller sends the target in-band interrupt data to the I3C master according to the start signal.

[0090] S105. After the target in-band interrupt data is sent, the multiple sub-modules resend the interrupt requests except the highest-priority interrupt request or the interrupt requests corresponding to the unsuccessfully sent target in-band interrupt data to the arbitrator according to the arbitration result to reapply for arbitration.

[0091] When interrupt events occur simultaneously in multiple sub-modules 110, the sub-modules 110 may generate interrupt requests corresponding to their respective interrupt events. Furthermore, the sub-modules 110 may send the interrupt requests and their respective interrupt priorities to the arbiter 120, and send in-band interrupt data corresponding to the interrupt events to the interrupt handler 130. This allows the arbiter 120 to obtain the multiple interrupt requests and interrupt priorities, and the interrupt handler 130 to obtain the multiple in-band interrupt data.

[0092] The in-band interrupt data occupies 3 bytes. For example, the in-band interrupt data may include the I3C slave address, information about the submodule where the interrupt occurred, and the interrupt information. This allows the I3C host to directly retrieve the critical interrupt information from the in-band interrupt data without performing additional parsing.

[0093] The information of the submodule where the interrupt event occurs is, for example, the serial number corresponding to the submodule where the interrupt event occurs.

[0094] In this way, the arbitrator 120 can arbitrate multiple interrupt requests according to multiple interrupt priorities and obtain arbitration results. In addition, the arbitrator 120 can send the arbitration results to the multiple sub-modules 110 and the interrupt handler 130 so that the multiple sub-modules 110 and the interrupt handler 130 can obtain the arbitration results.

[0095] The arbitration result is used to identify the submodule corresponding to the highest-priority interrupt request among the multiple interrupt requests. If a submodule in the multiple submodules 110 agrees with the arbitration result, the interrupt request sent by the submodule has successfully arbitrated. If a submodule in the multiple submodules 110 disagrees with the arbitration result, the interrupt request sent by the submodule has failed arbitration.

[0096] In this way, the interrupt handler 130 can determine the target in-band interrupt data from the plurality of in-band interrupt data according to the arbitration result. Furthermore, the interrupt handler 130 can send the target in-band interrupt data and the initiation signal to the I3C slave controller 140, so that the I3C slave controller 140 can obtain the target in-band interrupt data and the initiation signal.

[0097] The initiation signal is used to indicate that the target in-band interrupt data has been determined.

[0098] Based on this, the I3C slave controller 140 can send the target in-band interrupt data to the I3C master 200 according to the initiation signal, so that the I3C master 200 can obtain the target in-band interrupt data.

[0099] Wherein, after receiving the initiation signal, the I3C slave controller 140 actively pulls down the data line SDA, and after receiving that the I3C master pulls down the clock line SCL, the I3C slave controller 140 can send the target in-band interrupt data to the I3C master 200 in the format of in-band interrupt.

[0100] Wherein, when the I3C slave controller 140 successfully sends the target in-band interrupt data to the I3C master, it means that the interrupt event corresponding to the target in-band interrupt data has been completed. When the I3C slave controller 140 fails to successfully send the target in-band interrupt data to the I3C master, the sub-module corresponding to the target in-band interrupt data will store, i.e. lock, the interrupt event corresponding to the target in-band interrupt data.

[0101] Further, after the target in-band interrupt data is sent, the plurality of sub-modules 110 can send the interrupt requests other than the interrupt request with the highest priority, or the interrupt request corresponding to the target in-band interrupt data that fails to be sent, to the arbitrator 120 again according to the arbitration result. That is, the plurality of sub-modules 110 send the in-band interrupt requests that fail to be arbitrated and the interrupt requests corresponding to the target in-band interrupt data that fails to be sent to the arbitrator 120 again to reapply for arbitration. Thus, the interrupt events corresponding to the target in-band interrupt data that fails to be sent and the interrupt requests other than the interrupt request with the highest priority can be avoided from being lost. That is, the interrupt events that fail to be sent and the interrupt events that fail to be arbitrated can be avoided from being lost.

[0102] In some examples, when the interrupt events occur at the same time, the plurality of sub-modules 110 can generate the interrupt flags corresponding to the respective interrupt events. If the respective interrupt enables are turned on, the plurality of sub-modules 110 can generate the interrupt requests corresponding to the interrupt flags. If the respective interrupt enables are not turned on, the plurality of sub-modules 110 can store the corresponding interrupt flags.

[0103] Wherein, the interrupt flag refers to a state flag bit or a signal in a computer system or a microprocessor. The interrupt flag is used to indicate the occurrence of a certain interrupt event. When a specific event (such as an external device request and an internal timer overflow, etc.) occurs, the corresponding interrupt flag will be set, which will usually trigger the CPU to pause the task being executed and execute the corresponding interrupt service program to process the interrupt event. That is, the interrupt flag is the basis for generating the interrupt request.

[0104] Interrupt enable refers to a control mechanism. Interrupt enable determines whether a specific interrupt source (i.e., the source of the interrupt event) can send an interrupt request to the CPU and be responded to by the CPU. In other words, interrupt enable is a switch. When the switch is turned on (i.e., interrupt enable is on), the corresponding interrupt source can send an interrupt request to the CPU when an interrupt event occurs, allowing the CPU to respond and process this interrupt request according to the established interrupt processing flow. When the switch is turned off (i.e., interrupt enable is off), even if an interrupt event occurs at the interrupt source, no interrupt request will be sent to the CPU. In this way, the CPU will not process this interrupt event.

[0105] The following combination Figure 3 , Figure 3 This is a timing diagram of an interrupt control circuit according to an embodiment of the present application, which details the working contents of the interrupt control circuit 100.

[0106] like Figure 3 As shown, at time t1 , an interrupt event INT_SRC occurs in any submodule among the multiple submodules 110 , and any submodule among the multiple submodules 110 may generate an interrupt flag IF corresponding to the interrupt event INT_SRC.

[0107] During the period t2-t3, any of the multiple sub-modules 110 can generate an interrupt request INT_REQ corresponding to its respective interrupt event INT_SRC based on the interrupt flag IF. Thus, any of the multiple sub-modules 110 can send the interrupt request INT_REQ and the corresponding interrupt priority to the arbiter 120. In this way, the arbiter 120 can arbitrate the multiple interrupt requests INT_REQ based on the multiple interrupt priority levels and obtain an arbitration result INT_NUM.

[0108] During the time period t3-t4, the interrupt handler 130 may determine the target in-band interrupt data IBI_DATA from the plurality of in-band interrupt data according to the arbitration result INT_NUM. Furthermore, the interrupt handler 130 may send the target in-band interrupt data IBI_DATA and the initiation signal FORCE_SDA to the I3C slave controller 140, so that the I3C slave controller 140 may obtain the target in-band interrupt data and the initiation signal FORCE_SDA, so that the I3C slave controller 140 may send the target in-band interrupt data IBI_DATA to the I3C host 200 via the data line SDA and the clock line SCL of the I3C bus, so that the I3C host 200 may obtain the target in-band interrupt data IBI_DATA.

[0109] At time t4, it can be determined that the sending of the target in-band interrupt data IBI_DATA is completed based on the sending completion signal I3C_IBI_DONE.

[0110] The interrupt control circuit provided in the present application, when an interrupt event occurs at the same time, multiple sub-modules generate interrupt requests corresponding to respective interrupt events, and send the interrupt requests and interrupt priorities corresponding to respective sub-modules to an arbitrator, and send in-band interrupt data corresponding to the interrupt event to an interrupt processor, so that the arbitrator obtains the interrupt requests and interrupt priorities corresponding to respective sub-modules, and the interrupt processor obtains the in-band interrupt data corresponding to the interrupt event. In this way, the arbitrator can arbitrate multiple interrupt requests according to multiple interrupt priorities, obtain an arbitration result, and send the arbitration result to the multiple sub-modules and the interrupt processor, which indicates the sub-module corresponding to the interrupt request with the highest priority among the multiple interrupt requests, so that the multiple sub-modules obtain the arbitration result. In this way, the interrupt processor can determine target in-band interrupt data from the multiple in-band interrupt data according to the arbitration result, and send the target in-band interrupt data and an initiation signal indicating that the target in-band interrupt data has been determined to the I3C slave controller, so that the I3C slave controller obtains the target in-band interrupt data and the initiation signal. Further, the I3C slave controller can send the target in-band interrupt data to the I3C master according to the initiation signal, so that the I3C master can obtain the target in-band interrupt data. Further, after the target in-band interrupt data is sent, the multiple sub-modules can send other interrupt requests in the multiple interrupt requests or interrupt requests corresponding to the target in-band interrupt data that is not successfully sent to the arbitrator again according to the arbitration result, to reapply for arbitration. Thus, the interrupt event corresponding to the target in-band interrupt data that is not successfully sent and the interrupt event corresponding to other interrupt requests in the multiple interrupt requests except the interrupt request with the highest priority can be avoided.

[0111] Based on the description of the above embodiment, an exemplary possible implementation of the arbitrator 120 is provided. Referring to Figure 4 , Figure 4 The structure diagram of the arbitrator in the interrupt control circuit provided in the embodiment of the present application is provided. As Figure 4 shown, the arbitrator 120 can include a first grouping circuit 121, a second grouping circuit 122, an obtaining circuit 123, and an arbitration circuit 124.

[0112] The first grouping circuit 121, the arbitration circuit 124, and the second grouping circuit 122 are connected with the multiple sub-modules 110, and the second grouping circuit 122 is further connected with the obtaining circuit 123.

[0113] Figure 4In some embodiments, the interrupt priority is denoted by INT SRCx PRI, the first priority group is denoted by PRIx INT, the second priority group is denoted by INT PRIx REQ, the third priority group is denoted by GET PRIx INT, the arbitration result is denoted by INT NUM, the target second priority group is denoted by INT REQ SEL, and the interrupt request is denoted by INT REQ.

[0114] In some embodiments, each of the plurality of interrupt priorities is a 4-bit binary number, and correspondingly, the configurable priority can include 16 gears.

[0115] In some embodiments, each of the plurality of interrupt priorities is a 4-bit binary number, and correspondingly, the configurable priority can include 16 gears.

[0116] In some embodiments, the plurality of sub-modules 110 includes 40 sub-modules. Correspondingly, the default priority can include 40 gears. In some embodiments, the plurality of interrupt requests is represented by a 40-bit array INT REQ, each bit of the array corresponds to one of the plurality of sub-modules 110, and is used to represent the interrupt request sent by the sub-module.

[0117] In some embodiments, the plurality of sub-modules 110 includes 40 sub-modules, and each of the plurality of interrupt priorities is a 4-bit binary number. Therefore, the plurality of interrupt priorities can include 40 interrupt priorities, and the configurable priority can include 16 gears. Figure 4 In some embodiments, the plurality of interrupt priorities includes interrupt priority INT SRC1 PRI[3:0], interrupt priority INT SRC2 PRI[3:0], and interrupt priority INT SRC40 PRI[3:0].

[0118] The first grouping circuit 121 can receive the plurality of interrupt priorities. The first grouping circuit 121 can group the plurality of interrupt priorities to obtain a plurality of first priority groups, and send the plurality of first priority groups to the second grouping circuit 122, so that the second grouping circuit 122 can obtain the plurality of first priority groups.

[0119] In some embodiments, each of the plurality of first priority groups includes a plurality of interrupt priorities with the same configurable priority, and is sorted according to the default priority. The default priority is negatively correlated with the number corresponding to each of the plurality of sub-modules 110.

[0120] wherein, since the configurable priority has 16 levels. Therefore, the plurality of first priority groups can include 16 first priority groups. Figure 4 The 16 first priority groups shown in FIG. 1 1 are respectively first priority group PRI0 INT [39:0], first priority group PRI1 INT [39:0] to first priority group PRI15 INT [39:0].

[0121] wherein, the default priority is negatively related to the number corresponding to each of the plurality of sub-modules 1 10. That is, the smaller the number corresponding to a sub-module, the higher the default priority corresponding to the sub-module. For example, the number corresponding to sub-module 2 is greater than the number corresponding to sub-module 5, and the default priority of sub-module 2 is higher than the default priority of sub-module 5. For another example, the number corresponding to sub-module 8 is less than the number corresponding to sub-module 5, and the default priority of sub-module 8 is lower than the default priority of sub-module 5.

[0122] For example, the first priority group PRI0 INT [39:0] in the plurality of first priority groups indicates that the configurable priority of this first priority group is 0. When the configurable priority of sub-module 1 and sub-module 4 in the plurality of sub-modules 1 10 is 0, bit0 corresponding to sub-module 1 and bit4 corresponding to sub-module 4 in the first priority group PRI0 INT [39:0] are set to 1. The bit0 corresponding to sub-module 1 and the bit4 corresponding to sub-module 4 in other first priority groups in the plurality of first priority groups except the first priority group PRI0 INT [39:0] are all set to 0.

[0123] For another example, the first priority group PRI3 INT [39:0] in the plurality of first priority groups indicates that the configurable priority of this first priority group is 3. For another example, the first priority group PRI5 INT [39:0] in the plurality of first priority groups indicates that the configurable priority of this first priority group is 5.

[0124] The second grouping circuit 122 can receive a plurality of interrupt requests. And, the second grouping circuit 122 can distribute the plurality of interrupt requests to the plurality of first priority groups to obtain a plurality of second priority groups, and respectively send the plurality of second priority groups to the acquisition circuit 123 and the arbitration circuit 124, so that the acquisition circuit 123 and the arbitration circuit 124 can acquire the plurality of second priority groups.

[0125] wherein, each second priority group contains a plurality of interrupt requests with the same configurable priority.

[0126] wherein, since the plurality of first priority groups can include 16 first priority groups. Therefore, the plurality of second priority groups can include 16 second priority groups. Figure 4The 16 second priority groups shown in FIG. 16 are respectively second priority group INT PRI0 REQ[39:0], second priority group INT PRI1 REQ[39:0], second priority group INT PRI1 REQ[39:0] to second priority group INT PRI15 REQ[39:0].

[0127] For example, the second grouping circuit 122 can perform a bitwise AND operation on the plurality of interrupt requests and the plurality of first priority groups to assign the plurality of interrupt requests to the plurality of first priority groups, so that the second grouping circuit 122 can obtain the plurality of second priority groups.

[0128] For example, the plurality of interrupt requests INT REQ[39:0] can be subjected to a bitwise AND operation with the first priority group PRI0 INT[39:0] having a configurable priority of 0 to obtain the second priority group INT PRI0 REQ[39:0] having a configurable priority of 0, which can be expressed by formula (1):

[0129]

[0130] According to formula (1), the second priority group INT PRI0 REQ[39:0] having a configurable priority of 0 includes the interrupt request corresponding to sub-module 1, the interrupt request corresponding to sub-module 13, and the interrupt request corresponding to sub-module 14.

[0131] In this way, the obtaining circuit 123 can determine whether there is an interrupt request in each of the plurality of second priority groups to obtain a plurality of third priority groups. Moreover, the obtaining circuit 123 can send the plurality of third priority groups to the arbitration circuit 124, so that the arbitration circuit 124 can obtain the plurality of third priority groups.

[0132] For example, the obtaining circuit 123 can perform a bitwise OR operation on the plurality of second priority groups to determine whether there is an interrupt request in each of the plurality of second priority groups.

[0133] In this way, the obtaining circuit 123 can determine whether there is an interrupt request in each of the plurality of second priority groups to obtain a plurality of third priority groups. Moreover, the obtaining circuit 123 can send the plurality of third priority groups to the arbitration circuit 124, so that the arbitration circuit 124 can obtain the plurality of third priority groups. Figure 4 The 16 third priority groups shown in FIG. 16 are respectively second priority group GET PRI0 INT, third priority group GET PRI1 INT, third priority group GET PRI2 INT to third priority group GET PRI15 INT.

[0134] For example, continuing to combine formula (1), the acquisition circuit 123 can perform a bitwise OR operation on the second priority group INT_PRI0_REQ[39:0] to determine whether there is an interrupt request in the second priority group INT_PRI0_REQ[39:0], so that the acquisition circuit 123 can obtain the third priority group GET_PRI0_INT.

[0135] Therefore, the arbitration circuit 124 can arbitrate the interrupt requests in the plurality of second priority groups according to the plurality of third priority groups to obtain an arbitration result, so that the arbitrator 120 can arbitrate the plurality of interrupt requests according to the plurality of interrupt priorities to obtain an arbitration result.

[0136] In summary, the first grouping circuit can receive a plurality of interrupt priorities, group the plurality of interrupt priorities to obtain a plurality of first priority groups, and send the plurality of first priority groups to the second grouping circuit, so that the second grouping circuit can obtain the plurality of first priority groups. Each first priority group contains a plurality of interrupt priorities with the same configurable priority, and is sorted according to a default priority, which is negatively related to the number corresponding to each of the plurality of sub-modules. The second grouping circuit can receive a plurality of interrupt requests and distribute the plurality of interrupt requests to the plurality of first priority groups to obtain a plurality of second priority groups, and send the plurality of second priority groups to the acquisition circuit and the arbitration circuit respectively, so that the acquisition circuit and the arbitration circuit can obtain the plurality of second priority groups. Each second priority group contains a plurality of interrupt requests with the same configurable priority. In this way, the acquisition circuit can determine whether there is an interrupt request in each second priority group in the plurality of second priority groups to obtain a plurality of third priority groups, and send the plurality of third priority groups to the arbitration circuit, so that the arbitration circuit can obtain the plurality of third priority groups. Further, the arbitration circuit can arbitrate the interrupt requests in the plurality of second priority groups according to the plurality of third priority groups to obtain an arbitration result. Therefore, the arbitrator can arbitrate the plurality of interrupt requests according to the plurality of interrupt priorities to obtain an arbitration result.

[0137] Based on the above description of the embodiments, an exemplary possible implementation of the first grouping circuit 121 is provided. As shown in FIG. 12, the first grouping circuit 121 can include an encoding conversion circuit 121-1 and a first sub-grouping circuit 121-2. Figure 4

[0138] The encoding conversion circuit 121-1 is connected to the plurality of sub-modules 110 and the first sub-grouping circuit 121-2 respectively.

[0139] ​The encoding conversion circuit 121-1 can convert the encoding form of the plurality of interrupt priorities from binary code to one-hot code to obtain a plurality of converted interrupt priorities. And the encoding conversion circuit 121-1 can send the plurality of converted interrupt priorities to the first sub-grouping circuit 121-2, so that the first sub-grouping circuit 121-2 can obtain the plurality of converted interrupt priorities.

[0140] Among them, since the plurality of interrupt priorities can include 40 interrupt priorities. Therefore, the plurality of converted interrupt priorities can include 40 converted interrupt priorities. Figure 4 The 40 converted interrupt priorities shown in the table are converted interrupt priority INT_SRC1_PRI[15:0], converted interrupt priority INT_SRC2_PRI[15:0] to converted interrupt priority INT_SRC1_PRI[15:0], respectively.

[0141] Among them, binary code is a kind of encoding method that uses binary numbers composed of 0 and 1 to represent information, and is the most basic encoding form in computers and digital systems.

[0142] Among them, one-hot code is a special encoding method, in which only one bit is 1 and the rest are 0 in an encoding group. If there are n different states, one-hot code needs n bits to represent. For example, assuming there are 4 different states, the 4 different states can be represented by one-hot code as follows: state 1 is 1000, state 2 is 0100, state 3 is 0010, and state 4 is 0001.

[0143] Among them, the encoding conversion circuit 121-1 can convert the encoding form of the plurality of interrupt priorities from binary code to one-hot code, in order to facilitate subsequent logical operations such as bitwise AND operation and bitwise OR operation.

[0144] In this way, the first sub-grouping circuit 121-2 can group the plurality of converted interrupt priorities according to the configurable priority to obtain a plurality of first priority groups. Thus, the first grouping circuit 121 can group the plurality of interrupt priorities to obtain a plurality of first priority groups.

[0145] In summary, the encoding conversion circuit can convert the encoding form of the plurality of interrupt priorities from binary code to one-hot code to obtain a plurality of converted interrupt priorities, and send the plurality of converted interrupt priorities to the first sub-grouping circuit, so that the first sub-grouping circuit can obtain the plurality of converted interrupt priorities. In this way, the first sub-grouping circuit can group the plurality of converted interrupt priorities according to the configurable priority to obtain a plurality of first priority groups. Thus, the first grouping circuit can group the plurality of interrupt priorities to obtain a plurality of first priority groups.

[0146] Based on the above description of the embodiments, an exemplary possible implementation of the arbitration circuit 124 is shown. As shown in Figure 5 The arbitration circuit 124 can include a first arbitration circuit 124-1 and a second arbitration circuit 124-2.

[0147] The first arbitration circuit 124-1 is connected to the plurality of sub-modules 110, the second grouping circuit 122, and the second arbitration circuit 124-2, respectively.

[0148] The first arbitration circuit 124-1 can select, from the plurality of second priority groups, a second priority group with the highest configurable priority and an interrupt request, to obtain a target second priority group. The first arbitration circuit 124-1 can send the target second priority group to the second arbitration circuit 124-2, so that the second arbitration circuit 124-2 can obtain the target second priority group.

[0149] For example, the first arbitration circuit 124-1 can perform a logical operation on the plurality of third priority groups and the plurality of second priority groups. In this way, the first arbitration circuit 124-1 can select, from the plurality of second priority groups, a second priority group with the highest configurable priority and an interrupt request, to obtain a target second priority group.

[0150] For example, the first arbitration circuit 124-1 can perform a logical operation on the plurality of third priority groups and the plurality of second priority groups. In this way, the first arbitration circuit 124-1 can select, from the plurality of second priority groups, a second priority group with the highest configurable priority and an interrupt request, to obtain a target second priority group.

[0151] For example, the first arbitration circuit 124-1 can perform a logical operation on the plurality of third priority groups and the plurality of second priority groups. In this way, the first arbitration circuit 124-1 can select, from the plurality of second priority groups, a second priority group with the highest configurable priority and an interrupt request, to obtain a target second priority group.

[0152] INT_REQ_SEL[39:0] = 40'h00_0000_C008 (2)

[0153] For example, the first arbitration circuit 124-1 can perform a logical operation on the plurality of third priority groups and the plurality of second priority groups. In this way, the first arbitration circuit 124-1 can select, from the plurality of second priority groups, a second priority group with the highest configurable priority and an interrupt request, to obtain a target second priority group.

[0154] In this way, the second arbitration circuit 124-2 can select, from the target second priority group, a number corresponding to a sub-module with the highest default priority. The arbitration circuit 124 can take the number corresponding to the sub-module with the highest default priority as an arbitration result. Thus, the arbitration circuit 124 can arbitrate interrupt requests in the plurality of second priority groups according to the plurality of third priority groups, to obtain an arbitration result.

[0155] wherein the number corresponding to the sub-module with the highest default priority is the arbitration result.

[0156] Further taking the target second priority group INT REQ SEL [39:0] shown in formula (2) as an example, based on formula (2), it can be known that the interrupt source with the highest default priority in the target second priority group INT REQ SEL [39:0] is sub-module 3. In this way, the second arbitration circuit 124-2 can take the number corresponding to sub-module 3 as the arbitration result, so that the second arbitration circuit 124-2 can obtain the arbitration result.

[0157] In summary, the first arbitration circuit can select a second priority group with the highest configurable priority and an interrupt request in a plurality of second priority groups according to a plurality of third priority groups, obtain a target second priority group, and send the target second priority group to the second arbitration circuit, so that the second arbitration circuit can obtain the target second priority group. In this way, the second arbitration circuit selects the number corresponding to the sub-module with the highest default priority in the target second priority group, and takes the number corresponding to the sub-module with the highest default priority as the arbitration result. Thus, the arbitration circuit can arbitrate the interrupt requests in a plurality of second priority groups according to a plurality of third priority groups, and obtain an arbitration result.

[0158] In addition, since the arbitrator 120 implements arbitration on the interrupt requests through logical combinations such as bitwise AND operation and bitwise OR operation, it does not need to store data, so that the area of the arbitrator 120 is small. For example, in the case where the configurable priority includes 16 levels and the default priority includes 40 levels in the embodiment of the present application, the arbitrator 120 can be implemented by only 2648 two-input NOT gate devices.

[0159] The working process of the interrupt control circuit 100 will be described in detail below. Figure 5 , ​ The working process of the interrupt control circuit 100 will be described in detail below.

[0160] After the chip of the interrupt control circuit 100 starts to power on, when the plurality of sub-modules 110 generate interrupt events at the same time, each sub-module generates an interrupt flag corresponding to the interrupt event. After generating the interrupt flag, the plurality of sub-modules 110 judge whether the interrupt enable corresponding to each sub-module is opened. If the plurality of sub-modules 110 judge that the interrupt enable corresponding to each sub-module is opened, an interrupt request is generated based on the interrupt flag corresponding to each sub-module. If the plurality of sub-modules 110 judge that the interrupt enable corresponding to each sub-module is not opened, the interrupt flag corresponding to each sub-module is stored.

[0161] wherein the interrupt flag is the original signal of the interrupt request.

[0162] After generating the interrupt request, the plurality of sub-modules 110 can send the interrupt request and the interrupt priority corresponding to each of the plurality of sub-modules 110 to the arbitrator 120 to apply for arbitration to the arbitrator 120. In addition, the plurality of sub-modules 110 can send the in-band interrupt data corresponding to the interrupt event to the interrupt handler 130, so that the interrupt handler 130 can obtain the in-band interrupt data.

[0163] In this way, the arbitrator 120 can arbitrate the plurality of interrupt requests according to the configurable priority and the default priority in the plurality of interrupt priorities, and obtain an arbitration result. In addition, the arbitrator 120 can send the arbitration result to the plurality of sub-modules 110 and the interrupt handler 130, so that the plurality of sub-modules 110 and the interrupt handler 130 can obtain the arbitration result.

[0164] If the sub-module in the plurality of sub-modules 110 is consistent with the arbitration result, the interrupt request sent by the sub-module is successful. In this way, the interrupt handler 130 can determine the target in-band interrupt data from the plurality of in-band interrupt data according to the arbitration result. In addition, the interrupt handler 130 can send the target in-band interrupt data and the initiation signal to the I3C slave controller 140, so that the I3C slave controller 140 can obtain the target in-band interrupt data and the initiation signal. In this way, the I3C slave controller 140 actively pulls down the data line SDA, and after receiving that the I3C master pulls down the clock line SCL, the target in-band interrupt data is sent, so that the I3C master can obtain the target in-band interrupt data.

[0165] During the process of sending the target in-band interrupt data by the I3C slave controller 140, an exception may occur, resulting in a failure to send the target in-band interrupt data. When the I3C slave controller 140 fails to send the target in-band interrupt data, the I3C slave controller 140 can save the target in-band interrupt data to lock the target in-band interrupt data, so as to avoid the interrupt event corresponding to the target in-band interrupt data from being lost due to the failure of in-band interrupt transmission. In addition, the I3C slave controller 140 can resend the interrupt request corresponding to the target in-band interrupt data that fails to be sent successfully to the arbitrator 120 to reapply for arbitration.

[0166] When the I3C slave controller 140 successfully sends the target in-band interrupt data, the corresponding sub-module is considered as the interrupt event corresponding to the target in-band interrupt data being completed, and the corresponding interrupt request is marked as completed.

[0167] If a submodule in the plurality of submodules 110 is inconsistent with the arbitration result, the interrupt request sent by the submodule fails arbitration. In this way, after the target in-band interrupt data is sent, the plurality of submodules 110 can send the interrupt requests other than the highest priority interrupt request from the plurality of interrupt requests to the arbitrator 120. In other words, the plurality of submodules 110 can send the interrupt request that failed arbitration from the plurality of interrupt requests to the arbitrator 120 to reapply for arbitration.

[0168] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An interrupt control circuit, characterized in that: The interrupt control circuit includes: multiple submodules, an arbiter, an interrupt processor and an I3C slave controller; The multiple submodules are respectively connected to the arbiter and the interrupt processor, the interrupt processor is further connected to the I3C slave controller, and the I3C slave controller is further connected to the I3C host via an I3C bus; The multiple sub-modules are configured to generate interrupt requests corresponding to the respective interrupt events when an interrupt event occurs at the same time, send the interrupt request and the interrupt priority levels corresponding to the multiple sub-modules to the arbitrator, and send in-band interrupt data corresponding to the interrupt event to the interrupt processor; The arbitrator is configured to arbitrate multiple interrupt requests according to multiple interrupt priorities, obtain an arbitration result, and send the arbitration result to the multiple sub-modules and the interrupt handler, wherein the arbitration result is used to indicate the sub-module corresponding to the interrupt request with the highest priority among the multiple interrupt requests; The interrupt processor is configured to determine target in-band interrupt data from a plurality of in-band interrupt data according to the arbitration result, and send the target in-band interrupt data and an initiation signal to the I3C slave controller, wherein the initiation signal is configured to indicate that the target in-band interrupt data has been determined; The I3C slave controller is configured to send the target in-band interrupt data to the I3C host according to the initiation signal; The multiple sub-modules are further configured to, after the target in-band interrupt data is sent, resend the other interrupt requests among the multiple interrupt requests except the interrupt request with the highest priority or the interrupt requests corresponding to the target in-band interrupt data that were not sent successfully to the arbitrator according to the arbitration result, so as to reapply for arbitration.

2. The circuit according to claim 1, wherein: The arbitrator includes: a first grouping circuit, a second grouping circuit, an acquisition circuit and an arbitration circuit; The first grouping circuit, the arbitration circuit, and the second grouping circuit are all connected to the multiple sub-modules, and the second grouping circuit is further connected to the acquisition circuit; The first grouping circuit is configured to receive the plurality of interrupt priority levels, group the plurality of interrupt priority levels to obtain a plurality of first priority groups, and send the plurality of first priority groups to the second grouping circuit, wherein each first priority group includes a plurality of interrupt priority levels having the same configurable priority level and is sorted according to a default priority level, wherein the default priority level is negatively correlated with the numbers corresponding to the plurality of submodules; The second grouping circuit is configured to receive the plurality of interrupt requests, and allocate the plurality of interrupt requests to the plurality of first priority groups to obtain a plurality of second priority groups, and send the plurality of second priority groups to the acquisition circuit and the arbitration circuit respectively, each second priority group including a plurality of interrupt requests having the same configurable priority; The acquisition circuit is configured to determine whether there is an interrupt request in each of the plurality of second priority groups, obtain a plurality of third priority groups, and send the plurality of third priority groups to the arbitration circuit; The arbitration circuit is configured to arbitrate the interrupt requests in the plurality of second priority groups according to the plurality of third priority groups to obtain the arbitration result.

3. The circuit according to claim 2, characterized in that The first grouping circuit includes: a code conversion circuit and a first sub-grouping circuit; The encoding conversion circuit is connected to the multiple sub-modules and the first sub-grouping circuit respectively; The code conversion circuit is configured to convert the coding forms of the plurality of interrupt priority levels from binary codes to one-hot codes to obtain a plurality of converted interrupt priority levels, and send the plurality of converted interrupt priority levels to the first sub-grouping circuit; The first sub-grouping circuit is configured to group the multiple converted interrupt priority levels according to the configurable priority level to obtain the multiple first priority groups.

4. The circuit according to claim 2, characterized in that The second grouping circuit is specifically configured to perform a bitwise AND operation on the multiple interrupt requests and the multiple first priority groups, so as to distribute the multiple interrupt requests to the multiple first priority groups.

5. The circuit according to claim 2, characterized in that The acquisition circuit is specifically configured to perform a bitwise OR operation on the plurality of second priority groups to determine whether there is an interrupt request in each of the plurality of second priority groups.

6. The circuit according to claim 2, characterized in that The arbitration circuit includes: a first arbitration circuit and a second arbitration circuit; The first arbitration circuit is respectively connected to the plurality of sub-modules, the second grouping circuit and the second arbitration circuit; the first arbitration circuit is configured to select, from among the plurality of second priority groups, a second priority group with the highest configurable priority and having an interrupt request, based on the plurality of third priority groups, to obtain a target second priority group, and send the target second priority group to the second arbitration circuit; The second arbitration circuit is configured to select a number corresponding to a submodule with the highest default priority in the target second priority group, and use the number corresponding to the submodule with the highest default priority as the arbitration result.

7. The circuit according to any one of claims 1 to 6, characterized in that: The multiple sub-modules are specifically configured to generate interrupt flags corresponding to the respective interrupt events when the interrupt events occur at the same time; The multiple sub-modules are further specifically configured to generate the interrupt request corresponding to the interrupt flag if the interrupt enable corresponding to each of them is enabled; and store the corresponding interrupt flag if the interrupt enable corresponding to each of them is not enabled.

8. The circuit according to any one of claims 1 to 6, characterized in that: The in-band interrupt data includes: I3C slave address information, information about the submodule where the interrupt event occurs, and interrupt information.

9. The circuit according to any one of claims 2 to 6, characterized in that: Each interrupt priority level among the multiple interrupt priority levels is a 4-bit binary array, and correspondingly, the configurable priority level includes 16 gears; the number of sub-modules in the multiple sub-modules is a preset number, and correspondingly, the default priority level includes a preset number of gears.

10. An interrupt control method, characterized in that: The method is performed by an interrupt control circuit, which includes: multiple submodules, an arbiter, an interrupt processor, and an I3C slave controller; the multiple submodules are respectively connected to the arbiter and the interrupt processor, the interrupt processor is also connected to the I3C slave controller, and the I3C slave controller is also connected to an I3C host via an I3C bus; the method includes: When interrupt events occur at the same time, the multiple submodules generate interrupt requests corresponding to the respective interrupt events, send the interrupt requests and the interrupt priorities corresponding to the multiple submodules to the arbitrator, and send in-band interrupt data corresponding to the interrupt events to the interrupt processor; The arbitrator arbitrates the multiple interrupt requests according to the multiple interrupt priorities, obtains an arbitration result, and sends the arbitration result to the multiple sub-modules and the interrupt handler, wherein the arbitration result is used to indicate the sub-module corresponding to the interrupt request with the highest priority among the multiple interrupt requests; The interrupt processor determines target in-band interrupt data from a plurality of in-band interrupt data according to the arbitration result, and sends the target in-band interrupt data and an initiation signal to the I3C slave controller, wherein the initiation signal is used to indicate that the target in-band interrupt data has been determined; The I3C slave controller sends the target in-band interrupt data to the I3C host according to the initiation signal; After the target in-band interrupt data is sent, the multiple sub-modules further send the other interrupt requests among the multiple interrupt requests except the interrupt request with the highest priority or the interrupt requests corresponding to the target in-band interrupt data that were not sent successfully to the arbitrator again according to the arbitration result to reapply for arbitration.

11. A chip, characterized in that: The chip includes the interrupt control circuit according to any one of claims 1 to 9.

12. An electronic device, characterized in that: include: The chip according to claim 11.

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