Radiation-proof SRAM (Static Random Access Memory) circuit and chip combining polarity reinforcement and source isolation technologies

Abstract

The invention discloses an anti-radiation SPH-14T SRAM (Static Random Access Memory) circuit and an anti-radiation SPH-14T SRAM chip combining polarity reinforcement and source isolation technologies, which are designed by adopting a polarity reinforcement principle that transistors of the same type have a single flip characteristic under spatial heavy ion bombardment, and the stability of redundant nodes S0 and S1 is ensured by utilizing the design method. And therefore, the anti-overturning capability of nodes in the circuit is enhanced. Secondly, the stability of a node Q and a node QB is improved through multiplexing of a pull-up PMOS tube and the source isolation technology, meanwhile, the circuit uses four transmission transistors for reading and writing, in the data writing process, a bit line writes data into an internal node QQB and an internal node S0S1 at the same time through transmission transistors N7, N8, N9 and N10, so that the data is more easily written into a storage node, and the stability of the storage node is improved. Therefore, the design greatly improves the data writing speed and noise margin (SNM) of the unit, and a simulation result shows that compared with the existing five SRAM units, the SPH-14T unit disclosed by the invention has more prominent advantages in the writing speed aspect and the noise margin aspect compared with other five SRAMs.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a unit circuit structure capable of improving the write speed of a storage unit and the unit's ability to resist single event upsets (SEUs). The present invention relates to a 14T radiation-resistant SRAM storage unit, hereinafter referred to as SPH-14T. Background Art

[0002] With the continuous advancement of complementary metal oxide semiconductor (CMOS) technology, the size of electronic devices is becoming smaller and their integration is increasing. Factors such as the space radiation environment in which they operate are all affecting device stability. Furthermore, the use of lower supply voltages to reduce device energy loss has further posed a severe challenge to device stability. Radiation effects in space can trigger single event effects (SEEs) in operating static random access memory (SRAM). SEEs can cause both hard and soft errors in electronic devices. Hard errors can cause physical damage to the device, leading to catastrophic consequences; soft errors, on the other hand, primarily affect the device's operating state, preventing it from transmitting correct information. Due to the limited energy of space radiation particles, the probability of causing soft errors in devices is much greater than the probability of causing hard errors. Among soft errors, the probability of a single event upset (SEU) is much higher than that of other types of errors. To improve the unit's SEU resistance, existing technologies mainly include the following solutions:

[0003] 1) If Figure 1 The figure shows a single-event upset-resistant SIS-10T circuit proposed by Soumitra Pal in 2022. It has four storage nodes and two transmission transistors. When an SEU occurs on a single storage node, that node is eventually recovered by the remaining nodes. However, if an SEU occurs on any two storage nodes, the stored information in that circuit node is flipped and cannot be recovered, resulting in erroneous data.

[0004] 2) If Figure 2 The figure shows a QUATRO-10T circuit proposed by Shah M. Jahinuzzaman and David J. Rennie in 2009. It has better SEU immunity than the traditional six-transistor cell structure, but the cell has poor write capability and the longest write delay.

[0005] 3) If Figure 3 The figure shows the SEA-14T circuit proposed by Soumitra Pal in 2021. This circuit uses two NMOS transistors to write data into the cell. Due to the cross-interlocking of internal nodes, the cell stability is relatively poor and its performance in noise tolerance is relatively poor.

[0006] 4) If Figure 4 The figure shows the RSP14T circuit proposed by Chunyu Peng in 2019. This circuit uses source isolation technology. When the cell stores a "1", the stacked PMOS structure connects transistor P2 to the weak "1" signal. Therefore, the amount of charge collected by the drain of transistor P2 will be reduced, the resistance of node QB to SEU is improved, and the cell becomes more stable.

[0007] 5) If Figure 5 The figure shows the RHBD-14T circuit proposed by Naga Raghuram CH in 2021. This circuit uses polarity reinforcement technology, which reduces the number of sensitive nodes but results in larger read and write delays and lower noise margin (SNM) values.

[0008] 6) If Figure 6 The figure shows the RH-12T circuit proposed by Chunyan Hu in 2017. This circuit uses polarity reinforcement technology to reduce the number of sensitive nodes. It is not only immune to perturbations at any single sensitive node, but can also tolerate perturbations at multiple nodes on a specific node.

[0009] 7) If Figure 7 The figure shows the EDP-12T circuit proposed by Soumitra Pal in 2023. This circuit uses polarity hardening technology to achieve single-node inversion self-recovery. Compared with other radiation-hardened SRAMs, EDP-12T has the lowest power consumption. Summary of the Invention

[0010] The purpose of the present invention is to provide an SPH-14T radiation-resistant SRAM memory cell based on polarity reinforcement technology and source isolation technology, which can improve the reading and writing speed of the memory cell, reduce the power consumption of the cell and improve the single event upset resistance of the cell.

[0011] The purpose of the present invention is achieved through the following technical solutions:

[0012] In a first aspect, the present invention provides an SRAM storage circuit that can effectively self-recover single-node data flipping, including a pull-up tube portion, a pull-down tube portion, and a transmission tube portion.

[0013] An SRAM storage circuit capable of effectively self-recovering single-node data flipping, characterized by comprising:

[0014] The pull-up tube part includes 4 PMOS tubes P1-P4, 2 NMOS tubes N3, N4, and is used for pulling up storage nodes S0, Q, QB, S1;

[0015] The pull-down tube part includes 4 NMOS tubes N1, N2, N5, N6, and is used for pulling down the storage nodes S0, Q, QB, S1;

[0016] The transmission tube part includes 4 NMOS tubes N7-N10; wherein the data of the node Q and the node S0 are written by the bit line BL through N7, N9; the data of the node QB and the node S1 are written by the bit line BLB through N8, N10;

[0017] Wherein, S0 and S1 are the connection nodes of two NMOS transistors, forming N polarity reinforcement; Q and QB are source isolation layout nodes; the width-length ratio of all pull-up PMOS transistors and transmission transistors is 120 / 65, and the width-length ratio of pull-up NMOS transistors and pull-down transistors is 280 / 65.

[0018] Preferably, the sources of P1 and P2 and the drains of N3 and N4 are connected to VDD, and the sources of N1, N2, N5, and N6 are grounded to GND;

[0019] S0 is connected to the source of N3, the drain of N5, the gate of P2, and the gate of P4;

[0020] S1 is connected to the source of N4, the drain of N6, the gate of P1, and the gate of P3;

[0021] Q is connected to the drain of N1, the drain of P3, the gate of N1, the gate of N5, and the gate of N3;

[0022] QB is connected to the drain of N2, the drain of P4, the gate of N2, the gate of N6, and the gate of N4;

[0023] The drain of P1 is connected to the source of P3, the drain of P2 is connected to the source of P4, the drain of P3 is connected to the drain of N1, the drain of P4 is connected to the drain of N2, the source of N3 is connected to the drain of N5, and the source of N4 is connected to the drain of N6.

[0024] Preferably, the drain of N7 is connected to Q, the gate is connected to WL, and the source is connected to BL;

[0025] The source of N8 is connected to QB, the gate is connected to WL, and the drain is connected to BLB.

[0026] The source of N9 is connected to S0, the gate is connected to WWL, and the drain is connected to BL.

[0027] The source of N8 is connected to S1, the gate is connected to WWL, and the drain is connected to BLB.

[0028] Preferably, the gate length of all MOS transistors is 65 nm; the gate width of all PMOS transistors and the gate width of transmission tubes N7-N10 are 120 nm; and the gate width of NMOS transistors N1-N6 is 280 nm.

[0029] Compared with the prior art, the present application has the following beneficial effects:

[0030] 1. The present application discloses an SRAM storage circuit capable of effectively self-recovering single-node data rollover, which has the ability of complete SNU self-recovery and is improved in read-write speed, noise tolerance and other indicators.

[0031] 2. The circuit has the ability of DNU self-recovery by layout design to pull apart the sensitive node. DETAILED DESCRIPTION

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 The structural schematic diagram of the SIS-10T circuit in the prior art is provided as the background art of the present application;

[0034] Figure 2 The structural schematic diagram of the QUATRO-10T circuit in the prior art is provided as the background art of the present application;

[0035] Figure 3 The structural schematic diagram of the SEA-14T circuit in the prior art is provided as the background art of the present application;

[0036] Figure 4 The structural schematic diagram of the RSP-14T circuit in the prior art is provided as the background art of the present application;

[0037] Figure 5 The structural schematic diagram of the RHBD1-4T circuit in the prior art is provided as the background art of the present application;

[0038] Figure 6 The structural schematic diagram of the RH-12T circuit in the prior art is provided as the background art of the present application;

[0039] Figure 7 The structural schematic diagram of the EDP-12T circuit in the prior art is provided as the background art of the present application

[0040] Figure 8A structure schematic diagram of a SPH-14T anti-radiation SRAM memory cell provided by the embodiment of the present application is shown in the figure.

[0041] Figure 9 A timing waveform diagram of an RHDS-14T anti-radiation SRAM memory cell circuit provided by the embodiment of the present application is shown in the figure (the simulation conditions are: Corner: TT; Temperature: 27℃; VDD: 1.2V).

[0042] Table 1 is a circuit area, read / write time and power consumption simulation comparison table of a prior art SRAM cell circuit and a 14T anti-radiation SRAM memory cell circuit provided by the embodiment of the present application (the simulation conditions are: Corner: TT; Temperature: 27℃; VDD: 1.2V).

[0043] Figure 10 Transient waveform simulation diagrams of the RHDS-14T anti-radiation SRAM memory cell circuit provided by the embodiment of the present application at different time and different nodes under the injection of double exponential current source pulses (the simulation conditions are: VDD: 1.2V).

[0044] Figure 11 A HSNM, RSNM and WSNM comparison diagram of a prior art SRAM cell circuit and the RHDS-14T anti-radiation SRAM memory cell circuit provided by the embodiment of the present application is shown in the figure (the simulation conditions are: Corner: TT; Temperature: 27℃; VDD: 1.2V). DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0046] It should be noted that when a component is referred to as being "mounted on" another component, it can be directly on the other component or there can be a middle component. When a component is referred to as being "disposed on" another component, it can be directly disposed on the other component or there can be a middle component. When a component is referred to as being "fixed on" another component, it can be directly fixed on the other component or there can be a middle component.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0048] Embodiment 1

[0049] Referring to Figure 8 The circuit structure diagram of the SPH-14T circuit provided for this embodiment 1 is shown. In general, the SPH-14T circuit includes 10 NMOS tubes N1-N10, 4 PMOS tubes P1-P4.

[0050] As shown, in terms of function, the SPH-14T circuit includes: a pull-up tube part, a pull-down tube part, a transmission tube part. Figure 6

[0051] The following are explained one by one:

[0052] 1. The pull-up tube part includes 4 PMOS tubes P1-P4, 2 NMOS tubes N3, N4, and is used for pulling up storage nodes S0, Q, QB, S1;

[0053] Specifically, the sources of P1, P2 and the drains of N3, N4 are connected to VDD, and the sources of N1, N2, N5 are connected to ground GND;

[0054] The pull-down tube part includes 4 NMOS tubes N1, N2, N5, N6 and is used for pulling down storage nodes S0, Q, QB, S1;

[0055] S0 is connected to the source of N3, the drain of N5, the gate of P2, and the gate of P4;

[0056] S1 is connected to the source of N4, the drain of N6, the gate of P1, and the gate of P3;

[0057] Q is connected to the drain of N1, the drain of P3, the gate of N1, the gate of N5, and the gate of N3;

[0058] QB is connected to the drain of N2, the drain of P4, the gate of N2, the gate of N6, and the gate of N4;

[0059] The drain of P1 is connected to the source of P3, the drain of P2 is connected to the source of P4, the drain of P3 is connected to the drain of N1, the drain of P4 is connected to the drain of N2, the source of N3 is connected to the drain of N5, and the source of N4 is connected to the drain of N6.

[0060] Then, S0, S1 are the connection nodes of two NMOS transistors, forming N-polarity reinforcement: as​Figure 8 As shown, S0 is the connection node of N3, N5; S1 is the connection node of N4, N6; according to the N polarity reinforcement principle, when these nodes have SEU, only "1-0" and "0-0" voltage pulses are generated, i.e. only negative pulses are generated. Therefore, if the data stored in these nodes is 0, the voltage logic is unchanged when SEU occurs, and these nodes are not sensitive nodes.

[0061] Q and QB are two source isolation technology layout nodes, the pull-up PMOS tube of the traditional inverter is replaced by two PMOS tubes in series and an STI layer is added to effectively suppress the charge collection of the transistor, and when these nodes have SEU, the voltage pulse generated is not enough to flip the node from 0 to 1, so when the data stored in these nodes is 0, they can also be considered as non-sensitive nodes.

[0062] In this embodiment 1, the suggested parameter configuration is that the width-length ratio of all pull-up PMOS transistors and transmission transistors is 120 / 65, and the width-length ratio of pull-up NMOS transistors and pull-down transistors is 280 / 65.

[0063] 2, a transmission tube part, which includes four NMOS tubes N7-N10; wherein the data of node Q and node S0 are written by bit line BL through N7, N9; the data of node QB and node S1 are written by bit line BLB through N8, N10;

[0064] The drain of N7 is connected to Q, the gate is connected to WL, and the source is connected to BL;

[0065] The source of N8 is connected to QB, the gate is connected to WL, and the drain is connected to BLB.

[0066] The source of N9 is connected to S0, the gate is connected to WWL, and the drain is connected to BL.

[0067] The source of N8 is connected to S1, the gate is connected to WWL, and the drain is connected to BLB.

[0068] In general, when WL=1 and WWL=1, the transmission tube part is open, and the SPH-14T circuit is in transparent mode; the signals of bit line BL and BLB are directly output to Q, QB, S0, S1 through transmission tube part N7, N8, N9, N10;

[0069] When WL and WWL=0, the transmission tube part is cut off, and the SPH-14T circuit is in holding mode, and the transmission tube part no longer writes data;

[0070] The bombardment occurs in holding mode: when the storage node is bombarded, the SPH-14T circuit can restore the storage node.

[0071] The SNU recovery mechanism of the SPTRL circuit is introduced as follows:

[0072] Take the storage data as 0 for example, i.e. S0 = Q = 0, S1 = QB = 1. Referring to the above description, since the polarity reinforcement technology and the source isolation technology are used, the sensitive nodes include two, which are QB and S1 respectively.

[0073] (1) SNU self-recovery mechanism:

[0074] The SNU includes two cases, and the SNU occurs at QB and S1 respectively.

[0075] Case 1: The SNU occurs at QB. QB changes from 1 to 0, so that N1, N5 and N4 are turned off, so that S1 enters a high resistance state, and the original voltage is maintained unchanged. Transistors P1 and P3 remain closed, and the Q state is not changed. Transistors N2 and N6 remain off, and the QB state is restored to 1.

[0076] Case 2: The SNU occurs at S1. S4 changes from 1 to 0, so that P1 and P3 are turned on, and the remaining transistors are not affected. For Q, N1 remains on, and the width-length ratio of N1 is greater than that of P1 and P3. Therefore, the node Q is a weak 0, and the transistor switching state is not changed; for the remaining nodes, the state remains unchanged, and the error cannot affect the voltage logic of other nodes. Finally, through N4 off and N6 on, S1 is restored to 1.

[0077] This embodiment 1 also carries out simulation verification, and the simulation conditions are as follows: Corner: TT; Temperature: 27℃; VDD: 1.2V, and the verification result is shown in Figure 10 .

[0078] It can be known from Figure 10 that the SPH-14T circuit can realize complete SNU self-recovery.

[0079] Embodiment 2

[0080] This embodiment 2 carries out simulation comparison on the SPH-14T circuit proposed in embodiment 1 and the other seven kinds of latch circuit proposed in the background art, compares the related performances: read speed (RAT), write speed (WAT), average power consumption of the circuit, and the result is shown in Table 1; the noise margin of the SRAM circuit (read noise margin (RSNM), hold noise margin (HSNM), write noise margin (WSNM), and the result is shown in Figure 10 . Table 1 Simulation comparison table of circuit area, read-write time and power consumption of the prior art SRAM unit circuit and the 14T anti-radiation SRAM storage unit circuit provided in the embodiment of the present application (simulation conditions: Corner: TT; Temperature: 27℃; VDD: 1.2V)

[0081] From Table 1, in terms of read-write speed: the RAT of the RH-12T circuit is the maximum, being 65.48ps; the RATs of the SPH-14T circuit and the RSP-14T circuit are the minimum, being 50.53ps and 50.49ps respectively; and the WAT of the SPH-14T circuit is also the minimum, being 36.63ps. Therefore, the SRH-14T circuit has the advantage of faster transmission speed compared with other circuits.

[0082] In terms of power consumption: the SPH-14T circuit has a larger power consumption of 7.73uW due to the use of polarity reinforcement technology and the direct connection of the NMOS tube with the VDD end.

[0083] In terms of noise margin: the WSNM of the SPH-14T is slightly smaller than that of the SIS-10T, but the SPH-14T has the second largest HSNM and the third largest RSNM among the other SRAM circuits. This indicates that the SPH-14T has good stability among the eight circuits.

[0084] In summary, the SPH-14T circuit proposed in Embodiment 1 has lower read speed and write speed and larger noise margin, indicating that the SPH-14T has good comprehensive performance and stability.

[0085] The technical features of the above-described embodiments can be combined arbitrarily, and to make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present disclosure.

[0086] The above-described embodiments only express several embodiments of the present disclosure, and the description is more specific and detailed, but it should not be understood as limiting the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present disclosure, a number of modifications and improvements can be made, which are within the scope of the present disclosure. Therefore, the scope of protection of the present patent should be subject to the appended claims.

Claims

1. An SRAM storage circuit capable of effectively self-recovering single-node data flipping, characterized in that: include: The pull-up tube part includes four PMOS tubes P1 to P4 and two NMOS tubes N3 and N4, which are used to pull up the storage nodes S0, Q, QB, and S1; The pull-down tube part includes four NMOS tubes N1, N2, N5, and N6 for pulling down the storage nodes S0, Q, QB, and S1; The transmission tube part includes four NMOS tubes N7 to N10. Among them, the data of node Q and node S0 are written by bit line BL through N7 and N9; the data of node QB and node S1 are written by bit line BLB through N8 and N10. Among them, S0 and S1 are the connection nodes of two NMOS transistors, forming N-polarity reinforcement; Q and QB are source isolation layout nodes; the width-to-length ratio of all pull-up PMOS transistors and transfer transistors is 120 / 65, and the width-to-length ratio of the pull-up NMOS transistors and pull-down transistors is 280 / 65.

2. The SRAM reinforced storage circuit based on polarity reinforcement and source isolation technology according to claim 1, characterized in that: The sources of P1 and P2 and the drains of N3 and N4 are connected to VDD, and the sources of N1, N2, and N5 are grounded to GND; S0 is connected to the source of N3, the drain of N5, the gate of P2, and the gate of P4; S1 connects the source of N4, the drain of N6, the gate of P1, and the gate of P3; Q is connected to the drain of N1, the drain of P3, the gate of N1, the gate of N5, and the gate of N3; QB connects the drain of N2, the drain of P4, the gate of N2, the gate of N6, and the gate of N4; The drain of P1 is connected to the source of P3, the drain of P2 is connected to the source of P4, the drain of P3 is connected to the drain of N1, the drain of P4 is connected to the drain of N2, the source of N3 is connected to the drain of N5, and the source of N4 is connected to the drain of N6.

3. The SRAM reinforced storage circuit based on polarity reinforcement and source isolation technology according to claim 1, characterized in that: The drain of N7 is connected to Q, the gate is connected to WL, and the source is connected to BL; The source of N8 is connected to QB, the gate is connected to WL, and the drain is connected to BLB. The source of N9 is connected to S0, the gate is connected to WWL, and the drain is connected to BL. The source of N8 is connected to S1, the gate is connected to WWL, and the drain is connected to BLB.

4. The latch storage circuit capable of effectively self-recovering three-node data flip according to claim 1, characterized in that: The gate length of all MOS transistors is 65nm; the gate width of all PMOS transistors and the gate width of transmission transistors N7-N10 are 120nm; the gate width of NMOS transistors N1-N6 is 280nm.

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