Current register, control method thereof and image sensor

Abstract

The invention provides a current register and a control method thereof, and an image sensor, and the current register comprises a transmission module which is used for obtaining a signal current; the operation register module comprises a first register transistor, a second register transistor and a switch control unit; by controlling the state of the switch control unit, the first register transistor and the second register transistor perform phase inversion, addition, subtraction or multiplication on the signal current to obtain a result current, and the result current is stored. According to the invention, through only one operation register module, phase reversal, addition, subtraction and accumulation operations can be realized, and positive and negative currents can be stored, so that the circuit complexity is greatly reduced while the operation function is ensured, the circuit area consumption is further reduced, the integration level is improved, the hardware cost is saved, and the cost is reduced. The problem that an existing current register is large in area overhead is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and in particular, to a current register and a control method thereof, and an image sensor. BACKGROUND

[0002] At present, the basic structure form followed by the development of modern computers is always Von Neumann architecture, the core idea of which is to store programs and data in the same memory and access programs and data using memory addresses. The basic components of Von Neumann architecture include a central processing unit (CPU), a memory, an input device and an output device, wherein the memory is used to store programs and data, including instructions, operands and calculation results; the central processing unit obtains instructions and data from the memory and executes them; and the input device and the output device are respectively used to input and output data.

[0003] However, the separation design of the computing unit and the storage unit in Von Neumann architecture leads to a "memory wall" bottleneck, that is, the transmission rate of data between the memory and the processor is much lower than the processing speed of the computing unit. This contradiction is further intensified with the rapid development of CMOS image sensor (CIS) technology: the resolution of modern CIS chips has entered the era of hundreds of millions of pixels (such as 108MP or more), the frame rate has been increased to 120fps or even higher, and the single-frame data volume increases exponentially, especially in practical application scenarios such as target detection and image recognition, the transmission and storage of massive data not only causes waste of bandwidth resources, but also significantly increases system power consumption and delay.

[0004] To solve the above problems, a local storage and calculation preprocessing technology is proposed by the research and development personnel, which realizes data processing nearby by embedding a computing unit into a storage array, and significantly improves the energy efficiency ratio. Among them, the sense and calculation chip based on the current domain becomes a research hotspot due to its natural parallelism, low voltage operation and anti-noise advantage. However, in the application of the prior art, the current register as an analog storage and calculation unit needs to be matched with multiple current registers to realize simple algorithms, resulting in large area overhead and difficulty in meeting the demand for high integration. SUMMARY

[0005] The present application relates to the technical field of integrated circuit design, and in particular, to a current register and a control method thereof, and an image sensor.

[0006] To solve the above technical problems, the application provides a current register, comprising: a transmission module, used for obtaining a signal current; an operation register module, comprising a first register transistor, a second register transistor and a switch control unit; by controlling the state of the switch control unit, the first register transistor and the second register transistor are used to realize the operation of the signal current in the form of inversion, addition, subtraction or multiplication to obtain a result current, and the result current is stored.

[0007] Optionally, in the current register, the switch control unit comprises a first switch, a second switch, a third switch and a fourth switch. The source of the first register transistor is connected to the ground, the gate and the source are connected through the first switch, and the gate and the drain are connected through the second switch; the drain of the first register transistor is also connected to the drain of the second register transistor and the transmission module; the gate and the drain of the second register transistor are connected through the third switch, and the gate and the source are connected through the fourth switch; and the source of the second register transistor is connected to a power supply.

[0008] Optionally, in the current register, the first switch, the second switch, the third switch and the fourth switch are all transistors. The gate of the first register transistor is connected to the drain of the first switch and the source of the second switch, the source of the first register transistor is connected to the source of the first switch, and the drain of the first register transistor is connected to the drain of the second switch; the gate of the second register transistor is connected to the source of the third switch and the drain of the fourth switch, the drain of the second register transistor is connected to the drain of the third switch, and the source of the second register transistor is connected to the source of the fourth switch; the gate of the first switch is connected to a first reset signal, the gate of the second switch is connected to a first write signal, the gate of the third switch is connected to a second write signal, and the gate of the fourth switch is connected to a second reset signal.

[0009] Optionally, in the current register, the first register transistor is an NMOS, the second register transistor is a PMOS, the first switch and the second switch are both NMOS, and the third switch and the fourth switch are both PMOS.

[0010] Optionally, in the current register, the transmission module comprises a transmission switch; one end of the transmission switch is connected to the drain of the first register transistor and the drain of the second register transistor, and the other end is connected to a bus.

[0011] Optionally, in the current register, the transmission switch is a transistor group switch, and the transistor group switch comprises a first transmission transistor and a second transmission transistor. The drain of the first transmission transistor is connected with the source of the second transmission transistor and is connected to the bus; the source of the first transmission transistor is connected with the drain of the second transmission transistor and is connected to the drain of the first register transistor and the drain of the second register transistor; the gate of the first transmission transistor is connected to an enable signal, and the gate of the second transmission transistor is connected to an inverse enable signal.

[0012] Optionally, in the current register, the first transmission transistor is an NMOS, and the second transmission transistor is a PMOS.

[0013] Optionally, in the current register, the switch control unit comprises a fifth switch, a sixth switch, a seventh switch and an eighth switch; the fifth switch, the sixth switch, the seventh switch and the eighth switch are all transistors. The source of the first register transistor is connected to ground, the gate of the first register transistor is connected with the source of the fifth switch, and the drain of the first register transistor is connected with the source of the sixth switch; the drain of the fifth switch is connected with the drain of the sixth switch; the source of the second register transistor is connected to a power supply, the gate of the second register transistor is connected with the source of the seventh switch, and the drain of the second register transistor is connected with the source of the eighth switch; the drain of the seventh switch is connected with the drain of the eighth switch; the drain of the sixth switch and the drain of the eighth switch are connected and connected to the bus; the gate of the fifth switch is connected to a first write signal, the gate of the sixth switch is connected to a first read signal, the gate of the seventh switch is connected to a second write signal, and the gate of the eighth switch is connected to a second read signal.

[0014] Optionally, in the current register, the first register transistor is an NMOS, the second register transistor is a PMOS, the fifth switch and the sixth switch are both NMOS, and the seventh switch and the eighth switch are both PMOS.

[0015] Optionally, in the current register, the transmission module is composed of the sixth switch and the eighth switch.

[0016] To solve the above technical problems, the application further provides a control method of a current register, which is used for realizing the positive current read and write of the current register as any one of the above. In the write process, the state of the transmission module is controlled to connect the operation register module with the bus; the state of the switch control unit is controlled to short the gate-drain of the first register transistor and to turn off the second register transistor; at this time, the positive current at the bus is input into the first register transistor through the transmission module and is converted into gate voltage at the gate of the first register transistor; In the holding state, the state of the transmission module is controlled to disconnect the operation register module from the bus; the state of the switch control unit is controlled to disconnect the gate-drain of the first register transistor and to keep the second register transistor turned off; at this time, the drain voltage of the first register transistor is discharged to 0 and the static current is 0; In the read process, the state of the transmission module is controlled to connect the operation register module with the bus; the state of the switch control unit is kept to disconnect the gate-drain of the first register transistor and to keep the second register transistor turned off; at this time, the first register transistor is in the saturation region and the written positive current is read out.

[0017] To solve the above technical problems, the application further provides a control method of the current register, which is used to realize the negative current read and write of the current register as claimed in any one of the above. In the write process, the state of the transmission module is controlled to connect the operation register module with the bus; the state of the switch control unit is controlled to turn off the first register transistor and to short the gate-drain of the second register transistor; at this time, the negative current at the bus is input into the second register transistor through the transmission module and is converted into gate voltage at the gate of the second register transistor; In the holding state, the state of the transmission module is controlled to disconnect the operation register module from the bus; the state of the switch control unit is controlled to disconnect the gate-drain of the second register transistor and to keep the first register transistor turned off; at this time, the drain voltage of the second register transistor is charged to the power supply voltage and the static current is 0; In the read process, the state of the transmission module is controlled to connect the operation register module with the bus; the state of the switch control unit is kept to disconnect the gate-drain of the second register transistor and to keep the first register transistor turned off; at this time, the second register transistor is in the saturation region and the written negative current is read out.

[0018] To solve the above technical problems, the application further provides a control method of the current register, which is used to realize the current inversion operation of the current register as claimed in any one of the above. Controlling the states of the transmission module and the switch control unit, so that the current register is in a holding state; at this time, the gate-drain electrode and the gate-source electrode of the first register transistor are disconnected, the gate-source electrode and the gate-drain electrode of the second register transistor are short-circuited, and the signal current is stored in the gate electrode of the first register transistor in the form of voltage; Controlling the state of the switch control unit, so that the gate-drain electrode and the gate-source electrode of the first register transistor are kept disconnected, and the gate-source electrode and the gate-drain electrode of the second register transistor are disconnected; at this time, the first register transistor works in the saturation region, the first register transistor transmits the signal current to the second register transistor, and generates a gate voltage at the gate electrode of the second register transistor; Controlling the state of the switch control unit, so that the gate-source electrode and the gate-drain electrode of the second register transistor are kept disconnected, and the gate-drain electrode and the gate-source electrode of the first register transistor are kept disconnected; at this time, the gate voltage of the first register transistor is discharged and the first register transistor is in an off state, the first register transistor transmits the current to the second register transistor for storage, and the current is inverted.

[0019] To solve the above technical problems, the application further provides a control method of a current register, which is used for realizing the current addition operation of the current register as any one of the above. Controlling the states of the transmission module and the switch control unit, so that the gate-drain electrode and the gate-source electrode of the first register transistor are disconnected, and the gate-source electrode and the gate-drain electrode of the second register transistor are disconnected; at this time, the second register transistor stores the signal current after the inversion operation; Controlling the state of the transmission module, so that the operation register module is connected to the bus; controlling the state of the switch control unit, so that the gate-drain electrode and the gate-source electrode of the first register transistor are short-circuited, and the gate-source electrode and the gate-drain electrode of the second register transistor are kept disconnected; at this time, another signal current to be added at the bus is input into the first register transistor through the transmission module, so that the current flowing through the first register transistor is the sum of the signal current stored in the second register transistor after the inversion operation and the input another signal current to be added, and a corresponding gate voltage is generated at the gate electrode of the first register transistor; Controlling the state of the switch control unit, so that the gate-drain electrode and the gate-source electrode of the first register transistor are disconnected, and controlling the states of the transmission module and the switch control unit, so that the operation register module is disconnected from the bus, and the gate-source electrode and the gate-drain electrode of the second register transistor are kept disconnected; at this time, the second register transistor is in an off state, and the first register transistor stores the result of the current addition operation in the form of voltage at the gate electrode.

[0020] To solve the above technical problems, the application further provides a control method of the current register, which is used to realize the current subtraction operation of the current register as any one of the above, and the control method comprises: controlling the states of the transmission module and the switch control unit, so that the operation register module is connected with the bus, the gate-drain of the first register transistor is short-circuited, and the gate-source is disconnected, and the gate-source of the second register transistor is short-circuited, and the gate-drain is disconnected; at this time, the first register transistor stores the input signal current; controlling the state of the switch control unit, so that the gate-drain of the first register transistor is disconnected, and the gate-source remains disconnected, and the gate-source of the second register transistor is disconnected, and the gate-drain is short-circuited; at this time, the other signal current to be subtracted at the bus is input into the operation register module through the transmission module, and since the first register transistor is in the saturation region, the current flowing through the second register transistor is the difference between the signal current stored by the first register transistor and the input other signal current to be subtracted, and a corresponding gate voltage is generated at the gate of the second register transistor; controlling the state of the switch control unit, so that the gate-source of the second register transistor remains disconnected, and the gate-drain is disconnected; controlling the states of the transmission module and the switch control unit, so that the operation register module is disconnected with the bus, and the gate-source of the first register transistor remains short-circuited, and the gate-drain is disconnected; at this time, the first register transistor is in the off state, and the second register transistor stores the result of the current subtraction operation in the form of voltage at the gate.

[0021] To solve the above technical problems, the application further provides an image sensor comprising the current register as any one of the above.

[0022] The current register and the control method thereof and the image sensor provided by the application comprise a transmission module for obtaining a signal current, and an operation register module for performing inversion, addition, subtraction or multiplication operation on the signal current to obtain a result current, and storing the result current. Only one operation register module can realize inversion, addition, subtraction and accumulation operation, and can also store positive and negative currents, so that the circuit complexity is greatly reduced while the operation function is ensured, thereby reducing the circuit area consumption, improving the integration, saving the hardware cost, and solving the problem of large area consumption of the existing current register. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 It is a circuit schematic diagram of the existing current register; Figure 2 It is a module structure schematic diagram of the current register provided by the embodiment; Figure 3 A circuit schematic diagram of the current register provided for the present embodiment; Figure 4 A specific circuit structure diagram of the current register provided for the present embodiment; Figure 5 A signal control timing diagram of the current register provided for the present embodiment; Figure 4 Figure 6 Another specific circuit structure diagram of the current register provided for the present embodiment; Figure 7 A signal control timing diagram of the current register provided for the present embodiment; Figure 6 A circuit structure diagram of the positive current read-write process of the current register provided for the present embodiment; Figure 8 A circuit structure diagram of the negative current read-write process of the current register provided for the present embodiment; Figure 9 A circuit structure diagram of the current inversion operation process of the current register provided for the present embodiment; Figure 10 A circuit structure diagram of the current addition operation process of the current register provided for the present embodiment; Figure 11 A circuit structure diagram of the current subtraction operation process of the current register provided for the present embodiment; Figure 12 A system structure diagram of the current division operation process of the current register provided for the present embodiment. Figure 13 DETAILED DESCRIPTION

[0024] The current register, the control method thereof, and the image sensor according to the present application are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and all use non-precise proportions, and are only used to facilitate and clearly assist the purpose of describing the present embodiment. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used.

[0025] ​​It should be noted that the "first", "second", and the like in the description and claims of the present application and the accompanying drawings are used to distinguish similar objects, so as to describe the embodiments of the present application, and are not used to describe a specific order or sequence, and it should be understood that the structures thus used can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0026] The existing current register, as shown in (a) of Figure 1 , generally includes a current source, a MOS tube and two switches, wherein the source of the MOS tube MN is grounded, the drain and the gate are connected through the switch Sw, and the drain is connected to the current source; the input and output end is led out through the switch Sr between the drain of the MOS tube MN and the current source. The working principle is roughly as follows: In the write stage, as shown in (b) of Figure 1 , both switches Sr and Sw are closed, the signal current Iin input through the switch Sr and the bias current Ib provided by the current source all flow through the MOS tube MN, at this time the drain current Ids of the MOS tube MN = Iin+Ib, and a corresponding self-bias voltage Vx is generated at the gate.

[0027] In the holding stage, both switches Sr and Sw are disconnected, and the self-bias voltage Vx is saved at the gate of the MOS tube MN.

[0028] In the read stage, the switch Sr is closed, and the read current Iread=Ids-Ib, that is, Iread=Iin.

[0029] As can be seen from the working principle of the existing current register, the MOS tube with gate-drain short circuit converts the input current into voltage and stores it at the gate of the MOS tube. The drain current of the MOS tube working in the saturation region mainly depends on the size of the gate voltage, so in the read stage, the gate voltage can be restored to the drain current; and according to Kirchhoff's current law, the current flowing through the MOS tube Ids equals Ib+Iread, and the read current Iread=Ids-Ib=Iin is obtained.

[0030] To solve the problem that multiple current registers are needed to cooperate with each other to realize the operations of inversion, addition, subtraction and accumulation (multiplication), resulting in large circuit area overhead, the present embodiment provides a current register, as shown in Figure 2 , comprising: A transmission module for obtaining a signal current from a bus; The operation register module includes a first register transistor, a second register transistor and a switch control unit; by controlling the state of the switch control unit, the first register transistor and the second register transistor perform the operations of inversion, addition, subtraction or multiplication on the signal current to obtain a result current, and store the result current.

[0031] The current register provided by the embodiment can realize inversion, addition, subtraction and accumulation operations only by one operation register module, and can store positive and negative currents, thereby greatly reducing the circuit complexity, reducing the circuit area consumption, improving the integration and saving the hardware cost while ensuring the operation function.

[0032] Specifically, in the embodiment, as shown in Figure 3 The operation register module includes a first register transistor M01, a second register transistor M02 and a switch control unit, and the switch control unit includes a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4.

[0033] The source of the first register transistor M01 is grounded, the gate and the source are connected through the first switch S1, and the gate and the drain are connected through the second switch S2; the drain of the first register transistor M01 is also connected with the drain of the second register transistor M02, and is connected with the transmission module; the gate and the drain of the second register transistor M02 are connected through the third switch S3, and the gate and the source are connected through the fourth switch S4; the source of the second register transistor M02 is connected with the power supply.

[0034] The transmission module includes a transmission switch Sc; one end of the transmission switch Sc is connected with the drain of the first register transistor M01 and the drain of the second register transistor M02, and the other end is connected with the bus.

[0035] In a specific embodiment, as shown in Figure 4 The first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are transistors, and are sequentially recorded as M11, M12, M13 and M14, respectively.

[0036] The gate of the first register transistor M01 is connected with the drain of the first switch M11 and the source of the second switch M12, the source of the first register transistor M01 is connected with the source of the first switch M11 and grounded, and the drain of the first register transistor M01 is connected with the drain of the second switch M12; the gate of the second register transistor M02 is connected with the source of the third switch M13 and the drain of the fourth switch M14, the drain of the second register transistor M02 is connected with the drain of the third switch M13, and the source of the second register transistor M02 is connected with the source of the fourth switch M14 and connected with a power supply. The gate of the first switch M11 is connected with a first reset signal Nrst, the gate of the second switch M12 is connected with a first write signal Nwrite, the gate of the third switch M13 is connected with a second write signal Pwrite, and the gate of the fourth switch M14 is connected with a second reset signal Prst.

[0037] In the embodiment, as shown in Figure 4 the transmission switch is a transistor group switch, which includes a first transmission transistor M21 and a second transmission transistor M22.

[0038] The drain of the first transmission transistor M21 is connected with the source of the second transmission transistor M22 and connected with the bus; the source of the first transmission transistor M21 is connected with the drain of the second transmission transistor M22 and connected with the drain of the first register transistor M01 and the drain of the second register transistor M02; the gate of the first transmission transistor M21 is connected with an enable signal EN, and the gate of the second transmission transistor M22 is connected with an inverse enable signal ENB.

[0039] In actual application, the first register transistor is NMOS, the second register transistor is PMOS, the first switch and the second switch are both NMOS, the third switch and the fourth switch are both PMOS, the first transmission transistor is NMOS, and the second transmission transistor is PMOS. In addition, the inverse enable signal ENB is the inverse signal of the enable signal EN, that is, the inverse enable signal ENB can be obtained by inverting the enable signal EN.

[0040] Further, corresponding to the circuit structure of the current register as shown in Figure 4 the embodiment provides corresponding signal control timing, as shown in Figure 5The timing of the enable signal EN, the first reset signal Nrst, the first write signal Nwrite, the second write signal Pwrite and the second reset signal Prst corresponding to the write, hold, read, inversion, inverted read, addition and subtraction operations are provided. The state control of the transistor switch is realized by the level input of each signal, and the above-mentioned working process is realized correspondingly.

[0041] In actual application, the signal timing corresponding to each process can be combined according to actual needs, so as to realize, for example, data writing and reading of non-integer multiplication, which is not limited in the present application.

[0042] In another specific embodiment, as shown in Figure 6 The operation register module includes a first register transistor M01, a second register transistor M02 and a switch control unit, and the switch control unit includes a fifth switch M31, a sixth switch M32, a seventh switch M33 and an eighth switch M34, which are all transistors.

[0043] The source of the first register transistor M01 is connected to ground, the gate of the first register transistor M01 is connected to the source of the fifth switch M31, and the drain of the first register transistor M01 is connected to the source of the sixth switch M32; the drain of the fifth switch M31 is connected to the drain of the sixth switch M32; the source of the second register transistor M02 is connected to a power supply, the gate of the second register transistor M02 is connected to the source of the seventh switch M33, and the drain of the second register transistor M02 is connected to the source of the eighth switch M34; the drain of the seventh switch M33 is connected to the drain of the eighth switch M34; the drain of the sixth switch M32 and the drain of the eighth switch M34 are connected and connected to the bus. The gate of the fifth switch M31 is connected to the first write signal Nwrite, the gate of the sixth switch M32 is connected to the first read signal Nread, the gate of the seventh switch M33 is connected to the second write signal Pwrite, and the gate of the eighth switch M34 is connected to the second read signal Pread.

[0044] In the embodiment, the sixth switch M32 and the eighth switch M34 are not only used to control the state of the first register transistor M01 and the second register transistor M02, but also used as a transmission module to realize the transmission of signal current. In this way, compared with the current register shown in Figure 4 The circuit structure of the current register shown in Figure 6 is more simple and the circuit area is smaller.

[0045] In practical applications, the first register transistor M01 is an NMOS, the second register transistor M03 is a PMOS, the fifth switch M31 and the sixth switch M32 are both NMOS, and the seventh switch M33 and the eighth switch M34 are both PMOS.

[0046] Corresponding to Figure 6 The circuit structure of the current register shown in the embodiment also provides corresponding signal control timing, as shown in Figure 7 The timing of the first write signal Nwrite, the first read signal Nread, the second write signal Pwrite, and the second read signal Pread corresponding to the write, hold, read, inversion, inverted read, addition, and subtraction operations is provided. By the level input of each signal, the state control of the transistor switch is realized, and the working process described above is realized.

[0047] Similarly, in practical applications, the signal timing corresponding to each process can be combined according to actual needs, so as to realize, for example, data writing and reading of non-integer multiplication, which is not limited in the present application.

[0048] In the following, the working principle of the current register provided by the embodiment for realizing inversion, addition, subtraction, and accumulation operations, as well as storing positive and negative currents, is described in conjunction with the circuit schematic diagram of the current register shown in Figure 3

[0049] Referring to Figure 8 The control method for realizing positive current reading and writing of the current register provided by the embodiment mainly includes: In the writing process, the state of the transmission module is controlled to connect the operation register module to the bus, and the state of the switch control unit is controlled to short the gate-drain of the first register transistor and turn off the second register transistor. Specifically, as shown in Figure 8 In the writing process, the state of the transmission module is controlled to connect the operation register module to the bus, and the state of the switch control unit is controlled to short the gate-drain of the first register transistor and turn off the second register transistor. Specifically, as shown in

[0050] ​In the holding state, the state of the transmission module is controlled so that the operation register module is disconnected from the bus; the state of the switch control unit is controlled so that the gate-drain of the first register transistor is disconnected, and the second register transistor is still in the off state. Specifically, as shown in (b) of Figure 8 the transmission switch Sc is controlled to be disconnected so that the operation register module is disconnected from the bus; at the same time, the second switch S2 is controlled to be disconnected, the first switch S1 and the third switch S3 are kept disconnected, and the fourth switch S4 is kept connected, so that the gate-drain of the first register transistor M01 is disconnected, and the gate voltage Vx is saved in the gate of the first register transistor M01; at the same time, since the second register transistor M02 is in the off state, and the transmission switch Sc is also in the open circuit, at this time, the first register transistor M01 will discharge the charge at the drain, and the drain voltage will drop to 0, i.e. V2=0, so in the holding stage, the static current of the first register transistor M01 is 0.

[0051] In the readout process, the state of the transmission module is controlled so that the operation register module is connected to the bus; the state of the switch control unit is kept so that the gate-drain of the first register transistor is still disconnected, and the second register transistor is still in the off state. Specifically, as shown in (c) of Figure 8 the transmission switch Sc is controlled to be connected so that the operation register module is connected to the bus; at the same time, the states of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are kept unchanged (the first switch S1, the second switch S2 and the third switch S3 are disconnected, and the fourth switch S4 is connected). At this time, since the second register transistor M02 is still in the off state, and the first register transistor M01 is in the saturation region, the positive current written from the first register transistor M01 is read, i.e. Iread=Iin.

[0052] Referring to Figure 9 , the control method for implementing negative current read and write provided by the current register mainly includes: In the write process, the state of the transmission module is controlled so that the operation register module is connected to the bus; the state of the switch control unit is controlled so that the first register transistor is in the off state, and the gate-drain of the second register transistor is short-circuited. Specifically, as shown in (d) of Figure 9As shown in (a), the transmission switch Sc is controlled to close, connecting the arithmetic register module to the bus. Simultaneously, the first switch S1 is closed, the second switch S2 is opened, the third switch S3 is closed, and the fourth switch S4 is opened, shorting the gate and drain of the second register transistor M02 into a diode-connected state. Simultaneously, the first register transistor M01 is turned off, and the gate voltage V1 of the first register transistor M01 is zero. At this point, the negative current Iin on the bus is input to the second register transistor M02 via the transmission module (transmission switch Sc), and is converted at the gate of the second register transistor M02 to generate a gate voltage Vz.

[0053] In the hold state, the state of the transmission module is controlled so that the operation register module is disconnected from the bus; the state of the switch control unit is controlled so that the gate and drain of the second register transistor are disconnected and the first register transistor is still in the off state. Figure 9 As shown in (b), the transmission switch Sc is controlled to be disconnected, so that the operation register module is disconnected from the bus; at the same time, the third switch S3 is controlled to be disconnected, the first switch S1 remains closed, and the second switch S2 and the fourth switch S4 remain open, so that the gate and drain of the second register transistor M02 are disconnected, and the gate voltage Vz is stored at the gate of the second register transistor M02. At the same time, since the first register transistor M01 is in the off state, the transmission switch Sc is also open. Therefore, at this time, the drain voltage of the second register transistor M02 is charged to the power supply voltage, that is, V2=VDD. Therefore, in the holding stage, the static current of the second register transistor M02 is 0.

[0054] During the readout process, the state of the transmission module is controlled so that the operation register module is connected to the bus; the state of the switch control unit is maintained so that the gate and drain of the second register transistor are still disconnected and the first register transistor is still in the off state. Figure 9 As shown in (c), the transmission switch Sc is controlled to be closed, so that the arithmetic register module is connected to the bus. At the same time, the states of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 remain unchanged (the first switch S1 is closed, and the second switch S2, the third switch S3, and the fourth switch S4 are open). At this time, because the first register transistor M01 is still in the off state and the second register transistor M02 is in the saturation region, the written negative current is read from the second register transistor M02, that is, Iread = Iin.

[0055] Since the circuit structure of the current register provided in this embodiment is symmetrical in the vertical direction, the reading and writing process of the negative current is also completely symmetrical with the reading and writing process of the positive current.

[0056] SeeFigure 10 The control method for implementing current inversion operation using a current register provided in this embodiment mainly includes: A1, controls the states of the transmission module and the switch control unit so that the current register is in a hold state; at this time, the gate-drain and gate-source of the first register transistor are disconnected, the gate-drain and gate-source of the second register transistor are disconnected, and the gate-source is short-circuited, and the signal current is stored in the gate of the first register transistor in the form of voltage.

[0057] Specifically, such as Figure 10 (b) in the positive current reading and writing control method can be realized based on the current register provided in this embodiment. Figure 8 In state (b) in FIG, the transmission switch Sc is disconnected, so that the operation register module is disconnected from the bus; at the same time, the first switch S1, the second switch S2, and the third switch S3 are disconnected, and the fourth switch S4 is closed, so that the gate and drain of the first register transistor M01 are disconnected, the second register transistor M02 is in the off state, the gate voltage Vx is stored at the gate of the first register transistor M01, and the static current is 0.

[0058] A2, controls the state of the switch control unit so that the gate-drain and gate-source of the first register transistor remain disconnected, and the gate-source of the second register transistor is disconnected and the gate-drain is short-circuited; at this time, the first register transistor operates in the saturation region, the first register transistor transfers the signal current to the second register transistor, and generates a gate voltage at the gate of the second register transistor.

[0059] Specifically, such as Figure 10 In (d) of FIG5 , the transmission switch Sc is kept open, the fourth switch S4 is opened first, and then the third switch S3 is closed, so that the first register transistor M01 operates in the saturation region and the second register transistor M02 is in a diode connection state. At this time, the operating current of the current register is Iin, that is, the first register transistor M01 transfers the signal current to the second register transistor M02 and generates a gate voltage Vz at the gate of the second register transistor M02.

[0060] A3, controls the state of the switch control unit so that the gate-source and gate-drain of the second register transistor remain disconnected, and the gate-drain of the first register transistor remains disconnected and the gate-source is short-circuited; at this time, the gate voltage of the first register transistor is discharged and is in the off state, and the first register transistor transfers the current to the second register transistor for storage, and the current is reversed.

[0061] Specifically, such as Figure 10In (e) of the method, the transmission switch Sc is kept open, the third switch S3 is first closed, so that the gate voltage Vz is kept at the gate of the second register transistor M02; then the first switch S1 is closed, the voltage Vx kept at the gate of the first register transistor M01 is discharged, and the first register transistor M01 enters the off state with a static current of 0.

[0062] In this way, the current kept by the first register transistor M01 is transferred to the second register transistor M02 in the form of voltage, and the current direction is changed.

[0063] Referring to Figure 11 The control method for implementing the current addition operation of the current register provided in the embodiment mainly includes the following steps. B1, the state of the transmission module and the switch control unit is controlled, so that the gate-drain of the first register transistor is disconnected, and the gate-source is short-circuited, and the gate-source of the second register transistor is disconnected, and the gate-drain is disconnected; at this time, the second register transistor stores a signal current after the inversion operation.

[0064] Specifically, as Figure 11 In (e) of the method, the transmission switch Sc is kept open, the third switch S3 is first closed, so that the gate voltage Vz is kept at the gate of the second register transistor M02; then the first switch S1 is closed, the voltage Vx kept at the gate of the first register transistor M01 is discharged, and the first register transistor M01 enters the off state with a static current of 0. Figure 10 In (e) of the method, the transmission switch Sc is kept open, the third switch S3 is first closed, so that the gate voltage Vz is kept at the gate of the second register transistor M02; then the first switch S1 is closed, the voltage Vx kept at the gate of the first register transistor M01 is discharged, and the first register transistor M01 enters the off state with a static current of 0.

[0065] B2, the state of the transmission module is controlled, so that the operation register module is connected with the bus; the state of the switch control unit is controlled, so that the gate-drain of the first register transistor is short-circuited, and the gate-source is disconnected, and the gate-source of the second register transistor is kept disconnected, and the gate-drain is kept disconnected; at this time, another signal current to be added at the bus is input to the first register transistor through the transmission module, so that the current flowing through the first register transistor is the sum of the signal current to be added and the signal current stored by the second register transistor after the inversion operation, and a corresponding gate voltage is generated at the gate of the first register transistor.

[0066] Specifically, as Figure 11In step (f), the transmission switch Sc is controlled to be closed, the first switch S1 is controlled to be opened, the second switch S2 is controlled to be closed, and the states of the third switch S3 and the fourth switch S4 remain unchanged (remain open), so that the first register transistor M01 enters the write state. At this time, a signal current Iin2 to be added is injected from the bus through the transmission switch Sc, so that the current flowing through the first register transistor M01 is Iin1+Iin2, and a corresponding self-bias voltage Vx2 is generated at the gate.

[0067] B3, control the state of the switch control unit so that the gate and drain of the first register transistor are disconnected and the gate and source remain disconnected, and then control the states of the transmission module and the switch control unit so that the operation register module is disconnected from the bus, the gate and source of the second register transistor are short-circuited, and the gate and drain remain disconnected; at this time, the second register transistor is in the off state, and the first register transistor stores the result of the current addition operation in the form of voltage at the gate.

[0068] Specifically, such as Figure 11 In step (g) of the circuit, the second switch S2 is first opened, allowing the self-bias voltage Vx2 to be stored at the gate of the first register transistor M01. The transmission switch Sc is then opened, and the fourth switch S4 is closed, keeping the first switch S1 and the third switch S3 open. At this point, the second register transistor M02 is off, and the quiescent current is zero.

[0069] In this way, the addition operation of the two input signal currents Iin1 and Iin2 is realized, and the summed signal current is stored in the current register.

[0070] See Figure 12 The control method for implementing current subtraction operation using the current register provided in this embodiment mainly includes: C1 controls the states of the transmission module and the switch control unit so that the operation register module is connected to the bus, the gate and drain of the first register transistor are short-circuited and the gate and source are disconnected, and the gate and source of the second register transistor are short-circuited and the gate and drain are disconnected; at this time, the first register transistor stores the input signal current.

[0071] Specifically, such as Figure 12 (a) in the positive current reading and writing control method can be realized based on the current register provided in this embodiment. Figure 8 In state (a) in FIG, the signal current Iin1 is written into the current register, and a corresponding gate voltage Vx is generated at the gate of the first register transistor M01.

[0072] C2, control the state of the switch control unit, so that the first register transistor gate drain is disconnected, the gate source remains disconnected, the second register transistor gate source is disconnected, and the gate drain is shorted; at this time, another signal current to be subtracted at the bus is input to the operation register module via the transmission module, and since the first register transistor is in the saturation region, the current flowing through the second register transistor is the difference between the signal current stored in the first register transistor and the input another signal current to be subtracted, and a corresponding gate voltage is generated at the gate of the second register transistor.

[0073] Specifically, as shown in (h) of FIG. 6, the second switch S2 is first disconnected, so that the gate voltage Vx is saved at the gate of the first register transistor M01; then the fourth switch S4 is disconnected, and the third switch S3 is closed, so that the second register transistor M02 enters the write state; at this time, another signal current Iin2 to be subtracted is recharged from the bus through the transmission switch Sc. Since the first register transistor M01 is in the saturation region, the current flowing through the first register transistor M01 is still Iin1, and according to Kirchhoff's current law, the current flowing through the second register transistor M02 is Iin1-Iin2, and a corresponding self-bias voltage Vz2 is generated at the gate of the second register transistor M02. Figure 12 C3, control the state of the switch control unit, so that the second register transistor gate source remains disconnected, and the gate drain is disconnected; control the state of the transmission module and the switch control unit, so that the operation register module is disconnected with the bus, and the gate source of the first register transistor remains shorted, and the gate drain is disconnected; at this time, the first register transistor is in the off state, and the second register transistor stores the result of the current subtraction operation in the form of voltage at the gate.

[0074] Specifically, as shown in (i) of FIG. 6, the third switch S3 is first disconnected, so that the self-bias voltage Vz2 is saved at the gate of the second register transistor M02; then the transmission switch Sc is disconnected, and the first switch S1 is closed, so that the first register transistor M01 is in the off state, and the static current is 0.

[0075] Figure 12 In this way, the subtraction operation of the two input signal currents Iin1 and Iin2 is realized, and the subtracted signal current is saved in the current register.

[0076] In this way, the subtraction operation of the two input signal currents Iin1 and Iin2 is realized, and the subtracted signal current is saved in the current register.

[0077] ​It should be noted that since the current of the second register transistor M02 cannot be negative, the signal current Iin2 must be less than or equal to the signal current Iin1 during the subtraction operation. In practical applications, to implement a subtraction operation when the signal current Iin2 is greater than the signal current Iin1, it is necessary to use another current register to temporarily store Iin1. Then, the order of subtraction is reversed (Iin2 as the minuend and Iin1 as the subtrahend), obtaining the result of the operation Iin2 - Iin1. The result is then inverted to obtain Iin1 - Iin2 (Iin2 > Iin1).

[0078] The current register provided in this embodiment can implement current multiplication (accumulation) operations through iterative addition. For example, the signal current Ix is first written; the signal current Ix is then inverted and added to obtain 2Ix; the signal current Ix is inverted and added again to obtain 3Ix; and so on. In this way, integer multiple current multiplication operations can be implemented. Furthermore, based on the current register provided in this embodiment, multiplication operations can be completed using only one current register.

[0079] For the current register provided in this embodiment, when implementing the current division operation, it is necessary to use multiple current registers, such as Figure 13 As shown, N+1 registers AREG are connected to the bus. AREG0 is read, and AREG1 through AREG N are written. According to Kirchhoff's current law, the current flowing out of a circuit node is equal to the current flowing in. Therefore, when the current flowing out of AREG0 is I0, each register AREG1 through AREG N shares I0 equally, resulting in each register receiving a current of I0 / N. This achieves division by integer multiples of current.

[0080] Furthermore, for non-integer multiples of multiplication or division, it can be obtained in the form of a fraction by combining integer multiples of multiplication and integer multiples of division. For example, to implement 1.5Iy, it can be decomposed into Iy×3 / 2, that is, first perform a three-fold accumulation operation on Iy, and then perform a 2-fold division operation, that is, 1.5Iy can be obtained. Those skilled in the art can understand the implementation process of the current register provided in this embodiment for other arbitrary multiples of multiplication and division through the above examples, and this application will not go into details.

[0081] This embodiment also provides an image sensor, including the current register described above.

[0082] When the current register provided by this embodiment is used in an image sensor, the circuit complexity can be greatly reduced while ensuring the calculation function, thereby reducing circuit area consumption, improving integration, and saving hardware expenses.

[0083] It should be noted that the various embodiments described in the specification are progressive in nature, and each embodiment highlights the differences from other embodiments, and the same and similar parts between embodiments can be mutually referred to, and in addition, the different parts between the various embodiments can also be used in combination with each other, and the present application is not limited thereto.

[0084] The current register and the control method thereof and the image sensor provided by the embodiment include a transmission module configured to obtain a signal current; an operation register module including a first register transistor, a second register transistor and a switch control unit; by controlling the state of the switch control unit, the first register transistor and the second register transistor are enabled to perform the inverse, addition, subtraction or multiplication operation on the signal current to obtain a result current, and the result current is stored. By using only one operation register module, the inverse, addition, subtraction and accumulation operations can be realized, and the positive and negative currents can also be stored, so that the circuit complexity is greatly reduced while the operation function is ensured, and the circuit area consumption is reduced, the integration is improved, the hardware cost is saved, and the problem of large area overhead of the current register is solved.

[0085] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way, and any modification or modification made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A current register, characterized in that: include: Transmission module, used to obtain signal current; An operation register module includes a first register transistor, a second register transistor and a switch control unit; by controlling the state of the switch control unit, the first register transistor and the second register transistor perform inversion, addition, subtraction or multiplication operations on the signal current to obtain a result current, and store the result current.

2. The current register according to claim 1, wherein: The switch control unit includes a first switch, a second switch, a third switch and a fourth switch; The source of the first register transistor is grounded, the gate and source are connected through the first switch, and the gate and drain are connected through the second switch; the drain of the first register transistor is also connected to the drain of the second register transistor and to the transmission module; the gate and drain of the second register transistor are connected through the third switch, and the gate and source are connected through the fourth switch; the source of the second register transistor is connected to the power supply.

3. The current register according to claim 2, characterized in that: The first switch, the second switch, the third switch and the fourth switch are all transistors; The gate of the first register transistor is connected to the drain of the first switch and the source of the second switch, the source of the first register transistor is connected to the source of the first switch, and the drain of the first register transistor is connected to the drain of the second switch; the gate of the second register transistor is connected to the source of the third switch and the drain of the fourth switch, the drain of the second register transistor is connected to the drain of the third switch, and the source of the second register transistor is connected to the source of the fourth switch; the gate of the first switch is connected to a first reset signal, the gate of the second switch is written with a first write signal, the gate of the third switch is connected to a second write signal, and the gate of the fourth switch is connected to a second reset signal.

4. The current register according to claim 3, characterized in that: The first register transistor is an NMOS transistor, the second register transistor is a PMOS transistor, the first switch and the second switch are both NMOS transistors, and the third switch and the fourth switch are both PMOS transistors.

5. The current register according to claim 2, characterized in that: The transmission module includes a transmission switch; one end of the transmission switch is connected to the drain of the first register transistor and the drain of the second register transistor, and the other end of the transmission switch is connected to a bus.

6. The current register according to claim 5, characterized in that: The transmission switch is a transistor group switch, and the transistor group switch includes a first transmission transistor and a second transmission transistor; The drain of the first transfer transistor is connected to the source of the second transfer transistor and is connected to the bus; the source of the first transfer transistor is connected to the drain of the second transfer transistor and is connected to the drain of the first register transistor and the drain of the second register transistor; the gate of the first transfer transistor is connected to an enable signal, and the gate of the second transfer transistor is connected to an anti-enable signal.

7. The current register according to claim 6, characterized in that: The first transfer transistor is an NMOS transistor, and the second transfer transistor is a PMOS transistor.

8. The current register according to claim 1, wherein: The switch control unit includes a fifth switch, a sixth switch, a seventh switch and an eighth switch; the fifth switch, the sixth switch, the seventh switch and the eighth switch are all transistors; The source of the first register transistor is grounded, the gate of the first register transistor is connected to the source of the fifth switch, and the drain of the first register transistor is connected to the source of the sixth switch; the drain of the fifth switch is connected to the drain of the sixth switch; the source of the second register transistor is connected to a power supply, the gate of the second register transistor is connected to the source of the seventh switch, and the drain of the second register transistor is connected to the source of the eighth switch; the drain of the seventh switch is connected to the drain of the eighth switch; the drain of the sixth switch is connected to the drain of the eighth switch and is connected to a bus; the gate of the fifth switch is connected to a first write signal, the gate of the sixth switch is connected to a first read signal, the gate of the seventh switch is connected to a second write signal, and the gate of the eighth switch is connected to a second read signal.

9. The current register according to claim 8, characterized in that: The first register transistor is an NMOS transistor, the second register transistor is a PMOS transistor, the fifth switch and the sixth switch are both NMOS transistors, and the seventh switch and the eighth switch are both PMOS transistors.

10. The current register according to claim 8, characterized in that: The transmission module is composed of the sixth switch and the eighth switch.

11. A method for controlling a current register, for realizing positive current reading and writing of the current register according to any one of claims 1 to 10, characterized in that: The control method includes: During the write process, the state of the transmission module is controlled so that the operation register module is connected to the bus; the state of the switch control unit is controlled so that the gate and drain of the first register transistor are short-circuited and the second register transistor is in the off state; at this time, the positive current at the bus is input into the first register transistor through the transmission module and converted at the gate of the first register transistor to obtain a gate voltage; In the hold state, the state of the transmission module is controlled so that the operation register module is disconnected from the bus; the state of the switch control unit is controlled so that the gate and drain of the first register transistor are disconnected and the second register transistor is still in the off state; at this time, the drain voltage of the first register transistor is discharged to 0 and the quiescent current is 0; During the readout process, the state of the transmission module is controlled so that the operation register module is connected to the bus; the state of the switch control unit is maintained so that the gate and drain of the first register transistor are still disconnected and the second register transistor is still in the off state; at this time, the first register transistor is in the saturation region, and the written positive current is read out.

12. A method for controlling a current register, for realizing negative current reading and writing of the current register according to any one of claims 1 to 10, characterized in that: The control method includes: During the writing process, the state of the transmission module is controlled so that the operation register module is connected to the bus; the state of the switch control unit is controlled so that the first register transistor is in the off state and the gate and drain of the second register transistor are short-circuited; at this time, the negative current at the bus is input into the second register transistor through the transmission module and converted at the gate of the second register transistor to obtain a gate voltage; In the hold state, the state of the transmission module is controlled so that the operation register module is disconnected from the bus; the state of the switch control unit is controlled so that the gate and drain of the second register transistor are disconnected, and the first register transistor is still in the off state; at this time, the drain voltage of the second register transistor is charged to the power supply voltage and the quiescent current is 0; During the readout process, the state of the transmission module is controlled so that the operation register module is connected to the bus; the state of the switch control unit is maintained so that the gate and drain of the second register transistor are still disconnected and the first register transistor is still in the off state; at this time, the second register transistor is in the saturation region, and the written negative current is read out.

13. A method for controlling a current register, for implementing a current inversion operation of the current register according to any one of claims 1 to 10, characterized in that: The control method includes: Controlling the states of the transmission module and the switch control unit so that the current register is in a hold state; at this time, the gate-drain and gate-source of the first register transistor are disconnected, the gate-drain and gate-source of the second register transistor are disconnected, and the signal current is stored in the gate of the first register transistor in the form of a voltage; Controlling the state of the switch control unit so that the gate-drain and gate-source of the first register transistor remain disconnected, and the gate-source of the second register transistor is disconnected and the gate-drain is short-circuited; at this time, the first register transistor operates in a saturation region, the first register transistor transfers the signal current to the second register transistor, and generates a gate voltage at the gate of the second register transistor; Control the state of the switch control unit so that the gate-source and gate-drain of the second register transistor remain disconnected, and the gate-drain of the first register transistor remains disconnected and the gate-source is short-circuited; at this time, the gate voltage of the first register transistor is discharged and is in the off state, and the first register transistor transfers current to the second register transistor for storage, and the current is reversed.

14. A method for controlling a current register, for implementing a current addition operation of a current register according to any one of claims 1 to 10, characterized in that: The control method includes: Controlling the states of the transmission module and the switch control unit so that the gate-drain of the first register transistor is disconnected and the gate-source is short-circuited, and the gate-source and gate-drain of the second register transistor are disconnected; at this time, the second register transistor stores a signal current that has undergone an inverted operation; Controlling the state of the transmission module so that the operation register module is connected to the bus; controlling the state of the switch control unit so that the gate and drain of the first register transistor are short-circuited and the gate and source are disconnected, and the gate and source of the second register transistor remain disconnected and the gate and drain remain disconnected; at this time, the other signal current to be added at the bus is input into the first register transistor via the transmission module, so that the current flowing through the first register transistor is the sum of the signal current stored in the second register transistor after the inversion operation and the input other signal current to be added, and a corresponding gate voltage is generated at the gate of the first register transistor; The state of the switch control unit is controlled so that the gate-drain of the first register transistor is disconnected and the gate-source remains disconnected, and then the states of the transmission module and the switch control unit are controlled so that the operation register module is disconnected from the bus, the gate-source of the second register transistor is short-circuited, and the gate-drain remains disconnected; at this time, the second register transistor is in the off state, and the first register transistor stores the result of the current addition operation in the form of voltage at the gate.

15. A method for controlling a current register, for implementing a current subtraction operation of the current register according to any one of claims 1 to 10, characterized in that: The control method includes: Controlling the states of the transmission module and the switch control unit so that the operation register module is connected to the bus, the gate and drain of the first register transistor are short-circuited and the gate and source are disconnected, and the gate and source of the second register transistor are short-circuited and the gate and drain are disconnected; at this time, the first register transistor stores the input signal current; Controlling the state of the switch control unit so that the gate-drain of the first register transistor is disconnected and the gate-source remains disconnected, and the gate-source of the second register transistor is disconnected and the gate-drain is short-circuited; at this time, the other signal current to be subtracted at the bus is input into the arithmetic register module via the transmission module. Since the first register transistor is in a saturation region, the current flowing through the second register transistor is the difference between the signal current stored in the first register transistor and the input other signal current to be subtracted, and a corresponding gate voltage is generated at the gate of the second register transistor; Control the state of the switch control unit so that the gate-source and gate-drain of the second register transistor remain disconnected; control the states of the transmission module and the switch control unit so that the operation register module is disconnected from the bus, the gate-drain of the first register transistor remains disconnected, and the gate-source is short-circuited; at this time, the first register transistor is in the off state, and the second register transistor stores the result of the current subtraction operation in the form of voltage at the gate.

16. An image sensor, characterized in that: Comprising the current register according to any one of claims 1 to 10.

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