Image coding circuit and image coding method for calculating quantization distortion in frequency domain

Abstract

The invention discloses an image coding circuit and an image coding method for calculating quantization distortion in a frequency domain, and relates to the technical field of image coding. The image coding method comprises the following steps: calculating a pixel difference value between a prediction pixel and a current pixel; performing discrete cosine transform on the pixel difference to generate a discrete cosine transform coefficient; quantizing the discrete cosine transform coefficient to generate a quantized value; storing the quantized value in a storage circuit; calculating a quantization distortion based on the quantization value and a quantization step size; calculating a bit rate based on the quantized value; generating a prediction mode based on the quantization distortion and the bit rate; reading the quantized value from the storage circuit based on the prediction mode; performing an inverse quantization operation on the quantized value to generate an inverse quantized value; performing inverse discrete cosine transform operation on the inverse quantized value to generate an inverse discrete cosine transform coefficient; and generating a reconstructed pixel based on the current pixel and the inverse discrete cosine transform coefficient.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of image encoding, and in particular to an image encoding circuit and an image encoding method for calculating quantization distortion in frequency domain. BACKGROUND

[0002] Figure 1 is a function block diagram of an embodiment of the prior art image encoding circuit. The image encoding circuit 100 includes a subtraction circuit 110, a Discrete Cosine Transform (DCT) circuit 120, a Quantization circuit 130, an Inverse Quantization circuit 140, an Inverse Discrete Cosine Transform circuit 150, a pixel reconstruction circuit 160, a time domain quantization distortion calculation circuit 170, and a Rate-distortion optimization (RDO) circuit 180.

[0003] The input of the image encoding circuit 100 includes a current pixel P_curr and a predicted pixel P_pred, and the output of the image encoding circuit 100 includes a reconstructed pixel P_rcst and a prediction mode MD. The time domain quantization distortion calculation circuit 170 performs a minimum mean square error calculation on the predicted pixel P_pred and the reconstructed pixel P_rcst in time domain to generate a quantization distortion QD. The Rate-distortion optimization circuit 180 generates the prediction mode MD based on the quantization distortion QD.

[0004] The drawback of the image encoding circuit 100 is that the Inverse Quantization circuit 140 performs real-time inverse quantization operation on the output of the Quantization circuit 130, which results in difficulty in sharing hardware resources between the Quantization circuit 130 and the Inverse Quantization circuit 140 while ensuring throughput. Furthermore, the time domain quantization distortion calculation circuit 170 has to wait until the pixel reconstruction circuit 160 generates the reconstructed pixel P_rcst before calculating the quantization distortion QD, which limits the performance of the image encoding circuit 100. SUMMARY

[0005] In view of the deficiencies of the prior art, an object of the present application is to provide an image encoding circuit and an image encoding method to improve the deficiencies of the prior art.

[0006] An embodiment of the present application provides an image encoding circuit, comprising a subtraction circuit, a discrete cosine transform circuit, a quantization circuit, a storage circuit, a frequency domain quantization distortion calculation circuit, a bit rate calculation circuit, a mode decision circuit, a dequantization circuit, an inverse discrete cosine transform circuit, and a pixel reconstruction circuit. The subtraction circuit is configured to calculate a pixel difference between a predicted pixel and a current pixel. The discrete cosine transform circuit is coupled to the subtraction circuit and configured to perform a discrete cosine transform on the pixel difference to generate a discrete cosine transform coefficient. The quantization circuit is coupled to the discrete cosine transform circuit and configured to quantize the discrete cosine transform coefficient to generate a quantized value. The storage circuit is coupled to the quantization circuit and configured to store the quantized value. The frequency domain quantization distortion calculation circuit is coupled to the quantization circuit and configured to calculate a quantization distortion based on the quantized value and a quantization step. The bit rate calculation circuit is coupled to the quantization circuit and configured to calculate a bit rate based on the quantized value. The mode decision circuit is coupled to the frequency domain quantization distortion calculation circuit and the bit rate calculation circuit and configured to generate a prediction mode based on the quantization distortion and the bit rate. The dequantization circuit is coupled to the storage circuit and the mode decision circuit and configured to read the quantized value from the storage circuit according to the prediction mode and perform a dequantization operation on the quantized value to generate a dequantized value. The inverse discrete cosine transform circuit is coupled to the dequantization circuit and configured to perform an inverse discrete cosine transform operation on the dequantized value to generate an inverse discrete cosine transform coefficient. The pixel reconstruction circuit is coupled to the inverse discrete cosine transform circuit and configured to generate a reconstructed pixel based on the current pixel and the inverse discrete cosine transform coefficient.

[0007] Another embodiment of the present application provides an image encoding method, comprising the steps of: calculating a pixel difference between a predicted pixel and a current pixel; performing a discrete cosine transform on the pixel difference to generate a discrete cosine transform coefficient; quantizing the discrete cosine transform coefficient to generate a quantized value; storing the quantized value to a storage circuit; calculating a quantization distortion based on the quantized value and a quantization step; calculating a bit rate based on the quantized value; generating a prediction mode based on the quantization distortion and the bit rate; reading the quantized value from the storage circuit according to the prediction mode; performing a dequantization operation on the quantized value to generate a dequantized value; performing an inverse discrete cosine transform operation on the dequantized value to generate an inverse discrete cosine transform coefficient; and generating a reconstructed pixel based on the current pixel and the inverse discrete cosine transform coefficient.

[0008] Another embodiment of the present application provides an image encoding circuit, comprising a subtraction circuit, a discrete cosine transform circuit, a storage circuit, a quantization circuit, a dequantization circuit, a bit rate calculation circuit, a frequency domain quantization distortion calculation circuit, an inverse discrete cosine transform circuit, a mode decision circuit, and a pixel reconstruction circuit. The subtraction circuit is configured to calculate a pixel difference between a predicted pixel and a current pixel. The discrete cosine transform circuit is coupled to the subtraction circuit and configured to perform a discrete cosine transform on the pixel difference to generate a discrete cosine transform coefficient. The storage circuit is coupled to the discrete cosine transform circuit and configured to store the discrete cosine transform coefficient. The quantization circuit is coupled to the discrete cosine transform circuit and configured to quantize the discrete cosine transform coefficient to generate a quantized value. The dequantization circuit is coupled to the quantization circuit and configured to perform a dequantization operation on the quantized value to generate a dequantized value. The bit rate calculation circuit is coupled to the quantization circuit and configured to calculate a bit rate based on the quantized value. The frequency domain quantization distortion calculation circuit is coupled to the storage circuit and the dequantization circuit and configured to calculate a quantization distortion based on the discrete cosine transform coefficient and the dequantized value. The inverse discrete cosine transform circuit is coupled to the dequantization circuit and configured to perform an inverse discrete cosine transform operation on the dequantized value to generate an inverse discrete cosine transform coefficient. The mode decision circuit is coupled to the frequency domain quantization distortion calculation circuit and the bit rate calculation circuit and configured to generate a prediction mode based on the quantization distortion and the bit rate. The pixel reconstruction circuit is coupled to the inverse discrete cosine transform circuit and configured to generate a reconstructed pixel based on the current pixel and the inverse discrete cosine transform coefficient.

[0009] The technical means embodied by the embodiments of the present application can improve at least one of the shortcomings of the prior art, and thus the present application can improve performance and save costs compared to the prior art.

[0010] The features, implementations, and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a functional block diagram of an embodiment of the prior art image encoding circuit;

[0012] Figure 2 is a functional block diagram of an embodiment of the electronic device of the present application;

[0013] Figures 3A-3B is a flowchart of an embodiment of the image encoding method of the present application;

[0014] Figure 4 is a flowchart of an embodiment of step S380 of Figure 3B

[0015] Figure 5 is a functional block diagram of an embodiment of the frequency domain quantization distortion calculation circuit of the present application; ​

[0016] Figures 6A-6B is a flowchart of an embodiment of the quantization distortion calculation of the present application;

[0017] Figure 7 is a functional block diagram of another embodiment of the electronic device of the present application; and

[0018] Figure 8 is a functional block diagram of another embodiment of the frequency domain quantization distortion calculation circuit of the present application.

[0019] 100, 220, 720: image encoding circuit;

[0020] 110, 520: subtraction circuit;

[0021] 120: discrete cosine transform circuit;

[0022] 130: quantization circuit;

[0023] 140: inverse quantization circuit;

[0024] 150: inverse discrete cosine transform circuit;

[0025] 160: pixel reconstruction circuit;

[0026] 170: time domain quantization distortion calculation circuit;

[0027] 180: bit rate-distortion optimization circuit;

[0028] MD: prediction mode;

[0029] P_curr: current pixel;

[0030] P_pred: predicted pixel;

[0031] P_rcst: reconstructed pixel;

[0032] QD: quantization distortion;

[0033] 200, 700: electronic device;

[0034] 210, 710: calculation circuit;

[0035] 222, 722: storage circuit;

[0036] 224, 724: frequency domain quantization distortion calculation circuit;

[0037] 226: bit rate calculation circuit;

[0038] 228: mode decision circuit;

[0039] P_diff: pixel difference;

[0040] QM: quantization matrix

[0041] RT: rate

[0042] SL: scaling list mode

[0043] q step : quantization step size

[0044] x(k): discrete cosine transform coefficient

[0045] x id (k): inverse discrete cosine transform coefficient

[0046] x iq (k): dequantized value

[0047] x q (k): quantized value

[0048] x quot (k): integer approximation value

[0049] x remain (k): difference value

[0050] S310, S320, S330, S340, S345, S350, S360, S370, S380, S385, S390, S395, S410, S420, S610, S620, S630, S632, S640, S650, S660, S670, S680, S690, S695: step

[0051] 515: register

[0052] 510: mode selection circuit

[0053] 525: addition circuit

[0054] 530, 545, 550, 555: multiplication circuit

[0055] 535: scaling list compensation circuit

[0056] 540: product-sum circuit

[0057] 560: selection circuit

[0058] S_UV: chrominance component

[0059] S_UV': weighted chrominance component

[0060] S_Y: luminance component

[0061] S1: compensation value

[0062] S2, S4, S5, S6, S8: numerical values;

[0063] S3: multiplier;

[0064] Wt: weight;

[0065] S7: difference. DETAILED DESCRIPTION

[0066] The technical terms in the following description are referred to the conventional terms in the technical field, and the explanations of the terms are subject to the descriptions or definitions in the present description.

[0067] The disclosure of the present application includes an image encoding circuit and an image encoding method. Since some components included in the image encoding circuit of the present application can be known components individually, the details of the known components will be omitted in the following description without affecting the sufficient disclosure and implementability of the device invention. In addition, some or all processes of the image encoding method of the present application can be in the form of software and / or firmware, and can be executed by the image encoding circuit of the present application or its equivalent device, and the following description of the method invention will focus on the content of the steps rather than the hardware without affecting the sufficient disclosure and implementability of the method invention.

[0068] Figure 2 is a functional block diagram of an embodiment of an electronic device of the present application. The electronic device 200 includes a computing circuit 210 and an image encoding circuit 220 coupled to each other. The computing circuit 210 can be a circuit or electronic component with program execution capability, such as a central processing unit, a microprocessor, a micro processing unit, a digital signal processor, an application specific integrated circuit (ASIC), or an equivalent circuit thereof.

[0069] The image encoding circuit 220 includes a subtraction circuit 110, a discrete cosine transform circuit 120, a quantization circuit 130, a dequantization circuit 140, a discrete cosine inverse transform circuit 150, a pixel reconstruction circuit 160, a storage circuit 222, a frequency domain quantization distortion calculation circuit 224, a bit rate calculation circuit 226, and a mode decision circuit 228 coupled to each other. Figure 1 Components with the same numbers in Figure 2 have similar or substantially the same functions, and will not be described again. The storage circuit 222 can be a volatile memory (e.g., static random access memory (SRAM)).

[0070] Figures 3A-3B This is a flowchart of an embodiment of the image encoding method of the present application. Figures 3A-3B The process includes the following steps.

[0071] Step S310: The calculation circuit 210 sets the scaling list mode SL, the scaling list QM and the quantization step size q step In some embodiments, the scaling list QM used in the frequency domain is the same as the scaling list QM used in the time domain. That is, the scaling list QM used by the frequency domain quantization distortion calculation circuit 224 is the same as the scaling list QM used by the time domain quantization distortion calculation circuit 170.

[0072] Step S320 : The subtraction circuit 110 subtracts the predicted pixel P_pred from the current pixel P_curr to generate a pixel difference P_diff.

[0073] Step S330 : The DCT circuit 120 performs a 2D DCT on the pixel difference P_diff to generate a DCT coefficient x(k).

[0074] Step S340: The quantization circuit 130 quantizes the DCT coefficient x(k) to generate a quantized value x q (k).

[0075] Step S345: The quantization circuit 130 converts the quantized value x q (k) is stored together with its corresponding label in the storage circuit 222. For example, the label can be an intra-frame prediction of N*N pixels or an inter-frame prediction of N*N pixels, where N is an integer greater than 1 (e.g., 8, 16, or 32).

[0076] Step S350: The frequency domain quantization distortion calculation circuit 224 calculates the quantization value x based on the quantization value x. q (k), scaling list mode SL, quantization step size q step And the scaling table QM calculates the quantization distortion QD. Step S350 will be used in conjunction with Figures 6A-6B Details.

[0077] Step S360: The bit rate calculation circuit 226 calculates the bit rate based on the quantized value x q (k) Calculate the bit rate RT. Based on the quantized value x q (k) Calculating the bit rate RT is well known to those skilled in the art and will not be described in detail.

[0078] Step S370: The mode decision circuit 228 determines the value of the quantized value x based on the quantized value x.q (k) generates a prediction mode MD from the bit rate RT. The prediction mode MD indicates the size of the coding block (e.g., 16*16 pixels, 8*8 pixels, or 4*4 pixels) and the coding manner (e.g., intra prediction or inter prediction).

[0079] Step S380: The inverse quantization circuit 140 reads the corresponding quantization value x q (k) from the storage circuit 222 based on the prediction mode MD. For example, if the prediction mode MD indicates the intra prediction of 16*16 pixels (i.e., one example of the label described in step S345), the inverse quantization circuit 140 reads the corresponding quantization value x q (k) to perform the inverse quantization operation. Compared with the prior image encoding circuit 100, the image encoding circuit 220 does not need to perform the inverse quantization operation on all the quantization values x q (k).

[0080] Step S385: The inverse quantization circuit 140 performs the inverse quantization operation on the quantization value x q (k) read in the previous step to generate the inverse quantization value x iq (k).

[0081] Step S390: The inverse discrete cosine transform circuit 150 performs the inverse discrete cosine transform operation on the inverse quantization value x iq (k) to generate the inverse discrete cosine transform coefficient x id (k).

[0082] Step S395: The pixel reconstruction circuit 160 generates the reconstructed pixel P_rcst based on the current pixel P_curr and the inverse discrete cosine transform coefficient x id (k). The operation details of the inverse discrete cosine transform circuit 150 and the pixel reconstruction circuit 160 are well known to those skilled in the art, and thus are not described herein.

[0083] Figure 4 is a flowchart of one embodiment of step S380. Figure 3B The flow of includes the following steps. Figure 4

[0084] Step S410: The inverse quantization circuit 140 finds the label corresponding to the prediction mode MD from the storage circuit 222 based on the prediction mode MD.

[0085] Step S420: The inverse quantization circuit 140 reads the quantization value x q (k) corresponding to the label.

[0086] ​According to the Parseval theorem, the total energy of a signal in the time domain is equal to the total energy of the signal in the frequency domain, i.e. the total energy of a signal is invariant after Fourier transform. Therefore, the present application can calculate the quantization distortion in the frequency domain, and the result obtained is equivalent to that of the time domain quantization distortion calculation circuit 170 of Figure 1 The following description is based on the calculation of the quantization distortion QD by the Sum of Square Error (SSE), but the present application is not limited thereto. The scaling list QM can be a matrix for applying different scaling factors to different frequency components of the image. The setting of the scaling list QM based on the actual coding requirements is well known to those skilled in the art, and therefore will not be described in detail.

[0087] The frequency domain quantization distortion calculation circuit 224 calculates the quantization distortion QD in the frequency domain based on the scaling list mode SL, the quantization step q step , the scaling list QM and the quantization value x q (k). The scaling list mode SL has the following three modes: (A) no adjustment of the quantization value x q (k) and the inverse quantization value x iq (k) (SL = 0); (B) adjustment of the quantization value x q (k) based on the scaling list QM, but no adjustment of the inverse quantization value x lq (k) (SL = 1); and (C) adjustment of the quantization value x q (k) and the inverse quantization value x iq (k) based on the scaling list QM (SL = 2).

[0088] The calculation details of the three modes are described below, and the equations corresponding to the three modes are shown below.

[0089] (A) When SL = 0

[0090]

[0091] x quot (k) = floor(x q (k) + f) (2)

[0092] x remain (k) = x q (k) - x quot (k) (3)

[0093] x iq = q step x quot (k) (4)

[0094]

[0095] (B) when SL = 1

[0096]

[0097] x quot (k) = floor(x q (k) + f) (9)

[0098] x remain (k) = x q (k) - x quot (k) (10)

[0099] x iq (k) = x quot (k) q step (11)

[0100]

[0101] (C) when SL = 2

[0102]

[0103] x quot (k) = floor(x q (k) + f) (14)

[0104] x remain (k) = x q (k) - x quot (k) (15)

[0105]

[0106] x(k) is a discrete cosine transform coefficient (k = 1, 2,..., N 2 , N 2 is the size of the current prediction unit, x quot (k) is an integer approximation of the quantized value x q (k), f is a threshold value for the rounding operation (1 / 6 for P-frames and 1 / 3 for I-frames) (see equations (2), (9), (14)), q step is the quantization step size, QM(k) is the scaling list QM, and x s (k) is the distortion caused by QM(k).

[0107] Figure 5is a functional block diagram of an embodiment of the frequency-domain quantization distortion computation circuit 224 of the present application. The frequency-domain quantization distortion computation circuit 224 includes a mode selection circuit 510 (including a register 515), a subtraction circuit 520, an addition circuit 525, a multiplication circuit 530, a scaling list compensation circuit 535, a multiply-accumulate (MAC) circuit 540, a multiplication circuit 545, a multiplication circuit 550, a multiplication circuit 555, and a selection circuit 560, which are coupled to one another.

[0108] Figures 6A-6B is a flowchart of an embodiment of the quantization distortion computation of the present application. Figures 6A-6B The flow of includes the following steps.

[0109] Step S610: The mode selection circuit 510 receives the quantized value x q (k) and performs the corresponding operation according to the scaling list mode SL, which is detailed as follows.

[0110] In mode (A) (when SL = 0), the mode selection circuit 510 does not output the quantized value x q (k) and the reciprocal of the scaling list QM (i.e., 1 / QM, which can be pre-stored in the register 515) to the scaling list compensation circuit 535, and outputs 1 to the multiplication circuit 530 (i.e., the multiplier S3 is 1).

[0111] In mode (B) (when SL = 1), the mode selection circuit 510 outputs the quantized value x q (k) and the reciprocal 1 / QM of the scaling list QM to the scaling list compensation circuit 535, and outputs 1 to the multiplication circuit 530 (i.e., the multiplier S3 is 1).

[0112] In mode (C) (when SL = 2), the mode selection circuit 510 does not output the quantized value x q (k) and the reciprocal 1 / QM of the scaling list QM to the scaling list compensation circuit 535, and outputs the reciprocal 1 / QM of the scaling list QM to the multiplication circuit 530 (i.e., the multiplier S3 is 1 / QM).

[0113] Step S620: The subtraction circuit 520 computes the difference between the quantized value x q (k) and its integer approximation x quot (k) to obtain the difference x remain (k) (refer to equations (3), (10), (15)). In some embodiments, the integer approximation x quot (k) is provided by the quantization circuit 130.

[0114] Step S630: The scaling list compensation circuit 535 provides the compensation value S1 to the adding circuit 525 according to the scaling list mode SL. Step S630 includes sub-step S632: When SL=1, the scaling list compensation circuit 535 calculates the compensation value S1 based on the scaling list QM and the quantization value x q (k) generates x s (i.e., S1 = x s , refer to equation (8). However, when SL=0 or 2, the compensation value S1 is 0. In other words, when SL=0 or 2, the scaling list compensation circuit 535 and the adding circuit 525 can be omitted.

[0115] Step S640: The adding circuit 525 calculates the difference x based on the compensation value S1. remain (k) Compensation is performed to generate a value S2. More specifically, when SL=0 or 2, since the compensation value S1 is 0, the value S2 is equal to the difference x remain (k) (In other words, the adding circuit 525 can be omitted). When SL=1, the adding circuit 525 adds the difference x remain (k) plus x s (i.e., S2 = x remain (k)+x s (k), refer to equation (12)).

[0116] Step S650: The multiplication circuit 530 multiplies the value S2 by the multiplier S3 to generate the value S4. When SL=0 or 1 (S3=1), S4=S2. When SL=2 (S3=1 / QM), (Refer to equation (17)) In other words, when SL=0 or 1, the multiplication circuit 530 can be omitted.

[0117] Step S660: The multiplication-accumulation circuit 540 performs a multiplication-accumulation operation on the value S4 to generate the value S5. More specifically, the multiplication-accumulation circuit 540 calculates the square of the value S4 based on equation (5), (12) or (17) and then accumulates it. For example, when SL=0, (Part of equation (5)) When SL = 1, S5 = ∑ k (x remain (k)+x s (k)) 2 (Part of Equation (12)). When SL = 2, (Part of Equation (17)).

[0118] Step S670: The multiplication circuit 550 calculates the quantization step size q step The square of , to produce the value S6 (ie, ).

[0119] Step S680: Multiplication circuit 545 multiplies value S5 by value S6 to generate luminance component S_Y and chrominance component S_UV.

[0120] Step S690: Multiplication circuit 555 multiplies chrominance component S_UV by weight Wt to generate weighted chrominance component S_UV'.

[0121] Step S695: Selection circuit 560 selects weighted chrominance component S_UV' or luminance component S_Y as quantization distortion QD.

[0122] Steps S670-S695 are well known to those skilled in the art.

[0123] As described above, because inverse quantization circuit 140 does not need to calculate all quantization values x q (k), the amount of calculation and the calculation time can be greatly reduced, which not only improves the performance of image encoding circuit 220, but also reduces power consumption. Simulation results show that, compared with existing image encoding circuit 100, image encoding circuit 220 of the present application is about 10% faster when determining the mode, and reduces the amount of calculation of inverse quantization circuit 140 and inverse discrete cosine transform circuit 150 by about 26.8%. In addition, because inverse quantization circuit 140 does not need to perform inverse quantization operation on the output of quantization circuit 130 in real time, quantization circuit 130 and inverse quantization circuit 140 can share hardware resources to save costs while ensuring throughput.

[0124] Figure 7 is a functional block diagram of another embodiment of an electronic device of the present application. Electronic device 700 includes calculation circuit 710 and image encoding circuit 720 coupled to each other. Calculation circuit 710 can be a circuit or electronic component with program execution capability, such as a central processing unit, a microprocessor, a micro processing unit, a digital signal processor, an application specific integrated circuit (ASIC), or an equivalent circuit thereof.

[0125] Image encoding circuit 720 includes subtraction circuit 110, discrete cosine transform circuit 120, quantization circuit 130, inverse quantization circuit 140, inverse discrete cosine transform circuit 150, pixel reconstruction circuit 160, bit rate calculation circuit 226, mode decision circuit 228, storage circuit 722, and frequency domain quantization distortion calculation circuit 724 coupled to each other.

[0126] The storage circuit 722 is used to store the discrete cosine transform coefficients x(k) generated by the discrete cosine transform circuit 120. The storage circuit 722 can be a volatile memory (e.g., SRAM). The frequency domain quantization distortion calculation circuit 724 is coupled to the storage circuit 722 and the inverse quantization circuit 140. The frequency domain quantization distortion calculation circuit 724 calculates the quantization distortion QD based on the discrete cosine transform coefficients x(k) and the inverse quantization values x iq (k) from the storage circuit 722, and then calculates the inverse quantization values x

[0127] Figure 8 is a functional block diagram of another embodiment of the frequency domain quantization distortion calculation circuit of the present application. The frequency domain quantization distortion calculation circuit 724 includes a subtraction circuit 520, a multiply-accumulate circuit 540, a multiplication circuit 545, a multiplication circuit 550, a multiplication circuit 555, and a selection circuit 560, which are coupled to each other.

[0128] The subtraction circuit 520 calculates the difference between the inverse quantization value x iq (k) from the storage circuit 722, and then calculates the inverse quantization values x iq (k) and the discrete cosine transform coefficients x(k) to generate a difference value S7 (= x iq (k) - x(k), as shown in equation (5).

[0129] The multiply-accumulate circuit 540 performs multiply-accumulate operation on the difference value S7 to generate a value S8 (=∑ k (x iq (k) - x(k)) 2 , as shown in equation (5). Figure 8 The rest of the circuits in Figure 5 are similar to the circuits with the same numbers in

[0130] In the embodiments of Figure 7 and Figure 8 , since the inverse discrete cosine transform circuit 150 can not perform inverse discrete cosine transform on all the inverse quantization values x iq (k), the calculation amount and the calculation time can be greatly reduced, which not only improves the performance of the image encoding circuit 720, but also reduces the power consumption. In addition, the discrete cosine transform circuit 120 and the inverse discrete cosine transform circuit 150 can also share hardware resources to save costs.

[0131] Although the foregoing embodiments are based on the error sum of squares to calculate the quantization distortion, this is not a limitation of the present application, and those skilled in the art can appropriately apply the present application to other types of quantization distortion calculation methods based on the disclosure of the present application.

[0132] Although the present application is illustrated above by way of example, the embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit contents of the present application. Any changes thus made can fall within the scope of the patent protection sought for the present application. In other words, the scope of the patent protection of the present application shall be defined by the patentable scope of the claims.

Claims

1. An image encoding circuit, characterized in that: include: a subtraction circuit for calculating a pixel difference between a predicted pixel and a current pixel; a discrete cosine transform circuit, coupled to the subtraction circuit, for performing a discrete cosine transform on the pixel difference to generate a discrete cosine transform coefficient; a quantization circuit, coupled to the discrete cosine transform circuit, for quantizing the discrete cosine transform coefficient to generate a quantized value; a storage circuit, coupled to the quantization circuit, for storing the quantization value; a frequency domain quantization distortion calculation circuit, coupled to the quantization circuit, for calculating a quantization distortion based on the quantization value and a quantization step size; a bit rate calculation circuit, coupled to the quantization circuit, for calculating a bit rate based on the quantization value; a mode decision circuit, coupled to the frequency domain quantization distortion calculation circuit and the bit rate calculation circuit, for generating a prediction mode based on the quantization distortion and the bit rate; an inverse quantization circuit coupled to the storage circuit and the mode decision circuit, configured to read the quantized value from the storage circuit according to the prediction mode and perform an inverse quantization operation on the quantized value to generate an inverse quantized value; an inverse discrete cosine transform circuit, coupled to the inverse quantization circuit, for performing an inverse discrete cosine transform operation on the inverse quantized value to generate an inverse discrete cosine transform coefficient; as well as A pixel reconstruction circuit is coupled to the IDCT circuit and is configured to generate a reconstructed pixel based on the current pixel and the IDCT coefficient.

2. The image encoding circuit according to claim 1, wherein: The quantization circuit stores the quantization value and a label corresponding to the quantization value in the storage circuit. The inverse quantization circuit finds the label corresponding to the prediction mode from the storage circuit based on the prediction mode, and reads the quantization value corresponding to the label.

3. The image encoding circuit according to claim 2, wherein: The tag indicates an N*N pixel intra prediction or an N*N pixel inter prediction, where N is an integer greater than 1.

4. The image encoding circuit according to claim 2, wherein: The subtraction circuit is a first subtraction circuit, and the frequency domain quantization distortion calculation circuit includes: a second subtraction circuit, coupled to the quantization circuit, for calculating a difference between the quantized value and an integer approximation of the quantized value; a multiply-accumulate circuit, coupled to the second subtraction circuit, for performing a multiply-accumulate operation on the difference to generate a numerical value; and A multiplication circuit is coupled to the product-accumulation circuit and is used for multiplying the value by the square of the quantization step size to generate a luminance component and a chrominance component.

5. The image encoding circuit according to claim 2, wherein: The subtraction circuit is a first subtraction circuit, and the frequency domain quantization distortion calculation circuit includes: a second subtraction circuit, coupled to the quantization circuit, for calculating a difference between the quantized value and an integer approximation of the quantized value; a scaling list compensation circuit for generating a compensation value based on a scaling list and the quantized value; an adding circuit, coupled to the second subtracting circuit and the scaling table compensation circuit, configured to add the compensation value to the difference to generate a first value; a multiply-accumulate circuit, coupled to the adding circuit, for performing a multiply-accumulate operation on the first value to generate a second value; and A multiplication circuit is coupled to the product-accumulation circuit and is configured to multiply the second value by the square of the quantization step size to generate a luminance component and a chrominance component.

6. The image encoding circuit according to claim 5, wherein: The compensation value is equal to the quantized value divided by the scaling list and then the quantized value is subtracted.

7. The image encoding circuit according to claim 2, wherein: The subtraction circuit is a first subtraction circuit, and the frequency domain quantization distortion calculation circuit includes: a second subtraction circuit, coupled to the quantization circuit, for calculating a difference between the quantized value and an integer approximation of the quantized value; a first multiplication circuit, coupled to the second subtraction circuit, configured to multiply the difference by a multiplier to generate a first value; a multiply-accumulate circuit, coupled to the first multiplication circuit, configured to perform a multiply-accumulate operation on the first value to generate a second value; and A second multiplication circuit is coupled to the product-accumulation circuit and is configured to multiply the second value by the square of the quantization step size to generate a luminance component and a chrominance component.

8. The image encoding circuit according to claim 7, wherein: The multiplier is the inverse of a scaling list.

9. A method for image encoding, characterized in that: include: Calculating a pixel difference between a predicted pixel and a current pixel; performing a discrete cosine transform on the pixel difference to generate a discrete cosine transform coefficient; quantizing the discrete cosine transform coefficient to generate a quantized value; storing the quantized value in a storage circuit; Calculating a quantization distortion based on the quantization value and a quantization step size; calculating a bit rate based on the quantized value; generating a prediction model based on the quantization distortion and the bit rate; reading the quantized value from the storage circuit based on the prediction mode; performing a dequantization operation on the quantized value to generate a dequantized value; performing an inverse discrete cosine transform operation on the dequantized value to generate an inverse discrete cosine transform coefficient; as well as A reconstructed pixel is generated based on the current pixel and the IDCT coefficient.

10. The image encoding method according to claim 9, wherein: The quantized value and a label corresponding to the quantized value are stored in the storage circuit, and the step of reading the quantized value from the storage circuit based on the prediction mode includes: Finding the label corresponding to the predicted mode from the storage circuit based on the predicted mode; and The quantized value corresponding to the tag is read.

11. The image encoding method according to claim 10, wherein: The step of calculating the quantization distortion based on the quantization value and the quantization step size includes: calculating a difference between the quantized value and an integer approximation of the quantized value; performing a multiply-add operation on the difference to generate a value; and The value is multiplied by the square of the quantization step size to generate a luma component and a chroma component.

12. The image encoding method according to claim 10, wherein: The step of calculating the quantization distortion based on the quantization value and the quantization step size includes: calculating a difference between the quantized value and an integer approximation of the quantized value; generating a compensation value based on a scaling list and the quantized value; compensating the difference based on the compensation value to generate a first value; performing a product-add operation on the first value to generate a second value; and Multiplying the second value by the square of the quantization step size to generate a luminance component and a chrominance component; The compensation value is equal to the quantization value divided by the scaling list and then subtracted from the quantization value.

13. The image encoding method according to claim 10, wherein: The step of calculating the quantization distortion based on the quantization value and the quantization step size includes: calculating a difference between the quantized value and an integer approximation of the quantized value; multiplying the difference by a multiplier to generate a first value; performing a product-add operation on the first value to generate a second value; and Multiplying the second value by the square of the quantization step size to generate a luminance component and a chrominance component; The multiplier is the inverse of a scaling list.

14. An image encoding circuit, characterized in that: include: a subtraction circuit for calculating a pixel difference between a predicted pixel and a current pixel; a discrete cosine transform circuit, coupled to the subtraction circuit, for performing a discrete cosine transform on the pixel difference to generate a discrete cosine transform coefficient; a storage circuit, coupled to the discrete cosine transform circuit, for storing the discrete cosine transform coefficients; a quantization circuit, coupled to the discrete cosine transform circuit, for quantizing the discrete cosine transform coefficient to generate a quantized value; an inverse quantization circuit, coupled to the quantization circuit, for performing an inverse quantization operation on the quantized value to generate an inverse quantized value; a bit rate calculation circuit, coupled to the quantization circuit, for calculating a bit rate based on the quantization value; a frequency domain quantization distortion calculation circuit, coupled to the storage circuit and the inverse quantization circuit, for calculating a quantization distortion based on the discrete cosine transform coefficient and the inverse quantization value; an inverse discrete cosine transform circuit, coupled to the inverse quantization circuit, for performing an inverse discrete cosine transform operation on the inverse quantized value to generate an inverse discrete cosine transform coefficient; a mode decision circuit, coupled to the frequency domain quantization distortion calculation circuit and the bit rate calculation circuit, for generating a prediction mode based on the quantization distortion and the bit rate; as well as A pixel reconstruction circuit is coupled to the IDCT circuit and is configured to generate a reconstructed pixel based on the current pixel and the IDCT coefficient.

15. The image encoding circuit according to claim 14, wherein: The subtraction circuit is a first subtraction circuit, and the frequency domain quantization distortion calculation circuit includes: a second subtraction circuit, coupled to the inverse quantization circuit, for calculating a difference between the inverse discrete cosine transform coefficient and the discrete cosine transform coefficient; a multiply-accumulate circuit, coupled to the second subtraction circuit, for performing a multiply-accumulate operation on the difference to generate a numerical value; and A multiplication circuit is coupled to the product-accumulation circuit and is used for multiplying the value by the square of a quantization step length to generate a luminance component and a chrominance component.

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