Groove SiC MOSFET device and preparation method thereof

Abstract

The invention discloses a groove SiC MOSFET device and a preparation method thereof. The preparation method comprises the following steps: epitaxial growth; performing P-type ion implantation for the first time; performing first-stage groove etching; performing N-type ion implantation; implanting P-type ions for the second time; carrying out second-stage groove etching; growing gate oxide, polycrystalline silicon and an interlayer insulating layer; carrying out metal deposition; the beneficial effects of the invention are that the multi-stage trench structure is combined with the plane gate and the trench gate, so that the channel density is increased, the current capability is provided, and the conduction loss is reduced; the MPS diode structure is integrated, the forward voltage drop of the body diode is reduced, the discharge capacity is improved when inrush current occurs in the circuit, the reverse follow current capacity can be improved through the parallel Schottky diode structure, and electronic elements needed by a peripheral circuit are reduced; by integrating the built-in field plate structure, the electric field concentration effect at the bottom of the trench gate is effectively relieved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power devices, in particular to a trench SiC MOSFET device and a preparation method thereof. BACKGROUND

[0002] Power devices play a crucial role in power supply, power processing and other systems. Compared with Si materials, wide-bandgap semiconductors have a larger bandgap, and therefore usually have advantages such as high frequency, high power density, high breakdown voltage, and strong radiation resistance. SiC material has characteristics such as high critical breakdown field, high thermal conductivity and high saturated electron drift speed. Compared with the current mainstream switching device Si IGBT, the unipolar conduction characteristics and high saturated electron drift speed of SiC MOSFET make it have lower switching loss and higher working frequency. Compared with planar gate SiC MOSFET, trench gate SiC MOSFET has better electrical characteristics, including high cell density, low conduction loss, strong switching performance, etc. However, the trench gate is limited by process level and gate oxide reliability, etc. For example, the gate trench bottom electric field concentration, poor surge current and short circuit resistance, which usually causes long-term reliability problems. SUMMARY

[0003] The application provides a multi-stage trench gate SiC MOSFET device integrating an MPS diode structure and a field plate structure. By combining planar gate and trench gate through a multi-stage trench structure, the channel density is increased to provide current capacity, reduce conduction loss, and integrate a hybrid PIN Schottky (MPS) diode structure to reduce the forward voltage drop of the body diode, increase the discharge capacity when surge current occurs in the circuit, and improve the reverse current flow capability by parallel Schottky diode structure to reduce the required electronic components in the circuit. Finally, by integrating the built-in field plate structure, the trench gate bottom electric field concentration effect is effectively alleviated.

[0004] The technical solutions of the application are specifically introduced as follows.

[0005] The application provides a trench SiC MOSFET device, which adopts a multi-stage trench structure combining planar gate and trench gate. The device includes a drain, an n-type substrate, an n-type epitaxial layer, a trench, a source and a gate. The drain is arranged on the back surface of the n-type substrate, the source and the gate are arranged on the front surface of the n-type substrate, the n-type epitaxial layer is arranged above the n-type substrate, and a plurality of multi-stage trenches are arranged on the n-type epitaxial layer. The outer side of the multi-stage trench is provided with a horizontal channel and a vertical channel for current conduction, and an area for ohmic contact is arranged beside the channel to form a path for forward current flow. The inner side of the trench is connected to a distal gate through a polysilicon layer, a gate oxide layer is arranged between the gate and the channel, and the gate and the source are isolated by an interlayer insulation layer.

[0006] In the application, a double-layer multi-stage trench is arranged on the n-type epitaxial layer, the outer side of the first-stage trench of the upper layer is respectively provided with an N-type injection area and a P-type injection area, and the two longitudinal channels composed of the N-type injection area and the P-type injection area, the other side of the two longitudinal channels is respectively connected with the P-type injection area, the lower side of the two sides of the first-stage trench is respectively provided with two P-type injection areas, the second-stage trench is arranged between the two P-type injection areas, the two sides of the P-type injection area are respectively provided with the transverse channel composed of the N-type injection area and the P-type injection area and the longitudinal channel composed of the N-type injection area and the P-type injection area; the lower side of the second-stage trench is provided with three P-type injection areas; the polysilicon layer is arranged close to the inner side of the first-stage and second-stage trench to connect the conduction channel and the gate, the gate oxide layer is arranged between the gate and the channel, the gate and the source are isolated through the interlayer insulation layer, and the interlayer insulation layer is partially arranged on the upper side of the two P-type injection areas to form a field plate structure.

[0007] In the application, the junction depth of the N-type injection area is between 0.2-0.4 μm, the junction depth of the P-type injection area is between 0.5-0.8 μm, and the depth of the second-stage trench exceeds the junction depth of the P-type injection area but does not exceed the junction depth where the P-type injection area is located.

[0008] The application further provides a preparation method of the trench SiC MOSFET device. Step one, epitaxial growth An epitaxial layer is grown on an N-type conductive 4H-SiC conductive substrate; Step two, first P-type ion injection An injection blocking layer is deposited on the epitaxial layer, the injection area is first etched through photolithography, and then P-type impurities are injected through high-energy ions to form a P-type injection area; Step three, first-stage trench etching A mask layer is first deposited on the epitaxial layer, and then the first-stage trench area is etched through photolithography and reactive ion etching, and the depth of the trench does not exceed the junction depth of the P-type injection area; Step four, N-type ion injection An injection blocking layer is deposited on the epitaxial layer, the injection area is first etched through photolithography, and then N-type impurities are injected through high-energy ions to form an N-type injection area; Step five, second P-type ion injection An injection blocking layer is deposited on the epitaxial layer, the injection area is first etched through photolithography, and then P-type impurities are injected through high-energy ions to the P-type injection area; Step six, second-stage trench etching A mask layer is first deposited on the epitaxial layer, and then the second-stage trench area is etched through photolithography and reactive ion etching; Step seven, gate oxide, polysilicon, and interlayer insulation layer growth Thermal oxidation to grow gate oxide SiO2, then deposit polysilicon to form polysilicon layer, then deposit interlayer dielectric SiO2 to isolate gate and source, form oxide structure, wherein part of P-type implant region layer surface is covered with part of oxide layer; Step eight, metal deposition Sputtering gate metal to form ohmic contact with P-type implant region and N-type implant region, and Schottky contact with P-type region of P-type implant region, then deposit metal to form metal electrode; after front passivation layer and PI layer deposition is completed, sputter metal to form back metal electrode, i.e. drain electrode.

[0009] In the present application, in step one, the substrate doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 , and the epitaxial layer doping concentration is 1×10 15 cm -3 ~1×10 17 cm -3 .

[0010] In the present application, in step two, the P-type impurity is any one of Al or B, and the P-type impurity concentration is 1×10 19 cm -3 ~1×10 21 cm -3 .

[0011] In the present application, in step four, the N-type impurity is any one of N or P, and the N-type impurity concentration is 1×10 18 cm -3 ~1×10 20 cm -3 .

[0012] In the present application, in step five, the P-type impurity is any one of Al or B, and the P-type impurity concentration is 1×10 17 cm -3 ~1×10 18 cm -3 .

[0013] In the present application, in steps two, four and five, the barrier layer material is selected from any one of SiO2, POLY or Si3N4 materials.

[0014] In the present application, in steps three and six, the mask layer material is selected from any one of SiO2, POLY or Si3N4 materials; when reactive ion etching, any one of fluorine-based, chlorine-based, bromine-based gas is used for etching.

[0015] In the present application, in step eight, one or both of Ni and Ti is sputtered to form an ohmic contact with the P-type and N-type injection regions; Al is deposited to form a metal electrode; and one or more of Ni, Ti and Ag is sputtered to form a back metal electrode.

[0016] In the present application, in a specific embodiment, the drain is Ag, 1-5 μm thick, the substrate is silicon carbide, 330-380 μm thick, the silicon carbide epitaxial layer is 4-60 μm thick; the ohmic contact layer of the metal and the semiconductor is 0.4-0.6 μm thick, and is a nickel-carbon-silicon composite; the polysilicon layer is 0.3-0.8 μm thick, the gate oxide is 10-80 nm thick, and the source is 2-6 μm thick.

[0017] Compared with the prior art, the present application has the following advantages: 1. The multi-stage trench structure is combined with the planar gate and the trench gate to increase the channel density and thus to provide current capacity and reduce conduction loss. 2. The integrated MPS diode structure reduces the forward voltage drop of the body diode, increases the discharge capacity when inrush current occurs, and improves the reverse current flow capacity and reduces the required electronic components of the peripheral circuit through the parallel Schottky diode structure. 3. The integrated built-in field plate structure effectively alleviates the electric field concentration effect at the bottom of the trench gate. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a preparation schematic diagram of epitaxial growth.

[0019] Figure 2 is a preparation schematic diagram of the first P-type ion implantation.

[0020] Figure 3 is a preparation schematic diagram of the first-stage trench etching.

[0021] Figure 4 is a preparation schematic diagram of N-type ion implantation.

[0022] Figure 5 is a preparation schematic diagram of the second P-type ion implantation.

[0023] Figure 6 is a preparation schematic diagram of the second-stage trench etching.

[0024] Figure 7 is a preparation schematic diagram of the growth of the gate oxide, the polysilicon and the interlayer insulating layer.

[0025] Figure 8 is a preparation schematic diagram of metal deposition. DETAILED DESCRIPTION

[0026] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0027] Example 1

[0028] The present invention provides a method for preparing a trench SiC MOSFET device, comprising the following steps: 1. Epitaxial Growth A 4H-SiC epitaxial layer 102 is grown on an N-type 4H-SiC conductive substrate 100 by liquid phase epitaxy (LPE) or chemical vapor deposition (CVD). The substrate 100 has a doping concentration of 1e19 cm -3 ~1e20cm -3 , the doping concentration of epitaxial layer 102 is 1e15cm -3 ~1e17cm -3 .

[0029] 2. First P-type ion implantation An injection barrier layer is deposited on the epitaxial layer 102, usually made of materials such as SiO2 / POLY (polycrystalline silicon) / Si3N4. The injection area is first etched out by photolithography, and then P-type impurities such as Al, B, etc. are injected by high-energy ions to form Figure 2 The P-type implanted regions 201 to 207 have the same junction depth, where the P-type impurity concentration in the regions 201 to 207 is 1e19 cm -3 ~1e21cm -3 .

[0030] 3. First-level trench etching First, a mask layer is deposited on the epitaxial layer 102, usually SiO2 / POLY (polysilicon) / Si3N4 and other materials, and then etched out by photolithography and reactive ion etching, usually fluorine-based, chlorine-based, bromine-based gases. Figure 3 In the first-level trench region shown, the trench depth does not exceed the junction depth of the P-type implant regions 201 - 207 .

[0031] 4. N-type ion implantation An injection barrier layer is deposited on the epitaxial layer 102, which is usually made of materials such as SiO2 / POLY (polycrystalline silicon) / Si3N4. The injection area is first etched out by photolithography, and then N-type impurities such as N and P are injected by high-energy ions to form Figure 4 The N-type implanted regions 401 to 406 are shown, where the N-type impurity concentration in the regions 401 to 406 is 1e18 cm -3 ~1e20cm -3 , and the junction depth of the N-type regions 401 to 406 is 0.2 to 0.4 μm, the N-type implanted regions 401 to 402 have the same junction depth, and the N-type implanted regions 403 to 406 have the same junction depth.

[0032] V. Second P-type ion implantation An implantation stop layer, such as SiO2 / POLY / Si3N4, is deposited on the epitaxial layer 102. The implantation area is first etched by photolithography and etching, and then P-type impurities, such as Al and B, are implanted by high-energy ion implantation to form the P-type implantation areas 501-506 shown in FIG. 5. The P-type impurity concentration of the areas 501-506 is 1e17cm-1e18cm-1. Figure 5 -3 -3 The junction depth of the P-type areas is 0.5-0.8 μm. The P-type implantation areas 501-504 have the same junction depth, and the P-type implantation areas 505-506 have the same junction depth.

[0033] VI. Second-stage trench etching A mask layer, such as SiO2 / POLY / Si3N4, is first deposited on the epitaxial layer 102, and then the second-stage trench area shown in FIG. 6 is etched by photolithography and reactive ion etching, such as fluorine-based, chlorine-based, and bromine-based gas. Figure 6 The trench depth exceeds the junction depth of the areas 501-504 but does not exceed the junction depth of the P-type areas 201-207.

[0034] VII. Growth of gate oxide, polysilicon, and interlayer insulating layer The gate oxide layer SiO2 is grown by thermal oxidation at 900-1400 °C, and then the poly layer shown in FIG. 7 is formed by depositing polysilicon, and then the interlayer insulating layer SiO2 is deposited to isolate the gate and the source, forming the oxide layer structure shown in FIG. 7. The P-type implantation areas 203 and 205 have a portion of the oxide layer on the surface. Figure 7

[0035] VIII. Metal deposition Ni and Ti metals (gate) are sputtered to form ohmic contact with the areas 201-206, 401, and 402 and Schottky contact with the P-type areas 203 / 204 / 205, and then Al metal is deposited to form the metal electrode 800 (source). After the front passivation layer and the polyimide (PI) layer are deposited, Ni / Ti / Ag metals are sputtered to form the back metal electrode (drain). The passivation layer material can be SiO2 / Si3N4. Since the present application shows a cell structure, the passivation layer and the PI layer are not shown in FIG. 8. Figure 8

[0036] Working principle:

[0037] ​​​​When the positive gate voltage is applied beyond the threshold voltage, the channels formed by 401 and 505, 403 and 501, 404 and 502, 402 and 506, 406 and 504, 405 and 503 are fully open, and the electrons flow from the source through the N-type regions 401 / 402 / 403 / 404 / 405 / 406 into the channel region, then into the N-type epitaxial layer 102 and the substrate 100, and finally into the drain 802. The present application effectively increases the channel density and current density per unit area by combining the lateral channels formed by 403 and 501 and 406 and 504 with the vertical channels formed by 404 and 502, 402 and 506, 401 and 505, 405 and 503, thereby reducing the on-resistance and further reducing the on-loss. When the source-drain is in a reverse bias state, the P-type regions formed by 207 and 501 / 206, 201 and 504 / 202 form a PN junction with the N-type epitaxial layer 102, which can alleviate the electric field at the bottom of the first-stage trench; the P-type regions formed by 206 / 502 / 205 and 202 / 203 / 503 form a PN junction with the N-type epitaxial layer 102, which can alleviate the electric field at the bottom of the second-stage trench. At the same time, the SiO2 layer on top of 205 and 203 forms a field plate structure, which can push the electric field at the bottom of the trench away from the trench bottom, further alleviating the concentration of the electric field at the bottom of the second-stage trench. When the source-drain is in a forward bias state, the Schottky diode formed by the Schottky contact between the metal 800 and the N-type epitaxial layer 102 is first turned on, followed by the ohmic contact between the metal 800 and the P-type and N-type regions. By integrating the Schottky diode, the reverse current capability of the device can be improved, and the number of electronic components required by the peripheral circuit can be reduced. When inrush current occurs in the circuit, the P-type regions where 201 / 203 / 204 / 205 / 207 inject a large number of holes into the N-type epitaxial layer 102 region, reducing the resistance of the epitaxial layer, increasing the discharge capacity of the device, and improving the reliability of the device in circuit applications.

Claims

1. A trench SiC MOSFET device, characterized in that: It adopts a multi-level trench structure combined with a planar gate and a trench gate; it includes a drain, an n-type substrate, an n-type epitaxial layer, a trench, a source and a gate; the drain is arranged on the back of the n-type substrate, the source and gate are arranged on the front of the n-type substrate, the n-type epitaxial layer is arranged above the n-type substrate, and a multi-level trench with two or more layers is arranged on the n-type epitaxial layer; the outer sides of the multi-level trench are provided with a horizontal channel and a vertical channel for current conduction, and an area for ohmic contact is provided next to the channel to form a path for forward current flow; the inner side of the trench is connected to the remote gate through a polysilicon layer, a gate oxide layer is provided between the gate and the channel, and the gate and source are isolated by an interlayer insulating layer.

2. The trench SiC MOSFET device according to claim 1, wherein: A double-layer multi-level trench is provided on the n-type epitaxial layer. The outer sides of the first-level trench of the upper layer are respectively provided with an N-type injection region (401) and a P-type injection region (505), and two longitudinal trenches consisting of an N-type injection region (402) and a P-type injection region (502). The other sides of the two longitudinal trenches are respectively connected to the P-type injection regions (201) and (207). Two P-type injection regions (202) and (206) are respectively provided below the two sides of the first-level trench. A second-level trench is provided between the two P-type injection regions (202) and (206). The two sides of the P-type injection regions (202) and (206) are respectively provided with a lateral trench consisting of an N-type injection region (403) and a P-type injection region (501), and a longitudinal trench consisting of an N-type injection region (404) and a P-type injection region (502), an N-type injection region (406) and a P-type injection region (504). The invention discloses a conductive layer comprising a lateral channel and a longitudinal channel composed of an N-type injection region (405) and a P-type injection region (503); three P-type injection regions (203), (204), and (205) are provided below the second-level groove; polysilicon layers (709) and (711) are provided near the inner side of the first-level groove, and polysilicon layers (713) and (715) are provided near the inner side of the second-level groove to connect the conductive channel and the gate; a gate oxide layer is provided between the gate and the channel; the gate and the source are isolated by interlayer insulating layers (701), (703), (705), and (707); and the interlayer insulating layers (705) and (707) partially cover the upper sides of the P-type injection regions (203) and (205) to form a field plate structure.

3. The trench SiC MOSFET device according to claim 1, wherein: The junction depth of the N-type implantation region (401-406) is between 0.2-0.4 μm, the junction depth of the P-type implantation region (501-506) is between 0.5-0.8 μm, and the second-level trench depth exceeds the junction depth of the P-type implantation region (501-504) but does not exceed the junction depth of the P-type implantation region (201-207).

4. A method for preparing a trench SiC MOSFET device according to claim 2 or 3, characterized in that: The following steps are involved: Step 1: Epitaxial Growth Growing an epitaxial layer (102) on an N-type conductive 4H-SiC conductive substrate (100); Step 2: First P-type ion implantation Depositing an injection barrier layer on the epitaxial layer (102), first etching an injection region by photolithography, and then injecting P-type impurities by high-energy ion implantation to form P-type injection regions (201-207) with the same junction depth; Step 3: First-level trench etching First, a mask layer is deposited on the epitaxial layer (102), and then a first-level trench region is etched by photolithography and reactive ion etching, wherein the trench depth does not exceed the junction depth of the P-type implantation region (201-207); Step 4: N-type ion implantation An injection barrier layer is deposited on the epitaxial layer (102), an injection region is first etched by photolithography, and then N-type impurities are injected by high-energy ion injection to form N-type injection regions (401-406); wherein the N-type injection regions (401-402) have the same junction depth, and the N-type injection regions (403-406) have the same junction depth; Step 5: Second P-type ion implantation An injection barrier layer is deposited on the epitaxial layer (102), an injection region is first etched out by photolithography, and then P-type impurities are injected into the P-type injection region (501-506) by high-energy ion injection; wherein the P-type injection regions (501-504) have the same junction depth, and the P-type injection regions (505-506) have the same junction depth; Step 6: Second-level trench etching First, a mask layer is deposited on the epitaxial layer (102), and then a second-level trench region is etched through photolithography and reactive ion etching; Step 7: Growth of gate oxide, polysilicon, and interlayer insulation layer First, a gate oxide layer SiO2 is grown by thermal oxidation, and then polysilicon is deposited to form a polysilicon layer (709, 711, 713, 715), and then an interlayer insulating layer SiO2 is deposited to isolate the gate and the source, forming an oxide layer structure (701, 703, 705, 707), wherein a portion of the oxide layer is placed on the surface of the P-type implantation region (203, 205); Step 8: Metal Deposition The gate metal is sputtered to form an ohmic contact with the P-type injection region (201-206), the N-type injection region (401), and (402), and a Schottky contact is formed with the P-type injection region (203), (204), and the P-type region gap of (205), and then metal is deposited to form a metal electrode (800), i.e., the source; after the front passivation layer and the PI layer are deposited, metal is sputtered again to form a back metal electrode, i.e., the drain.

5. The preparation method according to claim 4, characterized in that In step 1, the substrate (100) has a doping concentration of 1×10 19 cm -3 ~1×10 20 cm -3 , the doping concentration of the epitaxial layer (102) is 1×10 15 cm -3 ~1×10 17 cm -3 .

6. The preparation method according to claim 4, characterized in that In step 2, the P-type impurity is either Al or B, and the P-type impurity concentration is 1×10 19 cm -3 ~1×10 21 cm -3 .

7. The preparation method according to claim 4, characterized in that In step 4, the N-type impurity is either N or P, and the N-type impurity concentration is 1×10 18 cm -3 ~1×10 20 cm -3 , the junction depth of the N-type implanted regions 401 to 406 is between 0.2 μm and 0.4 μm.

8. The preparation method according to claim 4, characterized in that In step 5, the P-type impurity is either Al or B, and the P-type impurity concentration is 1×10 17 cm -3 ~1×10 18 cm -3 , the junction depth of the P-type injection region (501~506) is between 0.5~0.8μm.

9. The preparation method according to claim 4, characterized in that In step 2, step 4 and step 5, the barrier layer material is selected from any one of SiO2, POLY or Si3N4 materials.

10. The preparation method according to claim 4, characterized in that In step 3 and step 6, the mask layer material is selected from any one of SiO2, POLY or Si3N4 materials; during reactive ion etching, any one of fluorine-based, chlorine-based and bromine-based gases is used for etching; in step 8, one or two metals selected from Ni and Ti are sputtered to form ohmic contacts with the P-type injection region (201-206) and the N-type injection region (401) and (402); metal Al is deposited to form a metal electrode (800); and one or more metals selected from Ni, Ti and Ag are sputtered to form a back metal electrode.

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