Transistor device and manufacturing method thereof, power module, and power conversion circuit

Abstract

The invention provides a transistor device, a manufacturing method, a power module and a power conversion circuit. The transistor device comprises a first doping type substrate, a first doping type buffer layer and a first doping type drift layer which are stacked in sequence, active columns arranged in an array are arranged in the first doping type drift layer, and the top surfaces of the active columns are flush with the top surface of the first doping type drift layer; the active columns comprise first active columns and second active columns, gate grooves are formed between the first active columns, source grooves are formed between the second active columns, and the depth of the source grooves is larger than that of the gate grooves; the grid grooves are formed in the two sides of the source groove, one of the two sides of the grid grooves is the grid groove, the other one of the two sides of the grid grooves is the source groove, or the grid grooves are formed in the two sides of the grid grooves. The avalanche reliability of the device is remarkably enhanced, and the requirement of a power electronic system for a high-reliability device is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a transistor device and a manufacturing method, a power module and a power conversion circuit. BACKGROUND

[0002] Compared with Si, wide band gap semiconductor material SiC and GaN have about 3 times of band gap width, 10 times of critical breakdown field strength, and higher electron mobility. Therefore, SiC and GaN devices have higher voltage resistance, working frequency, efficiency and temperature resistance than Si devices. The power electronic system based on wide band gap semiconductor material SiC and GaN devices not only reduces the switching loss by more than half, but also has smaller volume, weight and comprehensive cost advantages, which is the development direction of the new generation of power electronic system.

[0003] Compared with the low channel mobility and gate reliability problem caused by the high MOS interface state of SiC MOSFET, there is no MOS gate structure in SiC junction field effect transistor (JFET), so the device is relatively simple and mature. The conventional SiC junction field effect transistor (JFET) is a trench type structure or a planar structure, which is connected by the P+ region of the gate to pinch off the N type region, so as to realize the turn-off of the device. However, due to the existence of the gate P+ region, the avalanche breakdown position when the device breaks down is often at the edge of the gate P+ region, and the avalanche current passes through the gate, which will damage the gate drive control chip. The invention of the junction field effect transistor device with avalanche capability has very important significance for the power electronic system using the junction field effect transistor device. SUMMARY

[0004] The present application mainly provides a transistor device and a manufacturing method, a power module and a power conversion circuit to solve the technical problems in the background art.

[0005] The technical solution adopted by the present application to solve the above technical problems is:

[0006] The transistor device comprises a first doped type substrate, a first doped type buffer layer and a first doped type drift layer which are stacked in sequence.

[0007] An array of active columns is arranged in the first doped type drift layer, the top surface of the active column is flush with the top surface of the first doped type drift layer; the active column comprises a first active column and a second active column, the first active column is a gate trench, the second active column is a source trench, and the depth of the source trench is greater than the depth of the gate trench.

[0008] The two sides of the source trench are the gate trenches, one of the two sides of the gate trench is a gate trench and the other is a source trench, or both sides of the gate trench are gate trenches.

[0009] Further, the number ratio of the gate trenches is greater than or equal to that of the source trenches.

[0010] The source trench comprises a plurality of levels of trenches, and a lower level of the plurality of levels of trenches has a smaller width than an upper level of the plurality of levels of trenches.

[0011] Further, the upper surface of the active pillar is sequentially provided with a first doping type doping layer and a source ohmic contact.

[0012] The surface of the side wall of the gate trench is sequentially provided with a first implantation region of a second doping type and a gate dielectric layer, and the bottom of the gate trench is sequentially provided with the first implantation region and a gate ohmic contact; the upper surface of the gate ohmic contact is sequentially provided with a metal layer, a first isolation layer and a second isolation layer; the bottom surface of the first doping type doping layer is lower than the top surface of the gate dielectric layer; the surface of the side wall of the source trench is sequentially provided with the second implantation region and a source dielectric layer, and the bottom of the source trench is sequentially provided with the second implantation region and a source ohmic contact.

[0013] Further, the upper surface of the source ohmic contact is sequentially provided with the metal layer, the first isolation layer and the second isolation layer.

[0014] A pressure block metal is arranged on the surface of the second isolation layer and the source ohmic contact.

[0015] Further, the upper surface of the source ohmic contact, the second isolation layer and the source ohmic contact is provided with a pressure block metal.

[0016] According to the technical scheme of the transistor device, a manufacturing method of the transistor device is also provided, comprising the following steps:

[0017] S100: epitaxially growing a first doping type buffer layer and a first doping type drift layer on a first doping type substrate;

[0018] S200: implanting a first doping type doping layer in an active region on the surface of the first doping type drift layer, forming a dielectric mask on the surface of the first doping type doping layer, forming an active pillar and a gate trench between the active pillars by etching, implanting a second doping type first implantation region in the bottom and the side wall of the gate trench;

[0019] S300: Masking the first doping type doping layer, the first implantation region on the side wall of the gate trench and the first implantation region partially on the bottom of the gate trench, removing the first implantation region on the bottom of the gate trench which is not needed to be masked, and further etching to obtain a source trench, wherein both sides of the source trench are the gate trenches, one of the two sides of the gate trench is the gate trench and the other is the source trench, or both sides of the gate trench are the gate trenches.

[0020] Further, it further comprises:

[0021] S400: Ion implantation of the second doping type on the bottom and side wall of the source trench to form a second implantation region of the second doping type, and the junction depth of the second implantation region is greater than the junction depth of the first implantation region, masking the side wall and part of the bottom of the source trench, removing the second dielectric layer on the bottom which is not needed to be masked, and further etching to obtain a primary trench; repeating the above steps to obtain a multi-stage trench.

[0022] S500: Removing all masks, forming a gate dielectric layer on the side wall of the gate trench and a source dielectric layer on the side wall of the source trench; forming a gate ohmic contact on the bottom of the gate trench and a source ohmic contact on the bottom of the source trench, and forming a source ohmic contact on the surface of the first doping type doping layer.

[0023] Further, it further comprises:

[0024] S600: Forming a metal layer on the gate ohmic contact and the source ohmic contact; forming a first isolation layer on the metal layer, forming a second isolation layer on the first isolation layer and filling the gate trench and the source trench;

[0025] S700: Forming a pressure block metal on the surface of the second isolation layer and the source ohmic contact.

[0026] Further, it further comprises:

[0027] S600: Masking the source trench, forming a metal layer on the gate ohmic contact; forming a first isolation layer on the metal layer, forming a second isolation layer on the first isolation layer and filling the gate trench;

[0028] S700: Removing the mask of the source trench, forming a pressure block metal on the surface of the source ohmic contact, the second isolation layer and the source ohmic contact.

[0029] According to the above technical scheme of the transistor device, a power module is also provided, comprising: at least one semiconductor device as described above;

[0030] A substrate for carrying the semiconductor device.

[0031] According to the technical scheme of the transistor device above, a power conversion circuit is further provided, the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction.

[0032] The power conversion circuit comprises a circuit board and at least one semiconductor device as described above, and the semiconductor device is electrically connected with the circuit board.

[0033] According to the technical scheme of the transistor device above, a vehicle is further provided, comprising a load and a power conversion circuit as described above, the power conversion circuit is used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current, or converting direct current into alternating current, and then inputting to the load.

[0034] Compared with the prior art, the present application has the following beneficial effects:

[0035] Firstly, the present application shifts the avalanche breakdown position from the edge of the gate P+ region of the traditional JFET to the edge of the drift layer source P+ region by optimizing the distribution and depth of the gate trench and the source trench in the device structure, avoids the avalanche current flowing through the gate, thereby protecting the gate drive control chip from damage, significantly enhancing the avalanche reliability of the device, and meeting the demand of the power electronic system for high reliability devices.

[0036] Secondly, the array arrangement of the active column structure of the present application cooperates with the multi-stage trench design, increases the current conduction cross-sectional area, reduces the obstruction of current flow, effectively reduces the on-resistance of the device, and improves the efficiency of the device in the large current working scenario.

[0037] Thirdly, the present application forms a multi-stage trench through step-by-step etching and ion implantation, can accurately control the size and doping topography of the trench, makes the device still maintain the uniformity of performance when arranged in a large area array, and improves the yield of finished products.

[0038] The present application will be explained in detail below in combination with the drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 SiC JEFT device structure schematic diagram of the multi-stage trench of the present application

[0040] Figure 2 SiC JEFT device structure schematic diagram of another gate-source trench distribution multi-stage trench of the present application

[0041] Figure 3 Schematic diagram of sequentially growing buffer layer and epitaxial layer structure on the substrate in the embodiment of the present application

[0042] Figure 4 Schematic diagram after completing trench etching in embodiment 1 of the present application

[0043] Figure 5 Schematic diagram of completing ion doping of second doping type at bottom and sidewall of trench in embodiment 1 of the present application

[0044] Figure 6 Schematic diagram of completing ohmic contact of source region and gate region in embodiment 1 of the present application

[0045] Figure 7 Schematic diagram of structure of completing metal layer and isolation medium layer in gate trench in embodiment 1 of the present application

[0046] Figure 8 Schematic diagram of completing chip manufacturing in embodiment 1 of the present application

[0047] Figure 9 Schematic diagram of structure of completing chip manufacturing in embodiment 3 of the present application

[0048] Figure 10 Flow chart of the present application.

[0049] In the figure: 100, first doping type substrate; 101, first doping type buffer layer; 102, first doping type drift layer; 102a, first active column; 102b, second active column; 103, first doping type doping layer; 104a, first injection region; 104b, second injection region; 21, gate trench; 22, source trench; 201a, gate medium layer; 201b, source medium layer; 301, gate ohmic contact; 302, source ohmic contact; 303, source ohmic contact; 400, metal layer; 500, first isolation layer; 600, second isolation layer; 700, briquetting metal. DETAILED DESCRIPTION

[0050] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings, in which several embodiments of the present application are given, but the present application can be realized in different forms and is not limited to the embodiments described in the text, on the contrary, these embodiments are provided to make the disclosed content of the present application more thorough and comprehensive.

[0051] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there can be a middle element, and when an element is referred to as being "connected" to another element, it can be directly connected to the other element or there can be a middle element, the terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for illustrative purposes.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. The use herein of the terms "and / or" and "at least one of" includes any and all combinations of one or more of the associated listed items.

[0053] As shown in Figure 1 Specific embodiments 1 provide a transistor device and manufacturing method, power module, power conversion circuit, device structure, the transistor device includes a first doped type substrate 100, a first doped type buffer layer 101 and a first doped type drift layer 102 which are stacked in sequence;

[0054] An array of active pillars is arranged in the first doped type drift layer 102, the top surface of the active pillars is flush with the top surface of the first doped type drift layer 102; the active pillars include first active pillars 102a and second active pillars 102b, gate trenches 21 are between the first active pillars 102a, source trenches 22 are between the second active pillars 102b, the depth of the source trenches 22 is greater than the depth of the gate trenches 21;

[0055] Both sides of the source trenches 22 are the gate trenches 21, one of the two sides of the gate trenches 21 is the gate trench 21 and the other is the source trench 22. By making the depth of the source trenches 22 greater than the depth of the gate trenches 21, the maximum electric field in the off state is constrained at the junction edge of the second type doped region at the bottom of the source trenches 22, effectively avoiding the concentration of high electric field in the gate region, thereby improving the voltage withstand capability and reliability of the device. This structure design makes the avalanche breakdown occur far away from the gate region, reducing the risk of avalanche current passing through the gate. At the same time, this structure can be realized by two-step etching under the same photolithography mask, simplifying the process flow.

[0056] Preferably, the depth of the source trenches 22 is greater than the depth of the gate trenches 21, so that the maximum electric field in the off state is at the junction edge of the second type doped region at the bottom of the source trenches 22.

[0057] Preferably, the bottom of the source trenches 22 is a multi-stage trench structure composed of multiple stepped trenches, second type doped ions are simultaneously implanted under the multi-stage trenches, forming a stepped P + region, which can disperse the concentration of electric field and improve the robustness of avalanche.

[0058] Preferably, the top of the mesa is a source ohmic contact 303 of the source region, the bottom of the source trench 22 is a source ohmic contact 302 of the source region, and the source ohmic contact 303 on the top of the mesa and the source ohmic contact 302 on the bottom of the source trench 22 are in electrical communication. The bottom of the gate trench 21 is a gate ohmic contact 301 of the gate region. The double-path conduction design (top of the mesa + bottom of the trench) effectively reduces the series resistance of the source region, and the source ohmic contact 302 on the bottom of the source trench 22 directly collects avalanche current, avoiding the current crowding effect in the traditional structure and improving the dynamic conduction characteristics. The source ohmic contact 303 and the source ohmic contact 302 are formed synchronously by a self-alignment process, eliminating the alignment error of the traditional step-by-step process and improving the process stability.

[0059] Preferably, the source ohmic contact 303 on the top of the mesa, the source ohmic contact 302 on the bottom of the source trench 22, and the gate ohmic contact 301 on the bottom of the gate trench 21 are formed simultaneously by a self-alignment process. The distance between the synchronously formed gate ohmic contact 301 and the source ohmic contact 302 is accurately controllable, effectively reducing the gate-source capacitance and switching loss. This process avoids short circuit defects caused by multiple photolithography alignments, improving production yield. Thermal annealing synchronously forms all ohmic contacts 301, 302, 303, improving the temperature characteristics of the contact resistance.

[0060] Preferably, there is a gate dielectric layer 201a on both sides of the inner sidewall of the gate trench 21, which protects the sidewall of the trench from forming an ohmic contact when the ohmic contact is formed on the bottom of the mesa and the gate trench 21, thereby avoiding gate-source short circuit on the sidewall of the trench.

[0061] Preferably, there is a metal layer 400 on the gate ohmic contact 301 on the bottom of the gate trench 21, which can effectively reduce the resistance of the entire gate.

[0062] Preferably, the gate ohmic contact 301 in the gate trench 21 and the source ohmic contact 303 on the mesa are isolated by a dielectric first isolation layer 500 and a second isolation layer 600, ensuring that the gate and the source are not short-circuited.

[0063] Preferably, the gate trenches 21 and the source trenches 22 are distributed in a certain proportion, and the number of gate trenches 21 is greater than or equal to that of source trenches 22. The N region between the two gate trenches 21 and the N-type region between the gate trench 21 and the source trench 22 are both conductive channels, which can be controlled by the gate voltage.

[0064] Specific embodiment 2 differs from embodiment 1 in that both sides of the gate trench 21 are gate trenches 21.

[0065] As shown in Figures 3-6 The present application also provides a manufacturing method of a transistor device, comprising:

[0066] Epitaxial growth of a first doped type buffer layer 101 and a first doped type drift layer 102 on a first doped type substrate 100. The concentration and thickness of the drift layer is determined by the breakdown voltage of the device design.

[0067] Further, a first doped type doping layer 103 is formed by implantation on the surface of the active region.

[0068] A dielectric mask 10 is formed on the surface. SiC surface is etched by plasma method to form SiC gate trench 21. Second type doping ion implantation is performed by vertical implantation and angle implantation to form second type doping first implantation region 104a on the bottom and sidewall of the gate trench 21 without dielectric mask on the active region. The region of the first doped type drift layer 102 between two gate trenches 21 forms a controllable conductive channel first active pillar 102a. The conductive channel can be depleted or turned on by applying a certain voltage between the gate and the source, thus achieving the control of the turn-off and turn-on of the device.

[0069] The mask is removed, RCA cleaning is performed, and a dielectric mask is formed on the surface. SiC surface is etched by plasma method to form source trench 22. The depth of the source trench 22 is greater than or equal to that of the gate trench 21.

[0070] Anisotropic etching of the dielectric layer is performed to etch away the dielectric on the bottom of the trench while retaining the dielectric on the sidewall as a protective layer for multi-stage trench etching. Plasma etching is performed to form a second stage trench on the bottom of the trench. In this way, a multi-stage trench can be formed. The thickness of the dielectric layer is determined by the width of the second stage trench. Second type doping ion implantation is performed by vertical implantation and angle implantation to form second type doping second implantation region 104b on the bottom and sidewall of the source trench 22. The region of the first doped type drift layer 102 between the gate trench 21 and the source trench 22 forms a controllable conductive channel second active pillar 102b. The conductive channel can be depleted or turned on by applying a certain voltage between the gate and the source, thus achieving the control of the turn-off and turn-on of the device.

[0071] All dielectric masks are removed, and the wafer is cleaned by RCA and buffer HF solvent. A thin layer of carbon film is isotropically deposited on the surface, including the mesa and the trench, and then high-temperature annealing is performed to activate the implanted ions, forming a high-efficiency doping. The annealing temperature is above 1500°C.

[0072] The wafer is cleaned by RCA. Sacrificial oxidation process is performed, i.e., thermal oxidation is performed first, and then acid is used for removal. Since the thermal oxidation rate of silicon carbide is relatively low, high-temperature thermal oxidation is required, and the thermal oxidation temperature is preferably greater than or equal to 1100°C. The sacrificial oxidation process can effectively remove or reduce the damage layer and roughness of the sidewall caused by etching.

[0073] A thermal oxidation process is performed to grow a dense thin oxide layer on the SiC surface, further reducing sidewall defects and protecting the sidewalls.

[0074] An isotropically deposited dielectric layer, such as SiO2, is then anisotropically etched away from the top of the mesa and the bottom of the trench, while retaining the dielectric on the sidewalls. This forms a gate dielectric layer 201a on the sidewalls of the gate trench 21 and a source dielectric layer 201b on the sidewalls of the source trench 22.

[0075] A metal layer is deposited and thermally annealed so that the metal at the top of the mesa and the bottom of the trench reacts with the SiC to form an ohmic contact, while the metal does not react with the dielectric on the sidewalls. An acid solution is used to selectively remove the metal on the sidewalls, leaving the ohmic contact metal after the reaction. Annealing is performed again at a higher annealing temperature than the previous temperature to further improve the ohmic contact. A gate ohmic contact 301 is formed at the bottom of the gate trench 21, a source ohmic contact 302 is formed at the bottom of the source trench 22, and a source ohmic contact 303 is formed on the top of the mesa.

[0076] Metal is deposited and etched back to form a metal layer 400 on the bottom ohmic contact metal in the gate trench 21 and the source trench 22. The metal layer 400 in the gate trench 21 helps reduce the gate resistance of the chip, and the metal layer 400 in the source trench 22 helps reduce the resistance of the avalanche current from the bottom of the source trench 22 to the source.

[0077] A dielectric is deposited and etched back to form a first isolation layer 500 on the metal in the gate trench 21 and the source trench 22. The first isolation layer 500 in the gate trench 21 isolates the gate and source, and also reduces the difficulty of subsequent dielectric filling of the trench.

[0078] like Figure 8 As shown, a second dielectric isolation layer 600 is deposited to fill the trench, and a portion of the dielectric on the mesa is selectively removed using photolithography and etching, exposing the source ohmic contact 303 metal in the middle of the mesa. The second isolation layer 600 further isolates the gate and source. Source and gate metal blocks 700 are deposited and etched for electrical connection to external circuits in chip applications. A dielectric layer is then deposited and etched to form a passivation layer, followed by a polyimide protective layer.

[0079] The back of the wafer is thinned to remove most of the substrate and retain only part of the supporting layer to further reduce the resistance of the substrate. Metal is deposited and laser annealed to form an ohmic contact. A thick block metal 800 is then made on the back of the wafer for electrical connection with the external circuit.

[0080] Preferably, the heavily doped first-doping type doped layer 103 at the top of the mesa overlaps to a certain extent with the gate dielectric layer 201a on the sidewall of the gate trench 21. That is, the bottom of the heavily doped first-doping type doped layer 103 at the top of the mesa is lower than the highest point of the gate dielectric layer 201a on the sidewall of the gate trench 21. This prevents simultaneous ohmic contact between the first-doping type doped layer 103 at the top of the mesa and the second-doping type first implanted region 104a on the sidewall, thereby preventing a short circuit between the source and the gate.

[0081] Preferably, the first active pillar 102a and the second active pillar 102b in the conductive channel region between the two trenches are subjected to ion implantation of the first type of doping to increase the doping concentration of the conductive channel, thereby further reducing the on-resistance.

[0082] like Figure 9 As shown. The device structure of the specific embodiment 3 of the present application is similar to that of the embodiment 1. The difference from the embodiment 1 is that the structure inside the source trench 22 is inconsistent with the gate trench 21. The block metal 700 fills the source trench 22 and is directly connected to the source ohmic contact 302 inside the source trench 22, which can further reduce the on-resistance between the bottom of the source trench 22 and the source. The device preparation method is similar to that of the embodiment 1. The difference from the embodiment 1 is that after the ohmic contact process is completed for the source trench 22 and the gate trench 21 at the same time, the process of the source trench 22 and the gate trench 21 are separated. The structure inside the gate trench 21 is completed first. Before making the metal pad, the source trench 22 is opened and the source trench 22 is filled at the same time when the block metal 700 is deposited.

[0083] The present application also provides a power module comprising: at least one semiconductor device as described above;

[0084] A substrate is used to carry the semiconductor device.

[0085] The present application also provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction;

[0086] The power conversion circuit includes a circuit board and at least one semiconductor device as described above, wherein the semiconductor device is electrically connected to the circuit board.

[0087] The present application also provides a vehicle comprising: a load and the power conversion circuit as described above, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0088] The application is described above by way of example with reference to the accompanying drawings, and it is obvious that the specific implementation of the application is not limited to the above-described manner, and as long as such non-essential improvements are made by adopting the method concept and technical solutions of the application, or the concept and technical solutions of the application are directly applied to other occasions without improvement, they are all within the protection scope of the application.

Claims

1. A transistor device, characterized in that include: A first doping type substrate (100), a first doping type buffer layer (101) and a first doping type drift layer (102) stacked in sequence; Active columns arranged in an array are provided in the first doping type drift layer (102), and the top surfaces of the active columns are flush with the top surface of the first doping type drift layer (102); the active columns include a first active column (102a) and a second active column (102b), a gate trench (21) is provided between the first active columns (102a), a gate trench (21) is provided between the second active column (102b) and the first active column (102a), and a source trench (22) is provided between the second active columns (102b), and the depth of the source trench (22) is greater than the depth of the gate trench (21); Both sides of the source trench (22) are the gate trench (21), one of the two sides of the gate trench (21) is the gate trench (21) and the other is the source trench (22), or both sides of the gate trench (21) are the gate trench (21).

2. The transistor device according to claim 1, wherein: The number ratio of the gate trenches (21) is greater than or equal to that of the source trenches (22); The source trench (22) comprises a multi-level trench, wherein the width of a lower-level trench in the multi-level trench is smaller than the width of an upper-level trench.

3. The transistor device according to claim 1, wherein: The upper surface of the active column is sequentially provided with a first doping type doping layer (103) and a source ohmic contact (303); The surface of the side wall of the gate trench (21) is sequentially provided with a first injection region (104a) of a second doping type and a gate dielectric layer (201a); the bottom of the gate trench (21) is sequentially provided with the first injection region (104a) and a gate ohmic contact (301); the upper surface of the gate ohmic contact (301) is sequentially provided with a metal layer (400), a first isolation layer (500) and a second isolation layer (600); the bottom surface of the first doping type doping layer (103) is lower than the top surface of the gate dielectric layer (201a); The second injection region (104b) and the source dielectric layer (201b) are sequentially provided on the surface of the sidewall of the source trench, and the second injection region (104b) and the source ohmic contact (302) are sequentially provided on the bottom of the source trench.

4. The transistor device according to claim 3, wherein: The metal layer (400), the first isolation layer (500) and the second isolation layer (600) are sequentially provided on the upper surface of the source ohmic contact (302); A pressing block metal (700) is provided on the surface of the second isolation layer (600) and the source ohmic contact (303).

5. The transistor device according to claim 3, wherein: A pressing block metal (700) is provided on the upper surfaces of the source ohmic contact (302), the second isolation layer (600), and the source ohmic contact (303) at the bottom of the trench.

6. A method for manufacturing a multi-level trench SiC junction field effect transistor, applied to the transistor device according to any one of claims 1 to 5, characterized in that: The following steps are involved: S100: epitaxially growing a first doping type buffer layer (101) and a first doping type drift layer (102) on a first doping type substrate (100); S200: implanting a first doping type doping layer (103) into an active region on a surface of a first doping type drift layer (102), forming a dielectric mask (10) on a surface of the first doping type doping layer (103), forming active pillars (102a, 102b) and a gate trench (21) located between the active pillars (102a, 102b) by etching, and implanting a second doping type ion into a bottom and sidewall of the gate trench (21) to form a second doping type first implantation region (104a); S300: Masking the first doping type doping layer (103), the first injection region (104a) located on the sidewall of the gate trench (21), and a portion of the first injection region (104a) located at the bottom of the gate trench (21), removing the first injection region (104a) at the bottom of the gate trench (21) that does not require masking, and further etching to obtain a source trench (22), wherein both sides of the source trench (22) are the gate trench (21), one of the two sides of the gate trench (21) is the gate trench (21) and the other is the source trench (22), or both sides of the gate trench (21) are the gate trench (21).

7. The method for manufacturing a multi-level trench SiC junction field effect transistor according to claim 6, characterized in that: Also includes: S400: performing ion implantation of a second doping type on the bottom and sidewalls of the source trench (22) to form a second implantation region (104b) of the second doping type, wherein the junction depth of the second implantation region (104b) is greater than the junction depth of the first implantation region (104a), masking is performed on the sidewalls and a portion of the bottom of the source trench (22), removing the second dielectric layer at the bottom that does not require masking, and further etching to obtain a primary trench; Repeat the above steps to obtain multi-level grooves; S500: removing all masks, forming a gate dielectric layer (201a) on the sidewall of the gate trench, forming a source dielectric layer (201b) on the sidewall of the source trench; forming a gate ohmic contact (301) at the bottom of the gate trench, forming a source ohmic contact (302) at the bottom of the source trench, and forming a source ohmic contact (303) on the surface of the first doping type doping layer (103).

8. The method for manufacturing a multi-level trench SiC junction field effect transistor according to claim 7, characterized in that: Also includes: S600: forming a metal layer (400) on both the gate ohmic contact (301) and the source ohmic contact (302); forming a first isolation layer (500) on the metal layer (400); forming a second isolation layer (600) on the first isolation layer (500) and filling the gate trench and the source trench; S700: forming a compact metal (700) on the surface of the second isolation layer (600) and the source ohmic contact (303).

9. The method for manufacturing a multi-level trench SiC junction field effect transistor according to claim 7, wherein: Also includes: S600: masking the source trench and forming a metal layer (400) on the gate ohmic contact (301); forming a first isolation layer (500) on the metal layer (400), and forming a second isolation layer (600) on the first isolation layer (500) and filling the gate trench; S700: removing the mask of the source trench, and forming a compression block metal (700) on the upper surface of the source ohmic contact (302), the second isolation layer (600), and the source ohmic contact (303).

10. Power module, characterized by , comprising: at least one semiconductor device according to any one of claims 1 to 5; A substrate is used to carry the semiconductor device.

11. Power conversion circuit, characterized in that , the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board.

12. Vehicle, characterized in that , comprising: a load and the power conversion circuit according to claim 11, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load.

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