Method for drying display panel and apparatus for drying display panel

Abstract

A method for drying a display panel and an apparatus for drying a display panel are provided. The method for drying a display panel includes: providing a display panel including a first light emitting element, a second light emitting element, and a third light emitting element on a stage including a thermal heater; providing an infrared heater on the objective table; providing an infrared blocking mask between the display panel and the infrared heater; and baking at least one of the first light-emitting element and the second light-emitting element and the third light-emitting element at different baking temperatures by the thermal heater and the infrared heater.

Description

Technical Field

[0001] Embodiments relate to a method for drying a display panel and an apparatus for drying a display panel, and more particularly, to a drying method and an apparatus for forming pixels of a light-emitting display panel. Background Art

[0002] Liquid crystal displays (LCDs), emissive display devices, and the like are used as display devices for displaying images. A liquid crystal display is a display device that includes a backlight unit and displays images by blocking or transmitting light emitted from the backlight unit. For example, an emissive display device is a display device that has recently attracted attention. Unlike LCDs, emissive display devices have self-luminous properties, so they do not require a separate light source.

[0003] The display device may include a display panel that provides a screen for displaying an image. For example, an emissive display device may include a light-emitting display panel, and a plurality of pixels may be arranged on the light-emitting display panel. Each pixel may be implemented as a light-emitting element. When manufacturing the light-emitting display panel, various processes may be performed, such as a process of depositing various materials on a substrate, or a heat treatment process, as well as a drying process and a baking process. The heat treatment process may be performed to induce physical or chemical changes in the material to form a layer or film with desired properties, or to remove a carrier liquid. Summary of the Invention

[0004] Typical heat treatment processes apply the same temperature to the entire object being heated, and it can be difficult to provide differentiated temperatures for each pixel, which is a delicate area in a display panel. Accordingly, if the applied temperature differs depending on the color of the pixel, the heat treatment process may be divided into multiple steps, increasing manufacturing time and costs.

[0005] Embodiments are directed to providing a method for drying a display panel and an apparatus for drying a display panel, which provide different baking temperatures for pixels of different colors.

[0006] However, the embodiments are not limited to those described herein. The above and other embodiments will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0007] According to an embodiment, a method for drying a display panel includes: providing a display panel including a first light-emitting element, a second light-emitting element, and a third light-emitting element on a stage including a thermal heater; providing an infrared heater on the stage; providing an infrared blocking mask between the display panel and the infrared heater; and baking at least one of the first light-emitting element and the second light-emitting element and the third light-emitting element at different baking temperatures by the thermal heater and the infrared heater.

[0008] The infrared blocking mask may include infrared transmitting holes at positions corresponding to the first and second light emitting elements, and may include an infrared blocking layer at a position corresponding to the third light emitting element.

[0009] The thermal heater may apply heat to the first light emitting element, the second light emitting element, and the third light emitting element, and the infrared heater may apply heat to the first light emitting element and the second light emitting element through the infrared transmission hole.

[0010] The infrared blocking layer may include at least one of an infrared reflecting layer and an infrared absorbing layer.

[0011] The baking temperature for the third light-emitting element may be lower than the baking temperatures for the first and second light-emitting elements.

[0012] The first light emitting element, the second light emitting element, and the third light emitting element may each include one of an organic emission layer, a quantum dot light emitting layer, and an organic light emitting-quantum dot light emitting layer.

[0013] The first and second light emitting elements may include quantum dot light emitting layers, and the third light emitting element may include an organic emission layer.

[0014] The method may further include setting the temperature of the heat provided by the thermal heater to be lower than the temperature of the heat provided by the infrared heater.

[0015] Providing the infrared blocking mask may include installing the infrared blocking mask directly below the infrared heater or directly above the display panel.

[0016] The first light emitting element, the second light emitting element, and the third light emitting element may emit light of different colors.

[0017] According to another embodiment, a method for drying a display panel includes: providing a display panel including a first light-emitting element, a second light-emitting element, and a third light-emitting element on a stage including a thermal heater; providing an infrared blocking mask on the stage; providing an infrared heater on the infrared blocking mask; and baking at least one of the first light-emitting element, the second light-emitting element, and the third light-emitting element at different temperatures by the thermal heater and the infrared heater, wherein the thermal heater applies heat to the first light-emitting element, the second light-emitting element, and the third light-emitting element, and the infrared heater applies heat to at least one of the first light-emitting element, the second light-emitting element, and the third light-emitting element due to the infrared blocking mask.

[0018] The infrared blocking mask may include an infrared blocking layer at a position corresponding to one or more of the first light emitting element, the second light emitting element, and the third light emitting element.

[0019] The infrared blocking layer may include at least one of an infrared reflecting layer and an infrared absorbing layer.

[0020] The method may further include setting the temperature of the heat provided by the thermal heater to be lower than the temperature of the heat provided by the infrared heater.

[0021] The method may further include installing an infrared blocking mask directly below the infrared heater or directly above the display panel.

[0022] The infrared blocking mask may be formed using at least one of a photolithography process and an inkjet process.

[0023] The drying apparatus of the display panel according to the embodiment includes: a drying chamber; a stage disposed in the drying chamber and including a thermal heater; an infrared blocking mask disposed on the stage; and an infrared heater disposed on the infrared blocking mask.

[0024] The infrared blocking mask may include an infrared blocking layer and infrared transmitting holes.

[0025] The infrared blocking layer may include at least one of an infrared reflecting layer and an infrared absorbing layer.

[0026] An infrared blocking mask may be provided directly below the infrared heater.

[0027] According to the embodiment, a method of drying pixels of different colors at different baking temperatures can be provided by a thermal heater, an infrared heater, and an infrared reflection-absorption mask. Accordingly, the manufacturing time of the display panel can be shortened and the cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of a drying apparatus according to an embodiment.

[0029] Figure 2 is a flow chart of a drying method according to an embodiment.

[0030] Figure 3 is a process diagram schematically illustrating a mask manufacturing process according to an embodiment.

[0031] Figure 4 is a process diagram schematically illustrating a mask manufacturing process according to another embodiment.

[0032] Figure 5 is a schematic cross-sectional view of a display panel according to an embodiment.

[0033] Figure 6 is a schematic cross-sectional view of a display panel according to another embodiment.

[0034] Figure 7 is a schematic cross-sectional view of a display panel according to yet another embodiment. DETAILED DESCRIPTION

[0035] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed herein. However, it is apparent that various embodiments can be put into practice without these specific details or with one or more equivalent arrangements. Here, various embodiments are not necessarily exclusive and do not necessarily limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment can be used or implemented in another embodiment.

[0036] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0037] The use of cross hatching and / or shading is generally provided in the accompanying drawings to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or demand for a particular material, material properties, size, ratio, commonality between the illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiments can be implemented differently, a specific processing sequence can be performed in a sequence different from that described. For example, the processing of two consecutive descriptions can be performed substantially simultaneously or in an order opposite to that described. In addition, the same reference numerals refer to the same elements.

[0038] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or coupled to the other element or layer, or there can be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there can be no intervening element or layer. For this reason, the term "connected" can refer to physical connection, electrical connection and / or fluid connection, and with or without intervening elements. For the purposes of this disclosure, "at least one of A and B" can be understood to mean only A, only B or any combination of A and B. In addition, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as only X, only Y, only Z or any combination of two or more of X, Y and Z. As used herein, the term "and / or" includes any and all combinations of one or more relevant listed items.

[0039] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure.

[0040] For descriptive purposes, spatially relative terms such as "below," "beneath," "below," "above," "above," "above," and "side" (e.g., as in "sidewall") may be used herein to describe the relationship between one element and another element(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as being "below" or "beneath" other elements or features would subsequently be oriented as being "above" the other elements or features. Thus, the term "below" can encompass both above and below orientations. Furthermore, the device can be oriented otherwise (e.g., rotated 90 degrees or in other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0041] As used herein, the term is for describing the purpose of a particular embodiment and is not intended to limit. Unless the context clearly indicates otherwise, the "one", "an" and "the (described)" in the singular as used herein are intended to also include plural forms. In addition, when used in this specification, the terms "comprising", "comprising", "including" and / or "comprising" specify the existence of the described features, integral bodies, steps, operations, elements, parts and / or their groups, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms, and not as terms of degree, and as such, are used to explain the inherent deviation in the measured values, calculated values ​​and / or provided values ​​that those of ordinary skill in the art will recognize.

[0042] Various embodiments are described herein with reference to cross-sectional and / or exploded views that are schematic illustrations of embodiments and / or intermediate structures. As such, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments disclosed herein should not necessarily be construed as limited to the specific illustrated shapes of the regions, but rather are to include deviations in shape due to, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not necessarily reflect the actual shapes of the regions of the device, and as such, are not necessarily intended to be limiting.

[0043] Figure 1 is a schematic diagram of a drying apparatus according to an embodiment.

[0044] refer to Figure 1The drying device 1 according to the embodiment can be used to dry the layers (e.g., light-emitting layers) that make up the pixels of a display panel. For example, an inkjet process can be used to form the layers of the pixels, and the drying device 1 can bake the layers of the light-emitting element to a selected temperature. In addition, the scope of the present disclosure extends to all processes for manufacturing thin films using inks, such as all processes for manufacturing printed OLEDs, solar cells, sensors, and quantum dot (QD) filters.

[0045] For better understanding and ease of description, Figure 1 In the embodiment, the display panel DP suitable for the drying device 1 is shown to include a substrate SUB, a circuit element layer CL and a light emitting element layer EL. Figures 5 to 7 The structure of the display panel DP according to the embodiment will be described.

[0046] The circuit element layer CL and the light emitting element layer EL may be provided on the substrate SUB. The circuit element layer CL may include a semiconductor layer ACT for driving the light emitting layer. The light emitting element layer EL may be provided on the circuit element layer CL. The light emitting element layer EL may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3 that emit light of different colors. For example, the first light emitting element ED1 may emit red light, the second light emitting element ED2 may emit green light, and the third light emitting element ED3 may emit blue light. The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may correspond to a red light emitting area RLA, a green light emitting area GLA, and a blue light emitting area BLA, respectively (refer to FIG. 1 ). Figures 5 to 7 ), or red pixels, green pixels, and blue pixels. The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may include a quantum dot light-emitting layer including quantum dots, or may include an organic emission layer including an organic material. Each of the light-emitting elements ED1, ED2, and ED3 may be an organic light-emitting element or a quantum dot light-emitting element. Figures 5 to 7 The specific configuration of each component layer is described in .

[0047] The drying device 1 can bake each light emitting element, or bake light emitting elements of a specific color at a temperature different from light emitting elements of other colors. The drying device 1 can include a drying chamber 10 and a stage 100, a clamper 200, an infrared heater 210 and an infrared blocking mask 220 arranged in the drying chamber 10.

[0048] The drying chamber 10 may load the display panel DP that has undergone the inkjet process so as to perform a baking process on the display panel DP. The stage 100, the thermal heater 110, the clamper 200, the infrared heater 210, and the infrared blocking mask 220 may be disposed in the drying chamber 10.

[0049] The stage 100 may support the display panel DP during the baking process. The stage 100 may be a tray or a chuck for the display panel. The stage 100 may be implemented to move up and down to adjust the distance from the infrared heater 210.

[0050] In the case where the substrate SUB includes a plastic material, a carrier substrate made of glass or the like may be provided between the thermal heater 110 and the substrate SUB. The carrier substrate may prevent the plastic material of the substrate SUB from being directly heated and changing characteristics of the substrate SUB.

[0051] The stage 100 may include a thermal heater 110. The thermal heater 110 may be arranged in contact with or close to the upper surface of the stage 100 and may heat the display panel DP mounted on the stage 100. The thermal heater 110 may heat the entire display panel DP disposed on the stage 100. The thermal heater 110 may be set to an appropriate temperature to remove the solvent from the ink on the display panel DP. For example, the selected temperature of the thermal heater 110 may be adjusted to be consistent with the organic emission layer having a relatively lower baking temperature than the quantum dot light-emitting layer.

[0052] The clamp 200 can be fixedly or movably arranged at a selected position within the drying chamber 10. In the case where the display panel DP is mounted on the stage 100, the clamp 200 can be arranged on the upper portion of the display panel DP. The clamp 200 can clamp the infrared heater 210 and can be moved up and down to adjust the distance from the stage 100 or the display panel DP mounted on the stage 100. The clamp 200 can be moved left and right to align with the stage 100 or the display panel DP mounted on the stage 100.

[0053] The holder 200 can fix the infrared heater 210 at a selected position. The holder 200 can be fixed in the drying chamber 10 or be movably set in the drying chamber 10. The infrared heater 210 can be set to contact the lower surface of the holder 200 or be arranged close to the lower surface of the holder 200. The infrared heater 210 can linearly apply heat to the display panel DP with infrared rays at multiple positions between the display panel DP and the holder 200.

[0054] The infrared heater 210 can be set to an appropriate temperature to remove the solvent from the ink on the display panel DP. For example, the selected temperature of the infrared heater 210 can be set to a temperature higher than the temperature of the thermal heater 110, consistent with the quantum dot light-emitting layer having a relatively higher baking temperature than the organic emission layer. The infrared rays emitted by the infrared heater 210 can be partially blocked by the infrared blocking mask 220 disposed below the infrared heater 210.

[0055] The infrared blocking mask 220 may be disposed below the infrared heater 210. The infrared blocking mask 220 may be disposed in contact with the bottom (or lower surface) of the infrared heater 210 or close to the lower surface of the infrared heater 210, and may partially block infrared rays emitted from the infrared heater 210 at multiple locations between the display panel DP and the infrared heater 210. For example, the infrared blocking mask 220 may be mounted on a bracket disposed between the display panel DP and the infrared heater 210, but the scope of the present disclosure is not limited thereto. For example, the infrared blocking mask 220 may be implemented to move up and down to adjust the distance from the display panel DP and the infrared heater 210.

[0056] The infrared blocking mask 220 may include a glass substrate 221 (refer to Figures 3 and 4 ), infrared blocking layer 222 and infrared transmission hole 223. The infrared blocking mask 220 may have a structure in which the infrared blocking layer 222 and the infrared transmission hole 223 are formed on a glass substrate 221. The infrared blocking layer 222 may be a reflective layer (222-1, refer to Figure 3 ) or an absorbing layer for absorbing infrared rays (222-2, reference Figure 3 ).

[0057] An infrared blocking layer 222 may be formed at a position corresponding to the third light-emitting element ED3. The infrared blocking layer 222 may overlap the third light-emitting element ED3. The infrared blocking layer 222 may block infrared rays emitted from the infrared heater 210 from reaching the third light-emitting element ED3, thereby preventing the baking temperature of the light-emitting layer in the third light-emitting element ED3 from increasing. However, the embodiment is not limited thereto, and the infrared blocking layer 222 may also be formed at a position corresponding to the first light-emitting element ED1 or the second light-emitting element ED2 in addition to the third light-emitting element ED3 to block infrared rays.

[0058] The infrared transmission hole 223 may be a region in which the infrared blocking layer 222 is not formed. The infrared transmission hole 223 may be formed at a position corresponding to the first light emitting element ED1 and the second light emitting element ED2. The infrared transmission hole 223 may overlap with the first light emitting element ED1 and the second light emitting element ED2. The infrared transmission hole 223 may transmit infrared rays emitted from the infrared heater 210, and may allow the infrared rays to reach the first light emitting element ED1 and the second light emitting element ED2, so that the baking temperature of the light emitting layer in the first light emitting element ED1 and the second light emitting element ED2 may be increased. However, the embodiment is not limited thereto, and in addition to the first light emitting element ED1 and the second light emitting element ED2, the infrared transmission hole 223 may also be formed at a position corresponding to the third light emitting element ED3, so that the infrared rays may reach the third light emitting element ED3. Reference will be made later Figure 3 and Figure 4 Information related to a method of forming the infrared blocking layer 222 and the infrared transmitting holes 223 of the infrared blocking mask 220 will be described.

[0059] Figure 2 is a schematic flow chart of a drying method according to an embodiment.

[0060] like Figure 2 As shown in , the drying method according to the embodiment may include: step S10 of providing a display panel DP including a first light-emitting element ED1, a second light-emitting element ED2 and a third light-emitting element ED3 on a stage 100 including a thermal heater 110; step S20 of providing an infrared heater 210 on the stage 100; and step S30 of providing an infrared blocking mask 220 between the display panel DP and the bottom (or lower surface) of the infrared heater 210.

[0061] For example, the stage 100, the holder 200, the infrared heater 210, and the infrared blocking mask 220 can each be moved up and down to adjust the distance between them. The infrared blocking mask 220 can be set below (e.g., directly below) the infrared heater 210, or above (e.g., directly above) the display panel DP and the substrate SUB. For example, more detailed information about the stage 100, the holder 200, and the infrared blocking mask 220 can be found in the above description.

[0062] The drying method may include step S40 of baking at least one of the light-emitting layer of the first light-emitting element ED1 and the light-emitting layer of the second light-emitting element ED2, and the light-emitting layer of the third light-emitting element ED3 at different temperatures using the thermal heater 110 and the infrared heater 210. For example, the baking temperature applied to the light-emitting layer of the third light-emitting element ED3 may be lower than the baking temperature applied to the light-emitting layer of the first light-emitting element ED1 and the light-emitting layer of the second light-emitting element ED2. However, embodiments are not limited thereto, and the drying method may include baking at different temperatures any one or more of the light-emitting layer of the first light-emitting element ED1, the light-emitting layer of the second light-emitting element ED2, and the light-emitting layer of the third light-emitting element ED3.

[0063] For example, the thermal heater 110 can provide heat to all light-emitting layers of the first, second, and third light-emitting elements ED1, ED2, and ED3. Due to the infrared blocking mask 220, the infrared heater 210 may not provide additional heat to the light-emitting layer of the third light-emitting element ED3, but may provide additional heat to the light-emitting layers of the first and second light-emitting elements ED1 and ED2. The infrared blocking mask 220 may include an infrared blocking layer 222 at a position corresponding to the third light-emitting element ED3. The infrared blocking layer 222 may further include an infrared reflective layer 222-1 or an infrared absorbing layer 222-2. However, embodiments are not limited thereto, and the infrared heater 210 may apply heat to any one or more of the first, second, and third light-emitting elements ED1, ED2, and ED3, and the infrared blocking layer 222 may be positioned to correspond to light-emitting elements to which the infrared heater 210 does not apply heat. For example, more detailed information regarding the infrared blocking mask 220 can be found in the above description.

[0064] For example, the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may further include an inkjet process for organic light-emitting elements, an inkjet process for quantum dot light-emitting elements, or an inkjet process for converged organic light-emitting-quantum dot light-emitting elements. For example, the third light-emitting element ED3 may be a device having a lower baking temperature than the first light-emitting element ED1 and the second light-emitting element ED2. The first light-emitting element ED1 and the second light-emitting element ED2 may be light-emitting elements including quantum dots, and the third light-emitting element ED3 may be a light-emitting element including an organic material. More detailed information regarding the configuration of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 will be referred to the embodiment of the display panel DP described later.

[0065] For example, the temperature provided by the thermal heater 110 may be lower than the temperature provided by the infrared heater 210 .

[0066] The infrared blocking mask 220 may be manufactured using at least one of a photolithography process and an inkjet process. More detailed information on the manufacturing process of the infrared blocking mask 220 may be referred to in the later described Figure 3 and Figure 4 Example of .

[0067] Figure 3 is a process diagram schematically illustrating a mask manufacturing process according to an embodiment.

[0068] refer to Figure 3 , shows a process of manufacturing an infrared blocking mask 220 through a photolithography process. For example, the infrared blocking mask 220 may include an infrared blocking layer 222 and infrared transmitting holes 223. The infrared blocking layer 222 may be at least one of a reflective layer 222-1 for reflecting infrared rays and an absorbent layer 222-2 for absorbing infrared rays. The reflective layer 222-1 may be formed of a metal material such as silver (Ag) and aluminum (Al), and the absorbent layer 222-2 may be formed of a material capable of absorbing infrared rays, such as antimony oxide, tin oxide, tungsten oxide, titanium oxide, an infrared absorbing polymer, an organic-inorganic solar cell material, and a metamaterial.

[0069] The manufacturing process can be Figure 3 , and the like. The process proceeds in the order of step (a), step (b), and step (c). Referring to step (a), a glass substrate 221 from which foreign matter has been removed is prepared, and subsequently, a material for reflecting or absorbing infrared rays is applied to (e.g., completely applied to) the glass substrate 221. For more detailed information about these materials, reference may be made to the above description. In step (b), the material provided in the area through which infrared rays can pass may be removed by a photolithography process. In step (c), the area where the applied material remains may form an infrared blocking layer 222, and the area where the applied material is removed may form an infrared transmission hole 223.

[0070] Figure 4 is a process diagram schematically illustrating a mask manufacturing process according to another embodiment.

[0071] refer to Figure 4 , shows a process of manufacturing the infrared blocking mask 220 by an inkjet process. The manufacturing process can be as follows Figure 4The process of the present invention is carried out in the order of steps (a), (b) and (c) in the process. First, with reference to step (a), a glass substrate 221 from which foreign matter has been removed can be prepared, and selective surface treatment SSM can be performed by specifying an area for infrared transmission. By selective surface treatment SSM, the precision of the inkjet process can be improved by preventing the material to be applied by the inkjet process from adhering to unnecessary areas. Hydrophobic materials can be used for selective surface treatment SSM, but embodiments are not limited thereto. In step (b), a material for reflecting or absorbing infrared rays can be applied by an inkjet process, but does not include an area for infrared transmission. For more detailed information about these materials, reference can be made to the above description. In step (c), an infrared blocking layer 222 can be formed in an area where the material is applied by the inkjet process, and an infrared transmission hole 223 can be formed in an area where the material is not applied by the selective surface treatment SSM.

[0072] As described above, different from the manufacturing method of ordinary shadow mask and fine metal mask (FMM), Figure 3 and Figure 4 The method of manufacturing the infrared blocking mask 220 according to the embodiment can prevent the mask from warping due to a large-area process. Without the mask warping, the accuracy of the process through the mask can be improved.

[0073] In the following, through Figure 5 To describe Figure 1 The description of the possible embodiments is omitted. Figure 5 is a schematic cross-sectional view of a display panel according to an embodiment.

[0074] refer to Figure 5 , shows an embodiment of an inkjet process for an organic light-emitting-quantum dot light-emitting element convergence type display panel. For example, the display panel DP according to the embodiment may include a substrate SUB, a circuit element layer CL, and a light-emitting element layer EL.

[0075] The display panel DP according to the embodiment may include a substrate SUB. The substrate SUB may be a flexible substrate including a polymer such as polyimide, polyamide, or polyethylene terephthalate. The substrate SUB may be a rigid substrate including glass. The substrate SUB may include a flexible material such as plastic that is bent, curved, folded, or rolled, or may include a rigid substrate.

[0076] The circuit element layer CL may be disposed on the substrate SUB. The circuit element layer CL may include a buffer layer BF, a semiconductor layer ACT, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer IL1, and a passivation layer IL2.

[0077] The buffer layer BF of the circuit element layer CL may be disposed on the substrate SUB. In another example, the buffer layer BF may be omitted. The buffer layer BF may include silicon nitride (SiN x ), silicon oxide (SiO2) or silicon oxynitride (SiO x N y Since the buffer layer BF is disposed between the substrate SUB and the semiconductor layer ACT and blocks impurities from the substrate SUB during a crystallization process for forming polycrystalline silicon, the characteristics of the polycrystalline silicon may be improved and the substrate SUB may be planarized, thereby alleviating stress of the semiconductor layer AC formed on the buffer layer BF.

[0078] The semiconductor layer ACT may be disposed on the buffer layer BF. The semiconductor layer ACT may be made of polycrystalline silicon or an oxide semiconductor. The semiconductor layer ACT may include a channel region C, a source region S, and a drain region D. The source region S and the drain region D may be located on either side of the channel region C, respectively. The channel region C may be an intrinsic semiconductor that is not doped with impurities, and the source region S and the drain region D may be an impurity semiconductor doped with conductive impurities. The semiconductor layer ACT may be made of an oxide semiconductor. For example, a separate protective layer may be added to protect the oxide semiconductor material that is susceptible to external environments (such as high temperatures).

[0079] The gate insulating layer GI may be provided on the semiconductor layer ACT. The gate insulating layer GI may include silicon nitride (SiN x ), silicon oxide (SiO2) and silicon oxynitride (SiO x N y ) is a single layer or multiple layers of at least one of the above.

[0080] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may be a multilayer including metal layers stacked on each other and formed of at least one of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, molybdenum (Mo), and molybdenum alloy.

[0081] The interlayer insulating layer IL1 may be disposed over the gate electrode GE and the gate insulating layer GI. The interlayer insulating layer IL1 may include silicon nitride (SiN x ), silicon oxide (SiO2) or silicon oxynitride (SiO x N y Openings that expose the source region S and the drain region D, respectively, may be provided in the interlayer insulating layer IL1.

[0082] The source electrode SE and the drain electrode DE may be disposed on the interlayer insulating layer IL1 and may be respectively connected (eg, electrically connected) to the source region S and the drain region D of the semiconductor layer ACT through openings formed in the interlayer insulating layer IL1.

[0083] A passivation layer IL2 may be provided over the interlayer insulating layer IL1, the source electrode SE, and the drain electrode DE. Since the passivation layer IL2 covers and planarizes the interlayer insulating layer IL1, the source electrode SE, and the drain electrode DE, the first electrodes E1a, E1b, and E1c may be formed on the passivation layer IL2 without steps or step differences. The passivation layer IL2 may be made of an organic material such as a polyacrylate resin or a polyimide resin, or a laminated film of an organic material and an inorganic material.

[0084] The light emitting element layer EL may be disposed on the passivation layer IL2. The light emitting element layer EL may include first electrodes E1a, E1b, and E1c, barrier ribs PDL, pixel openings OP1, OP2, and OP3, first, second, and third light emitting layers EML1, EML2, and EML3, a second electrode E2, a capping layer CPL, and an encapsulation layer ENC.

[0085] The first electrodes E1a, E1b, and E1c of the light emitting element layer EL may be disposed above the passivation layer IL2 as the upper end portion of the circuit element layer CL. The first electrodes E1a, E1b, and E1c may be connected (eg, electrically connected) to the drain electrode DE through the opening of the passivation layer IL2.

[0086] A driving transistor including a gate electrode GE, a semiconductor layer ACT, a source electrode SE, and a drain electrode DE may be connected (eg, electrically connected) to the first electrodes E1a, E1b, and E1c and may supply current to the first, second, and third light emitting elements ED1, ED2, and ED3. Figure 5 In addition to the driving transistor shown in , the display panel according to the embodiment may further include a switching transistor connected (e.g., electrically connected) to the data line and transmitting a data voltage in response to a scan signal, and a compensation transistor connected (e.g., electrically connected) to the driving transistor and compensating for a threshold voltage of the driving transistor in response to the scan signal.

[0087] The barrier ribs PDL may be disposed on the passivation layer IL2 and the first electrodes E1a, E1b, and E1c. The barrier ribs PDL may have pixel openings OP1, OP2, and OP3 that overlap with the first electrodes E1a, E1b, and E1c and define light-emitting areas. The barrier ribs PDL may include an organic material such as a polyacrylate resin or a polyimide resin, or a silicon dioxide-based inorganic material. In a plan view, the pixel openings OP1, OP2, and OP3 may have a planar shape similar to that of the first electrodes E1a, E1b, and E1c and may have a rhombus or an octagonal shape similar to a rhombus, but the embodiment is not limited thereto and may have any shape such as a quadrilateral or other polygonal shape.

[0088] According to the embodiment, the first light-emitting element ED1 may overlap the red light-emitting area RLA, the second light-emitting element ED2 may overlap the green light-emitting area GLA, and the third light-emitting element ED3 may overlap the blue light-emitting area BLA. The first light-emitting element ED1 may include a first electrode E1a, a first light-emitting layer EML1, and a second electrode E2. The second light-emitting element ED2 may include a first electrode E1b, a second light-emitting layer EML2, and a second electrode E2. The third light-emitting element ED3 may include a first electrode E1c, a third light-emitting layer EML3, and a second electrode E2. The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may further include a functional layer including at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron injection layer (EIL), and an electron transport layer (ETL). The functional layer may include portions disposed between the first electrodes E1a, E1b, and E1c and the first, second, and third light-emitting layers EML1, EML2, and EML3, and portions disposed between the first, second, and third light-emitting layers EML1, EML2, and EML3 and the second electrode E2.

[0089] The barrier ribs PDL may be used to separate or define the red, green, and blue light emitting areas RLA, GLA, and BLA. The barrier ribs PDL may have a first opening OP1 overlapping the red light emitting area RLA, a second opening OP2 overlapping the green light emitting area GLA, and a third opening OP3 overlapping the blue light emitting area BLA.

[0090] The non-luminescent area NLA may be disposed between the red, green, and blue luminescent areas RLA, GLA, and BLA. Each luminescent area may correspond to a light-emitting element. For example, the blue, red, and green luminescent areas BLA, RLA, and GLA may correspond to blue, red, and green pixels, respectively. The shapes and arrangements of the red, green, and blue luminescent areas RLA, GLA, and BLA may be modified in various ways.

[0091] The first opening OP1 and the first electrode E1a of the first light-emitting element ED1 may overlap with each other, the second opening OP2 and the first electrode E1b of the second light-emitting element ED2 may overlap with each other, and the third opening OP3 and the first electrode E1c of the third light-emitting element ED3 may overlap with each other. At least portions of the first electrode E1a of the first light-emitting element ED1, the first electrode E1b of the second light-emitting element ED2, and the first electrode E1c of the third light-emitting element ED3 may overlap with the barrier ribs PDL. Using the barrier ribs PDL as an example, the first electrode E1a of the first light-emitting element ED1, the first electrode E1b of the second light-emitting element ED2, and the first electrode E1c of the third light-emitting element ED3 may be spaced apart from each other.

[0092] The first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may be disposed in the first opening OP1, and each may be manufactured by an inkjet process.

[0093] The first light emitting layer EML1 , the second light emitting layer EML2 , and the third light emitting layer EML3 may emit light of different colors.

[0094] The first light emitting layer EML1 may emit red light. The first light emitting layer EML1 may include first quantum dots QD1. The second light emitting layer EML2 may emit green light. The second light emitting layer EML2 may include second quantum dots QD2.

[0095] The third light emitting layer EML3 may emit blue light. The third light emitting layer EML3 may include an organic material such as a low-molecular organic material or a polymer organic material having a molecular weight of 10,000 or more, such as poly(3,4-ethylenedioxythiophene) (PEDOT).

[0096] Quantum dots including first and second quantum dots QD1 and QD2 will now be described in detail below.

[0097] In the present description, quantum dots (hereinafter referred to as semiconductor nanocrystals) may include Group II-VI compounds, Group III-V compounds, Group IV-VI compounds, Group IV elements or compounds, Group I-III-VI compounds, Group II-III-VI compounds, Group I-II-IV-VI compounds, or combinations thereof.

[0098] The II-VI compound may be selected from the group consisting of binary compounds, ternary compounds, and quaternary compounds, the binary compound being selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof; the ternary compound being selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, C The group II-VI compound may further include a Group III metal.

[0099] The III-V compound may be selected from the group consisting of a binary compound selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; a ternary compound selected from the group consisting of GaNPs, GaNAs, GaNSb, GaPAs, GaPSb, AlNPs, AlNAs, AlNSb, AlPAs, AlPSb, InNPs, InNAs, InNSb, InPAs, InPSb, and mixtures thereof; a quaternary compound selected from the group consisting of GaAlNPs, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNPs, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNPs, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof. The III-V compound may further include a Group II metal (e.g., InZnP).

[0100] The IV-VI Group compound can be selected from the group consisting of binary compounds, ternary compounds and quaternary compounds, the binary compound is selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and their mixtures; the ternary compound is selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and their mixtures; the quaternary compound is selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and their mixtures.

[0101] The Group IV element or compound may be a single substance of Si or Ge, or a combination thereof; or a binary element compound of SiC or SiGe, or a combination thereof, but the embodiment is not limited thereto.

[0102] Examples of the Group I-III-VI compound may include CuInSe 2 , CuInS 2 , CuInGaSe, and CuInGaS, but the embodiment is not limited thereto.

[0103] The Group II-III-VI compound may be ZnGaS, ZnAlS, ZnInS, ZnGaSe, ZnAlSe, ZnInSe, ZnGaTe, ZnAlTe, ZnInTe, ZnGaO, ZnAlO, ZnInO, HgGaS, HgAlS, HgInS, HgGaSe, HgAlSe, HgInSe, HgGaTe, HgAlTe, HgInTe, MgGaS, MgAlS, MgInS, MgGaSe, MgAlSe, MgInSe, or a combination thereof, but the embodiment is not limited thereto.

[0104] The Group I-II-IV-VI compound may be selected from CuZnSnSe or CuZnSnS, but the embodiment is not limited thereto.

[0105] In an embodiment, the quantum dots may not include cadmium. The quantum dots may include semiconductor nanocrystals based on Group III-V compounds containing indium and phosphorus. The Group III-V compounds may further include zinc. The quantum dots may include semiconductor nanocrystals based on Group II-VI compounds containing chalcogen elements (e.g., sulfur, selenium, tellurium, or a combination thereof) and zinc.

[0106] In quantum dots, the binary, ternary, or quaternary compounds described above may be present in a uniform concentration within the particle, or within the same particle whose concentration distribution can be partially divided into different states. For example, they may have a core / shell structure in which one quantum dot surrounds another quantum dot. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0107] In some embodiments, quantum dots may have a core / shell structure comprising a core comprising the nanocrystals described above and a shell surrounding the core. The shell of the quantum dot may serve as a protective layer for maintaining semiconductor properties by preventing chemical modification of the core and / or as a charging layer for imparting electrophoretic properties to the quantum dot. The shell may be monolayer or multilayer. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center. Examples of quantum dot shells include metal or non-metal oxides, semiconductor compounds, or combinations thereof.

[0108] For example, the metal oxide or non-metal oxide may include binary compounds such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4 and NiO, or ternary compounds such as MgAl2O4, CoFe2O4, NiFe2O4 and CoMn2O4, but the embodiments are not limited thereto.

[0109] For example, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, and AlSb, but the embodiment is not limited thereto.

[0110] The interface between core and shell can have concentration gradient, makes the concentration of the element present in the shell gradually reduce as it approaches its center.For example, semiconductor nanocrystal can have the structure that comprises a semiconductor nanocrystal core and the multilayer shell around this core.In an embodiment, multilayer shell can have two or more layers, for example two layers, three layers, four layers, five layers or more layers.Two adjacent layers of shell can have single composition or different composition.In multilayer shell, each layer can have the composition that changes along radius.

[0111] The quantum dots may have a full width at half maximum (FWHM) of about 45 nm or less, about 40 nm or less, or about 30 nm or less, and within this range, color purity or color reproducibility may be improved. For example, since light emitted by the quantum dots is emitted in all directions, a wide viewing angle may be improved.

[0112] In quantum dots, the shell material and the core material can have different energy band gaps. For example, the energy band gap of the shell material can be larger than the energy band gap of the core material. In another example, the energy band gap of the shell material can be smaller than the energy band gap of the core material. Quantum dots can have multiple shells. In a multilayer shell, the energy band gap of the outer layer can be larger than the energy band gap of the inner layer (e.g., the layer closer to the core). In a multilayer shell, the energy band gap of the outer layer can be smaller than the energy band gap of the inner layer.

[0113] Quantum dots can control the absorption or emission wavelength by adjusting the composition and size of the quantum dots. The maximum peak emission wavelength of the quantum dots can be ultraviolet (UV) to infrared wavelengths, or wavelengths greater than the above wavelength range.

[0114] Quantum dots can have a quantum efficiency of about 10% or more, for example, about 30% or more, about 50% or more, about 60% or more, about 70% or more, about 90% or more, or even 100%. Quantum dots can have a relatively narrow spectrum. Quantum dots can have, for example, a full width at half maximum of an emission wavelength spectrum of about 50 nm or less, about 45 nm or less, about 40 nm or less, or about 30 nm or less.

[0115] The quantum dot may have a particle size of about 1 nm or more and about 100 nm or less. The size of the particle refers to the diameter of the particle, or the diameter converted by assuming a sphere from a two-dimensional (2D) image obtained by using a transmission electron microscope. The quantum dot may have a size of about 1 nm to about 50 nm, for example, about 2 nm or more, about 3 nm or more, or about 4 nm or more and about 50 nm or less, about 40 nm or less, about 30 nm or less, about 20 nm or less, about 15 nm or less, or about 10 nm or less. The shape of the quantum dot is not limited thereto. For example, the shape of the quantum dot may include a sphere, a polyhedron, a pyramid, a multi-pod, a square, a cuboid, a nanotube, a nanorod, a nanowire, a nanosheet, or a combination thereof, but embodiments are not limited thereto.

[0116] Quantum dots may be commercially available or may be suitably synthesized. In the case of quantum dots, the particle size can be controlled relatively freely during colloidal synthesis and can be uniformly controlled.

[0117] The quantum dot may include an organic ligand (e.g., having a hydrophobic portion). The organic ligand portion may be bonded to the surface of the quantum dot. The organic ligand portion may include RCOOH, RNH2, R2NH, R3N, RSH, R3PO, R3P, ROH, RCOOR, RPO(OH)2, RHPOOH, R2POOH, or a combination thereof, and in this article, R is independently substituted or unsubstituted C3 to C40 aliphatic hydrocarbon group (such as substituted or unsubstituted C3 to C40 (e.g., C5 or greater and C24 or less) alkyl or substituted or unsubstituted alkenyl), substituted or unsubstituted C6 to C40 (e.g., C6 or greater and C20 or less) aromatic hydrocarbon group (such as substituted or unsubstituted C6 to C40 aryl) or a combination thereof.

[0118] Examples of the organic ligand may include: a thiol compound such as methanethiol, ethanethiol, propanethiol, butanethiol, pentanethiol, hexanethiol, octanethiol, dodecanethiol, hexadecanethiol, octadecanethiol, or benzylthiol; an amine such as methaneamine, ethaneamine, propanethiol, butanethiol, pentylamine, hexylamine, octylamine, nonylamine, decylamine, dodecylamine, hexadecylamine, octadecylamine, dimethylamine, diethylamine, dipropylamine, tributylamine, or trioctylamine; a carboxylic acid compound such as formic acid, acetic acid, propionic acid, butanethiol, pentanethiol, hexanethiol, heptanethiol, octanethiol, dodecane acid, hexadecane acid, octadecane acid, oleic acid, or benzylthiol. Acid; a phosphine compound such as methyl phosphine, ethyl phosphine, propyl phosphine, butyl phosphine, pentyl phosphine, octyl phosphine, dioctyl phosphine, tributyl phosphine, trioctyl phosphine, diphenyl phosphine or triphenyl phosphine; an oxide of a phosphine compound such as methyl phosphine oxide, ethyl phosphine oxide, propyl phosphine oxide, butyl phosphine oxide, pentyl phosphine oxide, tributyl phosphine oxide, octyl phosphine oxide, dioctyl phosphine oxide, trioctyl phosphine oxide, diphenyl phosphine oxide or triphenyl phosphine oxide; and a C5 to C20 alkyl phosphinic acid such as hexyl phosphinic acid, octyl phosphinic acid, dodecyl phosphinic acid, tetradecyl phosphinic acid, hexadecyl phosphinic acid or octadecyl phosphinic acid, but embodiments are not limited thereto. The quantum dot may include a single hydrophobic organic ligand or a mixture of at least two hydrophobic organic ligands. The hydrophobic organic ligand may not include a photopolymerizable portion (e.g., an acrylate group, a methacrylate group, etc.).

[0119] Reference again Figure 5 The second electrode E2 may be disposed on the functional layer. The second electrode E2 may be continuously disposed above the red light emitting area RLA, the green light emitting area GLA, the blue light emitting area BLA, and the non-light emitting area NLA. The second electrode E2 may receive a common voltage through a common voltage transmitting portion in the non-display area.

[0120] For example, the first electrodes E1a, E1b, and E1c may be anodes serving as hole injection electrodes, and the second electrode E2 may be cathodes serving as electron injection electrodes. However, the embodiment is not limited thereto, and depending on a driving method of the display panel, the first electrodes E1a, E1b, and E1c may be cathodes, and the second electrode E2 may be an anode.

[0121] The capping layer CPL may be disposed on the second electrode E2 and may be continuously disposed on the red light emitting area RLA, the green light emitting area GLA, the blue light emitting area BLA, and the non-light emitting area NLA.

[0122] The encapsulation layer ENC may be disposed on the capping layer CPL. The encapsulation layer ENC may seal the display layer by covering not only the upper surface of the display layer including the first, second, and third light emitting elements ED1, ED2, and ED3 but also the side surfaces thereof.

[0123] Because the light-emitting element is very susceptible to moisture and oxygen, the encapsulation layer ENC can seal the display layer and block the influx of external moisture and oxygen. The encapsulation layer ENC may include multiple layers and may be formed from a composite layer including both an inorganic layer and an organic layer. The encapsulation layer ENC may be formed from three layers in which an inorganic layer, an organic layer, and an inorganic layer are sequentially formed.

[0124] Reference again Figure 5 , which shows a convergence display panel including a first light-emitting layer (EML1) and a second light-emitting layer (EML2) as quantum dot light-emitting layers, and a third light-emitting layer (EML3) as an organic light-emitting layer. However, the baking temperatures of the quantum dot light-emitting layer and the organic light-emitting layer can be different. The efficiency of each light-emitting layer according to the baking temperature is shown in Table 1 below.

[0125] [Table 1]

[0126]

[0127] As shown in Table 1, the optimal baking temperature for the quantum dot light-emitting layer is about 180°C, and when the process is performed below about 140°C, the problem of a sharp drop in efficiency occurs. The optimal baking temperature for the organic emission layer is about 140°C, and when the process is performed above about 150°C, the problem of a sharp drop in efficiency occurs. When the baking temperature of one of the quantum dot light-emitting layer and the organic emission layer is used as a reference, the efficiency is significantly reduced. In order to solve this problem, when manufacturing a convergent display panel, there is a method of dividing the baking process into two stages. When this two-stage manufacturing process is applied, the production time and cost increase compared to non-convergent display panels. However, as shown in the present disclosure, when different temperatures can be applied to each light-emitting element, all light-emitting elements can be manufactured at one time, thereby significantly saving production time and cost. In the following, reference is made to Figure 6 and Figure 7 A display panel according to another embodiment will be described. Figure 6 is a schematic cross-sectional view of a display panel according to another embodiment. Figure 7 is a schematic cross-sectional view of a display panel according to another embodiment. Figure 5 Descriptions of parts that are the same as (or similar to) those described in .

[0128] refer to Figure 6 , shows an embodiment of an inkjet process organic light emitting element display panel. Figure 5 Unlike the embodiment, a first-first light-emitting layer EML1-1 and a second-first light-emitting layer EML2-1 may be formed instead of the first light-emitting layer EML1 and the second light-emitting layer EML2-1, and the first-first light-emitting layer EML1-1 and the second-first light-emitting layer EML2-1 may include an organic material instead of quantum dots. Instead of the third light-emitting layer EML3, a third-first light-emitting layer EML3-1 may be formed, and the configuration material may be the same as that of the third light-emitting layer EML3. For example, compared to the first-first light-emitting layer EML1-1 that emits red light and the second-first light-emitting layer EML2-1 that emits green light, the third-first light-emitting layer EML3-1 that emits blue light may have difficulty ensuring efficiency due to high baking temperatures. To address this issue, it is necessary to apply the present disclosure and perform a baking process on the third light-emitting element ED3 at a relatively lower temperature than the first and second light-emitting elements ED1 and ED2.

[0129] refer to Figure 7 , shows an embodiment of an inkjet process quantum dot light emitting element display panel. Figure 5Unlike the embodiment, a third-second light-emitting layer EML3-2 may be formed instead of the third light-emitting layer EML3, and the third-second light-emitting layer EML3-2 may include third quantum dots QD3 instead of organic materials. For more detailed information about the third quantum dots QD3, reference may be made to the first and second quantum dots QD1 and QD2 mentioned above.

[0130] At the end of this detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without actually departing from the principles of the present disclosure and the spirit and scope of the present disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A method for drying a display panel, the method comprising: providing a display panel including a first light emitting element, a second light emitting element, and a third light emitting element on a stage including a thermal heater; providing an infrared heater on the stage; providing an infrared blocking mask between the display panel and the infrared heater; as well as At least one of the first light emitting element and the second light emitting element and the third light emitting element are baked at different baking temperatures by the thermal heater and the infrared heater.

2. The method according to claim 1, wherein The infrared blocking mask includes infrared transmitting holes located at positions corresponding to the first light-emitting element and the second light-emitting element, and includes an infrared blocking layer located at a position corresponding to the third light-emitting element, and the infrared blocking layer includes at least one of an infrared reflecting layer and an infrared absorbing layer.

3. The method according to claim 2, wherein: the thermal heater applies heat to the first light emitting element, the second light emitting element, and the third light emitting element, The infrared heater applies heat to the first light emitting element and the second light emitting element through the infrared transmission hole, and The baking temperature for the third light emitting element is lower than the baking temperatures for the first and second light emitting elements.

4. The method according to claim 2, wherein: The first light emitting element and the second light emitting element include quantum dot light emitting layers, and The third light emitting element includes an organic emission layer.

5. The method according to claim 1, wherein The temperature of the heat provided by the thermal heater is set to be lower than the temperature of the heat provided by the infrared heater.

6. The method according to any one of claims 1 to 5, wherein Providing the infrared blocking mask includes installing the infrared blocking mask directly below the infrared heater or directly above the display panel.

7. A method for drying a display panel, the method comprising: providing a display panel including a first light emitting element, a second light emitting element, and a third light emitting element on a stage including a thermal heater; providing an infrared blocking mask on the stage; providing an infrared heater on the infrared blocking mask; as well as At least one of the first light emitting element, the second light emitting element, and the third light emitting element is baked at different temperatures by the thermal heater and the infrared heater, wherein The thermal heater applies heat to the first light emitting element, the second light emitting element, and the third light emitting element, and The infrared heater applies heat to at least one of the first light emitting element, the second light emitting element, and the third light emitting element due to the infrared blocking mask.

8. The method according to claim 7, wherein: The infrared blocking mask includes an infrared blocking layer located at a position corresponding to one or more of the first light emitting element, the second light emitting element, and the third light emitting element, and the infrared blocking layer includes at least one of an infrared reflecting layer and an infrared absorbing layer.

9. A device for drying a display panel, the device comprising: drying room; a stage disposed in the drying chamber and comprising a thermal heater; an infrared blocking mask, disposed on the stage; as well as An infrared heater is provided on the infrared blocking mask.

10. The apparatus according to claim 9, wherein The infrared blocking mask includes an infrared blocking layer and infrared transmitting holes, and is disposed directly below the infrared heater.

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