Display device and driving method thereof

Abstract

A display device and a driving method thereof are disclosed. The display device includes: a display panel including at least one pixel; a source driver configured to output a data voltage to be supplied to the at least one pixel in a refresh frame and stop outputting the data voltage to be supplied to the at least one pixel in at least one skip frame following the refresh frame; and a bias controller configured to output a first turn-on bias stress voltage to be supplied to the at least one pixel in the refresh frame, and output a second turn-on bias stress voltage to be supplied to the at least one pixel in the at least one skip frame. First and second on-bias stress voltages are applied to one electrode of a driving transistor included in at least one pixel to improve a brightness difference caused by a change in a leakage characteristic of the at least one pixel, and the first and second on-bias stress voltages are set differently, threshold voltage characteristics of the driving transistor are made different in the refresh frame and the at least one skip frame.

Description

Technical Field

[0001] The present disclosure relates to a device, and in particular, for example but not limited to, to a display apparatus and a driving method thereof. Background Art

[0002] Display devices include a plurality of pixels arranged in a matrix, and use these pixels to achieve brightness corresponding to image data. In display devices, technologies are known that vary the refresh rate based on image properties. This variable refresh rate technology increases the data refresh cycle as image variability decreases, thereby reducing power consumption.

[0003] The data refresh operation is performed in the refresh frame, not in the skip frame. As the number of skip frames provided between adjacent refresh frames increases, the data refresh period increases, and low-speed driving is achieved.

[0004] The descriptions provided in the discussion of related art section should not be admitted to be prior art merely by virtue of being mentioned in or associated with that section. The discussion of related art section may include information describing one or more aspects of the subject technology, and the descriptions in that section do not limit the present invention. Summary of the Invention

[0005] The inventors of the present disclosure have recognized that a luminance deviation between a refresh frame and a skipped frame may occur due to variations in leakage characteristics occurring in pixels.

[0006] Such brightness deviation is more noticeable in low-speed driving with a long data refresh cycle, and therefore may be recognized as flicker.

[0007] In order to overcome the above-mentioned problems of the related art, the present disclosure may provide a display device and a driving method thereof, which may reduce a luminance deviation occurring between a refresh frame and a skip frame and thus may enhance display quality.

[0008] To achieve these objects and other advantages and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a display device includes: a display panel including at least one pixel; a source driver configured to output a data voltage to be supplied to the at least one pixel in a refresh frame and to stop outputting the data voltage to be supplied to the at least one pixel in at least one skipped frame following the refresh frame; and a bias controller configured to output a first on-bias stress voltage to be supplied to the at least one pixel in the refresh frame and to output a second on-bias stress voltage to be supplied to the at least one pixel in the at least one skipped frame, wherein the first on-bias stress voltage and the second on-bias stress voltage are applied to one electrode of a driving transistor included in the at least one pixel to improve luminance difference caused by variation in leakage characteristics of the at least one pixel, and the first on-bias stress voltage and the second on-bias stress voltage are set differently so that a threshold voltage characteristic of the driving transistor is different in the refresh frame and the at least one skipped frame.

[0009] A voltage difference between the first on-bias stress voltage and the second on-bias stress voltage may be determined based on the number of skipped frames following the refresh frame.

[0010] A voltage difference between the first on-bias stress voltage and the second on-bias stress voltage may increase in proportion to the number of skipped frames following the refresh frame.

[0011] When the number of skipped frames following the refresh frame is plural, the second on-bias stress voltages corresponding to the plural skipped frames may be equal to each other.

[0012] When the number of skipped frames following the refresh frame is plural, the second on-bias stress voltages corresponding to the plural skipped frames may be different.

[0013] When the luminance of at least one skipped frame is lower than the luminance of the refresh frame, the second on-bias stress voltage may be lower than the first on-bias stress voltage.

[0014] When the luminance of at least one skipped frame is higher than the luminance of the refresh frame, the second on-bias stress voltage may be higher than the first on-bias stress voltage.

[0015] The display device may further include a gate driver configured to provide a light-emitting control signal to at least one pixel based on pulse width modulation to control the on and off timing of the light-emitting device included in the at least one pixel, wherein the off duty cycle of the light-emitting control signal may include a first off duty cycle and a second off duty cycle that is longer than the first off duty cycle.

[0016] The first off-duty cycle can be set between the on-duty cycles of the refresh frame and between the on-duty cycles of at least one skipped frame, and the second off-duty cycle can be set immediately before the first on-duty cycle of the refresh frame, immediately after the last on-duty cycle of at least one skipped frame, and between the last on-duty cycle of the refresh frame and the first on-duty cycle of at least one skipped frame.

[0017] The on-duty ratios of the light emitting control signals may be equal in length to each other in the refresh frame and at least one skipped frame.

[0018] In another aspect of the present disclosure, a method for driving a display device includes a display panel, the display panel includes at least one pixel, and the driving method includes the following steps: outputting a data voltage to be supplied to the at least one pixel in a refresh frame, and stopping outputting the data voltage to be supplied to the at least one pixel in at least one skip frame following the refresh frame; and outputting a first on-bias stress voltage to be supplied to the at least one pixel in the refresh frame, and outputting a second on-bias stress voltage to be supplied to the at least one pixel in the at least one skip frame, wherein the first on-bias stress voltage and the second on-bias stress voltage are applied to one electrode of a driving transistor included in the at least one pixel to improve a luminance difference caused by a variation in leakage characteristics of the at least one pixel, and wherein the first on-bias stress voltage and the second on-bias stress voltage are set differently so that a threshold voltage characteristic of the driving transistor is different in the refresh frame and the at least one skip frame.

[0019] Other systems, methods, features and advantages will be or will become apparent to those skilled in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features and advantages be included in this description and be within the scope of the present disclosure. Additional aspects and advantages are discussed below in conjunction with the embodiments of the present disclosure.

[0020] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate one or more embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0022] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0023] Figure 2is a diagram illustrating an example of a variable refresh rate technology applied to a display device according to an embodiment of the present disclosure;

[0024] Figure 3 is a diagram illustrating a pixel according to an embodiment of the present disclosure;

[0025] Figure 4 is a diagram for describing the operation of a pixel during a first on-bias stress (OBS) period of a refresh frame;

[0026] Figure 5 is a diagram for describing the operation of a pixel during the initialization period of a refresh frame;

[0027] Figure 6 is a diagram for describing the operation of a pixel over a programmed period of a refresh frame;

[0028] Figure 7 is a diagram for describing the operation of a pixel during the second OBS period of a refresh frame;

[0029] Figure 8 is a diagram for describing the operation of a pixel over a light emitting period of a refresh frame;

[0030] Figure 9 is a diagram for describing the operation of pixels in the third OBS period of a skipped frame;

[0031] Figure 10 is a diagram for describing operation of pixels in the fourth OBS period of a skipped frame;

[0032] Figure 11 is a diagram for describing the operation of a pixel over a light-emission period of a skipped frame;

[0033] Figure 12 and Figure 13 is a diagram showing an example in which a luminance deviation occurring between a refresh frame and a skip frame is greater in a high gray level than in a low gray level;

[0034] Figure 14 and Figure 15 is a diagram showing an example of differently setting an OBS voltage applied to pixels in a refresh frame and an OBS voltage applied to pixels in a skip frame;

[0035] Figure 16 is a diagram showing a connection configuration between an OBS controller and pixels;

[0036] Figure 17 and Figure 18 is a diagram illustrating an example in which a difference between OBS voltages applied to pixels in a refresh frame and a skip frame varies based on a frame frequency;

[0037] Figure 19is a diagram illustrating an EM duty cycle control technique for further reducing a luminance deviation between a refresh frame and a skip frame; and

[0038] Figure 20 and Figure 21 is a diagram showing an example of reducing the control range of the OBS voltage through the EM duty cycle control technique.

[0039] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and depictions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0040] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the present disclosure to those skilled in the art.

[0041] The advantages and features of the present disclosure and their implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is limited only by the scope of the claims.

[0042] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be shown in the accompanying drawings. In the following description, detailed descriptions of known functions or configurations associated with the document will be omitted when they are determined to unnecessarily obscure the main points of the inventive concept. The described progression of processing steps and / or operations are examples; however, except for steps and / or operations that must occur in a specific order, the order of steps and / or operations is not limited to that set forth herein and may be changed as known in the art. The same reference numerals represent the same elements throughout. The names of the elements used in the following description may be selected solely for the convenience of writing the specification and may therefore be different from the names used in the actual product.

[0043] In the following description, if a detailed description of a well-known function or configuration related to this document is determined to unnecessarily obscure the gist of the inventive concept, the detailed description thereof will be omitted or may be briefly discussed.

[0044] Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0045] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings for describing various embodiments of the present disclosure are merely exemplary, and the present disclosure is not limited thereto. The same reference numerals always refer to the same elements. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, the terms "including," "having," "comprising," etc. imply that other parts may be added, unless the term "only" is used. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0046] In addition, when referring to any size, relative size, etc., the numerical value or corresponding information (e.g., level, range, etc.) of an element or feature should be considered to include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all meanings of the term "can."

[0047] Even if not explicitly stated, elements in the various embodiments of the present disclosure should be construed as including a margin of error.

[0048] When describing a positional relationship, for example, when the positional relationship between two components is described as "on," "over," "under," and "beside," unless "only" or "directly" is used, one or more other components may be disposed between the two components.

[0049] When describing a temporal relationship, if the temporal order is described as, for example, "after," "subsequently," "next," and "before," discontinuities may be included unless more restrictive terms such as "immediately," "immediately," or "directly" are used.

[0050] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0051] Furthermore, when an element or layer is “connected,” “coupled,” or “adhered” to another element or layer, unless otherwise specified, the element or layer may be not only directly connected or adhered to the other element or layer, but also indirectly connected or adhered to the other element or layer with one or more intermediate elements or layers “disposed” or “interposed” between the elements or layers. This should be understood to mean that the elements may be arranged so as to be in direct contact with each other, or may be arranged so as not to be in direct contact with each other.

[0052] The expression "first element", "second element" and / or "third element" should be understood to refer to one of the first element, the second element and the third element or any or all combinations of the first element, the second element and the third element. For example, A, B and / or C can refer to only A; only B; only C; any or some combination of A, B and C; or all of A, B and C.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It should also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, for example, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein. For example, the term "part" or "unit" may apply to, for example, a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function as would be understood by one of ordinary skill in the art.

[0054] In the following description, when it is determined that a detailed description of a related known function or configuration unnecessarily obscures the main points of the present disclosure, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0055] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0056] Reference Figure 1 The display panel according to an embodiment of the present disclosure may be an organic light-emitting display device. The display panel 100 may include a screen AA that displays an input image. The screen AA may include a pixel array that displays pixel data (hereinafter referred to as "image data") DATA of the input image. The pixel array may include a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and a plurality of pixels SP.

[0057] The pixels SP may be arranged on the screen AA in a matrix type defined by intersections between the data lines DL and the gate lines GL. The pixels SP may be arranged on the screen AA in various types such as stripe and diamond types based on positions of pixels SP emitting light of the same color.

[0058] The pixel array may include a plurality of pixel columns and a plurality of pixel rows L1 to Ln intersecting the pixel columns. Each pixel column may include pixels SP arranged along the Y-axis direction. A pixel row may include pixels SP arranged along the X-axis direction. One vertical period may be a frame period required to write image data DATA for one frame to all pixels on the screen. One horizontal period may be the time obtained by dividing one frame period by the number of pixel rows L1 to Ln. One horizontal period may be the time required to write image data DATA for one pixel row sharing the gate line GL to the pixels SP of one pixel row.

[0059] Each pixel SP may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel for various color combinations. Each pixel SP may also include a white (W) sub-pixel.

[0060] Each pixel SP can be implemented using a pixel circuit connected to a data line DL and a gate line GL. The pixel circuit may include a light-emitting device, a driving transistor, one or more switching transistors, and a capacitor. The light-emitting device may be implemented as an organic light-emitting diode (OLED). The driving current applied to the light-emitting device may be controlled based on the gate-source voltage of the driving transistor. The gate-source voltage of the driving transistor may be determined by a data voltage corresponding to the image data DATA. Figure 1 , “D1 to D3” shown in circles may be data lines, and “Gn-2 to Gn” may be gate lines. Figure 1 Each pixel SP may be further connected to a front-end gate line and a current-end gate line. For example, each pixel SP disposed in an n-th pixel row Ln may be connected to a front-end gate line Gn-1 and an n-th gate line Gn.

[0061] The pixel circuit can sample the threshold voltage of the driving transistor in the middle of the pixel programming operation performed in a frame period, and can allow the sampled threshold voltage to be reflected in the gate-source voltage (hereinafter referred to as Vgs) of the driving transistor, and thus can prevent or reduce the distortion of the driving current caused by the threshold voltage change of the driving transistor.

[0062] All semiconductor layers of the transistors constituting the pixel circuit may include low-temperature polysilicon (hereinafter referred to as LTPS). LTPS-type pixel circuits can be distinguished from hybrid-type pixel circuits, in which some transistors include LTPS and other transistors include oxide. This embodiment can be used in LTPS-type pixel circuits.

[0063] The pixel circuit may be driven based on a variable refresh rate technique. To implement the variable refresh rate technique, one or more skip frames may be provided between adjacent refresh frames. The refresh rate (i.e., frame frequency) may be determined based on the number of skip frames provided between adjacent refresh frames.

[0064] A data refresh operation including pixel initialization and data programming may be performed in the refresh frame. When the data refresh operation is performed, the light emitting device may be turned off, and an anode reset operation may be performed at this time, wherein the light emitting device is initialized to an anode reset voltage.

[0065] The data refresh operation for the pixel SP can be omitted in the skip frame, and the data refresh condition Vgs (driving current) set in the refresh frame can be maintained. The anode reset operation for turning off the light-emitting device can be performed in the skip frame. Therefore, the length of time the light-emitting device is turned on in the skip frame can be substantially equal to the length of time the light-emitting device is turned on in the refresh frame.

[0066] In each of the refresh frame and the skip frame, when performing the anode reset operation, on-bias stress (OBS) may be performed on the driving transistor. In the hybrid pixel circuit and the LTPS pixel circuit, the OBS operation may be used for different purposes.

[0067] In a hybrid pixel circuit, the OBS operation can be used to prevent or reduce image quality defects caused by the hysteresis characteristics of the drive transistor. When the grayscale value of the image data DATA changes from black to white, due to the time required to change the hysteresis characteristics of the drive transistor, the grayscale response time in the first frame of reproducing the white image may increase, and therefore, a dim first frame (DFF) phenomenon may occur. The OBS operation can apply an OBS voltage to one electrode of the drive transistor to increase the Vgs of the drive transistor, and thus the DFF characteristics can be reduced. In a hybrid pixel circuit, the OBS voltage can be controlled to reduce the hysteresis characteristic difference between the refresh frame and the skipped frame.

[0068] On the other hand, in the LTPS pixel circuit according to this embodiment, the OBS operation can be used to improve the brightness difference caused by the change in the leakage characteristics of the pixel between the refresh frame and the skipped frame. In the LTPS pixel circuit, the OBS operation can differentially control the OBS voltage so that a difference in hysteresis characteristics can optionally occur between the refresh frame and the skipped frame, thereby improving the brightness difference between the refresh frame and the skipped frame.

[0069] A touch sensor may be provided on the display panel 100. The touch sensor may be arranged as an on-box type or an attached type on the screen AA of the display panel 100, or may be implemented as an in-cell type touch sensor embedded in a pixel array. Even without a touch sensor, a touch input may be sensed only through the pixels SP, and in this case, the touch sensor may be omitted.

[0070] The display panel driver may include a source driver 110 and gate drivers 120L and 120R. The display panel driver may write image data DATA into the pixels SP of the display panel 100 based on the control of the timing controller 130.

[0071] The source driver 110 can convert the image data received from the timing controller 130 into a gamma compensation voltage using a digital-to-analog converter (DAC) to generate a data voltage. The source driver 110 can supply the data voltage to the data line DL. The data voltage can be provided to the data line DL and can be applied to the gate of the driving transistor through the switching transistor of the sub-pixel SP. The source driver 110 can be implemented with a plurality of source driver integrated circuits (ICs).

[0072] The gate drivers 120L and 120R may be provided on the display panel 100 in a bezel area BZ outside the screen where no image is displayed. The gate drivers 120L and 120R may sequentially provide gate signals to the gate lines GL based on the control of the timing controller 130. The gate signals may select pixel rows L1 to Ln to be charged with data voltages and may simultaneously activate the pixels SP provided in the pixel rows L1 to Ln. The gate drivers 120L and 120R may output the gate signals using multiple stages and may shift the gate signals. The gate signals may swing between an on level and an off level.

[0073] The timing controller 130 may receive video data DATA and timing signals synchronized with the video data DATA from a host system (not shown). The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal Vsync may define a vertical period. The horizontal synchronization signal Hsync may define a horizontal period. The data enable signal DE may define the time during which the video data DATA is transmitted in a vertical period or a horizontal period. The vertical period and the horizontal period may be determined by counting the data enable signal DE, and therefore, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted.

[0074] The timing controller 130 may generate a source timing control signal DDC for controlling the operation timing of the source driver 110 and a gate timing control signal GDC for controlling the operation timing of the gate drivers 120L and 120R based on the timing signals Vsync, Hsync, and DE received from the host system.

[0075] The host system may be one of a television (TV), a set-top box, a navigation system, a personal computer (PC), a home theater, an automotive display system, a mobile device, and a wearable device. In the mobile device and the wearable device, the source driver 110, the timing controller 130, and the level shifters 140L and 140R may be integrated into one driver IC.

[0076] In order to reduce RC delay deviation occurring in the display panel 100 including a large screen, the gate drivers 120L and 120R may be implemented as a double bank type, and thus, gate signals having the same phase may be supplied to the same gate line GL from both sides of the display panel 100. The gate drivers 120L and 120R may include a first side gate driver 120L disposed in the left bezel region BZ of the display panel 100 and a second side gate driver 120R disposed in the right bezel region BZ of the display panel 100.

[0077] The level shifters 140L and 140R may convert the voltage of the gate timing control signal GDC output from the timing controller 130 into on-level voltage and off-level voltage and may supply the on-level voltage and off-level voltage to the gate drivers 120L and 120R.

[0078] The level shifters 140L and 140R may include a first level shifter 140L connected to the first side gate driver 120L through a first signal line and a second level shifter 140R connected to the second side gate driver 120R through a second signal line.

[0079] Figure 2 is a diagram illustrating an example of a variable refresh rate technology applied to a display device according to an embodiment of the present disclosure.

[0080] refer to Figure 2 The data refresh period implemented in the pixels of the display panel can vary based on the properties of the input image. When the amount of image change is large, the data refresh period can be reduced, while when the amount of image change is small, the data refresh period can be increased. As the data refresh period increases, low-speed driving can be performed, and as the data refresh period decreases, high-speed driving can be performed.

[0081] The data refresh period may be 1 / frame rate. For example, at 120Hz, the data refresh period is 1 second / 120; at 60Hz, the data refresh period is 1 second / 60; at 24Hz, the data refresh period is 1 second / 24; and at 1Hz, the data refresh period is 1 second.

[0082] The number of skipped frames provided between two adjacent refresh frames may vary based on the frame frequency. For example, the number of skipped frames may be 0 at 120 Hz, 1 at 60 Hz, 4 at 24 Hz, and 119 at 1 Hz.

[0083] Figure 3 is a diagram illustrating pixels SP arranged in an n-th pixel row Ln according to an embodiment of the present disclosure.

[0084] Reference Figure 3 , the pixel SP disposed in the nth pixel row Ln may be implemented with a pixel circuit including a light emitting device OLED, a driving transistor T1 , switching transistors T2 to T8 , and a capacitor Cst.

[0085] The transistors T1 to T8 and the capacitor Cst can control the driving current Ioled flowing in the light-emitting device OLED to drive the light-emitting device OLED. Each of the transistors T1 to T8 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0086] Each of the transistors T1 to T8 may be implemented as a PMOS transistor including a semiconductor layer having LTPS. Therefore, the on-level voltage of each of the transistors T1 to T8 may be a low voltage, and the off-level voltage thereof may be a high voltage.

[0087] The light emitting device OLED may include an anode (or pixel electrode), a cathode (or common electrode), and an organic compound layer (configured with a common layer and a light emitting layer) disposed therebetween. The anode of the light emitting device OLED may be connected to the third node NC, and the cathode of the light emitting device OLED may be connected to the second source voltage ELVSS.

[0088] The driving transistor T1 may include a first electrode connected to the first node NA, a second electrode connected to the second node NB, and a gate connected to the fourth node ND. The driving transistor T1 may generate a driving current Ioled based on the voltage of the fourth node ND (or the data voltage stored in the capacitor Cst), and may apply the driving current Ioled to the light emitting device OLED.

[0089] The switching transistor T2 may include a first electrode connected to the data line (or receiving the data voltage Vdata), a second electrode connected to the first node NA, and a gate receiving the first scan signal SC1(n). The switching transistor T2 may be turned on in response to the first scan signal SC1(n) and may transmit the data voltage Vdata to the first node NA.

[0090] The switching transistor T3 may include a first electrode connected to the fourth node ND, a second electrode connected to the second node NB, and a gate that receives the first scan signal SC1(n). The switching transistor T3 may be turned on in response to the first scan signal SC1(n) and may short-circuit the gate and the second electrode of the driving transistor T1. Therefore, when the switching transistor T3 is turned on, the driving transistor T1 may operate as a diode.

[0091] The capacitor Cst may be connected between the fourth node ND and the input terminal of the first source voltage ELVDD. The capacitor Cst may maintain the voltage of the fourth node ND.

[0092] The switching transistors T4 and T5 may be connected between the first source voltage ELVDD and the light emitting diode OLED, and may form a current moving path through which the driving current Ioled generated by the driving transistor T1 moves.

[0093] The switching transistor T4 may include a first electrode connected to the second node NB, a second electrode connected to the third node NC, and a gate receiving the light emission control signal EM(n). The switching transistor T5 may include a first electrode connected to the input terminal of the first source voltage ELVDD, a second electrode connected to the first node NA, and a gate receiving the light emission control signal EM(n).

[0094] The switching transistors T4 and T5 may be turned on in response to the light emitting control signal EM(n). When the switching transistors T4 and T5 are turned on, the light emitting device OLED may emit light having a brightness corresponding to the driving current Ioled.

[0095] The switching transistor T6 may include a first electrode connected to an input terminal of the initialization voltage Vint, a second electrode connected to the fourth node ND, and a gate receiving the front-end scan signal SC1(n-1). The switching transistor T6 may be turned on in response to the front-end scan signal SC1(n-1) and may apply the initialization voltage Vint to the fourth node ND.

[0096] The switching transistor T7 may include a first electrode connected to an input terminal of the anode reset voltage VAR, a second electrode connected to the third node NC, and a gate receiving the second scan signal SC2(n). The switching transistor T7 may be turned on in response to the second scan signal SC2(n) and may transfer the anode reset voltage VAR to the third node NC.

[0097] The switching transistor T8 may include a first electrode connected to an input terminal of the OBS voltage VOBS, a second electrode connected to the first node NA, and a gate receiving the second scan signal SC2(n). The switching transistor T8 may be turned on in response to the second scan signal SC2(n) and may transmit the OBS voltage VOBS to the first node NA.

[0098] Figure 4 : is a diagram for explaining the operation of pixels in the first OBS period of a refresh frame.

[0099] Reference Figure 4 , in the first OBS period Tobs1 of the refresh frame, the switching transistors T7 and T8 may be turned on in response to the second scan signal SC2 (n), and the other switching transistors T2 to T6 may be turned off.

[0100] In the first OBS period Tobs1 of the refresh frame, as the switching transistor T8 is turned on, the OBS voltage VOBS may be applied to the first node NA. Based on the OBS voltage VOBS, the drain-source channel of the driving transistor T1 may be turned on to the maximum extent, and the driving transistor T1 may maintain a stronger saturation state.

[0101] At this time, the gate-source voltage of the driving transistor T1 (i.e., Vgs=Vdata(n-1)-|Vth|-VOBS) may be applied. Vdata(n-1) may be the data voltage previously charged in the fourth node ND, and Vth may be the threshold voltage of the driving transistor T1. Therefore, the hysteresis characteristic of the driving transistor T1 may be reduced.

[0102] In the first OBS period Tobs1 of the refresh frame, as the switching transistor T7 is turned on, the anode reset voltage VAR may be applied to the third node NC. Based on the anode reset voltage VAR, residual charges charged in the parasitic capacitor formed between the anode and cathode of the light emitting device may be reset.

[0103] Figure 5 is a diagram for explaining the operation of pixels during the initialization period of a refresh frame.

[0104] Reference Figure 5, in the initialization period Ti of the refresh frame, the switching transistor T6 may be turned on in response to the front-end scan signal SC1 (n-1), and the other switching transistors T2 to T5, T7, and T8 may be turned off.

[0105] In the initialization period Ti of the refresh frame, as the switching transistor T6 is turned on, the fourth node ND may be initialized to the initialization voltage Vint.

[0106] Figure 6 is a diagram used to illustrate the operation of pixels over a programming period of a refresh frame.

[0107] Reference Figure 6 , in the programming period Tp of the refresh frame, the switching transistors T2 and T3 may be turned on in response to the first scan signal SC1 (n), and the other switching transistors T4 to T8 may be turned off.

[0108] In the programming period Tp of the refresh frame, as the switching transistors T2 and T3 are turned on, a threshold voltage sampling operation and a data programming operation may be performed sequentially or simultaneously.

[0109] The data voltage Vdata(n) can be applied to the first node NA via the switching transistor T2. The data voltage Vdata(n) can be applied to the second node NB via the driving transistor T1, and then to the fourth node ND via the switching transistor T3. When the switching transistor T3 is turned on, the driving transistor T1 can operate like a diode, and thus the potential at the gate of the driving transistor T1 connected to the fourth node ND can be programmed to "Vdata(n)-|Vth|". The threshold voltage Vth can be sampled and reflected in the potential at the gate of the programming driving transistor T1.

[0110] Figure 7 2 is a diagram for explaining the operation of pixels in the second OBS period of a refresh frame.

[0111] Reference Figure 7 , in the second OBS period Tobs2 of the refresh frame, the switching transistors T7 and T8 may be turned on in response to the second scan signal SC2 (n), and the other switching transistors T2 to T6 may be turned off.

[0112] The operation of the second OBS period Tobs2 of the refresh frame can be the same as that of the above reference Figure 4 The operation of the first OBS period Tobs1 of the refresh frame described is substantially the same and thus may be omitted or simply provided.

[0113] The first OBS period Tobs1 of the refresh frame and the second OBS period Tobs2 of the refresh frame can be respectively set before and after the programming period T. In this way, when OBS compensation is performed again after the predetermined time of the programming period Tp, the improvement effect of the DFF characteristic can be further enhanced.

[0114] Figure 8 : is a diagram for explaining the operation of pixels for the light emission period of a refresh frame.

[0115] Reference Figure 8 , in the light emitting period Te of the refresh frame, the switching transistors T4 and T5 may be turned on in response to the light emitting control signal EM(n), and the other switching transistors T2, T3, and T6 to T8 may be turned off.

[0116] In the light emission period Te of the refresh frame, the driving current Ioled supplied from the driving transistor T1 to the light emitting device OLED may be based on the Vgs of the driving transistor T1 set in the programming period Tp. The driving current Ioled may be independent of the threshold voltage Vth of the driving transistor T and may be associated with the data voltage Vdata(n).

[0117] Figure 9 : is a diagram for explaining the operation of pixels in the third OBS period of the skipped frame. Figure 10 is a diagram for describing the operation of pixels over the fourth OBS period of a skipped frame.

[0118] Reference Figure 9 and Figure 10 , in the third and fourth OBS periods Tobs3 and Tobs4 of the skipped frame, the switching transistors T7 and T8 may be turned on in response to the second scan signal SC2 (n), and the other switching transistors T2 to T6 may be turned off.

[0119] The operations of the third and fourth OBS periods Tobs3 and Tobs4 of the skip frame may be substantially the same as the operations of the first and second OBS periods Tobs1 and Tobs2 of the refresh frame, and thus may be omitted or simply provided.

[0120] The first and second OBS periods Tobs1 and Tobs2 of the refresh frame may be included in the off voltage period of the emission control signal EM(n), and the third and fourth OBS periods Tobs3 and Tobs4 of the skip frame may be included in the off voltage period of the emission control signal EM(n).

[0121] The lengths of the off voltage period of the light emitting control signal EM(n) may be equal to each other in the refresh frame and the skip frame, and thus the lengths of the light emitting sustaining time may be equal to each other in the refresh frame and the skip frame.

[0122] Figure 11 is a diagram for explaining the operation of a pixel over a light emitting period of a skipped frame.

[0123] Reference Figure 11 , in the light emitting period Te of the skipped frame, the switching transistors T4 and T5 may be turned on in response to the light emitting control signal EM(n), and the other switching transistors T2, T3, and T6 to T8 may be turned off.

[0124] In the emission period Te of the skipped frame, the driving current Ioled supplied from the driving transistor T1 to the light emitting device OLED may have the same magnitude as that of the driving current Ioled in the emission period Te of the refresh frame.

[0125] Figure 12 and Figure 13 is a diagram showing an example in which a luminance deviation occurring between a refresh frame and a skip frame is greater in a high grayscale than in a low grayscale.

[0126] refer to Figure 12 and Figure 13 Due to variations in leakage characteristics in LTPS-based pixels, a luminance deviation ΔL1 or ΔL2 may occur between refresh frames and skipped frames. Factors causing variations in leakage characteristics may include leakage current in LTPS-based pixels or coupling effects in LTPS-based pixels.

[0127] Such brightness deviation can increase with increasing data refresh period, increasing number of skipped frames and decreasing frame frequency. This may be due to poor data retention capability in skipped frames in LTPS-based pixels.

[0128] The luminance deviation ΔL1 or ΔL2 between the refresh frame and the skipped frame may vary based on the design layout of the pixels.

[0129] When the potential at the gate of the driving transistor increases more in the skip frame than in the refresh frame due to leakage current or coupling (for example, when leakage current / coupling occurs between the gate of the driving transistor and the input terminal of ELVDD), the brightness of the skip frame may be lower than that of the refresh frame by ΔL1, as shown in FIG. Figure 12 shown.

[0130] When the potential at the gate of the driving transistor decreases more in the skip frame than in the refresh frame due to leakage current or coupling (for example, when leakage current / coupling occurs between the gate of the driving transistor and the input terminal of Vint), the brightness of the skip frame may be higher than that of the refresh frame by ΔL2, as shown in FIG. Figure 13 shown.

[0131] The luminance deviation ΔL1 or ΔL2 may appear significantly in a high grayscale period near the white grayscale. However, in a low grayscale period close to the black grayscale, the luminance deviation ΔL1 or ΔL2 between the refresh frame and the skipped frame may not be recognized.

[0132] Therefore, a method may be needed to compensate for the brightness deviation of the high grayscale period without affecting the low grayscale period.

[0133] Figure 14 and Figure 15 is a diagram illustrating an example of differently setting an OBS voltage applied to pixels in a refresh frame and an OBS voltage applied to pixels in a skip frame.

[0134] The present embodiment may differentially apply the OBS voltage of the refresh frame and the OBS voltage of the skip frame to arbitrarily cause a difference in the threshold voltage Vth of the driving transistor, and thus, may compensate for a luminance deviation between the refresh frame and the skip frame.

[0135] Based on Figure 12 In the case where the brightness of the skipped frame is lower than the brightness of the refreshed frame by ΔL1, the present embodiment can also be as follows Figure 14 In this way, the OBS voltage Vb of the skipped frame is set to be smaller than the OBS voltage Va of the refresh frame, so that the driving current formula "Ioled=(Vgs-Vth) 2 ”, the luminance of the skipped frame can be increased in such a manner that the absolute value of Vth decreases. As a result, the luminance deviation equal to ΔL1 can be compensated.

[0136] Based on Figure 13 In the case where the brightness of the skipped frame is higher than the brightness of the refreshed frame by ΔL1, the present embodiment can also be as follows Figure 15 The OBS voltage Vc of the skip frame is set to be greater than the OBS voltage Va of the refresh frame. Therefore, in the driving current formula "Ioled=(Vgs-Vth) 2 ”, the brightness of the skipped frame can be reduced in such a manner that the absolute value of Vth increases. Therefore, the brightness deviation equal to ΔL2 can be compensated.

[0137] As described above, when the OBS voltage of the refresh frame and the OBS voltage of the skip frame are differentially applied, the luminance deviation of the high grayscale period can be effectively compensated without affecting the low grayscale period.

[0138] Figure 16 is a diagram showing a connection configuration between an OBS controller and pixels.

[0139] refer to Figure 16 The display device according to this embodiment may further include a bias controller 115 that may apply the OBS voltage VOBS differently in a refresh frame and a skip frame.

[0140] The bias controller 115 may be provided in the source driver 110 , but is not limited thereto. The bias controller 115 may be mounted on a printed circuit board (PCB) independently of the source driver 110 .

[0141] The bias controller 115 may output the OBS voltage VOBS of a first level to the OBS power line in the refresh frame, and may output the OBS voltage VOBS of a second level different from the first level to the OBS power line in the skip frame.

[0142] The OBS supply line may include a main line ML and a branch line BL. The main line ML may be provided in the bezel region BZ of the display panel 100. The branch line BL may branch from the main line ML and may be connected to the pixel SP of the screen AA. The branch line BL may be arranged in parallel with the gate line.

[0143] The OBS voltage VOBS output from the bias controller 115 may be provided to the pixel SP through the main line ML and the branch line BL.

[0144] Figure 17 and Figure 18 is a graph showing an example in which a difference between OBS voltages applied to pixels in a refresh frame and a skip frame varies based on a frame frequency.

[0145] The number of skipped frames (ie, holding time) of brightness change can be changed based on the frame frequency, and thus the voltage difference to be compensated with Vth can be changed. Therefore, the OBS voltage difference between refresh frames and skipped frames is usually set differently based on the frame frequency.

[0146] like Figure 17 As shown, as the frame frequency decreases, the OBS voltage difference between the refresh frame and the skipped frame can increase. The OBS voltage VOBS of the refresh frame can be fixed to V1 regardless of the frame frequency, and as the frame frequency decreases, the OBS voltage VOBS of the skipped frame can be controlled downward to a voltage range lower than V1.

[0147] Specifically, at 120 Hz, which consists only of the refresh frequency RF, the OBS voltage VOBS may be V1. At 60 Hz, where one skip frame SF is provided between adjacent refresh frames RF, the OBS voltage VOBS of the skip frame may be V2, which is lower than V1. At 30 Hz, where three skip frames SF are provided between adjacent refresh frames RF, the OBS voltage VOBS of the skip frame may be V3, which is lower than V2. At 30 Hz, the OBS voltage VOBS of the skip frame may be gradually reduced within a voltage range lower than V1. In this case, the OBS voltages VOBS between the three skip frames SF may be V4, V5, and V6, and may be different.

[0148] like Figure 18 As shown, as the frame frequency decreases, the OBS voltage difference between the refresh frame and the skipped frame can increase. The OBS voltage VOBS of the refresh frame can be fixed to V11 regardless of the frame frequency, and as the frame frequency decreases, the OBS voltage VOBS of the skipped frame can be controlled upward within a voltage range higher than V11.

[0149] Specifically, at 120 Hz, which consists only of the refresh frequency RF, the OBS voltage VOBS may be V11. At 60 Hz, where one skipped frame SF is provided between adjacent refresh frames RF, the OBS voltage VOBS of the skipped frame may be V12, which is higher than V11. At 30 Hz, where three skipped frames SF are provided between adjacent refresh frames RF, the OBS voltage VOBS of the skipped frame may be V13, which is higher than V12. At 30 Hz, the OBS voltage VOBS of the skipped frame may gradually increase within a voltage range higher than V11. In this case, the OBS voltages VOBS between the three skipped frames SF may be V14, V15, and V16, and may be different.

[0150] Figure 19 is a diagram illustrating an EM duty cycle control technique for further reducing the luminance deviation between a refresh frame and a skipped frame.

[0151] Reference Figure 19 The gate driver according to the present embodiment may provide a light emission control signal EM based on pulse width modulation (PWM) to the pixel for controlling the on and off timing of the light emitting device included in the pixel.

[0152] As described above, under low-speed driving conditions (e.g., 30 Hz) with skipped frames SF, a luminance deviation ΔL may sometimes occur between refresh frames RF and skipped frames SF. In this case, by differentially controlling the off-duty ratio of the light-emission control signal EM without fully controlling it, the luminance deviation ΔL can be reduced. When the luminance deviation ΔL between refresh frames RF and skipped frames SF is reduced, the control range of the OBS voltage VOBS used to compensate for the luminance deviation can be reduced, thereby reducing power consumption.

[0153] Figure 20 and Figure 21 is a diagram showing an example of reducing the control range of the OBS voltage through the EM duty cycle control technique.

[0154] Reference Figure 20 and Figure 21 In the comparative example, in order to reduce the brightness deviation between the refresh frame RF and the skipped frame SF, the on-duty ratio in the skipped frame SF can be increased more than that in the refresh frame RF. However, in this case, the side effect may be that the brightness deviation in the high grayscale period is reduced, but the brightness deviation in the low grayscale period is increased.

[0155] In the present embodiment, the on-duty ratios of the light emitting control signal EM may be equal to each other in the refresh frame RF and the skip frame SF, and thus, the luminance deviation may not be removed in the low grayscale period.

[0156] Furthermore, the present embodiment can dualize and differently set the off duty ratio of the light emitting control signal EM in the refresh frame RF and the skip frame SF, and can thus reduce the brightness deviation of the high grayscale period.

[0157] The off-duty ratio of the light emitting control signal EM according to the present embodiment may include a first off-duty ratio and a second off-duty ratio longer than the first off-duty ratio.

[0158] The first off-duty cycle may be set between the on-duty cycle of the refresh frame RF and the on-duty cycle of the skip frame SF. In addition, the second off-duty cycle may be set before the first on-duty cycle of the refresh frame RF, after the last on-duty cycle of the skip frame SF, and between the last on-duty cycle of the refresh frame RF and the first on-duty cycle of the skip frame SF.

[0159] When the first and second off-duty ratios are set as described above, a difference between the maximum (Max) luminance of the refresh frame RF and the minimum (Min) luminance of the skip frame SF may be reduced.

[0160] The present disclosure can achieve the following effects.

[0161] The present disclosure may differentially apply the OBS voltage in a refresh frame and a skip frame to reduce a luminance deviation caused by a leakage characteristic variation occurring between the refresh frame and the skip frame, and thus, may enhance display quality.

[0162] Effects according to the present disclosure are not limited to the above-described examples, and may include other various effects.

[0163] The features of the various embodiments of the present disclosure may be coupled or combined, in part or in whole, and may operate in conjunction with each other in various ways and be driven in a manner that will be fully understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of each other or together in an interdependent relationship.

[0164] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the technical concept and scope of the disclosure as defined by the appended claims.

[0165] CROSS-REFERENCE TO RELATED APPLICATIONS

[0166] This application claims the benefit of Korean Patent Application No. 10-2024-0050105, filed on April 15, 2024, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A display device, comprising: a display panel, the display panel comprising at least one pixel; a source driver configured to output a data voltage to be supplied to the at least one pixel in a refresh frame and stop outputting the data voltage to be supplied to the at least one pixel in at least one skip frame following the refresh frame; as well as a bias controller configured to output a first on-bias stress voltage to be supplied to the at least one pixel in the refresh frame and to output a second on-bias stress voltage to be supplied to the at least one pixel in the at least one skip frame, wherein the first on-bias stress voltage and the second on-bias stress voltage are applied to one electrode of a driving transistor included in the at least one pixel to improve brightness difference caused by variation in leakage characteristics of the at least one pixel, and The first on-bias stress voltage and the second on-bias stress voltage are set differently so that a threshold voltage characteristic of the driving transistor is different in the refresh frame and the at least one skipped frame.

2. The display device according to claim 1, wherein A voltage difference between the first on-bias stress voltage and the second on-bias stress voltage is determined based on a number of skipped frames following the refresh frame.

3. The display device according to claim 1, wherein A voltage difference between the first on-bias stress voltage and the second on-bias stress voltage increases in proportion to the number of skipped frames following the refresh frame.

4. The display device according to claim 3, wherein When the number of skipped frames following the refresh frame is plural, the second on-bias stress voltages corresponding to the at least one skipped frame are equal to each other.

5. The display device according to claim 3, wherein When the number of skipped frames following the refresh frame is plural, the second on-bias stress voltages corresponding to the at least one skipped frame are different from each other. The display device according to claim 1 , wherein: When the brightness of the at least one skipped frame is lower than the brightness of the refresh frame, the second on-bias stress voltage is lower than the first on-bias stress voltage.

7. The display device according to claim 1, wherein When the brightness of the at least one skipped frame is higher than the brightness of the refresh frame, the second on-bias stress voltage is higher than the first on-bias stress voltage.

8. The display device according to claim 1 , further comprising a gate driver configured to provide a light emitting control signal to the at least one pixel based on pulse width modulation to control on and off timing of the light emitting device included in the at least one pixel. in, The off-duty ratio of the light emitting control signal includes a first off-duty ratio and a second off-duty ratio that is longer than the first off-duty ratio.

9. The display device according to claim 8, wherein The first off-duty cycle is set between the on-duty cycles of the refresh frame and the on-duty cycle of the at least one skipped frame, and The second off-duty cycle is set immediately before the first on-duty cycle of the refresh frame, immediately after the last on-duty cycle of the at least one skipped frame, and between the last on-duty cycle of the refresh frame and the first on-duty cycle of the at least one skipped frame.

10. The display device according to claim 8, wherein The on-duty ratio of the light emitting control signal is the same in length in the refresh frame and the at least one skipped frame.

11. A method for driving a display device, the display device comprising a display panel, the display panel comprising at least one pixel, the method comprising the following steps: outputting a data voltage to be supplied to the at least one pixel in a refresh frame, and stopping outputting the data voltage to be supplied to the at least one pixel in at least one skip frame following the refresh frame; as well as outputting a first on-bias stress voltage to be supplied to the at least one pixel in the refresh frame, and outputting a second on-bias stress voltage to be supplied to the at least one pixel in the at least one skip frame, wherein the first on-bias stress voltage and the second on-bias stress voltage are applied to one electrode of a driving transistor included in the at least one pixel to improve brightness difference caused by variation in leakage characteristics of the at least one pixel, and The first on-bias stress voltage and the second on-bias stress voltage are set differently so that a threshold voltage characteristic of the driving transistor is different in the refresh frame and the at least one skipped frame.

12. The driving method according to claim 11, wherein: A voltage difference between the first on-bias stress voltage and the second on-bias stress voltage is determined based on a number of skipped frames following the refresh frame.

13. The driving method according to claim 11, wherein: A voltage difference between the first on-bias stress voltage and the second on-bias stress voltage increases in proportion to the number of skipped frames following the refresh frame.

14. The driving method according to claim 13, wherein: When the number of skipped frames following the refresh frame is plural, the second on-bias stress voltages corresponding to the at least one skipped frame are equal to each other.

15. The driving method according to claim 13, wherein: When the number of skipped frames following the refresh frame is plural, the second on-bias stress voltages corresponding to the at least one skipped frame are different from each other.

16. The driving method according to claim 11, wherein: When the brightness of the at least one skipped frame is lower than the brightness of the refresh frame, the second on-bias stress voltage is lower than the first on-bias stress voltage.

17. The driving method according to claim 11, wherein: When the brightness of the at least one skipped frame is higher than the brightness of the refresh frame, the second on-bias stress voltage is higher than the first on-bias stress voltage.

18. The driving method according to claim 11, further comprising the following steps: providing a light emitting control signal to the at least one pixel based on pulse width modulation to control on and off timing of a light emitting device included in the at least one pixel, The off duty cycle of the light emitting control signal includes a first off duty cycle and a second off duty cycle that is longer than the first off duty cycle.

19. The driving method according to claim 18, wherein: The first off-duty cycle is set between the on-duty cycles of the refresh frame and the on-duty cycle of the at least one skipped frame, and The second off-duty cycle is set immediately before the first on-duty cycle of the refresh frame, immediately after the last on-duty cycle of the at least one skipped frame, and between the last on-duty cycle of the refresh frame and the first on-duty cycle of the at least one skipped frame.

20. The driving method according to claim 18, wherein: The on-duty ratio of the light emitting control signal is the same in length in the refresh frame and the at least one skipped frame.

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