Rendering processing method and device, electronic equipment and storage medium

Abstract

The invention provides a rendering processing method and device, electronic equipment and a storage medium. The method comprises the steps that first configuration information of a depth range test DBT called by current first drawing of a rendering object is acquired; determining first driving information of the depth range test of the first drawing call according to the first configuration information, second configuration information of the depth range test of the first drawing call and second driving information of the depth range test of a previous second drawing call under the condition that the on-off state of the depth range test is turned on; the depth range test comprises an early DBT and a later DBT, and the first driving information comprises a first enabling flag of the early DBT, a second enabling flag of the later DBT and a second depth interval; and generating instruction information according to the first driving information and sending the instruction information to the graphics processing equipment, so that the graphics processing equipment executes a depth range test in the first drawing call based on the instruction information. According to the embodiment of the invention, the rendering efficiency can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of graphics processing technology, and in particular to a rendering processing method and device, an electronic device, and a computer-readable storage medium. Background Art

[0002] Graphics processing technology refers to the use of various hardware and software devices to process two- or three-dimensional visuals and images to achieve specific rendering effects. A graphics processing device can refer to a device used to perform graphics processing operations, such as a graphics processing unit (GPU) or other similar devices. During the graphics rendering process, minimizing expensive pixel shader (PS) calls is a key goal in order to optimize the overall performance of the graphics processing device and reduce power consumption.

[0003] Various rendering architectures in related technologies typically employ a depth test (Z-Test). This compares the depth values ​​of fragments at the same location to ensure that only the most foremost (i.e., visible) pixels are ultimately displayed. This not only ensures the correct visibility order but also filters out occluded fragments, thereby reducing unnecessary pixel shader execution. However, related technologies often fail to adequately filter fragments, resulting in low rendering efficiency. Summary of the Invention

[0004] The present disclosure provides a rendering processing method and device, an electronic device, and a computer-readable storage medium.

[0005] In a first aspect, the present disclosure provides a rendering processing method, comprising: obtaining first configuration information of a depth range test (DBT) for a current first draw call of a rendering object, the first configuration information including a switch state of the depth range test and a first depth interval; when the switch state of the depth range test is on, determining first driver information of the depth range test for the first draw call based on the first configuration information, second configuration information of the depth test for the first draw call, and second driver information of the depth range test for a second draw call; wherein the second draw call is a preceding draw call of the rendering object; the depth range test includes an early DBT and a late DBT, the first driver information including a first enable flag of the early DBT, a second enable flag of the late DBT, and a second depth interval of the depth range test; and generating instruction information based on the first driver information and transmitting the instruction information to a graphics processing device, so that the graphics processing device performs the depth range test in the first draw call based on the instruction information.

[0006] In a second aspect, the present disclosure provides a rendering processing method, comprising: obtaining first driver information of a depth range test (DBT) for a current first draw call of a rendering object, the depth range test including an early DBT and a late DBT, the first driver information including a first enable flag for the early DBT, a second enable flag for the late DBT, and a second depth interval for the depth range test; in response to the first draw call, rasterizing a first primitive in a tile of the rendering object to obtain a corresponding first fragment; when the first enable flag is valid, performing a depth range test on the first fragment according to a second depth interval to obtain an early DBT result for the first fragment; when the early DBT result of the first fragment passes, performing an early depth test and rendering processing on the first fragment, and obtaining a rendered second fragment if the early depth test passes; when the second enable flag is valid, performing a depth range test on the second fragment according to the second depth interval to obtain a late DBT result for the second fragment; when the late DBT result of the second fragment passes, performing a late depth test and rendering processing on the second fragment, and obtaining rendered first pixel data if the late depth test passes.

[0007] In a third aspect, the present disclosure provides a rendering processing device, comprising: a configuration information acquisition module, configured to acquire first configuration information of a depth range test (DBT) for a first draw call currently performing a rendering object, the first configuration information including an on / off state and a first depth interval of the depth range test; a driver information determination module, configured to determine, when the on / off state of the depth range test is on, first driver information for the depth range test of the first draw call based on the first configuration information, second configuration information of the depth test of the first draw call, and second driver information for the depth range test of a second draw call; wherein the second draw call is a preceding draw call of the rendering object; the depth range test includes an early DBT and a late DBT, the first driver information including a first enable flag of the early DBT, a second enable flag of the late DBT, and a second depth interval of the depth range test; and an instruction sending module, configured to generate instruction information based on the first driver information and send the instruction information to a graphics processing device, causing the graphics processing device to perform the depth range test in the first draw call based on the instruction information.

[0008] In a fourth aspect, the present disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the above-mentioned rendering processing method.

[0009] In a fifth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above-mentioned rendering processing method when executed by a processor.

[0010] In a sixth aspect, the present disclosure provides a computer program product comprising a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above-mentioned rendering processing method.

[0011] The embodiments provided by the present disclosure can combine a depth bounds test (DBT) with a depth test to obtain the depth bounds test configuration information for the current draw call. Based on the DBT configuration and depth test configuration of the previous draw call and the depth test configuration of the current draw call, the DBT driver information for the current draw call is determined. Furthermore, corresponding instruction information is generated and issued, causing a graphics processing device to perform a depth bounds test. This further eliminates invalid fragments based on the depth test, reduces unnecessary pixel shader execution, and improves rendering efficiency.

[0012] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings. In the accompanying drawings:

[0014] Figure 1 A schematic diagram of a rendering architecture of related technologies.

[0015] Figure 2 A schematic diagram of a rendering architecture of related technologies.

[0016] Figure 3A flowchart of a rendering processing method provided by an embodiment of the present disclosure.

[0017] Figure 4 A schematic diagram of a rendering architecture provided in an embodiment of the present disclosure.

[0018] Figure 5 A schematic diagram of the switch status of the depth test provided in an embodiment of the present disclosure.

[0019] Figure 6 A schematic diagram of the processing process of depth testing and depth range testing provided in an embodiment of the present disclosure.

[0020] Figure 7 A schematic diagram of the processing process of depth testing and depth range testing provided in an embodiment of the present disclosure.

[0021] Figure 8 A schematic diagram illustrating the switching states of the depth test and depth range test provided in an embodiment of the present disclosure.

[0022] Figure 9 A flowchart of a rendering processing method provided by an embodiment of the present disclosure.

[0023] Figure 10 A block diagram of a rendering processing device provided in an embodiment of the present disclosure.

[0024] Figure 11 A block diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] To enable those skilled in the art to better understand the technical solutions of the present disclosure, exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0026] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0027] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0029] Before introducing the embodiments of the present disclosure in detail, some related concepts are first explained for the sake of clarity.

[0030] A render target may refer to an object to be rendered, which may be a part of a virtual scene to be rendered, or may be a picture or video frame to be rendered.

[0031] A primitive refers to the basic geometric shapes that make up a graphic, such as a point, line, triangle, etc. For example, a graphic drawn by an application can be represented in a computer by stitching together a large number of basic geometric shapes.

[0032] The rendering pipeline is a key concept in computer graphics. It is a stage within the graphics processing unit (GPU) responsible for processing and transforming graphics data for rendering. The rendering pipeline's primary task is to convert input geometric primitives (such as points, lines, triangles, etc.) into visible pixels on the screen. The goal of the rendering pipeline is to efficiently process the graphics and produce the final image. Through parallel processing and specialized hardware support, the GPU is able to perform these calculations quickly, enabling real-time graphics rendering.

[0033] In related technologies, in order to optimize the overall performance of graphics processing devices and reduce power consumption, reduce pixel shader (PS) calls, and ensure that the GPU can still maintain high efficiency and low energy consumption when rendering high-resolution and complex scenes, there are multiple rendering processing methods.

[0034] In some embodiments, the rendering processing method of the related art includes Immediate Mode Rendering (IMR). Its core feature is that after processing, primitives are directly written to the global frame buffer without the need for block processing. IMR can use a standard depth test (Z-test), also known as a visibility test, or an early depth test (Early-Z).

[0035] Among them, Z-Test compares the depth values ​​of each fragment at the same position to ensure that only the front-most (visible) pixels are finally displayed. It not only ensures the correct visibility order, but also filters out obscured fragments, thereby reducing unnecessary pixel shader execution. Early-Z advances the depth test from after the pixel shader to after the rasterization stage and before the pixel shader, so that the depth comparison of the fragments can be performed as early as possible after rasterization, and those obviously invisible pixels are quickly eliminated. The elimination is completed before officially entering the high-cost PS stage, which greatly reduces the burden of subsequent fragment shading and effectively reduces unnecessary computing resource consumption and energy consumption.

[0036] In some embodiments, other related technologies of depth testing include Coarse-Z (coarse-grained depth testing, which usually calculates the depth range (minimum / maximum value) for a larger area (such as a block composed of multiple pixels) instead of fine processing pixel by pixel, which is used to quickly eliminate obviously occluded areas and reduce subsequent calculations), Hierarchical-Z (hierarchical depth testing, organizing depth buffer data in a pyramid-like hierarchy (such as a multi-level depth map from full resolution to low resolution), quickly judging the visibility of a large area through a high-level depth range, and then refining it layer by layer to the pixel level, which is an efficient occlusion removal technology), etc., and the present disclosure does not impose any restrictions on this.

[0037] Figure 1 This is a schematic diagram of a rendering architecture of the related technology, which is a schematic diagram of the IMR rendering pipeline. Figure 1 As shown, the rendering pipeline may include vertex processing 11; clip, project / cull 12; rasterization 13; early depth test (also known as early visibility test) 14; texture and shade 15; alpha test 16; late depth test (also known as late visibility test) 17; and alpha blend 18.

[0038] Among them, the graphics processing device can read geometry data from the system memory, and obtain primitives through vertex processing 11 and clipping, projection and culling 12 stages; the primitives are subjected to rasterization 13 to obtain corresponding fragments; the fragments are subjected to depth comparison through early depth test 14, and the obscured fragments are eliminated; the fragments that pass the early depth test 14 are subjected to texture and shadow processing based on the texture data read from the system memory in the texture and shadow stage 15, and then an alpha test 16 is performed; the fragments that pass the alpha test 16 will undergo a post-depth test 17 based on the depth buffer, and then alpha blending 18 with the data in the frame buffer to obtain the rendering result, such as the pixel data to be output.

[0039] It should be understood that the above is only a schematic diagram of the IMR rendering pipeline. Those skilled in the art can set the specific structure of various rendering pipelines according to actual conditions, and this disclosure does not limit this.

[0040] In some embodiments, the rendering processing method of the related technology also includes tile-based rendering (Tiled-Based Rendering, TBR). This processing method divides the rendering object into multiple tiles (tiles), and uses a local cache within each tile to perform depth testing and other preliminary processing. When rendering, the direct rendering target is no longer the current frame buffer and depth buffer, but a high-speed cache called a tile buffer, also known as an on-chip buffer. As a result, the read and write operations of the frame buffer and depth buffer in the IMR are changed to read and write operations of the high-speed memory in the GPU. Taking advantage of locality, global memory access is reduced, bandwidth consumption and power consumption are reduced, and overdrawing is effectively reduced.

[0041] In some embodiments, the rendering processing method of the related technology also includes tile-based deferred rendering (TBDR). TBDR further delays fragment shading processing on the basis of TBR, and performs hidden surface removal (HSR) through hardware-level features to solve the overdraw problem. First, the geometric data and depth information within each tile are collected, and delayed depth testing and culling are performed centrally. Expensive PS calculations are only performed on actually visible and valid fragments. The basic idea is: do not draw pixels that pass the early depth test (Early Z-Test) immediately, but only mark the primitives of these pixels, and only draw the marked pixels that eventually pass the HSR. In this way, the system memory bandwidth requirements can be significantly reduced, thereby minimizing invalid calculations and power consumption.

[0042] Figure 2 This is a schematic diagram of a rendering architecture of related technologies, and a schematic diagram of a TBDR rendering pipeline. Figure 2 As shown, the rendering pipeline may include vertex processing 21; clip, project and culling (clip, project / cull) 22; tiling 23; rasterization 24; early visibility test 25; texture and shade 26; alpha test 27; late depth test 28; and alpha blend 29.

[0043] The graphics processing device reads geometry data from system memory and, after vertex processing 21 and clipping, projection, and culling 22, obtains the primitives of the rendered object. Tiling 23 completes the segmentation of the rendered object, records the graphics data covering each tile, including the primitive list and vertex data, and writes them to system memory. For a tile, the rendering pipeline loads all the primitives (such as triangles) it contains into the fragment stage for processing. All primitives covering that tile can be directly read from the corresponding primitive list. Once all the primitives of a tile have been processed, processing can proceed to the next tile.

[0044] The primitives of each tile are rasterized 24 to obtain corresponding fragments. The fragments are compared with the depth of the early depth test 25, and occluded fragments are eliminated. Fragments that pass the early depth test 25 undergo texture and shading processing based on the texture data in system memory in the texture and shading stage 26, and then undergo alpha testing 27. Fragments that pass the alpha test 27 undergo a late depth test 28 based on the on-chip depth buffer. The fragments that pass the alpha test are alpha blended 29 with the data in the on-chip color buffer to obtain the rendering result, such as the pixel data to be output. The on-chip depth buffer exchanges data with the depth buffer in system memory, and the on-chip color buffer exchanges data with the frame buffer in system memory.

[0045] It should be understood that the above is only a schematic diagram of the TBDR rendering pipeline. Those skilled in the art can set the specific structure of various rendering pipelines according to actual conditions, and this disclosure does not limit this.

[0046] In general, technologies such as IMR, TBR, and TBDR are all optimized around reducing unnecessary fragment shading (also known as PS calls). By filtering out unnecessary fragments in advance at different stages, they can not only improve rendering efficiency but also reduce overall energy consumption, making them suitable for real-time rendering needs in high-resolution and complex scenes.

[0047] However, although relevant technologies have achieved certain results in improving performance, they still have the following shortcomings:

[0048] Redundancy in Full-Range Depth Comparison: Traditional depth testing only compares the depth value of the current fragment with the corresponding position in the frame buffer, failing to limit the depth range based on scene requirements. For example, when rendering only objects within a specific depth range (such as near the water surface), traditional methods process all fragments, even if they are outside the target range, resulting in unnecessary fragment shader calculations and wasted bandwidth.

[0049] Multi-stage rendering overhead for complex scenes: Certain effects (such as local shadows and refraction) require rendering the same area multiple times at different depths. Developers need to implement these effects through multiple draw calls or complex layered rendering logic, which increases the overhead of CPU-GPU communication and state switching.

[0050] Inefficient processing of transparency and blending effects: Rendering of transparent objects typically relies on depth write disabling and sorting, but traditional depth testing cannot flexibly control the blending area, which may lead to overdraw or sorting errors.

[0051] Limitations of Hidden Surface Removal (HSR): HSR technology relies on the accuracy of occlusion information. In dynamic or complex scenes, it may not be possible to effectively remove all occluded fragments, resulting in invalid PS calls and performance degradation.

[0052] According to the rendering processing method of the embodiment of the present disclosure, the depth bounds test (DBT) can be combined with the depth test (Z-test), allowing the user layer to configure the DBT in a draw call and obtain the configuration information of the depth range test of the current draw call at the driver layer; the DBT driver information of the current draw call is determined based on the DBT configuration and depth test configuration of the previous draw call and the depth test configuration of the current draw call; then, the corresponding instruction information is generated and issued, so that the graphics processing device performs the depth range test, thereby further removing invalid fragments based on the depth test, reducing unnecessary pixel shader execution, improving rendering efficiency, and reducing overall power consumption.

[0053] Moreover, according to the rendering processing method of the embodiment of the present disclosure, the depth range test can be divided into early DBT (Early-DBT) and late DBT (Late-DBT); and early DBT is coordinated with early depth test (Early-Z), and late DBT is coordinated with late depth test (Late-Z), which can reduce unnecessary calculations of early depth test and late depth test, and can optimize performance and ensure the correctness of DBT results respectively.

[0054] The rendering processing method according to the embodiments of the present disclosure can be executed by an electronic device such as a terminal device or a server. The terminal device can be an in-vehicle device, a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, an in-vehicle device, a wearable device, etc. The method can be implemented by a processor calling computer-readable program instructions stored in a memory. Alternatively, the method can be executed by a server.

[0055] Figure 3 This is a flowchart of a rendering processing method provided by an embodiment of the present disclosure. The method can be executed by a processing device in a terminal device, such as a central processing unit (CPU). Figure 3 , the method comprising:

[0056] In step S31 , first configuration information of a depth range test DBT of a current first draw call of a rendering object is obtained, where the first configuration information includes a switch state of the depth range test and a first depth interval.

[0057] In step S32 , when the depth range test is on, first driver information for the depth range test of the first draw call is determined based on the first configuration information, the second configuration information for the depth range test of the first draw call, and the second driver information for the depth range test of the second draw call.

[0058] The second draw call is a preceding draw call of the rendering object; the depth range test includes an early DBT and a late DBT; and the first driver information includes a first enable flag of the early DBT, a second enable flag of the late DBT, and a second depth interval of the depth range test.

[0059] In step S33 , instruction information is generated according to the first driving information and sent to a graphics processing device, so that the graphics processing device performs the depth range test in the first draw call based on the instruction information.

[0060] For example, the depth range test DBT technology allows only fragments whose depth values ​​are within a specified depth range to be processed during the rendering process, thereby eliminating fragments that do not need to be calculated. DBT can be set to execute after the shear test (Scissor-Test) and before the depth test (Z-Test). Unlike the depth test, DBT does not rely on interpolation calculations or the depth value output by the fragment shader, but makes judgments based on the depth value stored in the current depth buffer. DBT can further refine the culling in the depth direction (Z direction). Combined with the depth test, DBT can minimize the generation of useless fragments and shader calls in scenarios such as template shadow volumes, volumetric lights, or deferred rendering, thereby improving the efficiency of the rendering pipeline and application performance.

[0061] In some possible implementations, a corresponding interface can be configured at the user level of the processing device, allowing users to configure depth range test parameters in each draw call. This interface can adopt a standardized interface provided by graphics APIs (Application Programming Interfaces), such as Direct3D (a low-level graphics API optimized for the Windows platform), Vulkan (a cross-platform open source graphics API), and OpenGL (a cross-platform graphics API standard). This disclosure does not limit the specific type of interface.

[0062] In some possible implementations, a corresponding DBT module can be set up at the hardware layer of a graphics processing device (e.g., a GPU) to implement the DBT function. Depth range testing includes early DBT (Early-DBT) and late DBT (Late-DBT). Early DBT is set before the Early-Z depth test, while late DBT is set before the Late-Z depth test to remove invalid fragments in advance.

[0063] In some possible implementations, the parameters of the depth range test may include the switch state and depth interval of the depth range test. The switch state includes on or off. If the user wishes to disable the DBT function, the switch state is set to off; if the user wishes to enable the DBT function, the switch state is set to on. The depth interval may include the minimum depth value and maximum depth value (zmin, zmax) of the floating-point type FLOAT, which are used to limit the depth range tested by DBT. The maximum range of the depth interval can be [0.0f, 1.0f], or it can be set to be less than the maximum range, for example, [0.3f, 0.7f]. The parameters of the depth range test may also include other parameters, which are not limited by the present disclosure.

[0064] In some possible implementations, for a current first draw call of a rendering object, a driver layer of the processing device may obtain first configuration information of the first draw call in step S31 , including a switch state of a depth range test and a first depth interval.

[0065] In some possible implementations, if the switch is on, first driver information for the depth range test of the first draw call may be determined in step S32 based on the first configuration information, the second configuration information for the depth test of the first draw call, and the second driver information for the depth range test of the second draw call. The second draw call is a predecessor of the first draw call, such as a previous draw call for the same tile; the first driver information includes a first enable flag for early DBT, a second enable flag for the late DBT, and a second depth interval for the depth range test.

[0066] In some possible implementations, the depth test includes an early depth test and a late depth test, and the second configuration information for the depth test includes an enable flag for the early depth test and an enable flag for the late depth test. The second driver information for the depth range test of the second draw call may include enable flags for the early DBT and the late DBT, a third depth interval for the depth range test of the second draw call, and the like.

[0067] In some possible implementations, in step S32, data verification and conversion can be performed on the first depth interval. Data verification may include checking whether the minimum depth value zmin and the maximum depth value zmax of the first depth interval are NAN (Not a Number); if NAN exists, converting the NaN to 0.0f; checking the range of zmin and zmax and performing a clamp operation to [0.0f, 1.0f], that is, limiting values ​​outside the range of [0.0f, 1.0f] to the interval of [0.0f, 1.0f]; then checking whether zmin <= zmax is satisfied. If so, the process passes; if not, a warning is sent to the runtime. Furthermore, subsequent steps can still be performed, and the hardware will still process zmin <= zmax and determine it as a failure.

[0068] In some possible implementations, the adjusted zmin and zmax values ​​can be mapped to corresponding integer or floating-point values ​​based on the depth buffer (z-buffer) data format to obtain the second depth range. Depth buffer data formats include, for example, D16_UNORM (16-bit integer), D24_UNORM (24-bit integer), and D32_FLOAT (32-bit floating-point number). The floating-point interval [0.0f, 1.0f] can be converted to D16_UNORM and represented as [0, 65535]. This disclosure does not limit the specific data format of the depth buffer.

[0069] In some possible implementations, a first Early-DBT enabled flag and a second Late-DBT enabled flag can be determined based on first configuration information, second configuration information for the depth test of the first draw call, and second driver information for the depth range test of the second draw call. In other words, a dynamic decision can be made to enable Early-DBT and / or Late-DBT based on the configuration status of the current draw call and the preceding draw call, ensuring that the DBT function meets data dependencies and restrictions, avoiding potential processing errors, and configuring the corresponding enable flags to generate driver information.

[0070] In some possible implementations, the driver layer may package and transmit data in step S33, generating instruction information based on the first driver information. Specifically, the instruction information may encode the first enable flag, the second enable flag, and the second depth interval into a hardware instruction packet. The instruction information may also include an identifier of the depth buffer data format to facilitate the hardware module of the graphics processing device to adapt comparison logic, etc., but this disclosure does not limit this.

[0071] In some possible implementations, the generated instruction information is sent to a graphics processing device; after receiving the instruction information, the graphics processing device may perform a depth range test in the first draw call based on the instruction information, thereby implementing a DBT function.

[0072] According to the embodiments of the present disclosure, the depth range test can be combined with the depth test to obtain the configuration information of the depth range test of the current draw call; the DBT driver information of the current draw call is determined based on the DBT configuration and depth test configuration of the previous draw call and the depth test configuration of the current draw call; and then the corresponding instruction information is generated and issued, so that the graphics processing device performs the depth range test, thereby further removing invalid fragments based on the depth test, reducing unnecessary pixel shader execution, improving rendering efficiency, and reducing overall power consumption.

[0073] The rendering processing method according to an embodiment of the present disclosure is described below.

[0074] In some possible implementations, a rendering method for a render object includes tile-based deferred rendering (TBDR), where the render object is divided into multiple tiles. Specifically, the rendering processing method according to the present disclosure can be executed within a TBDR architecture, with a depth range test (DBT) module added before the depth test (Z-test) module of the graphics processing device, allowing DBT to be quickly executed directly using the z-buffer.

[0075] Figure 4 A schematic diagram of a rendering architecture provided by an embodiment of the present disclosure. Figure 4 As shown, the embodiment of the present disclosure is improved on the basis of the TBDR architecture, and the rendering pipeline 40 may include vertex processing 401; clip, project and culling (clip, project / cull) 402; tiling 403; rasterization 404; early DBT (Early-DBT) 405; early visibility test 406; texture and shade (textureand shade) 407; alpha test 408; late DBT (Late-DBT) 409; late visibility test (latevisibility test) 410; alpha blending (alpha blend) 411.

[0076] The early DBT 405 and the late DBT 409 may reuse the DBT module of the graphics processing device; the early depth test 406 and the late depth test 410 may reuse the Z-Test module of the graphics processing device.

[0077] During processing, the graphics processing device reads geometry data from system memory and, through vertex processing 401 and clipping, projection, and culling 402, obtains the primitives of the rendered object. In the tiling 403 stage, the rendered object is divided, and the graphics data covering each tile, including the primitive list and vertex data, is recorded and written to system memory. For a tile, the rendering pipeline loads all the primitives (such as triangles) it contains into the fragment stage for processing. All primitives covering the tile can be directly read from the corresponding primitive list. Once all the primitives of a tile have been processed, processing can proceed to the next tile.

[0078] Each tile's primitives undergo rasterization 404 to generate corresponding fragments. Early DBT 405 uses the on-chip depth buffer to remove fragments outside the depth range. Early depth testing 406 then performs a depth comparison to eliminate occluded fragments. Hidden surface removal (HSR) can also be performed before early depth testing 406.

[0079] Fragments that pass the early depth test 406 undergo texture and shading processing based on the texture data in system memory in the texture and shading stage 407, and then undergo an alpha test 408. Fragments that pass the alpha test 27 undergo a late DBT 409 and a late depth test 410 based on the on-chip depth buffer. These fragments then undergo alpha blending 411 with the data in the on-chip color buffer to produce the rendering result, i.e., the pixel data to be output. The on-chip depth buffer exchanges data with the depth buffer in system memory, and the on-chip color buffer exchanges data with the frame buffer in system memory.

[0080] In some possible implementations, corresponding to the processing process in the graphics processing device in the rendering architecture, a corresponding interface is configured at the user level in the processing device (e.g., CPU), allowing the user to configure the parameters of the depth range test in each draw call, including the on / off state of the depth range test and the depth interval.

[0081] The switch status includes on or off. If the user wants to disable the DBT function, set the switch status to off; if the user wants to enable the DBT function, set the switch status to on; the depth range can include the minimum depth value and maximum depth value (zmin, zmax) of the floating-point type FLOAT, which are used to limit the depth range tested by DBT.

[0082] In some possible implementations, for a current first draw call of a rendering object, a driver layer of a processing device may obtain first configuration information of the first draw call in step S31, including the on / off state of a depth range test and a first depth interval, and then determine first driver information for a depth range test (DBT) of the first draw call. The first driver information includes a first enable flag for an early DBT, a second enable flag for a late DBT, and a second depth interval for the depth range test.

[0083] In some possible implementations, if the switch state is off, the first enable flag and the second enable flag can be directly set to invalid, the second depth interval can be set to [0.0f, 0.0f] or empty, and the instruction information generated according to the first driver information is used to instruct the graphics processing device not to perform DBT in the first draw call.

[0084] In some possible implementations, if the switch is on, first driver information for the depth range test of the first draw call may be determined in step S32 based on the first configuration information, the second configuration information for the depth test of the first draw call, and the second driver information for the depth range test of the second draw call. The second draw call is a predecessor of the first draw call, for example, a previous draw call for the same tile. Depth testing includes early depth testing and late depth testing, and the second configuration information for the depth test includes, for example, enable flags for the early depth test and the late depth test. The second driver information for the depth range test of the second draw call may include, for example, a third enable flag for the early DBT and a fourth enable flag for the late DBT, and a third depth interval for the depth range test of the second draw call. The third depth interval is the depth interval actually used in the DBT of the second draw call after data verification and format conversion.

[0085] In other words, the DBT driver information in the previous draw call and the depth test configuration information in the current draw call can be used to jointly determine the DBT driver information in the current draw call, so that the DBT function meets data dependencies and restrictions and avoids possible processing errors.

[0086] In some possible implementations, the step of determining first driver information for a depth range test of the first draw call in step S32 may include: performing data verification and format conversion on the first depth interval to obtain the second depth interval; determining the first enable flag and the second enable flag based on the second configuration information when both the third enable flag and the fourth enable flag are invalid; and determining the first enable flag and the second enable flag based on a difference between the second depth interval and the third depth interval, the third enable flag, the fourth enable flag, and the second configuration information when at least one of the third enable flag and the fourth enable flag is valid.

[0087] For example, the first depth interval set by the user may be incorrect, and the data format of the depth buffer of the graphics processing device may be different from the data format of the first depth interval. Therefore, the data of the first depth interval needs to be verified and converted first.

[0088] In some possible implementations, the step of performing data verification and format conversion on the first depth interval may include: performing data verification on the minimum depth value and the maximum depth value of the first depth interval to determine the minimum depth value and the maximum depth value after verification; performing numerical conversion on the minimum depth value and the maximum depth value after verification according to the data format of the depth buffer of the graphics processing device to determine the second depth interval.

[0089] For example, data validation may include checking whether the minimum depth value zmin and the maximum depth value zmax of the first depth interval are NAN (Not a Number). If NAN exists, the NaN is converted to 0.0f. Furthermore, the range of zmin and zmax is checked and clamped to [0.0f, 1.0f], limiting values ​​outside the range to within the interval. Furthermore, the check is made to see if zmin <= zmax. If so, the process passes. If not, a warning is sent to the runtime. Subsequent steps can still be performed, and the hardware will still process zmin <= zmax, but the result will be considered a failure.

[0090] In some possible implementations, the adjusted zmin and zmax values ​​can be mapped to corresponding integer or floating-point values ​​based on the depth buffer (z-buffer) data format to obtain the second depth range. Depth buffer data formats include, for example, D16_UNORM (16-bit integer), D24_UNORM (24-bit integer), and D32_FLOAT (32-bit floating-point number). The floating-point interval [0.0f, 1.0f] can be converted to D16_UNORM and represented as [0, 65535]. This disclosure does not limit the specific data format of the depth buffer.

[0091] In this way, unreasonable depth values ​​can be corrected and the depth values ​​of the depth interval can be matched with the depth values ​​stored in the depth buffer of the graphics processing device for subsequent comparison, thereby improving the accuracy of the depth range test.

[0092] In some possible implementations, if both the third enable flag and the fourth enable flag are invalid, that is, the DBT function in the previous draw call is disabled, then the second configuration information of the depth test of the current draw call is used to directly determine whether early DBT and late DBT are enabled for the current draw call, and then the first enable flag and the second enable flag are set to be valid or invalid.

[0093] If at least one of the third enable flag and the fourth enable flag is valid, that is, the DBT function in the previous draw call is enabled, then based on the difference between the second depth interval and the third depth interval, the third enable flag and the fourth enable flag of DBT in the previous draw call, and the second configuration information of the depth test of the current draw call, it can be determined whether early DBT and late DBT are enabled in the current draw call, and the first enable flag and the second enable flag can be set to be valid or invalid.

[0094] In this way, the DBT function configuration of the current drawing call can be implemented on the basis of satisfying data dependencies and restrictions, thereby improving the correctness of the processing results and improving rendering efficiency.

[0095] The switch enabling scenarios for Early-Z and Late-Z depth testing can be divided into the following three categories:

[0096] 1) Turn on Early-Z and turn off Late-Z. Update the z-buffer in Early-Z. Its usage scenarios include: standard opaque rendering scenes; standard translucent rendering (disable alpha blending) scenes, etc.

[0097] 2) Turn off Early-Z and turn on Late-Z. Update the z-buffer in Late-Z. This is useful when modifying depth values. If the depth value is changed in the fragment shader, Early-Z cannot predict the final depth, causing it to fail.

[0098] 3) Enable Early-Z (discard some occluded fragments in advance to improve performance), enable Late-Z (discard all occluded fragments to ensure correct results), and update the z-buffer in Late-Z. Its usage scenarios include: scenes using discard / clip operations. Explicitly discarding fragments in the fragment shader will make Early-Z unable to determine in advance whether the fragment should be processed, requiring Late-Z to process it again; scenes with alpha testing or alpha blending enabled. These operations require determining the visibility of the fragment after the fragment shader is executed, requiring Late-Z to process it again.

[0099] It should be understood that those skilled in the art can set the switch status of Early-Z and Late-Z according to actual conditions, and the present disclosure does not limit this.

[0100] In some possible implementations, both Early-Z and Late-Z are processed strictly in submission order or the order of primitives within the same draw call. This way, when multiple fragments (e.g., fragments p0, p1, and p2) overlap in screen space, the subsequent fragment is always tested against the z-buffer write results of the preceding fragment, ensuring correct occlusion relationships in both Early-Z and Late-Z phases. The Early-Z and Late-Z switching of the preceding and succeeding fragments has certain dependencies and restrictions, which can be expressed as follows: 1. Each fragment in p0, p1, and p2 is executed in order-preserving Early-Z and Late-Z. 2. Each fragment in p0, p1, and p2 is executed in order-preserving Early-Z. 3. Each fragment in p0, p1, and p2 is executed in order-preserving Late-Z.

[0101] 4. The order of Early-Z reads of subsequent fragments and Late-Z writes of preceding fragments is uncertain. For example, if the Early-Z read of fragment p2 precedes the Late-Z write of fragment p1, the following situations may occur: (1) If p2 has Early-Z enabled and Late-Z disabled, there is no guarantee that the depth value z read by p2 is consistent with the depth value written by p1. Therefore, the Early-Z read of p2 must wait for the Late-Z write of p1 to complete.

[0102] (2) If p2 has Early-Z enabled and Late-Z enabled, and the depth test comparison modes of p1 and p2 are different, the Early-Z read operation of p2 must wait for the Late-Z write of p1 to complete; otherwise, p2 may be incorrectly discarded in Early-Z.

[0103] (3) If p2 has Early-Z and Late-Z enabled, and the depth test comparison modes of p1 and p2 are the same, the following situations may occur: ① If p2's Early-Z passes, then p2's Late-Z read operation must be after p1's Late-Z write operation, and the final result is correct.

[0104] ② If p2's Early-Z fails, p2 is discarded in Early-Z, and the final result is correct because: I) If p1's Late-Z fails and is discarded (the z-buffer is not updated), the depth value read by p2 is correct and p2 must be discarded; II) If p1's Late-Z passes and is retained (the z-buffer is updated), p1 and p2 are on both sides of p0. Even if p2 reads the updated depth value of p1, p2 must be discarded.

[0105] Figure 5 A schematic diagram of the on / off status of the depth test provided by an embodiment of the present disclosure, wherein "√" indicates on or synchronous waiting; "×" indicates off or no synchronous waiting required.

[0106] like Figure 5 As shown in the figure, if the Early-Z of the preceding fragment is turned on and the Late-Z is turned off, no matter how the Early-Z and Late-Z switch states of the subsequent fragment are set, there is no need to wait synchronously, and the processing result of the subsequent fragment is always correct.

[0107] like Figure 5As shown, if the Early-Z of the preceding fragment is on or off, and Late-Z is on, the processing result of the subsequent fragment may be wrong. It is necessary to set it according to the switch status of the Early-Z and Late-Z of the subsequent fragment and the depth test comparison mode, including: the Early-Z of the subsequent fragment is on, and the Late-Z is off, see the above case 4 (1), and synchronous waiting is required to ensure the correct processing result; the Early-Z of the subsequent fragment is off, and the Late-Z is on, then the Late-Z of the preceding fragment and the Late-Z of the subsequent fragment are different. For in-order execution, see case 3 above. There is no need for synchronous waiting, and the processing results of the subsequent fragments are always correct. For the subsequent fragments, Early-Z and Late-Z are turned on. If the depth test comparison modes of the previous fragment and the subsequent fragment are different, see case 4 (2) above. Synchronous waiting is required to ensure the correct processing results. For the subsequent fragments, Early-Z and Late-Z are turned on. If the depth test comparison modes of the previous fragment and the subsequent fragment are the same, see case 4 (3) above. There is no need for synchronous waiting, and the processing results of the subsequent fragments are always correct.

[0108] Similar to the depth test, the depth range test (DBT) requires reading the depth value z written to the z-buffer by the previous fragment and comparing it with the maximum and minimum depth values ​​of the depth interval. If the read occurs before the previous fragment is written, an incorrect depth value will be read, which may cause the DBT to fail and the fragment to be incorrectly discarded.

[0109] According to an embodiment of the present disclosure, the depth range test DBT includes an early DBT and a late DBT. The early DBT is set before the early depth test Early-Z, and the late DBT is set before the late depth test Late-Z, so as to remove invalid fragments in advance.

[0110] The above describes the limitations on the on / off states of depth testing for preceding and succeeding fragments. When both Early-Z and Late-Z are enabled for both, the Late-Z of the succeeding fragment can always correctly read the depth value written to the z-buffer by the preceding fragment, but Early-Z may be affected. Early-DBT and Late-DBT are similar, so in this case, Early-DBT needs to be disabled and Late-DBT enabled. Furthermore, whether the depth ranges of the preceding and succeeding fragments are the same or different can also affect the DBT processing results.

[0111] The following describes the restrictions between the depth test of the preceding fragment and the subsequent fragment and the switch state of DBT.

[0112] 1. The depth interval of the preceding fragment and the succeeding fragment is the same.

[0113] (1) Preceding fragment: If Early-DBT is enabled and Late-DBT is disabled, the following situations may occur for subsequent fragments: ① For subsequent fragments, if Early-Z is enabled and Late-Z is disabled, Early-DBT is enabled and Late-DBT is disabled. This is because the Early-DBT read operation of the subsequent fragment occurs after the Early-Z write operation of the preceding fragment.

[0114] ② For subsequent fragments, if Early-Z is disabled and Late-Z is enabled, Early-DBT is disabled and Late-DBT is enabled, because the Late-DBT read operation of the subsequent fragment occurs after the Early-Z write operation of the preceding fragment.

[0115] ③ For subsequent fragments, if Early-Z and Late-Z are enabled, Early-DBT and Late-DBT are also enabled. This is because the Early-DBT and Late-DBT read operations of the subsequent fragments are after the Early-Z write operations of the preceding fragments.

[0116] (2) If Early-DBT is disabled and Late-DBT is enabled for the preceding fragment, the following situations may occur for the following fragment: ① If Early-Z is enabled and Late-Z is disabled for the following fragment, Early-DBT is enabled and Late-DBT is disabled. This is because the Early-DBT read operation of the following fragment occurs after the Late-Z write operation of the preceding fragment (this is guaranteed by the Z-Test in the previous description).

[0117] ② For subsequent fragments, if Early-Z is disabled and Late-Z is enabled, Early-DBT is disabled and Late-DBT is enabled, because the Late-DBT read operation of the subsequent fragment occurs after the Late-Z write operation of the preceding fragment.

[0118] ③ For subsequent fragments, if Early-Z and Late-Z are enabled, Early-DBT and Late-DBT are enabled. Consider the following scenario: for three overlapping fragments p0, p1, and p2, even if p2 reads the depth value of p0 before p1 writes it during Early-DBT (both p1 and p2 are tested based on p0's depth value), if p2 passes Early-DBT, then regardless of whether p1 ultimately passes Late-DBT and writes back the new depth, p2 will still read the correct, updated depth value of p1 during Late-DBT.

[0119] If p2 fails Early-DBT, p1 will also fail Late-DBT because both p1 and p2 use the same depth interval. This means that in this scenario, the DBT behavior of the later fragments is always correct.

[0120] (3) For the preceding fragment, if Early-DBT is enabled and Late-DBT is enabled: ① For the following fragment, if Early-Z is enabled and Late-Z is disabled, Early-DBT is enabled and Late-DBT is disabled. This is because the Early-DBT read operation of the following fragment occurs after the Late-Z write operation of the preceding fragment (this is guaranteed by the Z-Test in the previous summary).

[0121] ② For subsequent fragments, if Early-Z is disabled and Late-Z is enabled, Early-DBT is disabled and Late-DBT is enabled, because the Late-DBT read operation of the subsequent fragment occurs after the Late-Z write operation of the preceding fragment.

[0122] ③ For subsequent fragments, if Early-Z and Late-Z are enabled, Early-DBT and Late-DBT are enabled. Consider the following scenario: for the three overlapping fragments p0, p1, and p2, even if p2 reads the depth value of p0 before p1 is written during the Early-DBT phase (at this time, both p1 and p2 are tested based on the depth value of p0), the following situation occurs: If p2 passes Early-DBT, then regardless of whether p1 ultimately passes Late-DBT and writes back the new depth, p2 can read the correct updated depth value of p1 during the Late-DBT phase. If p2 fails Early-DBT, because p1 and p2 use the same depth range, p1 will inevitably fail the subsequent Late-DBT. In other words, in this scenario, the DBT behavior of the subsequent fragment is always correct.

[0123] It can be seen that when the depth intervals of the preceding fragment and the succeeding fragment are the same, the DBT switch state of the succeeding fragment is consistent with the switch state of its depth test and will not be affected by the switch state of the DBT and depth test of the preceding fragment.

[0124] 2. The depth intervals of the preceding fragment and the succeeding fragment are different.

[0125] (1) For the preceding fragment, if Early-DBT is enabled, Late-DBT is disabled, and Early-Z is written to the z-buffer, the following situations may occur for the succeeding fragments: ① For the succeeding fragment, if Early-Z is enabled and Late-Z is disabled, Early-DBT is enabled and Late-DBT is disabled. This is because the Early-DBT read operation of the succeeding fragment occurs after the Early-Z write operation of the preceding fragment. ② For the succeeding fragment, if Early-Z is disabled and Late-Z is enabled, Early-DBT is disabled and Late-DBT is enabled. This is because the Late-DBT read operation of the succeeding fragment occurs after the Early-Z write operation of the preceding fragment.

[0126] ③ For subsequent fragments, if Early-Z and Late-Z are enabled, Early-DBT and Late-DBT are also enabled. This is because the Early-DBT and Late-DBT read operations of the subsequent fragments are after the Early-Z write operations of the preceding fragments.

[0127] (2) If Early-DBT is disabled and Late-DBT is enabled for the preceding fragment, the following situations may occur for the following fragment: ① If Early-Z is enabled and Late-Z is disabled for the following fragment, Early-DBT is enabled and Late-DBT is disabled. This is because the Early-DBT read operation of the following fragment occurs after the Late-Z write operation of the preceding fragment (this is guaranteed by the Z-Test in the previous summary).

[0128] ② For subsequent fragments, if Early-Z is disabled and Late-Z is enabled, Early-DBT is disabled and Late-DBT is enabled, because the Late-DBT read operation of the subsequent fragment occurs after the Late-Z write operation of the preceding fragment.

[0129] ③ For subsequent fragments, if Early-Z and Late-Z are turned on, Early-DBT is turned off and Late-DBT is turned on. Consider the following scenario, for the three overlapping fragments p0, p1 and p2, even if the depth value of p0 before p1 is written is read in the Early-DBT stage of p2 (at this time, both p1 and p2 are tested based on the depth value of p0), there is the following situation: If p2 does not pass the Early-DBT, because p1 and p2 use different depth ranges, it is impossible to determine whether p1's DBT passes. If p1 passes the Early-DBT and updates the depth value, p2's Early-DBT may pass, but p2 has been mistakenly discarded, such as Figure 6 Therefore, in this scenario, Early-DBT of p2 must be turned off to ensure the correct final result, as shown in Figure 7 shown.

[0130] (3) If both Early-DBT and Late-DBT are enabled for the preceding fragment, the following situations may occur for the succeeding fragment: ① If Early-Z is enabled and Late-Z is disabled for the succeeding fragment, Early-DBT is enabled and Late-DBT is disabled. This is because the Early-DBT read operation of the succeeding fragment occurs after the Late-Z write operation of the preceding fragment (this is guaranteed by the Z-Test in the previous description).

[0131] ② For subsequent fragments, if Early-Z is disabled and Late-Z is enabled, Early-DBT is disabled and Late-DBT is enabled, because the Late-DBT read operation of the subsequent fragment occurs after the Late-Z write operation of the preceding fragment.

[0132] ③ For subsequent fragments, if Early-Z and Late-Z are turned on, Early-DBT is turned off and Late-DBT is turned on. Consider the following scenario, for the three overlapping fragments p0, p1 and p2, even if the depth value of p0 before p1 is written is read in the Early-DBT stage of p2 (at this time, both p1 and p2 are tested based on the depth value of p0), the following situation occurs: If p2 turns on Early-DBT and fails, because p1 and p2 use different depth ranges, it is impossible to determine whether p1's DBT passes. If p1 passes DBT and updates the depth value, p2's Early-DBT may pass, but p2 has been mistakenly discarded, such as Figure 6 Therefore, in this scenario, Early-DBT of p2 must be turned off to ensure the correct final result, as shown in Figure 7 shown.

[0133] Figure 6 and Figure 7 A schematic diagram of the processing process of depth testing and depth range testing provided in an embodiment of the present disclosure. Figure 6 and Figure 7 In the figure, the depth interval of the preceding fragment is [0.1, 0.5], and the depth interval of the subsequent fragment is [0.5, 0.7]. The two are different. The depth value currently stored in the depth buffer z-buffer is z0=0.4, the depth value of the preceding fragment is z1=0.6, and the depth value of the subsequent fragment is z2=0.5.

[0134] like Figure 6 As shown, the preceding fragment has Early-Z and Late-Z turned on, and Early-DBT and Late-DBT turned on, and the subsequent fragment has Early-Z and Late-Z turned on, and Early-DBT and Late-DBT turned on.

[0135] For the preceding fragment, in its Early-DBT processing, z0=0.4 is in the depth range [0.1, 0.5], and Early-DBT passes; in Early-Z processing, z1=0.6>0.4, Early-Z passes, and the fragment shader call is executed; then Late-DBT processing is executed, z0=0.4 is in the depth range [0.1, 0.5], and Late-DBT passes; in Late-Z processing, z1=0.6>0.4, Late-Z passes, and the depth value in the depth buffer z-buffer is updated to z0=0.6.

[0136] For the subsequent fragment, Early-DBT processing begins before Late-Z updates the depth buffer z-buffer. The unupdated depth value z0 = 0.4 is read, which is outside the depth range [0.5, 0.7]. Early-DBT fails, and the subsequent fragment is discarded. However, after the depth value is updated, z0 = 0.6, which is within the depth range [0.5, 0.7], and Early-DBT should pass. Therefore, the subsequent fragment is incorrectly discarded.

[0137] like Figure 7 As shown, the preceding fragment turns on Early-Z and Late-Z, and turns on Early-DBT and Late-DBT, and the subsequent fragment turns on Early-Z and Late-Z, turns off Early-DBT, and turns on Late-DBT.

[0138] For the preceding fragment, the processing process is the same as Figure 6 The same, no further elaboration here.

[0139] For subsequent fragments, Early-DBT is not executed, and Early-Z is executed directly. If z2 = 0.5 > 0.4, Early-Z passes, and the fragment shader is called. Late-DBT is then executed, and the updated depth value z0 = 0.6 is read, which is within the depth range [0.5, 0.7]. Late-DBT passes, and subsequent processing continues. Therefore, the result remains correct in this case.

[0140] It can be seen that when the depth ranges of the preceding fragment and the succeeding fragment are different, if the preceding fragment turns on Late-Z and the succeeding fragment turns on both Early-Z and Late-Z, the succeeding fragment needs to turn off Early-DBT and turn on Late-DBT; under other conditions, the DBT switch state of the succeeding fragment is consistent with the switch state of its depth test, and will not be affected by the switch state of the depth test of the preceding fragment.

[0141] Figure 8 A schematic diagram illustrating the on / off states of the depth test and depth range test provided in an embodiment of the present disclosure, where "√" indicates on and "×" indicates off.

[0142] like Figure 8As shown, when both Early-DBT and Late-DBT of the preceding fragment are turned off, the on / off status of Early-DBT and Late-DBT of the succeeding fragment is determined based on the on / off status of Early-Z and Late-Z of the succeeding fragment. If both Early-Z and Late-Z are turned off, Early-DBT can be turned on to implement the DBT function; if at least one of Early-Z and Late-Z is turned on, the on / off status of Early-DBT and Late-DBT can be consistent with the on / off status of Early-Z and Late-Z.

[0143] like Figure 8 As shown, when at least one of the Early-DBT and Late-DBT of the preceding fragment is turned on, if the Early-Z and Late-Z of the succeeding fragment are both turned off, the on-off state of the Early-DBT and Late-DBT of the succeeding fragment is jointly determined according to the on-off state of the Early-DBT and Late-DBT of the preceding fragment and whether the depth interval is consistent; if at least one of the Early-Z and Late-Z of the succeeding fragment is turned on, the on-off state of the Early-DBT and Late-DBT of the succeeding fragment is jointly determined according to the on-off state of the Early-DBT and Late-DBT of the preceding fragment, the on-off state of the Early-Z and Late-Z of the succeeding fragment and whether the depth interval is consistent.

[0144] In some possible implementations, the depth test includes an early depth test and a late depth test, and the second configuration information of the depth test of the current draw call includes a fifth enable flag of the early depth test and a sixth enable flag of the late depth test.

[0145] When the third enable flag of the Early-DBT and the fourth enable flag of the Late-DBT of the preceding draw call are both invalid, determining the first enable flag and the second enable flag according to the second configuration information includes: when both the fifth enable flag and the sixth enable flag are invalid, determining that the first enable flag is valid and the second enable flag is invalid; and when at least one of the fifth enable flag and the sixth enable flag is valid, determining the first enable flag and the second enable flag according to the fifth enable flag and the sixth enable flag.

[0146] For example, on the processing device side, the preceding fragment corresponds to the preceding draw call, and the following fragment corresponds to the current draw call. If both Early-DBT and Late-DBT are disabled for the preceding draw call, the fifth enable flag of Early-Z and the sixth enable flag of Late-Z for the current draw call are used to determine whether the draw call is in the same state or not.

[0147] In some possible implementations, if both Early-Z and Late-Z are disabled for the current draw call (i.e., both the fifth and sixth enable flags are invalid), Early-DBT can be enabled for the current draw call to implement DBT. In this case, Early-DBT removes fragments outside the second depth interval, and Late-DBT does not need to be enabled again and can be disabled. Consequently, the first enable flag is enabled (e.g., set to 1) and the second enable flag is disabled (e.g., set to 0).

[0148] In some possible implementations, if at least one of Early-Z and Late-Z is enabled for the current draw call, that is, if at least one of the fifth enable flag and the sixth enable flag is valid, the first enable flag and the second enable flag are determined based on the fifth enable flag and the sixth enable flag. In other words, the first enable flag is made consistent with the fifth enable flag, and the second enable flag is made consistent with the sixth enable flag. This ensures that the on / off states of Early-DBT and Late-DBT are consistent with those of Early-Z and Late-Z, enabling coordination between depth range testing and depth testing.

[0149] In this way, the DBT function configuration of the current drawing call can be implemented on the basis of satisfying data dependencies and restrictions, thereby improving the correctness of the processing results and improving rendering efficiency.

[0150] In some possible implementations, when at least one of the third enable flag and the fourth enable flag is valid, determining the first enable flag and the second enable flag according to the difference between the second depth interval and the third depth interval, the third enable flag, the fourth enable flag, and the second configuration information includes: when both the fifth enable flag and the sixth enable flag are invalid, determining the first enable flag and the second enable flag in the following manner: if the third enable flag is valid and the fourth enable flag is invalid, determining that the first enable flag is valid and the second enable flag is invalid;

[0151] If the fourth enable flag is valid and the second depth interval is consistent with the third depth interval, determining that the first enable flag is valid and the second enable flag is valid;

[0152] If the fourth enable flag is valid and the second depth interval is inconsistent with the third depth interval, it is determined that the first enable flag is invalid and the second enable flag is valid.

[0153] For example, on the processing device side, if at least one of Early-DBT and Late-DBT of the previous draw call is enabled, that is, at least one of the third enable flag and the fourth enable flag is valid; and both Early-Z and Late-Z of the current draw call are not enabled, that is, both the fifth enable flag and the sixth enable flag are invalid, then a determination is made based on the difference between the second depth interval and the third depth interval, the third enable flag, and the fourth enable flag.

[0154] In some possible implementations, if the third enable flag of Early-DBT in the previous draw call is valid and the fourth enable flag of Late-DBT is invalid, Late-DBT is disabled, and the depth range has no effect on the DBT result, Early-DBT can be enabled for the current draw call to implement DBT. In this case, Early-DBT has already removed fragments outside the second depth range, so Late-DBT does not need to be enabled again and can be disabled, thereby setting the first enable flag to be valid and the second enable flag to be invalid.

[0155] In some possible implementations, if the fourth enable flag of the Late-DBT of the preceding draw call is valid (i.e., Late-DBT is enabled for the preceding fragment), and both Early-Z and Late-Z are disabled for the succeeding fragment, then Late-DBT is enabled for the succeeding fragment. Whether Early-DBT is enabled is determined by whether the depth intervals of the preceding and succeeding fragments are consistent. If the second depth interval is consistent with the third depth interval, the Early-DBT result is correct and can be enabled. If the second depth interval is inconsistent with the third depth interval, the Early-DBT result may be incorrect and cannot be enabled.

[0156] That is, when the fourth enable flag is valid and the second depth interval is consistent with the third depth interval, the first enable flag and the second enable flag are set to be valid; when the fourth enable flag is valid and the second depth interval is inconsistent with the third depth interval, the first enable flag is set to be invalid and the second enable flag is set to be valid. The consistency between the second depth interval and the third depth interval means that the maximum depth value and the minimum depth value of the second depth interval and the third depth interval are the same.

[0157] In this way, the DBT function configuration of the current drawing call can be implemented on the basis of satisfying data dependencies and restrictions, ensuring that the correct depth value is read during processing and the processing results are kept correct, thereby improving the correctness of the processing results, while reducing unnecessary pixel shader execution, improving rendering efficiency, and reducing overall power consumption.

[0158] In some possible implementations, when at least one of the third enable flag and the fourth enable flag is valid, the step of determining the first enable flag and the second enable flag according to the difference between the second depth interval and the third depth interval, the third enable flag, the fourth enable flag, and the second configuration information includes: when at least one of the fifth enable flag and the sixth enable flag is valid, determining the first enable flag and the second enable flag in the following manner: if a preset condition of the enable flag is met and the second depth interval is consistent with the third depth interval, determining that the first enable flag is valid and the second enable flag is valid; if the preset condition is met and the second depth interval is inconsistent with the third depth interval, determining that the first enable flag is invalid and the second enable flag is valid; if the preset condition is not met, determining the first enable flag and the second enable flag according to the fifth enable flag and the sixth enable flag, wherein the preset condition includes that the fourth enable flag, the fifth enable flag, and the sixth enable flag are all valid.

[0159] For example, on the processing device side, if at least one of Early-DBT and Late-DBT is enabled in the previous draw call, that is, at least one of the third enable flag and the fourth enable flag is valid; and at least one of Early-Z and Late-Z is enabled in the current draw call, that is, at least one of the fifth enable flag and the sixth enable flag is valid, then a determination is made based on the difference between the second depth interval and the third depth interval, the third enable flag and the fourth enable flag of the previous draw call, and the fifth enable flag and the sixth enable flag of the current draw call.

[0160] In some possible implementations, if the Late-DBT of the previous draw call is enabled, that is, the fourth enable flag is valid; and both Early-Z and Late-Z of the current draw call are enabled, that is, the fifth enable flag and the sixth enable flag are both valid, combined with the previous analysis and Figure 8 If the second depth interval is consistent with the third depth interval, the Early-DBT result will not be wrong and can be enabled; if the second depth interval is inconsistent with the third depth interval, the Early-DBT result may be wrong and cannot be enabled.

[0161] In this case, the preset conditions of the enable flag include that the fourth enable flag, the fifth enable flag, and the sixth enable flag are all valid; if the preset conditions are met and the second depth interval is consistent with the third depth interval, the first enable flag and the second enable flag are set to be valid, that is, Early-DBT and Late-DBT are turned on at the same time; if the preset conditions are met and the second depth interval is inconsistent with the third depth interval, the first enable flag is set to be invalid and the second enable flag is set to be valid, that is, Early-DBT is turned off and Late-DBT is turned on at the same time.

[0162] In some possible implementations, if the preset condition is not met, that is, the fourth enable flag, the fifth enable flag, and the sixth enable flag are not valid at the same time, combined with the above analysis and Figure 8 Whether the depth intervals are consistent does not affect the results of Early-DBT. In this case, the first and second enable flags can be determined based on the fifth and sixth enable flags. That is, the first enable flag is consistent with the fifth enable flag, and the second enable flag is consistent with the sixth enable flag, thereby maintaining the consistency of the on / off states of Early-DBT and Late-DBT with Early-Z and Late-Z.

[0163] In this way, while ensuring the correctness of the DBT processing results, the depth range test and the depth test can be coordinated, invalid fragments can be removed in advance before the depth test, unnecessary pixel shader execution can be reduced, rendering efficiency can be improved, and overall power consumption can be reduced.

[0164] In some possible implementations, after determining the first enable flag, the second enable flag, and the second depth interval, the first driver information for the current first draw call is obtained. The driver layer may then package and transmit the data in step S33, generating instruction information based on the first driver information. Specifically, the instruction information encodes the first enable flag, the second enable flag, and the second depth interval into a hardware instruction packet. This instruction information may also include an identifier of the depth buffer data format, which allows the graphics processing device's hardware module to adapt comparison logic, etc., but this disclosure does not limit this.

[0165] In some possible implementations, the generated instruction information is sent to a graphics processing device; after receiving the instruction information, the graphics processing device may perform a depth range test in the first draw call based on the instruction information, thereby implementing a DBT function.

[0166] Figure 9 This is a flowchart of a rendering processing method provided by an embodiment of the present disclosure. The method can be executed by a graphics processing device in a terminal device, such as a GPU. Figure 9 , the method comprising:

[0167] In step S91, first driver information of a depth range test (DBT) of a current first draw call of a rendering object is obtained, where the depth range test includes an early DBT and a late DBT. The first driver information includes a first enable flag of the early DBT, a second enable flag of the late DBT, and a second depth interval of the depth range test.

[0168] In step S92 , in response to the first drawing call, rasterization is performed on the first primitive in the tile of the rendering object to obtain a corresponding first fragment.

[0169] In step S93 , when the first enable flag is valid, a depth range test is performed on the first fragment according to the second depth interval to obtain an early DBT result of the first fragment.

[0170] In step S94 , if the early DBT result of the first fragment is passed, an early depth test and rendering process are performed on the first fragment, and a rendered second fragment is obtained if the early depth test is passed.

[0171] In step S95 , when the second enable flag is valid, a depth range test is performed on the second fragment according to the second depth interval to obtain a late DBT result of the second fragment.

[0172] In step S96, if the post-DBT result of the second fragment is passed, a post-depth test and rendering process are performed on the second fragment, and if the post-depth test is passed, the rendered first pixel data is obtained.

[0173] For example, after receiving the instruction information sent by the processing device, the graphics processing device can determine the first driving information of the DBT of the current first drawing call of the rendering object in step S91, including the early DBT first enable flag, the late DBT second enable flag and the DBT second depth range.

[0174] In some possible implementations, the rendering method of the rendering object includes tile-based deferred rendering (TBDR), wherein the rendering object is divided into multiple tiles, and the rendering object includes multiple primitives, each of the multiple tiles is covered by at least one primitive of the rendering object, and the first primitive is any one of the multiple primitives.

[0175] In some possible implementations, in response to the current first drawing call, Figure 4 The rendering architecture shown in the figure is used for rendering. Figure 4As shown, the graphics processing device reads geometric data from the system memory, and through the processing of the vertex processing 401 and the clipping, projection, and culling 402 stages, obtains the primitives of the rendering object; in the tiling 403 stage, the rendering object is sliced, and the graphic data covering each tile, including the primitive list, vertex data, etc., is recorded and written into the system memory.

[0176] In some possible implementation manners, for any primitive in any tile of the rendering object, which is called the first primitive, rasterization processing can be performed on the first primitive in step S92 to obtain the corresponding first fragment.

[0177] In the Early-Z execution stage of the first fragment, it is judged whether the first enable flag of the Early-DBT is valid; if the first enable flag is valid, then in step S93, the Early-DBT is performed on the first fragment according to the second depth interval, that is, depth range testing is performed through the DBT module.

[0178] In some possible implementation manners, step S93 may include: reading the depth value corresponding to the position information from the on-chip depth buffer of the graphics processing device according to the position information of the first fragment; when the depth value is within the second depth interval, determining that the early DBT result of the first fragment is passed. Among them, the position information may include the position coordinates of the pixel point corresponding to the first fragment on the screen.

[0179] For example, according to the position information, as Figure 4 shown, the DBT module can read the depth value z-buffer corresponding to the position information from the on-chip depth buffer of the graphics processing device; and compare the depth value with the second depth interval. If the depth value is within the second depth interval, that is, zmin≤z-buffer≤zmax, the early DBT result of the first fragment is passed, and the subsequent Early-Z processing is continued.

[0180] On the contrary, if the depth value is outside the second depth interval, that is, z-buffer<zmin or z-buffer>zmax, the early DBT result of the first fragment is not passed, and it is directly discarded, and the subsequent Early-Z processing and other processing steps are skipped.

[0181] By performing Early-DBT before Early-Z, fragments outside the preset depth interval can be culled at the earliest stage, significantly reducing the ineffective execution of subsequent depth testing and pixel shaders, thereby improving the overall rendering performance.

[0182] In some possible implementations, the rendering processing method according to an embodiment of the present disclosure further includes: determining that the early DBT result of the first fragment passes when the first enable flag is invalid. In other words, if the first enable flag is invalid, the early DBT processing can be skipped, the early DBT result of the first fragment is deemed to pass, and subsequent Early-Z processing and other processing can be performed directly. In this way, whether to perform DBT can be determined based on the enable flag, improving processing efficiency and flexibility.

[0183] In some possible implementations, if the early DBT result of the first fragment passes, an early depth test (Early-Z) and rendering process may be performed on the first fragment in step S94. If the Early-Z enable flag is invalid, Early-Z is skipped and the fragment is rendered directly; if the Early-Z enable flag is valid, Early-Z is executed and the fragment is rendered after Early-Z passes. Figure 4 As shown, the rendering process may include texture and shadow 407 and alpha test 408, and after processing, a rendered second fragment is obtained.

[0184] In some possible implementations, during the Late-Z execution phase, it may be determined whether the second enable flag of Late-DBT is valid; if the second enable flag is valid, then in step S95, Late-DBT is performed on the second fragment according to the second depth interval, i.e., a depth range test is performed through the DBT module.

[0185] Similarly, based on the position information of the second fragment, the DBT module can read the current depth value corresponding to that position information from the on-chip depth buffer of the graphics processing device and compare that depth value with the second depth range. If the depth value is within the second depth range, the late DBT result for the second fragment passes, and subsequent Late-Z processing continues.

[0186] On the contrary, if the depth value is outside the second depth range, the late DBT result of the second fragment fails and is directly discarded, and the subsequent Late-Z processing and other processing steps are skipped.

[0187] By executing Late-DBT before Late-Z, residual fragments whose depth exceeds the depth range can be eliminated twice, further reducing the memory bandwidth pressure and power consumption overhead caused by fragment processing and optimizing hardware resource utilization.

[0188] In some possible implementations, the rendering processing method according to an embodiment of the present disclosure further includes: determining that the late DBT result of the second fragment passes if the second enable flag is invalid. That is, if the second enable flag is invalid, the late DBT processing can be skipped, the late DBT result of the second fragment is deemed to pass, and subsequent Late-Z processing and other processing can be performed directly. In this way, whether to perform DBT can be determined based on the enable flag, improving processing efficiency and flexibility.

[0189] In some possible implementations, if the late DBT result of the first fragment passes, a late depth test (Late-Z) and rendering process may be performed on the second fragment in step S964. If the Late-Z enable flag is invalid, Late-Z is skipped and the fragment is rendered directly. If the Late-Z enable flag is valid, Late-Z is executed and the fragment is rendered after the Late-Z pass.

[0190] like Figure 4 As shown, the rendering process may include alpha blending 411 and other processes, and after the processing, the rendered first pixel data is obtained. In this way, the entire rendering process of the first primitive is implemented.

[0191] According to the rendering processing method of the embodiment of the present disclosure, the depth range test (DBT) is combined with the depth test (Z-test), allowing the DBT to be configured in the draw call. The processing device obtains the configuration information of the depth range test of the current draw call; based on the DBT configuration and depth test configuration of the previous draw call and the depth test configuration of the current draw call, the DBT driver information of the current draw call is determined; then, the corresponding instruction information is generated and issued, so that the graphics processing device performs the depth range test, thereby further removing invalid fragments based on the depth test, reducing unnecessary pixel shader execution, improving rendering efficiency, and reducing overall power consumption.

[0192] According to the rendering processing method of the embodiment of the present disclosure, the depth range test is divided into early DBT (Early-DBT) and late DBT (Late-DBT); and early DBT is coordinated with early depth test (Early-Z), and late DBT is coordinated with late depth test (Late-Z), which can reduce unnecessary calculations of early depth test and late depth test, and can respectively optimize performance and ensure the correctness of DBT results.

[0193] According to the rendering processing method of the embodiment of the present disclosure, a DBT hardware module is set in the graphics processing device, which can implement depth range testing before Early-Z and before Late-Z respectively. In this way, by executing Early-DBT before Early-Z, fragments outside the preset depth range can be eliminated at the earliest stage, significantly reducing the subsequent depth test and invalid execution of the pixel shader, thereby improving the overall rendering performance; by executing Late-DBT before Late-Z, the remaining fragments whose depth exceeds the depth range can be secondary eliminated, further reducing the memory bandwidth pressure and power consumption overhead caused by fragment processing, and optimizing hardware resource utilization.

[0194] Moreover, through segmented rendering for different depth ranges, special depth-based visual effects such as depth contouring, layered volumetric fog, depth of field blur or perspective deformation can be achieved, thus giving the rendering system greater flexibility and scalability.

[0195] It is understood that the above-mentioned various method embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, this disclosure will not go into details. It is understood by those skilled in the art that in the above-mentioned methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0196] In addition, the present disclosure also provides a rendering processing device, an electronic device, and a computer-readable storage medium, all of which can be used to implement any rendering processing method provided by the present disclosure. The corresponding technical solutions and descriptions can be found in the corresponding records in the method section and will not be repeated here.

[0197] Figure 10 A block diagram of a rendering processing device provided in an embodiment of the present disclosure.

[0198] Reference Figure 10 An embodiment of the present disclosure provides a rendering processing device, which includes: a configuration information acquisition module 81, which is used to obtain first configuration information of a depth range test DBT of a current first drawing call of a rendering object, wherein the first configuration information includes a switch state of the depth range test and a first depth interval.

[0199] The driver information determination module 82 is configured to, when the depth range test is on, determine first driver information for a depth range test of the first draw call based on the first configuration information, second configuration information for the depth test of the first draw call, and second driver information for the depth range test of the second draw call. The second draw call is a preceding draw call of the rendered object; the depth range test includes early DBT and late DBT; and the first driver information includes a first enable flag for the early DBT, a second enable flag for the late DBT, and a second depth interval for the depth range test.

[0200] The instruction sending module 83 is configured to generate instruction information according to the first driving information and send the instruction information to the graphics processing device, so that the graphics processing device performs the depth range test in the first drawing call based on the instruction information.

[0201] In some possible implementations, the second driving information includes a third enable flag for early DBT, a fourth enable flag for late DBT, and a third depth interval for the depth range test, wherein the driving information determination module 82 is configured to: perform data verification and format conversion on the first depth interval to obtain the second depth interval; determine the first enable flag and the second enable flag according to the second configuration information when both the third enable flag and the fourth enable flag are invalid; and determine the first enable flag and the second enable flag according to the difference between the second depth interval and the third depth interval, the third enable flag, the fourth enable flag, and the second configuration information when at least one of the third enable flag and the fourth enable flag is valid.

[0202] In some possible implementations, the depth test includes an early depth test and a late depth test, and the second configuration information includes a fifth enable flag for the early depth test and a sixth enable flag for the late depth test; wherein the driving information determination module 82 is used to: when both the fifth enable flag and the sixth enable flag are invalid, determine that the first enable flag is valid and the second enable flag is invalid; when at least one of the fifth enable flag and the sixth enable flag is valid, determine the first enable flag and the second enable flag according to the fifth enable flag and the sixth enable flag.

[0203] In some possible implementations, the driving information determination module 82 is configured to:

[0204] When both the fifth enable flag and the sixth enable flag are invalid, the first enable flag and the second enable flag are determined as follows: if the third enable flag is valid and the fourth enable flag is invalid, the first enable flag is determined to be valid and the second enable flag is invalid; if the fourth enable flag is valid and the second depth interval is consistent with the third depth interval, the first enable flag is determined to be valid and the second enable flag is valid; if the fourth enable flag is valid and the second depth interval is inconsistent with the third depth interval, the first enable flag is determined to be invalid and the second enable flag is valid.

[0205] In some possible implementations, the driving information determination module 82 is used to: when at least one of the fifth enable flag and the sixth enable flag is valid, determine the first enable flag and the second enable flag in the following manner: if the preset condition of the enable flag is met and the second depth interval is consistent with the third depth interval, determine that the first enable flag is valid and the second enable flag is valid; if the preset condition is met and the second depth interval is inconsistent with the third depth interval, determine that the first enable flag is invalid and the second enable flag is valid; if the preset condition is not met, determine the first enable flag and the second enable flag according to the fifth enable flag and the sixth enable flag, wherein the preset condition includes that the fourth enable flag, the fifth enable flag and the sixth enable flag are all valid.

[0206] In some possible implementations, the driving information determination module 82 is used to: perform data verification on the minimum depth value and the maximum depth value of the first depth interval to determine the minimum depth value and the maximum depth value after verification; perform numerical conversion on the minimum depth value and the maximum depth value after verification according to the data format of the depth cache of the graphics processing device to determine the second depth interval.

[0207] According to an embodiment of the present disclosure, a rendering processing device is further provided, which includes: a driver information acquisition module, configured to acquire first driver information of a depth range test DBT of a current first drawing call of a rendering object, wherein the depth range test includes an early DBT and a late DBT, and the first driver information includes a first enable flag of the early DBT, a second enable flag of the late DBT, and a second depth interval of the depth range test; a rasterization processing module, configured to perform rasterization processing on a first primitive in a tile of the rendering object in response to the first drawing call to obtain a corresponding first fragment; a first DBT module, configured to perform depth range processing on the first fragment according to the second depth interval when the first enable flag is valid. test to obtain an early DBT result of the first fragment; a first depth test and rendering module, for performing early depth test and rendering processing on the first fragment when the early DBT result of the first fragment is passed, and obtaining the rendered second fragment when the early depth test passes; a second DBT module, for performing a depth range test on the second fragment according to the second depth interval when the second enable flag is valid, and obtaining a late DBT result of the second fragment; a second depth test and rendering module, for performing late depth test and rendering processing on the second fragment when the late DBT result of the second fragment is passed, and obtaining the rendered first pixel data when the late depth test passes.

[0208] In some possible implementations, the first DBT module is further used to: when the first enable flag is invalid, determine that the early DBT result of the first fragment is passed; or the second DBT module is further used to: when the second enable flag is invalid, determine that the late DBT result of the second fragment is passed.

[0209] In some possible implementations, the first DBT module is configured to: read, based on the position information of the first fragment, a depth value corresponding to the position information from an on-chip depth buffer of a graphics processing device; and determine, when the depth value is within the second depth range, that an early DBT result of the first fragment is passed.

[0210] In some possible implementations, the rendering method of the rendering object includes tile-based deferred rendering (TBDR), wherein the rendering object is divided into multiple tiles, and the rendering object includes multiple primitives, each of the multiple tiles is covered by at least one primitive of the rendering object, and the first primitive is any one of the multiple primitives.

[0211] Figure 11 A block diagram of an electronic device provided in an embodiment of the present disclosure.

[0212] Reference Figure 11 An embodiment of the present disclosure provides an electronic device, which includes: at least one processor 701; at least one memory 702, and one or more I / O interfaces 703 connected between the processor 701 and the memory 702; wherein the memory 702 stores one or more computer programs that can be executed by the at least one processor 701, and the one or more computer programs are executed by the at least one processor 701 to enable the at least one processor 701 to perform the above-mentioned rendering processing method.

[0213] The present disclosure also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above-mentioned rendering method when executed by a processor. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0214] An embodiment of the present disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above-mentioned rendering processing method.

[0215] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium).

[0216] As is known to those skilled in the art, the term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically embodies computer-readable program instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0217] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0218] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, the state information of the computer-readable program instructions is used to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), so that the electronic circuit can execute the computer-readable program instructions, thereby implementing various aspects of the present disclosure.

[0219] The computer program product described herein may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0220] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0221] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0222] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0223] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0224] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A rendering processing method, characterized in that: include: Obtaining first configuration information of a depth range test (DBT) for a current first draw call of a rendering object, wherein the first configuration information includes a switch state of the depth range test and a first depth interval; When the depth range test is on, determining first driver information for the depth range test of the first draw call according to the first configuration information, second configuration information for the depth range test of the first draw call, and second driver information for the depth range test of the second draw call; The second draw call is a preceding draw call of the rendering object; the depth range test includes an early DBT and a late DBT, and the first driver information includes a first enable flag of the early DBT, a second enable flag of the late DBT, and a second depth interval of the depth range test; Instruction information is generated according to the first driving information and sent to a graphics processing device, so that the graphics processing device performs a depth range test in the first draw call based on the instruction information.

2. The method according to claim 1, characterized in that The second driving information includes a third enable flag of early DBT, a fourth enable flag of late DBT, and a third depth interval of the depth range test, The determining of the first driver information for the depth range test of the first draw call includes: Performing data verification and format conversion on the first depth interval to obtain the second depth interval; When both the third enable flag and the fourth enable flag are invalid, determining the first enable flag and the second enable flag according to the second configuration information; When at least one of the third enable flag and the fourth enable flag is valid, the first enable flag and the second enable flag are determined according to a difference between the second depth interval and the third depth interval, the third enable flag, the fourth enable flag, and the second configuration information.

3. The method according to claim 2, characterized in that The depth test includes an early depth test and a late depth test, and the second configuration information includes a fifth enable flag of the early depth test and a sixth enable flag of the late depth test; Wherein, when both the third enable flag and the fourth enable flag are invalid, determining the first enable flag and the second enable flag according to the second configuration information includes: When both the fifth enable flag and the sixth enable flag are invalid, determining that the first enable flag is valid and the second enable flag is invalid; When at least one of the fifth enable flag and the sixth enable flag is valid, the first enable flag and the second enable flag are determined according to the fifth enable flag and the sixth enable flag.

4. The method according to claim 2, characterized in that The depth test includes an early depth test and a late depth test, and the second configuration information includes a fifth enable flag of the early depth test and a sixth enable flag of the late depth test; Wherein, when at least one of the third enable flag and the fourth enable flag is valid, determining the first enable flag and the second enable flag according to the difference between the second depth interval and the third depth interval, the third enable flag, the fourth enable flag, and the second configuration information includes: When both the fifth enable flag and the sixth enable flag are invalid, the first enable flag and the second enable flag are determined in the following manner: If the third enable flag is valid and the fourth enable flag is invalid, determining that the first enable flag is valid and the second enable flag is invalid; If the fourth enable flag is valid and the second depth interval is consistent with the third depth interval, determining that the first enable flag is valid and the second enable flag is valid; If the fourth enable flag is valid and the second depth interval is inconsistent with the third depth interval, it is determined that the first enable flag is invalid and the second enable flag is valid.

5. The method according to claim 2, characterized in that The depth test includes an early depth test and a late depth test, and the second configuration information includes a fifth enable flag of the early depth test and a sixth enable flag of the late depth test; Wherein, when at least one of the third enable flag and the fourth enable flag is valid, determining the first enable flag and the second enable flag according to the difference between the second depth interval and the third depth interval, the third enable flag, the fourth enable flag, and the second configuration information includes: When at least one of the fifth enable flag and the sixth enable flag is valid, the first enable flag and the second enable flag are determined in the following manner: If the preset condition of the enable flag is met and the second depth interval is consistent with the third depth interval, determining that the first enable flag is valid and the second enable flag is valid; If the preset condition is met and the second depth interval is inconsistent with the third depth interval, determining that the first enable flag is invalid and the second enable flag is valid; If the preset condition is not met, determining the first enable flag and the second enable flag according to the fifth enable flag and the sixth enable flag, The preset condition includes that the fourth enable flag, the fifth enable flag and the sixth enable flag are all valid.

6. The method according to claim 2, characterized in that The performing data verification and format conversion on the first depth interval to obtain the second depth interval includes: Performing data verification on the minimum depth value and the maximum depth value of the first depth interval to determine the verified minimum depth value and the maximum depth value; The verified minimum depth value and maximum depth value are numerically converted according to a data format of a depth buffer of the graphics processing device to determine the second depth range.

7. A rendering processing method, characterized in that: include: Obtaining first driver information of a depth range test (DBT) for a current first draw call of a rendering object, where the depth range test includes an early DBT and a late DBT, and the first driver information includes a first enable flag of the early DBT, a second enable flag of the late DBT, and a second depth interval of the depth range test; In response to the first draw call, rasterize a first primitive in the tile of the rendering object to obtain a corresponding first fragment; When the first enable flag is valid, performing a depth range test on the first fragment according to the second depth interval to obtain an early DBT result of the first fragment; If the early DBT result of the first fragment is passed, perform early depth testing and rendering on the first fragment, and obtain a rendered second fragment if the early depth test passes; When the second enable flag is valid, performing a depth range test on the second fragment according to the second depth interval to obtain a late DBT result of the second fragment; If the post-DBT result of the second fragment is passed, a post-depth test and rendering process are performed on the second fragment, and if the post-depth test is passed, the rendered first pixel data is obtained.

8. The method according to claim 7, characterized in that The method further comprises: If the first enable flag is invalid, determining that the early DBT result of the first fragment is passed; or When the second enable flag is invalid, the later DBT result of the second fragment is determined to be passed.

9. The method according to claim 7, characterized in that Performing a depth range test on the first fragment according to the second depth interval to obtain an early DBT result of the first fragment includes: Reading, according to the position information of the first fragment, a depth value corresponding to the position information from an on-chip depth buffer of a graphics processing device; When the depth value is within the second depth range, the early DBT result of the first fragment is determined to be passed.

10. The method according to claim 7, characterized in that The rendering method of the rendering object includes tile-based deferred rendering (TBDR), wherein the rendering object is divided into multiple tiles, and the rendering object includes multiple primitives, each of the multiple tiles is covered by at least one primitive of the rendering object, and the first primitive is any one of the multiple primitives.

11. A rendering processing device, characterized in that: include: a configuration information acquisition module, configured to acquire first configuration information of a depth range test (DBT) of a current first draw call of a rendering object, wherein the first configuration information includes a switch state of the depth range test and a first depth interval; a driver information determination module, configured to, when the depth range test is on, determine first driver information for the depth range test of the first draw call based on the first configuration information, second configuration information for the depth test of the first draw call, and second driver information for the depth range test of the second draw call; The second draw call is a preceding draw call of the rendering object; the depth range test includes an early DBT and a late DBT, and the first driver information includes a first enable flag of the early DBT, a second enable flag of the late DBT, and a second depth interval of the depth range test; An instruction sending module is configured to generate instruction information according to the first driving information and send the instruction information to a graphics processing device, so that the graphics processing device performs a depth range test in the first drawing call based on the instruction information.

12. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor. The one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the rendering processing method according to any one of claims 1 to 10.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computer program implements the rendering processing method according to any one of claims 1 to 10.

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