Charge pump with low current mismatch and high output voltage swing

Abstract

The invention relates to the technical field of integrated circuits, in particular to a charge pump with low current mismatch and high output voltage swing, which comprises a current bias circuit used for copying bias current provided by a reference current source IREF and providing the copied bias current for a charging current source and a current absorber to provide accurate bias current; the charging current source is used for providing a charging path for a loop filter of a post-stage circuit; the current absorber is used for providing a discharge path for a loop filter of a post-stage circuit; and the charge pump core module is used for providing stable output voltage Vctrl for a loop filter of a post-stage circuit. According to the invention, the reverse jump voltage is used to reduce the influence of the clock feed-through effect on the output voltage; current mismatch can be effectively reduced; the output voltage swing is relatively high; and the operation speed of the charge pump circuit is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a charge pump with low current mismatch and high output voltage swing. Background Art

[0002] Phase-locked loop frequency synthesizer is an important component of modern communication system, and its performance characteristics directly determine the performance characteristics of the system. As an important component of the phase-locked loop, the performance of the charge pump directly affects the performance of the phase-locked loop. Figure 1 It is a traditional charge pump circuit, mainly composed of a charging current source I UP , a charging switch controlled by the UP signal, a discharging switch controlled by the DN signal, and a discharging current source I DN The load capacitor CL is the capacitor of the filter of the next stage circuit module of the charge pump. When the charging switch M1 is turned on and the discharging switch M2 is turned off, the charging current source I UP The filter capacitor CL is charged through the charging switch; when the charging switch is turned off and the discharge switch is turned on, the filter capacitor CL is connected to the discharge current source I DN Discharge is carried out. When both the charging switch and the discharging switch are turned off, the voltage on the capacitor CL remains unchanged. Since the next stage of the charge pump output is a loop filter, and the loop filter output voltage controls the output frequency of the voltage-controlled oscillator. Therefore, the output voltage range of the charge pump in the phase-locked loop is large, so the charge pump needs to have a certain output swing. This characteristic also leads to a huge impact of the channel length modulation effect on the charge and discharge current source of the charge pump, resulting in a mismatch between the charging current and the discharging current. The charge pump mismatch is as follows (1): (1) Ideally, the voltage in a phase-locked loop (PLL) must remain constant when locked. If the charge pump's charging and discharging currents are identical, the output voltage remains constant at the locked voltage. However, in reality, the charge and discharge currents are rarely identical. Therefore, after the PLL is locked, the output voltage will experience fluctuations periodic to the input reference frequency. This fluctuation manifests as spurious signals in the voltage-controlled oscillator's output frequency signal. The mismatch in charge and discharge currents also impacts phase noise and jitter performance. To minimize these effects and improve PLL performance, charge pump current matching must be carefully considered in PLL circuit design. Furthermore, conventional charge pumps exhibit non-ideal effects, such as clock feedthrough and charge sharing, which directly impact PLL performance. Due to the parasitic capacitance of MOS transistors, the pulse signal generated by the PFD can periodically affect the output voltage VCTRL, a phenomenon known as clock feedthrough. Charge pump switching also generates charge sharing. Both of these effects can cause instability in the control voltage VCTRL, and these non-ideal effects should be optimized in charge pump circuit design. Summary of the Invention

[0003] An object of the present invention is to provide a charge pump with low current mismatch and high output voltage swing, so as to solve the problems raised in the above background technology.

[0004] To solve the above technical problems, the present invention adopts a technical solution: a charge pump with low current mismatch and high output voltage swing, comprising: The current bias circuit is a wide-swing cascode current mirror circuit, which is used to replicate the bias current provided by the reference current source IREF and provide the replicated bias current to the charging current source and the current sink to provide accurate bias current; The charging current source is a low-voltage, high-matching precision current mirror circuit with operational amplifier feedback. One end of the charging current source is connected to the current bias circuit, and the other end of the charging current source is connected to the charge pump core module. The charging current source is used to provide a charging path for the loop filter of the subsequent circuit; The current sink is a low-voltage, high-matching precision current mirror circuit with operational amplifier feedback. One end of the current sink is connected to the current bias circuit, and the other end of the current sink is connected to the charge pump core module. The current sink is used to provide a discharge path for the loop filter of the subsequent circuit. The charge pump core module includes a first charge and discharge branch and a second charge and discharge branch. A rail-to-rail operational amplifier is connected between the first charge and discharge branch and the second charge and discharge branch. The charge pump core module is used to provide a stable output voltage Vctrl to the loop filter of the subsequent circuit.

[0005] Preferably, the current bias circuit includes nine NMOS transistors and nine PMOS transistors, wherein: the drain of the NMOS transistor M1 is connected to the reference current source IREF, the gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2 and the gate of the NMOS transistor M3, the drain of the NMOS transistor M2 is connected to the gate and drain of the PMOS transistor M4, the gate of the PMOS transistor M5, the gate of the PMOS transistor M10, the gate of the PMOS transistor M11, and the gate of the PMOS transistor M12, the drain of the NMOS transistor M3 is connected to The drain of the PMOS tube M5, the gate of the PMOS tube M6, the gate of the PMOS tube M7, the gate of the PMOS tube M8, and the gate of the PMOS tube M9 are connected; the gate of the NMOS tube M14 is connected to the gate and drain of the NMOS tube M13, the drain of the PMOS tube M10, the gate of the NMOS tube M15, and the gate of the NMOS tube M17; the drain of the NMOS tube M14 is connected to the source of the NMOS tube M13; the gate of the NMOS tube M16 is connected to the gate of the NMOS tube M18, and the gate of the NMOS tube M19. The drain of the OS transistor M15 is connected to the drain of the PMOS transistor M11, the drain of the NMOS transistor M16 is connected to the source of the NMOS transistor M15, the drain of the NMOS transistor M18 is connected to the source of the NMOS transistor M17, the drain of the NMOS transistor M17 is connected to the drain of the PMOS transistor M12, the source of the PMOS transistor M5 is connected to the drain of the PMOS transistor M6, the source of the PMOS transistor M10 is connected to the drain of the PMOS transistor M7, the source of the PMOS transistor M11 is connected to the drain of the PMOS transistor M8. The drain of the PMOS transistor M12 is connected to the drain of the PMOS transistor M9, the source of the PMOS transistor M4, the source of the PMOS transistor M6, the source of the PMOS transistor M7, the source of the PMOS transistor M8, and the source of the PMOS transistor M9 are connected to the power supply voltage VDD, and the source of the NMOS transistor M1, the source of the NMOS transistor M2, the source of the NMOS transistor M3, the source of the NMOS transistor M14, the source of the NMOS transistor M16, and the source of the NMOS transistor M18 are connected to the ground voltage VSS.

[0006] Preferably, the charging current source includes four PMOS transistors and an operational amplifier, wherein: the source of the PMOS transistor M33 and the source of the PMOS transistor M32 are connected to the power supply voltage VDD, the source of the PMOS transistor M34 and the drain of the PMOS transistor M33 and the positive input terminal of the operational amplifier OPA1 are connected, the gate of the PMOS transistor M33, the gate and drain of the PMOS transistor M34 are connected to the drain of the NMOS transistor M17, the drain of the PMOS transistor M32 and the source of the PMOS transistor M31 are connected to the negative input terminal of the operational amplifier OPA1, the gate of the PMOS transistor M31 is connected to the output terminal of the operational amplifier OPA1, and the drain of the PMOS transistor M31 is connected to the source of the PMOS transistor M29, the source of the PMOS transistor M27, the drain of the NMOS transistor M28, and the drain of the NMOS transistor M30.

[0007] Preferably, the current sink includes four NMOS transistors and an operational amplifier, wherein: the source of the NMOS transistor M20 and the source of the NMOS transistor M21 are connected to the ground voltage VSS, the gate of the NMOS transistor M20, the gate of the NMOS transistor M21, the gate and drain of the NMOS transistor M19 are connected to the drain of the PMOS transistor M12, the drain of the NMOS transistor M20 and the source of the NMOS transistor M19 are connected to the positive input terminal of the operational amplifier OPA3, the drain of the NMOS transistor M21 and the source of the NMOS transistor M22 are connected to the negative input terminal of the operational amplifier OPA3, the gate of the NMOS transistor M22 is connected to the output terminal of the operational amplifier OPA3, and the drain of the NMOS transistor M22 is connected to the source of the NMOS transistor M23, the source of the NMOS transistor M25, the drain of the PMOS transistor M24, and the drain of the PMOS transistor M26.

[0008] Preferably, the charge pump core module includes four NMOS tubes, four PMOS tubes and an operational amplifier, wherein: the drain of the NMOS tube M22 is connected to the source of the NMOS tube M23, the source of the NMOS tube M25, the drain of the PMOS tube M24, and the drain of the PMOS tube M26; the drain of the PMOS tube M31 is connected to the source of the PMOS tube M29, the source of the PMOS tube M27, the drain of the NMOS tube M28, and the drain of the NMOS tube M30; the gate of the NMOS tube M23 is connected to the input port DN-; the gate of the PMOS tube M24 is connected to the input port DN; the drain of the NMOS tube M23 is connected to the input port DN-; The source of the PMOS transistor M24, the source of the NMOS transistor M30, and the drain of the PMOS transistor M29 are connected to the negative input terminal and the output terminal of the operational amplifier OPA2, the gate of the NMOS transistor M30 is connected to the input port UP-, the gate of the PMOS transistor M29 is connected to the input port UP, the gate of the NMOS transistor M28 is connected to the input port UP, the gate of the PMOS transistor M27 is connected to the input port UP-, the source of the NMOS transistor M28, the drain of the NMOS transistor M25, the drain of the PMOS transistor M27, the source of the PMOS transistor M26, and the output port Vctrl are connected to the positive input terminal of the operational amplifier OPA2.

[0009] Preferably, the first charge and discharge branch is composed of an NMOS tube M23, a PMOS tube M24, a PMOS tube M29, and an NMOS tube M30, and the second charge and discharge branch is composed of an NMOS tube M25, a PMOS tube M26, a PMOS tube M27, and an NMOS tube M28.

[0010] From the above description of the structure of the present invention, it can be seen that compared with the prior art, the present invention has the following advantages: 1. The present invention uses a dummy switch composed of an NMOS transistor M23, a PMOS transistor M24, an NMOS transistor M25, a PMOS transistor M26, a PMOS transistor M27, an NMOS transistor M28, a PMOS transistor M29, and an NMOS transistor M30, rather than a traditional single-MOS transistor switch. This allows the reverse jump voltage to be used to reduce the impact of clock feedthrough on the output voltage when UP and DN signals arrive. A wide-swing cascode structure current mirror is used in the current bias circuit, and a low-voltage, high-matching precision current mirror with feedback from operational amplifiers OPA1 and OPA3 is used in the subsequent circuit. Both circuit structures can effectively reduce current mismatch, so that the current mismatch of the charge pump proposed by the present invention is approximately 0.049%. Therefore, the present invention can achieve lower current mismatch than traditional charge pumps. In addition, due to the use of a rail-to-rail operational amplifier OPA2 and a low-voltage, high-matching precision current mirror, the charge pump proposed in the present invention has a relatively high output voltage swing range (0.144V~1.656V). The large swing range can ensure that the charge pump circuit has good dynamic characteristics.

[0011] 2. The present invention adds two additional charge and discharge branches to the charge pump core module. By allowing current to flow alternately through the two charge and discharge branches, the current re-establishment time is eliminated, thereby improving the operating speed of the charge pump circuit. A rail-to-rail operational amplifier OPA2 is inserted between the two charge and discharge branches and connected in the form of unity gain, which can avoid the influence of charge injection and charge sharing effects on the output control voltage Vctrl. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings: Figure 1 This is a diagram of the traditional charge pump circuit structure; Figure 2 This is the overall circuit structure diagram of the charge pump proposed by the present invention; Figure 3 This is a structural diagram of a low-voltage, high-matching-precision current mirror circuit in a charge pump proposed by the present invention; Figure 4 This is a structural diagram of a rail-to-rail operational amplifier in the charge pump proposed by the present invention; Figure 5 is a low-frequency gain simulation curve of the rail-to-rail operational amplifier of the present invention; Figure 6 is a phase margin simulation curve of the rail-to-rail operational amplifier of the present invention; Figure 7 This is a simulation curve of the charge and discharge current matching characteristics of the charge pump circuit proposed in the present invention.

[0013] Figure: 1. Current bias circuit; 2. Charging current source; 3. Current sink; 4. Charge pump core module. DETAILED DESCRIPTION

[0014] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0015] Example refer to Figures 2 to 7 As shown, a charge pump with low current mismatch and high output voltage swing includes a current bias circuit 1, a charging current source 2, a current sink 3 and a charge pump core module 4; like Figure 2As shown, the current bias circuit 1 is a wide-swing cascode current mirror circuit, which is used to copy the bias current provided by the reference current source IREF and provide the copied bias current to the charging current source 2 and the current sink 3 to provide accurate bias current; the current bias circuit 1 includes nine NMOS transistors and nine PMOS transistors, wherein: the drain of the NMOS transistor M1 is connected to the reference current source IREF, the gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2 and the gate of the NMOS transistor M3, the drain of the NMOS transistor M2 is connected to the gate of the PMOS transistor M4 The gate and drain of the NMOS tube M14 are connected to the gate and drain of the NMOS tube M13, the gate of the PMOS tube M10, the gate of the PMOS tube M11, and the gate of the PMOS tube M12. The drain of the NMOS tube M3 is connected to the drain of the PMOS tube M5, the gate of the PMOS tube M6, the gate of the PMOS tube M7, the gate of the PMOS tube M8, and the gate of the PMOS tube M9. The gate of the NMOS tube M14 is connected to the gate and drain of the NMOS tube M13, the drain of the PMOS tube M10, the gate of the NMOS tube M15, and the gate of the NMOS tube M17. The gate of the NMOS tube M14 is connected to the gate and drain of the NMOS tube M13, the drain of the PMOS tube M10, the gate of the NMOS tube M15, and the gate of the NMOS tube M17. The drain of NMOS tube M4 is connected to the source of NMOS tube M13, the gate of NMOS tube M16 is connected to the gate of NMOS tube M18, the drain of NMOS tube M15, and the drain of PMOS tube M11, the drain of NMOS tube M16 is connected to the source of NMOS tube M15, the drain of NMOS tube M18 is connected to the source of NMOS tube M17, the drain of NMOS tube M17 is connected to the drain of PMOS tube M12, the source of PMOS tube M5 is connected to the drain of PMOS tube M6, and the source of PMOS tube M10 is connected to the drain of PMOS tube M7. The source of the PMOS transistor M11 is connected to the drain of the PMOS transistor M8, the source of the PMOS transistor M12 is connected to the drain of the PMOS transistor M9, the source of the PMOS transistor M4, the source of the PMOS transistor M6, the source of the PMOS transistor M7, the source of the PMOS transistor M8, and the source of the PMOS transistor M9 are connected to the power supply voltage VDD, and the source of the NMOS transistor M1, the source of the NMOS transistor M2, the source of the NMOS transistor M3, the source of the NMOS transistor M14, the source of the NMOS transistor M16, and the source of the NMOS transistor M18 are connected to the ground voltage VSS.

[0016] like Figure 2 and Figure 3As shown, the charging current source 2 is a low-voltage, high-matching precision current mirror circuit with operational amplifier feedback. One end of the charging current source 2 is connected to the current bias circuit 1, and the other end of the charging current source 2 is connected to the charge pump core module 4. The charging current source 2 is used to provide a charging path for the loop filter of the subsequent circuit; the charging current source 2 includes four PMOS tubes and an operational amplifier, wherein: the source of the PMOS tube M33 and the source of the PMOS tube M32 are connected to the power supply voltage VDD, the source of the PMOS tube M34 and the drain of the PMOS tube M33, the operational amplifier The gate of the PMOS tube M33 and the gate and drain of the PMOS tube M34 are connected to the drain of the NMOS tube M17. The drain of the PMOS tube M32 and the source of the PMOS tube M31 are connected to the negative input terminal of the operational amplifier OPA1. The gate of the PMOS tube M31 is connected to the output terminal of the operational amplifier OPA1. The drain of the PMOS tube M31 is connected to the source of the PMOS tube M29, the source of the PMOS tube M27, the drain of the NMOS tube M28, and the drain of the NMOS tube M30.

[0017] like Figure 2 and Figure 3 As shown, the current sink 3 is a low-voltage, high-matching precision current mirror circuit with operational amplifier feedback. One end of the current sink 3 is connected to the current bias circuit 1, and the other end of the current sink 3 is connected to the charge pump core module 4. The current sink 3 is used to provide a discharge path for the loop filter of the subsequent circuit; the current sink 3 includes four NMOS transistors and an operational amplifier, wherein: the source of the NMOS transistor M20 and the source of the NMOS transistor M21 are connected to the ground voltage VSS, the gate of the NMOS transistor M20, the gate of the NMOS transistor M21, and the gate of the NMOS transistor M1 are connected to the ground voltage VSS. The gate and drain of NMOS transistor M9 are connected to the drain of PMOS transistor M12, the drain of NMOS transistor M20 and the source of NMOS transistor M19 are connected to the positive input terminal of operational amplifier OPA3, the drain of NMOS transistor M21 and the source of NMOS transistor M22 are connected to the negative input terminal of operational amplifier OPA3, the gate of NMOS transistor M22 is connected to the output terminal of operational amplifier OPA3, and the drain of NMOS transistor M22 is connected to the source of NMOS transistor M23, the source of NMOS transistor M25, the drain of PMOS transistor M24, and the drain of PMOS transistor M26.

[0018] like Figure 3 As shown, the input end of the operational amplifier OPA3 is connected to the drain of the NMOS tube M20 and the drain of the NMOS tube M21. The NMOS tube M20 and the NMOS tube M21 are in the linear region. ds The value is always small. Analyzing the small signal model, the output resistance expression is obtained as follows (2): (2) Among them, A is the open-loop gain of the operational amplifier OPA3, gm22 is the transconductance of the NMOS tube M22, rds22 is the small signal resistance of the NMOS tube M22, and rds21 is the small signal resistance of the NMOS tube M21. That is, formula (2) shows that in order to compensate for the output resistance, the open-loop gain A of the operational amplifier OPA3 should be higher; the operational amplifier OPA3 increases the output resistance by forming a negative feedback structure with the NMOS tube M22; a large open-loop gain A can ensure that the drain voltages of the NMOS tubes M20 and M21 are the same, so that the output current accurately matches the input current; the output voltage of the current mirror needs to meet V out >V ds21 The requirements of the charge pump are met to ensure accurate replication of the output current; compared with the traditional structure, the output voltage of this structure is significantly reduced, and the output voltage swing is greatly improved; the overall structure of the charge pump proposed in the present invention Figure 2 In the figure, operational amplifier OPA1 and operational amplifier OPA3 are feedback amplifiers in the low-voltage and high-matching precision current mirror module. The output resistance should be increased while reducing the output voltage as much as possible. In order to obtain a large open-loop gain A, operational amplifier OPA1 and operational amplifier OPA3 use traditional two-stage operational amplifiers.

[0019] like Figure 5 、 Figure 6 and Figure 7As shown, the charge pump core module 4 includes a first charge and discharge branch and a second charge and discharge branch, a rail-to-rail operational amplifier is connected between the first charge and discharge branch and the second charge and discharge branch, and the charge pump core module 4 is used to provide a stable output voltage Vctrl to the loop filter of the subsequent circuit; the charge pump core module 4 includes four NMOS tubes, four PMOS tubes and an operational amplifier, wherein: the drain of the NMOS tube M22 is connected to the source of the NMOS tube M23, the source of the NMOS tube M25, the drain of the PMOS tube M24, and the drain of the PMOS tube M26, the drain of the PMOS tube M31 is connected to the source of the PMOS tube M29, the source of the PMOS tube M27, the drain of the NMOS tube M28, and the drain of the NMOS tube M30, the gate of the NMOS tube M23 is connected to the input port DN-, the gate of the PMOS tube M24 is connected to the input port DN, the drain of the NMOS tube M23, The source of the PMOS transistor M24, the source of the NMOS transistor M30, and the drain of the PMOS transistor M29 are connected to the negative input and output terminals of the operational amplifier OPA2; the gate of the NMOS transistor M30 is connected to the input port UP-; the gate of the PMOS transistor M29 is connected to the input port UP; the gate of the NMOS transistor M28 is connected to the input port UP; the gate of the PMOS transistor M27 is connected to the input port UP-; the source of the NMOS transistor M28, the drain of the NMOS transistor M25, the drain of the PMOS transistor M27, the source of the PMOS transistor M26, and the output port Vctrl are connected to the positive input terminal of the operational amplifier OPA2; the first charge and discharge branch is composed of the NMOS transistor M23, the PMOS transistor M24, the PMOS transistor M29, and the NMOS transistor M30; and the second charge and discharge branch is composed of the NMOS transistor M25, the PMOS transistor M26, the PMOS transistor M27, and the NMOS transistor M28. Among them, the specific circuit structure of the rail-to-rail operational amplifier OPA2 used in the present invention is as follows Figure 4As shown, the differential input pair of the rail-to-rail operational amplifier OPA2 is composed of a PMOS tube M41, an NMOS tube M42, an NMOS tube M43 and a PMOS tube M44. Tubes M42 and M43 are NMOS differential pairs to ensure that the operational amplifier can operate normally under a common-mode voltage close to the power supply voltage; M41 and M44 are PMOS differential pairs to ensure that the rail-to-rail operational amplifier OPA2 can operate normally under a common-mode voltage close to the ground potential; the output stage of the rail-to-rail operational amplifier OPA2 adopts a common-source amplification structure with a current source as the load to ensure that the entire operational amplifier output swings rail-to-rail; the frequency compensation scheme of the rail-to-rail operational amplifier adopts a Miller compensation capacitor to achieve circuit stability; in order to ensure good tracking characteristics and stability as a unity-gain amplifier, the rail-to-rail operational amplifier must ensure low-frequency gain and phase margin within the entire input common-mode voltage range. The low-frequency gain simulation curve of the rail-to-rail operational amplifier OPA2 used in the present invention is shown in FIG. Figure 5 As shown, the horizontal axis is the frequency, the vertical axis is the operational amplifier gain, and the low-frequency gain is 83dB under the condition that the power supply voltage VDD is 1.8V; the phase margin simulation curve of the rail-to-rail operational amplifier OPA2 used in the present invention is shown as follows Figure 6 As shown, the horizontal axis is the frequency, the vertical axis is the phase of the operational amplifier, and the phase margin is 75° when the power supply voltage VDD is 1.8V; Figure 7 This figure shows the charge-discharge current matching characteristics of the low-current-mismatch, high-output-voltage-swing charge pump circuit proposed in the present invention. The horizontal axis represents the output control voltage (Vctrl), and the vertical axis represents the charge-discharge current. The Iup curve represents the charge current, and the Idn curve represents the discharge current. The simulation results show that, with a power supply voltage (VDD) of 1.8V and a charge-discharge current of 20μA, the current mismatch ratio is less than 0.049% over an output voltage range of 0.144V to 1.656V.

[0020] Here’s how it works: UP- is the inverted signal of UP, and DN- is the inverted signal of DN; When the input port UP is at a high level and the input port DN is at a low level, the input port UP- is at a low level and the input port DN- is at a high level. At this time, the charge pump starts charging, the NMOS transistor M23 is turned on, the PMOS transistor M24 is turned on, the NMOS transistor M25 is turned off, the PMOS transistor M26 is turned off, the NMOS transistor M28 is turned on, the PMOS transistor M27 is turned on, the PMOS transistor M29 is turned off, and the NMOS transistor M30 is turned off. At this time, the discharge current flows through the NMOS transistor M23 and the PMOS transistor M24, so that the MOS transistors M21 and M22 that provide the discharge current in the charging state can also maintain the working state, eliminating the current re-establishment time and improving the speed of the charge pump circuit. The charging current flows through the NMOS transistor M28 and the PMOS transistor M27, causing the output control voltage Vctrl to continuously increase.

[0021] When the input port UP is at a low level and the input port DN is at a high level, the input port UP- is at a high level and the input port DN- is at a low level. At this time, the charge pump starts discharging, the NMOS transistor M23 is turned off, the PMOS transistor M24 is turned off, the NMOS transistor M25 is turned on, the PMOS transistor M26 is turned on, the NMOS transistor M28 is turned off, the PMOS transistor M27 is turned off, the NMOS transistor M30 is turned on, and the PMOS transistor M29 is turned on. At this time, the charging current flows through the NMOS transistor M30 and the PMOS transistor M29, thereby maintaining the MOS transistors M31 and M32 that provide the charging current in the discharge state in an operating state, eliminating the current re-establishment time and improving the speed of the charge pump circuit. The discharge current flows through the NMOS transistor M25 and the PMOS transistor M26, and the output control voltage Vctrl continues to decrease.

[0022] When the input port UP and the input port DN are both at a high level or a low level, the charge pump neither charges nor discharges, and the output control voltage Vctrl remains unchanged.

[0023] exist Figure 2 In the embodiment, when DN undergoes a level transition, the output control voltage Vctrl fluctuates through the parasitic capacitance of the MOS transistor M25. When UP undergoes a level transition, the output control voltage Vctrl fluctuates through the parasitic capacitance of the MOS transistor M28. This phenomenon is called the clock feedthrough effect. The MOS transistors M26 and M27 introduced in the present invention can reduce the influence of this non-ideal effect. For example, when DN transitions from a low level to a high level, the output control voltage Vctrl increases through the parasitic capacitance of the MOS transistor M25. At the same time, when DN− transitions from a high level to a low level, the output control voltage Vctrl decreases through the parasitic capacitance of the MOS transistor M26. In this way, the increasing and decreasing trends of the output control voltage Vctrl are offset.

[0024] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A charge pump with low current mismatch and high output voltage swing, characterized in that: include: The current bias circuit is a wide-swing cascode current mirror circuit, which is used to replicate the bias current provided by the reference current source IREF and provide the replicated bias current to the charging current source and the current sink to provide accurate bias current; The charging current source is a low-voltage, high-matching precision current mirror circuit with operational amplifier feedback. One end of the charging current source is connected to the current bias circuit, and the other end of the charging current source is connected to the charge pump core module. The charging current source is used to provide a charging path for the loop filter of the subsequent circuit; The current sink is a low-voltage, high-matching precision current mirror circuit with operational amplifier feedback. One end of the current sink is connected to the current bias circuit, and the other end of the current sink is connected to the charge pump core module. The current sink is used to provide a discharge path for the loop filter of the subsequent circuit. The charge pump core module includes a first charge and discharge branch and a second charge and discharge branch. A rail-to-rail operational amplifier is connected between the first charge and discharge branch and the second charge and discharge branch. The charge pump core module is used to provide a stable output voltage Vctrl to the loop filter of the subsequent circuit.

2. The charge pump with low current mismatch and high output voltage swing according to claim 1, wherein: The current bias circuit includes nine NMOS transistors and nine PMOS transistors, wherein: the drain of the NMOS transistor M1 is connected to the reference current source IREF, the gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2 and the gate of the NMOS transistor M3, the drain of the NMOS transistor M2 is connected to the gate and drain of the PMOS transistor M4, the gate of the PMOS transistor M5, the gate of the PMOS transistor M10, the gate of the PMOS transistor M11, and the gate of the PMOS transistor M12, the drain of the NMOS transistor M3 is connected to the gate of the PMOS transistor M4, the gate of the PMOS transistor M5, the gate of the PMOS transistor M10, the gate of the PMOS transistor M11, and the gate of the PMOS transistor M12, the drain of the NMOS transistor M3 is connected to the gate of the PMOS transistor M4. The drain of the S transistor M5, the gate of the PMOS transistor M6, the gate of the PMOS transistor M7, the gate of the PMOS transistor M8, and the gate of the PMOS transistor M9 are connected; the gate of the NMOS transistor M14 is connected to the gate and drain of the NMOS transistor M13, the drain of the PMOS transistor M10, the gate of the NMOS transistor M15, and the gate of the NMOS transistor M17; the drain of the NMOS transistor M14 is connected to the source of the NMOS transistor M13; the gate of the NMOS transistor M16 is connected to the gate of the NMOS transistor M18, and the gate of the NMOS transistor M19 is connected to the gate of the NMOS transistor M20. The drain of the NMOS tube M15 is connected to the drain of the PMOS tube M11, the drain of the NMOS tube M16 is connected to the source of the NMOS tube M15, the drain of the NMOS tube M18 is connected to the source of the NMOS tube M17, the drain of the NMOS tube M17 is connected to the drain of the PMOS tube M12, the source of the PMOS tube M5 is connected to the drain of the PMOS tube M6, the source of the PMOS tube M10 is connected to the drain of the PMOS tube M7, the source of the PMOS tube M11 is connected to the drain of the PMOS tube M8. The drains of the PMOS transistors M1 and M12 are connected, the source of the PMOS transistor M12 is connected to the drain of the PMOS transistor M9, the source of the PMOS transistor M4, the source of the PMOS transistor M6, the source of the PMOS transistor M7, the source of the PMOS transistor M8, and the source of the PMOS transistor M9 are connected to the power supply voltage VDD, and the source of the NMOS transistor M1, the source of the NMOS transistor M2, the source of the NMOS transistor M3, the source of the NMOS transistor M14, the source of the NMOS transistor M16, and the source of the NMOS transistor M18 are connected to the ground voltage VSS.

3. The charge pump with low current mismatch and high output voltage swing according to claim 1, wherein: The charging current source includes four PMOS transistors and an operational amplifier, wherein: the source of the PMOS transistor M33 and the source of the PMOS transistor M32 are connected to the power supply voltage VDD, the source of the PMOS transistor M34 is connected to the drain of the PMOS transistor M33 and the positive input terminal of the operational amplifier OPA1, the gate of the PMOS transistor M33, the gate and drain of the PMOS transistor M34 are connected to the drain of the NMOS transistor M17, the drain of the PMOS transistor M32 and the source of the PMOS transistor M31 are connected to the negative input terminal of the operational amplifier OPA1, the gate of the PMOS transistor M31 is connected to the output terminal of the operational amplifier OPA1, and the drain of the PMOS transistor M31 is connected to the source of the PMOS transistor M29, the source of the PMOS transistor M27, the drain of the NMOS transistor M28, and the drain of the NMOS transistor M30.

4. The charge pump with low current mismatch and high output voltage swing according to claim 1, wherein: The current sink includes four NMOS transistors and an operational amplifier, wherein: the source of the NMOS transistor M20 and the source of the NMOS transistor M21 are connected to the ground voltage VSS, the gate of the NMOS transistor M20, the gate of the NMOS transistor M21, the gate and drain of the NMOS transistor M19 are connected to the drain of the PMOS transistor M12, the drain of the NMOS transistor M20 and the source of the NMOS transistor M19 are connected to the positive input terminal of the operational amplifier OPA3, the drain of the NMOS transistor M21 and the source of the NMOS transistor M22 are connected to the negative input terminal of the operational amplifier OPA3, the gate of the NMOS transistor M22 is connected to the output terminal of the operational amplifier OPA3, and the drain of the NMOS transistor M22 is connected to the source of the NMOS transistor M23, the source of the NMOS transistor M25, the drain of the PMOS transistor M24, and the drain of the PMOS transistor M26.

5. The charge pump with low current mismatch and high output voltage swing according to claim 1, wherein: The charge pump core module includes four NMOS transistors, four PMOS transistors and an operational amplifier, wherein: the drain of the NMOS transistor M22 is connected to the source of the NMOS transistor M23, the source of the NMOS transistor M25, the drain of the PMOS transistor M24, and the drain of the PMOS transistor M26; the drain of the PMOS transistor M31 is connected to the source of the PMOS transistor M29, the source of the PMOS transistor M27, the drain of the NMOS transistor M28, and the drain of the NMOS transistor M30; the gate of the NMOS transistor M23 is connected to the input port DN-; the gate of the PMOS transistor M24 is connected to the input port DN; the drain of the NMOS transistor M23, the PMOS transistor M29, and the drain of the PMOS transistor M30 are connected; The source of the MOS transistor M24, the source of the NMOS transistor M30, and the drain of the PMOS transistor M29 are connected to the negative input terminal and the output terminal of the operational amplifier OPA2. The gate of the NMOS transistor M30 is connected to the input port UP-, the gate of the PMOS transistor M29 is connected to the input port UP, the gate of the NMOS transistor M28 is connected to the input port UP, and the gate of the PMOS transistor M27 is connected to the input port UP-. The source of the NMOS transistor M28, the drain of the NMOS transistor M25, the drain of the PMOS transistor M27, the source of the PMOS transistor M26, and the output port Vctrl are connected to the positive input terminal of the operational amplifier OPA2.

6. The charge pump with low current mismatch and high output voltage swing according to claim 5, characterized in that: The first charge and discharge branch is composed of an NMOS transistor M23, a PMOS transistor M24, a PMOS transistor M29, and an NMOS transistor M30, and the second charge and discharge branch is composed of an NMOS transistor M25, a PMOS transistor M26, a PMOS transistor M27, and an NMOS transistor M28.

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