Apparatus using chipset-based storage architecture

Abstract

The present disclosure relates to an apparatus using a chipset-based storage architecture. The memory architecture includes: a plurality of accelerator memory devices on a package substrate; a front-end chip on the package substrate and configured to perform communication with a host device; and a plurality of back-end chips configured to perform communication with the front-end chip on the package substrate and control at least a portion of the plurality of accelerator memory devices, and coupled to each other in a daisy chain scheme.

Description

[0001] Cross Reference to Related Applications

[0002] This application is a continuation-in-part of U.S. Patent Application No. 17 / 898,975, filed August 30, 2022, and published as US20230080284A1 on March 16, 2023, which claims priority to and the benefit of (1) Korean Patent Application No. 10-2021-0121036, filed September 10, 2021, and (2) Korean Patent Application No. 10-2022-0067871, filed June 2, 2022.

[0003] In addition, this application claims priority to and the benefit of Korean Patent Application No. 10-2024-0054450, filed April 24, 2024.

[0004] Further, this application claims priority to and the benefit of (1) U.S. Patent Application No. 18 / 641,141, filed April 19, 2024, (2) U.S. Patent Application No. 18 / 643,881, filed April 23, 2024, (3) U.S. Patent Application No. 18 / 773,410, filed July 15, 2024, and (4) U.S. Patent Application No. 18 / 802,751, filed August 13, 2024.

[0005] This application incorporates by reference all of the above prior applications in their entirety as part of the disclosure of this application. TECHNICAL FIELD

[0006] Embodiments of the disclosed technology relate to a storage architecture, and more particularly, to a chiplet-based storage architecture. BACKGROUND

[0007] Limited system resources in various embodiments of data storage systems or devices can not meet the needs of such data storage systems or devices, including data storage systems or devices that implement the latest system flexibility features. For example, when a storage architecture is configured in the form of a monolithic integrated circuit, a single-skeleton integrated circuit, or a system on chip (SoC), the storage architecture has an interface that is coupled to a host device of the storage architecture and that is compliant with a storage medium standard. This represents an example of a limitation that the storage architecture is only valid for a host device and a storage medium of a specific standard. SUMMARY

[0008] A storage architecture according to an embodiment of the disclosed technology can include a plurality of accelerator memory devices located on a package substrate, a front-end chip located on the package substrate and configured to perform communication with a host device, and a plurality of back-end chips configured to perform communication with the front-end chip on the package substrate and control at least a portion of the plurality of accelerator memory devices, the plurality of back-end chips being serially linked to each other based on a daisy chain scheme.

[0009] A storage architecture according to an embodiment of the disclosed technology can include a plurality of accelerator memory devices located on a package substrate, a front-end chip located on the package substrate and configured to perform communication with a host device, and a plurality of back-end chips configured to perform communication with the front-end chip on the package substrate and control at least a portion of the plurality of accelerator memory devices, the plurality of back-end chips being serially linked to each other based on a daisy chain scheme.

[0010] A storage architecture according to an embodiment of the disclosed technology can include a plurality of accelerator memory devices located on a package substrate, a front-end chip located on the package substrate and configured to perform communication with a host device, and a plurality of back-end chips configured to perform communication with the front-end chip on the package substrate and control at least a portion of the plurality of accelerator memory devices, the plurality of back-end chips being serially linked to each other based on a daisy chain scheme. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a block diagram illustrating a storage architecture according to an embodiment of the disclosed technology.

[0012] Figure 2 is a block diagram illustrating Figure 1 a configuration of a front-end chip of the storage architecture of

[0013] Figure 3 is a block diagram illustrating a back-end chip constituting a storage architecture according to an embodiment of the disclosed technology.

[0014] Figure 4 is a block diagram illustrating a back-end chip constituting a storage architecture according to another embodiment of the disclosed technology.

[0015] Figure 5 is a block diagram illustrating a back-end chip constituting a storage architecture according to yet another embodiment of the disclosed technology.

[0016] Figure 6 is a block diagram illustrating a back-end chip constituting a storage architecture according to yet another embodiment of the disclosed technology.

[0017] Figure 7is a block diagram illustrating a back-end chip constituting a storage architecture according to yet another embodiment of the disclosed technology.

[0018] Figure 8 is a block diagram illustrating a back-end chip constituting a storage architecture according to yet another embodiment of the disclosed technology.

[0019] Figure 9 is a block diagram illustrating a back-end chip constituting a storage architecture according to yet another embodiment of the disclosed technology.

[0020] Figure 10 is a block diagram illustrating a storage architecture according to another embodiment of the disclosed technology.

[0021] Figure 11 is a block diagram illustrating Figure 10 a configuration of a front-end chip of a storage architecture.

[0022] Figure 12 is a block diagram illustrating a storage architecture according to yet another embodiment of the disclosed technology.

[0023] Figure 13 is a block diagram illustrating Figure 12 a configuration of a first back-end package of a storage architecture.

[0024] Figure 14 is a block diagram illustrating a storage architecture according to yet another embodiment of the disclosed technology.

[0025] Figure 15 is a block diagram illustrating Figure 14 a configuration of a first back-end package of a storage architecture.

[0026] Figure 16 is a block diagram illustrating Figure 14 a configuration of a first back-end package of a storage architecture.

[0027] Figure 17 is a diagram illustrating a configuration of a back-end package and three sub-back-end packages coupled to a front-end chip in a daisy chain scheme according to an embodiment of the disclosed technology.

[0028] Figure 18 is a diagram illustrating an example of a storage module employing a storage architecture according to an embodiment of the disclosed technology.

[0029] Figure 19 is a block diagram illustrating a storage architecture according to yet another embodiment of the disclosed technology.

[0030] Figure 20 is a diagram illustrating an example of a storage module employing a storage architecture according to Figure 19

[0031] ​Figure 21A and Figure 21B is a block diagram illustrating a storage architecture according to yet another embodiment of the disclosed technology.

[0032] Figure 22 is an example of a configuration of a front-end chip of the storage architecture of Figure 21A and Figure 21B .

[0033] Figure 23 is an example of a configuration of a back-end chip of the storage architecture of Figure 21A and Figure 21B .

[0034] Figure 24 is a block diagram illustrating a storage architecture according to yet another embodiment of the disclosed technology.

[0035] Figure 25 is a block diagram illustrating a storage architecture according to yet another embodiment of the disclosed technology.

[0036] Figure 26 is an example of a configuration of a front-end link and a back-end link of the storage architecture of Figure 21A and Figure 21B .

[0037] Figure 27 is an example of a configuration of a front-end link and a back-end link of the storage architecture of

[0038] Figure 28 is a block diagram illustrating a configuration of a front-end link and a back-end link of a storage architecture according to an embodiment of the disclosed technology.

[0039] Figure 29 is a block diagram illustrating a configuration of a front-end link and a back-end link of a storage architecture according to another embodiment of the disclosed technology.

[0040] Figure 30 is a block diagram illustrating a configuration of a front-end link and a back-end link of a storage architecture according to yet another embodiment of the disclosed technology.

[0041] Figure 31 is an example of a packet transmission process in a front-end link and a back-end link of Figures 28-30 .

[0042] Figure 32 is an example of a communication process from a front-end link to a back-end link of Figures 28-30 .

[0043] Figure 33 is another example of a communication process from a front-end link to a back-end link of Figures 28-30 . DETAILED DESCRIPTION

[0044] Data storage systems in various computing or communication applications can include one or more memory devices for storing data and communicating with one or more host devices to perform various data storage operations according to commands or requests of the host devices. Such data storage systems require certain flexibility to enable the data storage systems to adapt to changes in the host devices or changes in the memory devices. The technology in this patent document provides a data storage architecture that allows an interface device or system between a host device and a memory system having one or more memory devices for storing data to implement different chipsets for communicating with the host device or the memory devices.

[0045] Figure 1 is a block diagram illustrating a storage architecture 100A of an interface device or system between a host device and a memory system having one or more memory devices for storing data according to embodiments of the disclosed technology. The storage architecture 100A can include a front-end chip 200 and a plurality of back-end chips, such as two back-end chips 310 and 320 as shown. Although Figure 1 The example of the storage architecture 100A in includes two back-end chips 310 and 320, but in various implementations, more back-end chips can be included in the storage architecture 100A. The front-end chip 200 can be disposed between a host device, such as a processor, and the back-end chips 310 and 320. The back-end chips 310 and 320 can be disposed between the front-end chip 200 and the memory devices. The front-end chip 200 can communicate with the host device and the back-end chips 310 and 320. The back-end chips 310 and 320 can communicate with the front-end chip 200 and the memory devices storing data.

[0046] The front-end chip 200 and the back-end chips 310 and 320 can be configured in a chip set structure. Accordingly, the front-end chip 200 and the back-end chips 310 and 320 can have a structure physically separated from each other, thereby acting independently of each other, and can transmit data and signals through a bus between the chips. As explained further below, the physical separation between the front-end chip 200 and the back-end chips (e.g., 310 and 320) allows the front-end chip 200 to be replaced separately from the back-end chips (e.g., 310 and 320), and the back-end chips (e.g., 310 and 320) to be replaced separately from the front-end chip 200. In various embodiments, a host device can operate at a faster speed than a memory device storing data. In such embodiments, the front-end chip 200 can be configured to support high-speed communication with a high-speed host device, while the back-end chips 310 and 320 can be configured to support low-speed communication with a low-speed memory device. In various embodiments of the disclosed technology, "high-speed" and "low-speed" denote a relative speed difference between a host device and a memory device. Due to the difference in speed and performance supported by the front-end chip 200 and the back-end chips 310 and 320, the front-end chip 200 can be manufactured through a relatively fine process compared to the back-end chips 310 and 320. A memory device in communication with the back-end chip 310 or 320 can be configured to include a volatile memory device such as a DRAM device, an accelerator memory device that performs an acceleration operation, or a non-volatile memory device such as a phase change memory (PCM) device or a flash memory device. In some embodiments, such a memory device can have a module structure including a volatile memory device, an accelerator memory device, and a non-volatile memory device.

[0047] The front-end chip 200 can include a host interface 210 for communication with a host device. In addition, the front-end chip 200 can include front-end links (FE.LINK) 221(1) and 221(2) for communication with the back-end chips 310 and 320, respectively. The back-end chips 310 and 320 can include back-end links (BE1.LINK) 311 and 312, respectively, for communication with the front-end chip 200. In an example, the host interface 210 of the front-end chip 200 can be configured by employing a Peripheral Component Interconnect Express (hereinafter referred to as "PCIe") protocol. In another example, the host interface 210 can be configured by employing a Compute Express Link (hereinafter referred to as "CXL") protocol. In some cases, the host interface 210 can be configured by employing both the PCIe protocol and the CXL protocol. The first front-end link 221(1) of the front-end chip 200 can be coupled to the back-end link 311 of the first back-end chip 310. The second front-end link 221(2) of the front-end chip 200 can be coupled to the back-end link 321 of the second back-end chip 320.

[0048] When the storage architecture 100A according to the present embodiment is employed in a computing system, in some implementations, only the front-end chip 200 can be replaced with another replacement front-end chip equipped with a revised or updated communication protocol with the host device, while the back-end chips 310 and 320 remain unchanged. In some other implementations, only the back-end chips 310 and 320 can be replaced with replacement front-end chips equipped with a revised or updated communication protocol with the memory devices, while the front-end chip 200 remains unchanged. In other implementations, both the front-end chip 200 and the back-end chips 310 and 320 can be replaced with updated front-end and back-end chips equipped with revised or updated communication protocols with the host and memory devices. In an example, the host device can support a PCIe protocol of the fifth generation standard, while the memory devices can support DDR5 standard DRAM, thus, the front-end chip 200 of the storage architecture 100A can support the PCIe fifth generation protocol, while the back-end chips 310 and 320 of the storage architecture 100A can support the DDR5 standard DRAM. When the storage architecture has a system on a chip (SOC) format, if the interface standard of the host device changes while the DRAM standard remains unchanged or vice versa, the storage architecture itself needs to change to support the changed standard of the host device. On the other hand, when only the interface standard of the host device changes, the storage architecture 100A according to the present embodiment can replace only the front-end chip 200 with a replacement front-end chip that supports the new interface standard with the host device. When only the DRAM standard changes while the host device standard remains unchanged, the storage architecture 100A allows replacing only the back-end chips 310 and 320 with updated back-end chips that support the changed DRAM standard, while keeping the current front-end chip to communicate with the host device.

[0049] Figure 2 is a block diagram illustrating an example of a configuration of the front-end chip 200, in which some examples of various components of the storage architecture 100A for implementing Figure 1 are shown in more detail. In an example, the front-end chip 200 according to the present example communicates with the host device in the PCIe fifth generation standard with 8 lanes (x8) for communication. In other implementations, the front-end chip 200 can communicate with the host device using a different communication protocol such as the Compute Express Link (CXL) standard for high-speed communication.

[0050] Referring to Figure 2, the front-end chip 200 can include a host interface 210, a plurality of (e.g., "K" number of) front-end links (FE.LINK) 221(1) through 221(K) ("K" is a natural number), a core logic circuit 230, a flow switching logic circuit 240, a PCI logic circuit 250, an NVMe (Non-Volatile Memory Express) logic circuit 260, and a link structure 270. The host interface 210 can include a PCIe physical layer 211, a PCIe link 212, and an interface logic circuit 213. The PCIe physical layer 211 can be a physical layer coupled with a host device according to the PCIe 5thgeneration standard. The PCIe physical layer 211 can transmit a signal and / or data transmitted from the host device to the PCIe link 212 according to the PCIe protocol. In addition, the PCIe physical layer 211 can transmit a signal and / or data transmitted from the PCIe link 212 to the host device according to the PCIe protocol. The PCIe link 212 can provide a path of signals and data between the PCIe physical layer 211 and the interface logic circuit 213. The PCIe link 212 can transmit a signal and / or data transmitted from the PCIe physical layer 211 to the interface logic circuit 213. In addition, the PCIe link 212 can transmit a signal and / or data transmitted from the interface logic circuit 213 to the PCIe physical layer 211.

[0051] The interface logic circuit 213 can control signal and data processing in the host interface 210. The interface logic circuit 213 can process a signal and / or data transmitted from the PCIe link 212, and can transmit the processed signal and / or data to the flow switching logic circuit 240. In addition, the interface logic circuit 213 can process a signal and / or data transmitted from the flow switching logic circuit 240, and can transmit the processed signal and / or data to the PCIe link 212. In an example, the interface logic circuit 213 can include a logic circuit for data integrity (DIF / DIX) 213A. The logic 213A can include an additional byte such as a data integrity field (DIF) in data, or can generate data integrity extension (DIX) data for checking data integrity. In an example, the interface logic circuit 213 can include a flow control logic circuit for controlling data transmission, such as an advanced extensible interface (AXI) flow control logic circuit (AXI-ST) 213B.

[0052] In an example, the interface logic circuit 213 can include a buffer memory circuit (DUAL PORT) 213C for buffering data in the host interface 210.

[0053] The first through "K"th front-end links 221(1) through 221(K) can be coupled to a memory device through an external bus, respectively, as described with reference to FIG. 1. Figure 1The front-end links 221(1) through 221(K) can be coupled to the link fabric 270 through an internal bus within the front-end chip 200. The front-end links 221(1) through 221(K) can send signals and / or data sent through the link fabric 270 to the memory device. In addition, the front-end links 221(1) through 221(K) can send signals and / or data sent from the memory device to the link fabric 270.

[0054] The core logic circuit 230 can perform a function of processing instructions and data in the front-end chip 200. The core logic circuit 230 can include a plurality of core circuits 231 and 232(1) through 232(M). In an example, the core logic circuit 230 can include a first core circuit (CORE1) 231 and a plurality (e.g., “M” number of) second core circuits (CORE2) 232(1) through 232(M) (“M” is a natural number). Although Figure 2Although not shown in the figure, each of the first core circuit 231 and the second core circuits 232(1) to 232(M) can include a register file. The first core circuit 230 can include a first instruction tightly coupled memory (ITCM1) circuit and a first data tightly coupled memory (DTCM1) circuit, and the first core circuit 231 can be coupled to the first instruction tightly coupled memory (ITCM1) circuit and the first data tightly coupled memory (DTCM1) circuit through an internal high-speed interface. Each of the second core circuits 232(1) to 232(M) can include a second instruction tightly coupled memory (ITCM2) circuit and a second data tightly coupled memory (DTCM2) circuit, and be coupled to the second instruction tightly coupled memory (ITCM2) circuit and the second data tightly coupled memory (DTCM2) circuit through an internal high-speed interface. The first core circuit 231 can be configured to have a faster processing speed than the second core circuits 232(1) to 232(M). In an example, a first operation speed of the first core circuit 231 can be in GHz, and a second operation speed of each of the second core circuits 232(1) to 232(M) can be in Hz. The first instruction tightly coupled memory (ITCM1) circuit can be configured to have a larger storage capacity than the second instruction tightly coupled memory (ITCM2) circuit. In some embodiments, the second data tightly coupled memory (DTCM2) circuit can have a larger storage capacity than the first data tightly coupled memory (DTCM1). In an example, each of the first instruction tightly coupled memory ITCM1 circuit, the first data tightly coupled memory DTCM1 circuit, the second instruction tightly coupled memory ITCM2 circuit, and the second data tightly coupled memory DTCM2 circuit can be configured with an SRAM circuit. Although not shown in the figure, the core logic circuit 230 can include a logic circuit for processing sub-commands generated through a split command.

[0055] The stream switching logic circuit 240 can control the transmission path of signals and data in the front-end chip 200. To this end, the stream switching logic circuit 240 can control various internal buses in the front-end chip 200. The stream switching logic circuit 240 can be coupled to other components in the front-end chip 200, i.e., the host interface 210, the core logic circuit 230, the PCI logic circuit 250, the NVMe logic circuit 260, and the link fabric 270, through internal buses.

[0056] The PCI logic circuit 250 can provide a means for connecting various peripheral devices of a PCI scheme. In an example, the PCI logic circuit 250 can utilize a PCI mezzanine card (PMC) configuration. The PMC can be configured by combining a common mezzanine card (CMD) and a PCI bus. The PCI logic circuit 250 can be removed from the front-end chip 200 when connection with peripheral devices of a PCI scheme is not needed.

[0057] The NVMe logic circuit 260 can perform interface connection for a high-speed non-volatile memory (NVMe) device. In an example, the NVMe logic circuit 260 can include a conversion logic circuit that converts a virtual memory circuit to a physical memory circuit. In an example, the NVMe logic circuit 260 can generate a physical region page (PRP) having physical memory information of an NVMe device on which a command is to be run. In an example, the NVMe logic circuit 260 can generate a scatter gather list (SGL) that corresponds to a chained list of distributed collection elements.

[0058] The link structure 270 can be disposed between the flow switching logic circuit 240 and the front-end links 221(1) through 221(K). The link structure 270 can serve as a transmission path of signals and / or data between the flow switching logic circuit 240 and the front-end links 221(1) through 221(K). In an example, the link structure 270 can be configured as a master bus. Although Figure 2 Although not shown in FIG. 27, the link structure 270 can be configured as a structure that provides routing between nodes.

[0059] Figure 3 is a block diagram illustrating an example of a back-end chip 300A of a storage architecture of a segment between a front-end chip and a memory device that communicates with a host device of a storage architecture 100A according to an embodiment of the disclosed technology. The following description of the back-end chip 300A can apply to each of the back-end chips 310 and 320 of the storage architecture 100A of Figure 1 is a block diagram illustrating an example of a back-end chip 300A of a storage architecture of a segment between a front-end chip and a memory device that communicates with a host device of a storage architecture 100A according to an embodiment of the disclosed technology. The following description of the back-end chip 300A can apply to each of the back-end chips 310 and 320 of the storage architecture 100A of Figure 1 The back-end chip 300A according to the present example is configured to be coupled to a DRAM device as a memory device in a storage system. The back-end chip 300A can include a back-end link 321, an extreme memory profile (XMP) enhancer (XMPE) 322, a DRAM controller 323, and a DRAM physical layer (DRAM PHY) 324. The back-end link 321 can be coupled to a front-end link (FEL) of a front-end chip (FEC) through an external bus. Figure 2221 (1) to 221 (K)). The XMP enhancer 322 may support a memory profile function of the DRAM device. The DRAM controller 323 may control access operations to the DRAM device, such as read operations and write operations. The DRAM physical layer 324 may perform an interface connection with the DRAM device. The DRAM physical layer 324 may communicate with the DRAM device through a bus having a bandwidth corresponding to the standard of the DRAM device. Although Figure 3 Although not shown in the figure, the back-end chip 300A according to this example can form a package together with the DRAM device. In this case, the package can be configured in such a way that the back-end chip 300A is arranged in a first region of the package substrate and the DRAM chips are stacked and arranged in a second region of the package substrate.

[0060] Figure 4 The present invention is a diagram showing a configuration according to an embodiment of the disclosed technology. Figure 1 The following description of the back-end chip 300B is applicable to the front-end chip 300B of the storage architecture 100A in the embodiment of the present invention. Figure 1 Each of the back-end chips 310 and 320 of the storage architecture 100A. Figure 4 In the example shown, the various memory devices connected to the backend chip 300B are DRAM devices. As shown, the backend chip 300B may include a backend link 321, a first AXI stream control logic circuit 331A, a power management logic circuit 333, an embedded application logic circuit 334, a system management service logic circuit 335, a tightly coupled memory (TCM) circuit 336, a memory management logic circuit 337, a second AXI stream control logic circuit 331B, a crossbar 338, and a DRAM controller / DRAM physical layer 339. The DRAM controller / DRAM physical layer 339 may include a third AXI stream control logic circuit 331C.

[0061] The back-end link 321 can be connected to the front-end chip ( Figure 2 200) front-end link ( Figure 2one of 221(1) through 221(K) of FIG. 21. The first AXI stream control logic circuit 331A can be coupled to the back-end link 321 through an internal bus. The internal bus coupled to the first AXI stream control logic circuit 331A can include a plurality of lanes, such as a read lane and a write lane. The first AXI stream control logic circuit 331A can provide a data transmission path between the back-end link 321 and the crossbar 338. The power management logic circuit 333 can manage power in the back-end chip 300B. The embedded application logic circuit 334 can perform operations according to a programmed embedded application. The system management services logic circuit 335 can perform system management services operations in the back-end chip 300B. The system management services logic circuit 335 can be coupled to the crossbar 338 through an internal bus.

[0062] The tightly coupled memory circuit 336 can be used as a buffer memory circuit in the back-end chip 300B. The memory management logic circuit 337 can perform control operations on the tightly coupled memory circuit 336. The second AXI stream control logic circuit 331B can be coupled to the crossbar 338 through an internal bus. The second AXI stream control logic circuit 331B can provide a data transmission path between the memory management logic circuit 337 and the crossbar 338. The crossbar 338 can be coupled to the first AXI stream control logic circuit 331A, the second AXI stream control logic circuit 331B, a third AXI stream control logic circuit 331C of the DRAM controller / DRAM physical layer 339, and the system management services logic circuit 335 through an internal bus. The crossbar 338 can be configured to specify various paths for signals and data received through the internal bus. The DRAM controller / DRAM physical layer 339 can be coupled to the crossbar 338 through the third AXI stream control logic circuit 331C. The DRAM controller / DRAM physical layer 339 can be coupled to a plurality of DRAM devices (DRAMs) through an external bus.

[0063] Figure 5 is a block diagram illustrating a back-end chip 300C of a memory architecture according to an embodiment of the disclosed technology. The following description of the back-end chip 300C can apply to each of the back-end chips 310 and 320 of the memory architecture 100A of FIG. 21. Figure 1 is a block diagram illustrating a back-end chip 300C of a memory architecture according to an embodiment of the disclosed technology. The following description of the back-end chip 300C can apply to each of the back-end chips 310 and 320 of the memory architecture 100A of FIG. 21. Figure 1 is a block diagram illustrating a back-end chip 300C of a memory architecture according to an embodiment of the disclosed technology. The following description of the back-end chip 300C can apply to each of the back-end chips 310 and 320 of the memory architecture 100A of FIG. 21. Figure 5 is a block diagram illustrating a back-end chip 300C of a memory architecture according to an embodiment of the disclosed technology. The following description of the back-end chip 300C can apply to each of the back-end chips 310 and 320 of the memory architecture 100A of FIG. 21. Figure 4 is a block diagram illustrating a back-end chip 300C of a memory architecture according to an embodiment of the disclosed technology. The following description of the back-end chip 300C can apply to each of the back-end chips 310 and 320 of the memory architecture 100A of FIG. 21. Figure 5 is a block diagram illustrating a back-end chip 300C of a memory architecture according to an embodiment of the disclosed technology. The following description of the back-end chip 300C can apply to each of the back-end chips 310 and 320 of the memory architecture 100A of FIG. 21. Figure 4The difference of the back-end chip 300B is that the acceleration engine 349 is used instead of the DRAM controller / DRAM physical layer ( Figure 4 339 in the backend chip 300C). The acceleration engine 349 can be connected to the crossbar switch 338 via the third AXI stream control logic circuit 331C and the internal bus in the backend chip 300C. The acceleration engine 349 can be connected to multiple accelerator memory devices via an external bus. The accelerator memory device can be configured in a form of a memory device and an operating processor configured in a single chip. Therefore, the acceleration engine 349 can control the algorithm operations and memory operations of the accelerator memory device.

[0064] Figure 6 1 is a block diagram illustrating a back-end chip 300D constituting a storage architecture according to an embodiment of the disclosed technology. The following description of the back-end chip 300D may be applicable to Figure 1 Each of the backend chips 310 and 320 of the storage architecture 100A. The backend chip 300D according to this example can be configured to be connected to multiple managed DRAM solution (MDS) modules. Figure 6 In, with Figure 4 and Figure 5 The same reference numerals denote the same components, and thus repeated descriptions will be omitted. Figure 6 , back-end chip 300D and Figure 5 The difference of the back-end chip 300C is that the MDS controller 359 is used instead of the DRAM controller / DRAM physical layer ( Figure 4 339) and the acceleration engine ( Figure 5 349 in the backend chip 300D). The MDS controller 359 can be connected to the crossbar switch 338 via the third AXI stream control logic circuit 331C and the internal bus in the backend chip 300D. The MDS controller 359 can be connected to the MDS module via the external bus. The MDS controller 359 can control access operations to the MDS module.

[0065] Figure 7 1 is a block diagram illustrating a back-end chip 300E constituting a storage architecture according to an embodiment of the disclosed technology. The following description of the back-end chip 300E may be applicable to Figure 1 Each of the back-end chips 310 and 320 of the storage architecture 100A. The back-end chip 300E according to this example can be configured to be connected to multiple PCM devices. Figure 7 In, with Figures 4-6 The same reference numerals denote the same components, and thus repeated descriptions will be omitted. Figure 7 , back-end chip 300E and Figure 4 Back-end chip 300B, Figure 5 Back-end chip 300C, Figure 6The difference of the back-end chip 300D may be that the PCM controller 369 is used instead of the DRAM controller / DRAM physical layer ( Figure 4 339), acceleration engine ( Figure 5 349) and MDS controller ( Figure 6 359). The PCM controller 369 can be connected to the crossbar switch 338 via the third AXI stream control logic circuit 331C and the internal bus. The PCM controller 369 can be connected to the PCM device via the external bus. The PCM controller 369 can control access operations to the PCM device.

[0066] Figure 8 1 is a block diagram illustrating a back-end chip 300F constituting a storage architecture according to an embodiment of the disclosed technology. The following description of the back-end chip 300F may be applicable to Figure 1 Each of the backend chips 310 and 320 of the storage architecture 100A. The backend chip 300F according to this example can be configured to be connected to the MDS module. Figure 8 The back-end chip 300F may include a back-end link 321, an AXI stream control logic circuit 372, a core circuit 373, a network connection logic circuit (NIC) 374, and an MDS controller 375. The back-end link 321 may be connected to the front-end chip ( Figure 2 200) front-end link ( Figure 2 221 (1) to 221 (K)). The AXI stream control logic circuit 372 can be connected to the back-end link 321 and the network connection logic circuit 374 through an internal bus. The AXI stream control logic circuit 372 can provide a data transmission path between the back-end link 321 and the network connection logic circuit 374. The core circuit 373 can perform the function of processing instructions and data within the back-end chip 300F. The core circuit 373 may include a tightly coupled memory TCM circuit. The network connection logic circuit 374 can be connected to the AXI stream control logic circuit 372, the core circuit 373 and the MDS controller 375 through an internal bus. The network connection logic circuit 374 can control the signal and data transmission between the AXI stream control logic circuit 372, the core circuit 373 and the MDS controller 375. The MDS controller 375 can be connected to the MDS module through an external bus. The MDS controller 375 can control access operations to the MDS module.

[0067] Figure 9 The following is a block diagram of a back-end chip 300G constituting a storage architecture according to an embodiment of the disclosed technology. Figure 1Each of the back-end chips 310 and 320 of the storage architecture 100A. The back-end chip 300G according to this example may be configured to be connected to a flash memory device. Figure 9 The back-end chip 300G may include a back-end link 321, a network connection logic circuit (NIC) 382, ​​a flash interface layer (FIL) 383, a write protection logic circuit (WRP) 384, a read protection logic circuit (RDP) 385, and a flash controller 386. The back-end link 321 may be connected to the front-end chip ( Figure 2 200) front-end link ( Figure 2 221 (1) to 221 (K)). The back-end link 321 can be connected to the network connection logic circuit 382 through the internal bus. The network connection logic circuit 382 can control data transmission in the back-end chip 300G. The flash interface layer 383 can perform interface connection operations during read operations and write operations of the flash memory device. The flash interface layer 383 may include a tightly coupled memory (TCM) circuit for buffering the memory circuit. The write protection logic circuit (WRP) 384 can perform a function of preventing unnecessary write operations in the flash memory device. The read protection logic circuit (RDP) 385 can perform a function of protecting software code stored in the flash memory device. The flash controller 386 can control access operations to the flash memory device.

[0068] Figure 10 1 is a block diagram illustrating a storage architecture 100B of an interface device or system between a host device and a memory system having one or more memory devices for storing data according to another embodiment of the disclosed technology. Figure 10 , the storage architecture 100B may include a front-end chip 400 and a plurality of back-end chips, such as a first back-end chip 500 and a second back-end chip 600, wherein these chips are implemented as separate chips to allow any one of them to be replaced without replacing the other chips. Figure 10 The storage architecture 100B in FIG. 1 includes two backend chips 500 and 600, but this is merely an example, and a greater number of backend chips may be included in the storage architecture 100B. The front-end chip 400 may be disposed between a host device, such as a processor, and the first back-end chip 500 and the second back-end chip 600. The first back-end chip 500 may be disposed between the front-end chip 400 and the first memory device. The second back-end chip 600 may be disposed between the front-end chip 400 and the second memory device. Thus, the front-end chip 400 may communicate with the host device and the first back-end chip 500 and the second back-end chip 600. The first back-end chip 500 may communicate with the front-end chip 400 and the first memory device. The second back-end chip 600 may communicate with the front-end chip 400 and the second memory device.

[0069] The front-end chip 400, the first back-end chip 500, and the second back-end chip 600 can be configured in a chip set structure. That is, each of the front-end chip 400, the first back-end chip 500, and the second back-end chip 600 can have a structure physically separated from each other to act independently of each other, and can transmit data and signals through a bus between chips. In general, a host device operates at a faster speed than a memory device. Accordingly, the front-end chip 400 can be configured to support high-speed communication with the host device. On the other hand, the first back-end chip 500 and the second back-end chip 600 can be configured to support low-speed communication with the first memory device and the second memory device, respectively. Since the front-end chip 400 supports different processing speed and performance from the first back-end chip 500 and the second back-end chip 600, the front-end chip 400 can be manufactured through a relatively fine process compared to the first back-end chip 500 and the second back-end chip 600. The speed supported by the first back-end chip 500 and the second back-end chip 600 can be different from each other according to a difference in speed standard of the first memory device and the second memory device. In an example, the first memory device can be a volatile memory device such as a DRAM device or an accelerator memory device, and the second memory device can be a non-volatile memory device such as a flash memory device.

[0070] The front-end chip 400 can include a host interface 410 for communication with a host device. In addition, the front-end chip 400 can include a first front-end link (FE.LINK) 421 for communication with the first back-end chip 500, and can include a second front-end link (FE.LINK) 422 for communication with the second back-end chip 600. The first front-end link 421 and the second front-end link 422 can have the same structure. The first back-end chip 500 can include a first back-end link (BE1.LINK) 521 for communication with the front-end chip 400. The second back-end chip 600 can include a second back-end link (BE2.LINK) 621 for communication with the front-end chip 400. The first back-end link 521 and the second back-end link 621 can have the same structure. In an example, the host interface 210 of the front-end chip 400 can be configured by employing a PCIe protocol and / or a CXL protocol. The first front-end link 421 of the front-end chip 400 can be coupled to the first back-end link 521 of the first back-end chip 500. The second front-end link 422 of the front-end chip 400 can be coupled to the second back-end link 621 of the second back-end chip 600.

[0071] When the storage architecture 100B according to this embodiment is adopted in a computing system, only the front-end chip 400 can be replaced, while the first back-end chip 500 and the second back-end chip 600 remain unchanged. Alternatively, only the second back-end chip 600 can be replaced, while the front-end chip 400 and the first back-end chip 500 remain unchanged. Alternatively, only the first back-end chip 500 can be replaced, while the front-end chip 400 and the second back-end chip 600 remain unchanged. In an example where the host device supports the PCIe protocol Gen 5 standard and the first memory device is a DDR5 standard DRAM device, the front-end chip 400 of the storage architecture 100B can support the PCIe Gen 5 protocol, while the first back-end chip 500 of the storage architecture 100B can support the DDR5 standard DRAM device. In this case, when the interface standard of the host device changes from, for example, PCIe Gen 5 to PCIe Gen 6, only the front-end chip 400 is replaced with a front-end chip that supports the PCIe Gen 6 standard. Similarly, when the standard of the DRAM device changes from DDR5 to DDR6, only the first back-end chip 500 is replaced with a first back-end chip that supports the DDR6 standard.

[0072] Figure 11 It shows Figure 10 A block diagram of an example of the configuration of the front-end chip 400 of the storage architecture 100B. It is assumed that the front-end chip 400 according to this example communicates with the host device in the PCIe fifth generation (consisting of 8 lanes (x8)) standard. However, this is only an example, and the front-end chip 400 can communicate with the host device in the CXL standard. Figure 11 In, with Figure 2 The same reference numerals denote the same components, and repeated descriptions will be omitted below. Figure 11 The front-end chip 400 may include: a host interface 410, a first front-end link (FE.LINK) 421, a core logic circuit 230, a stream switching logic circuit 240, a PCI logic circuit 250, an NVMe logic circuit 260, a link structure 270, and at least one or more (e.g., "K") second front-end links (FE.LINK) 422 (1) to 422 (K) ("K" is a natural number). The host interface 410 may have Figure 2 The front-end chip 400 of this example is configured with all front-end links ( Figure 2 221 (1) to 221 (K)) are connected to the front-end chip of the link structure 270 ( Figure 2 200 ) may differ in that the first front-end link 421 is coupled to the streaming switching logic 240 via the internal bus, and only the second front-end links 422 ( 1 ) to 422 (K) are coupled to the link structure 270 .

[0073] The first front-end link 421 can be coupled to the first memory device through an external bus, as described with reference to Figure 10 The first front-end link 421 can be coupled to the flow switch logic circuit 240 through an internal bus in the front-end chip 400. The first front-end link 421 can transmit signals and / or data transmitted through the flow switch logic circuit 240 to the first memory device. In addition, the first front-end link 421 can transmit signals and / or data transmitted from the first memory device to the flow switch logic circuit 240. The second front-end links 422(1) through 422(K) can be coupled to the second memory devices through external buses, respectively, as described with reference to Figure 10 The second front-end links 422(1) through 422(K) can be coupled to the link fabric 270 through an internal bus in the front-end chip 400. The second front-end links 422(1) through 422(K) can transmit signals and / or data transmitted from the flow switch logic circuit 240 and the NVMe logic circuit 260 to the second memory devices through the link fabric 270. In addition, the second front-end links 422(1) through 422(K) can transmit signals and / or data transmitted from the second memory devices to the flow switch logic circuit 240 and the NVMe logic circuit 260 through the link fabric 270.

[0074] Figure 12 is a block diagram illustrating a storage architecture 100C according to still another embodiment of the disclosed technology. Referring to Figure 12 , the storage architecture 100C according to the present embodiment can include a front-end chip 200 and a plurality of back-end packages, for example, a first back-end package 700(1) and a second back-end package 700(2). Although the storage architecture 100C of the present embodiment includes two back-end packages 700(1) and 700(2), this is merely an example, and the storage architecture 100C can include more than two back-end packages. The front-end chip 200 can have the same configuration as the front-end chip 200 constituting the storage architecture 100A described with reference to Figure 1 Thus, the front-end chip 200 can utilize the front-end chip 200 described with reference to Figure 2The elements described are configured. The first back-end package 700 (1) and the second back-end package 700 (2) can be connected to the front-end links 221 (1) and 221 (2) of the front-end chip 200, respectively. The first back-end package 700 (1) can have a packaging structure including a first back-end chip 710 (1) and a first memory chip 720 (1). The first back-end package 700 (1) can include a first back-end link 711 (1) connected to the first front-end link 221 (1) of the front-end chip 200. The second back-end package 700 (2) can have a packaging structure including a second back-end chip 710 (2) and a second memory chip 720 (2). The second back-end package 700 (2) can include a second back-end link 711 (2) connected to the second front-end link 221 (2) of the front-end chip 200. The first back-end chip 710 (1) and the second back-end chip 710 (2) can have the same structure as described in reference Figure 1 The back-end chips 310 and 320 are configured identically. Figures 3-9 The various examples of backend chips described may be applied to the first backend chip 710 ( 1 ) and the second backend chip 710 ( 2 ).

[0075] Figure 13 It shows Figure 12 1 is a cross-sectional view of an example of the configuration of the first back-end package 710 (1) of the storage architecture 100C. The configuration of the first back-end package 700 (1) in this example can also be applied to the second back-end package 700 (2). Figure 13 , the first back-end package 700 (1) may include: a packaging substrate 701; a first back-end chip 710 (1) disposed on a first surface, such as an upper surface of the packaging substrate 701; a plurality of memory chips 703 disposed above the upper surface of the packaging substrate 701; and a molding material 705 surrounding the first back-end chip 710 (1) and the plurality of memory chips 703. A plurality of connection structures 702 may be disposed on a second surface, such as a lower surface of the packaging substrate 701. In an example, the plurality of connection structures 702 may be solder balls. The connection structures 702 of the first back-end package 700 (1) may be electrically connected to the front-end chip ( Figure 12 The first back-end chip 710 (1) may be provided in a first region, for example, in a central region of the package substrate 701. The first back-end chip 710 (1) may include a first back-end link 711 (1). The first back-end link 711 (1) may be electrically coupled to the first front-end chip ( Figure 12 The first front-end link 221 (1) of 200). The plurality of memory chips 703 can be arranged in the second area, for example, the side area of ​​the package substrate 701. The plurality of memory chips 703 can be stacked in a stepped shape. Figure 13As shown, eight memory chips 703 can be stacked in the left side region of the package substrate 701, and the eight memory chips 703 can be stacked with the intervening middle substrate 704 therebetween. Similarly, eight memory chips 703 can be stacked in the right side region of the package substrate 701, and the eight memory chips 703 can be stacked with the intervening middle substrate 704 therebetween. Although not shown in Figure 13 , the first back-end chip 710(1) can be electrically connected to the package substrate 701 by a wire or a bump. In addition, the plurality of memory chips 703 can be electrically connected to the package substrate 701 by a wire.

[0076] Figure 14 is a block diagram illustrating a storage architecture 100D according to yet another embodiment of the disclosed technology. Figure 15 is a cross-sectional view illustrating a configuration of a first back-end package 740 of the storage architecture 100D of Figure 14 . In addition, Figure 16 is a cross-sectional view illustrating an example of a first sub-back-end package 750(1) of the storage architecture 100D of Figure 14 . In Figure 15 and Figure 16 , the same reference numerals as in Figure 13 denote the same components, and repetitive descriptions will be omitted below. First, referring to Figure 14 , the storage architecture 100D according to the present embodiment can include a front-end chip 200, a back-end package 740, and a plurality of, for example, first to “L”th sub-back-end packages 750(1) to 750(L) (“L” is a natural number). The front-end chip 200 can have the same configuration as the front-end chip 200 constituting the storage architecture 100A described with reference to Figure 1 . Thus, the front-end chip 200 can be configured with the elements described with reference to Figure 2 . The back-end package 740 can have the same configuration as the first back-end package 700(1) described with reference to Figure 12 and Figure 13 , except that the back-end package 740 further includes a sub-back-end link 742. The back-end package 740 can be coupled to the first front-end link 221(1) of the front-end chip 200 through the back-end link 741. The back-end package 740 can be coupled to the first sub-back-end package 750(1) through the sub-back-end link 742. As shown in Figure 15 , the back-end package 740 can include a back-end chip 743 disposed in a first region, for example, a center region of the package substrate 701. Although not shown in Figure 14 and Figure 15Although not shown in the figure, the back-end chip 743 can be electrically connected to the internal wires of the package substrate 701 through bumps, and can also be electrically connected to the connection structure 702 through the internal wires of the package substrate 701. In other words, the back-end link 741 of the back-end chip 743 can be electrically connected to the connection structure 702 through the bumps and the package substrate 701. Similarly, the sub-back-end link 742 of the back-end chip 743 can also be electrically connected to the connection structure 702 through the bumps and the package substrate 701.

[0077] The first to "L"th sub-backend packages 750 (1) to 750 (L) may be configured in the same manner as one another. The first sub-backend package 750 (1) may include a sub-backend chip 753 (1) and a memory chip 754 (1). Similarly, the "L"th sub-backend package 750 (L) may include a sub-backend chip 753 (L) and a memory chip 754 (L). Figure 16 As shown, the first sub-backend package 750 (1) may include a sub-backend chip 753 (1), which is arranged in a first area, for example, a central area of ​​the package substrate 701. The sub-backend chip 753 (1) may be different from the backend chip 743 constituting the backend package 740 in that the sub-backend chip 753 (1) does not include a backend link. Although not shown in the drawings, the sub-backend chip 753 (1) may be electrically connected to the internal wires of the package substrate 701 through the bumps, and may be electrically connected to the connection structure 702 through the internal wires. That is, the sub-backend link 752 (1) may be electrically connected to the connection structure 702 through the bumps and the package substrate 701. The sub-backend packages 750 (1) to 750 (L) may not be directly connected to the first frontend link 221 (1) of the frontend chip 200, but may be indirectly connected to the first frontend link 221 (1) of the frontend chip 200 through the backend package 740. The sub-backend link 752 (1) of the first sub-backend package 750 (1) can be connected to the sub-backend link 742 of the backend package 740. Although not shown in the figure, the sub-backend link 752 (1) of the first sub-backend package 750 (1) can also be connected to the sub-backend link of the second sub-backend package. In the same way, the sub-backend link 752 (L) of the "L"-th sub-backend package 750 (L) can be connected to the sub-backend link of the "L-1"-th sub-backend package. Therefore, the backend package 740 and the sub-backend packages 750 (1) to 750 (L) can be connected in a daisy chain scheme. The daisy chain scheme means that the backend package 740 and the sub-backend packages 750 (1) to 750 (L) are connected in series. In this embodiment, the daisy chain scheme includes first to fourth daisy chains, each daisy chain connecting the backend package 740 with two of the sub-backend packages 750 (1) to 750 (L).

[0078] Figure 17is a diagram illustrating an example of a configuration in which a back-end package 740 and three sub-back-end packages 750(1), 750(2), and 750(3) are coupled to a front-end chip in a daisy chain scheme according to an embodiment of the disclosed technology. In Figure 17 Figures 14-16 The same reference numbers are used throughout the drawings to refer to the same or like components. This example can correspond to the case where "L" is 3 in the example described with reference to Figure 14 Figure 17 A first daisy chain connection structure can be configured between the front-end chip 200 and the back-end package 740. Accordingly, the front-end link 221(1) of the front-end chip 200 can communicate with the back-end link of the back-end chip 743 constituting the back-end package 740. A second daisy chain connection structure can be configured between the back-end chip 740 and the first sub-back-end package 750(1). Accordingly, the sub-back-end link of the back-end chip 743 constituting the back-end package 740 can communicate with the sub-back-end link of the sub-back-end chip 753(1) constituting the first sub-back-end package 750(1). A third daisy chain connection structure can be configured between the first sub-back-end package 750(1) and the second sub-back-end package 750(2). Accordingly, the sub-back-end link of the back-end chip 753(1) constituting the first sub-back-end package 750(1) can communicate with the sub-back-end link of the sub-back-end chip 753(2) constituting the second sub-back-end package 750(2). A fourth daisy chain connection structure can be configured between the second sub-back-end package 750(2) and the third sub-back-end package 750(3). Accordingly, the sub-back-end link of the back-end chip 753(2) constituting the second sub-back-end package 750(2) can communicate with the sub-back-end link of the sub-back-end chip 753(3) constituting the third sub-back-end package 750(3). According to such a connection structure, the number of connections of the sub-back-end packages can be freely adjusted regardless of the front-end chip 200.

[0079] Figure 18 is a diagram illustrating an example of a storage module 810 employing a storage architecture according to an embodiment of the disclosed technology. Referring to Figure 1 ​​The storage module 810 can include a storage architecture 813, a plurality of memory chips (MEMs) 814, and a power management chip (PMIC) 815. The storage architecture 813 can be disposed on the substrate 811, for example, in a first region of the substrate 811. The substrate 811 can include a socket that can be coupled to a connector on, for example, a board. The socket pins 812 can be disposed in the socket so as to enable communication with a host device through the connector. The plurality of memory chips 814 can be disposed in a second region of the substrate 811. The plurality of memory chips 814 can be respectively disposed on an upper surface and a lower surface of the substrate 811. The power management chip 815 can be disposed in a third region of the substrate 811. The power management chip 815 can perform power supply and power management in the storage module 810. The first region can be a region of the substrate 811 closest to the socket pins 812. The third region can be a region of the substrate 811 farthest from the socket pins 812. The second region can be a region between the first region and the third region.

[0080] The storage architecture 813 can include one front-end chip FE.CHIP and four back-end chips BE.CHIP. The storage architecture 813 can be the same as the storage architecture 100A described with reference to Figure 1 Figure 2 The description of the front-end chip 200 described with reference to Figure 4 may be equally applicable to the front-end chip FE.CHIP constituting the storage architecture 813. In addition, the descriptions of the back-end chips 300B, 300C, and 300E described with reference to Figure 5 , Figure 7 and Figure 18 may be equally applicable to the back-end chips BE.CHIP constituting the storage architecture 813. Accordingly, the front-end chip FE.CHIP of the storage architecture 813 can perform interface connection and control operations with respect to a host device. The back-end chips BE.CHIP of the storage architecture 813 can perform interface connection and control operations with respect to the memory chips 814. That is, the front-end chip FE.CHIP can not affect the interface connection and control operations with respect to the memory chips 814. Similarly, the back-end chips BE.CHIP can not affect the interface connection and control operations with respect to the host device.

[0081] Each of the memory chips 814 can be in the form of a chip or a package. The memory chips 814 can be disposed to be assigned to a plurality of memory channels. As Figure 19 ​As shown, four memory chips 814 can be disposed in each of the four channels CH0 to CH3. Assuming that the memory chips 814 are disposed on the upper and lower surfaces of the substrate 811, respectively, and that each of the memory chips 814 has a capacity of 16 GB, 128 GB of capacity can be allocated to each of the channels CH0 to CH3, and 512 GB of capacity can be allocated to all of the channels CH0 to CH3. The memory devices 814 of the first channel CH0 can communicate with a first back-end chip BE.CHIP among the four back-end chips BE.CHIP. The memory devices 814 of the second channel CH1 can communicate with a second back-end chip BE.CHIP. The memory devices 814 of the third channel CH2 can communicate with a third back-end chip BE.CHIP. In addition, the memory devices 814 of the fourth channel CH3 can communicate with a fourth back-end chip BE.CHIP.

[0082] Figure 19 is a block diagram illustrating a storage architecture 100E according to yet another embodiment of the disclosed technology. Referring to Figure 10 , the storage architecture 100E can include the front-end chip 400, a back-end chip 820, a back-end package 840, and a plurality of, for example, two, sub-back-end packages 850(1) and 850(2). The front-end chip 400 can have the same configuration as the front-end chip 400 described with reference to Figure 10 . The back-end chip 820 can have the same configuration as the back-end chip 500 described with reference to Figure 10 . Accordingly, the back-end chip 820 can be coupled to the first front-end link 421 of the front-end chip 400 through a first back-end link 821. The back-end chip 820 can perform interface connection and control operations for a first memory device, for example, a DRAM device. The back-end package 840 can have the same configuration as the back-end package 800 described with reference to Figure 10 Figure 20 ​500). Therefore, the back-end package 840 can be connected to the second front-end link 422 of the front-end chip 400 through the second back-end link 841 of the second back-end chip 843. The second back-end chip 843 can perform interface connection and control operations on the memory chip 844 constituting the back-end package 840. The sub-back-end link 842 of the second back-end chip 843 constituting the back-end package 840 can be connected to the sub-back-end link 852 (1) of the sub-back-end chip 853 (1) constituting the first sub-back-end package 850 (1). The sub-back-end chip 853 (1) can perform interface connection and control operations on the memory chip 854 (1) constituting the first sub-back-end package 850 (1). The sub-back-end link 852 (1) of the first sub-back-end package 850 (1) can also be connected to the sub-back-end link 852 (2) of the sub-back-end chip 853 (2) constituting the second sub-back-end package 850 (2). The sub-backend chip 853 ( 2 ) may perform interface connection and control operations on the memory chip 854 ( 2 ) constituting the second sub-backend package 850 ( 2 ).

[0083] Figure 19 It shows the use of Figure 20 FIGURE 8 is a diagram illustrating an example of a storage module 870 of a storage architecture 100E. Figure 19 , according to the present example, the storage module 870 may include a substrate 871 having a socket provided with a notch pin 872. A front-end chip FE.CHIP may be provided in a first region of the substrate 871. A back-end chip BE.CHIP may be provided in a second region of the substrate 871. The first region of the substrate 871 may be a region closest to the notch pin 872, and the second region may be a region adjacent to the first region. In a third region of the substrate 871, a back-end package BE.PKG (1) and a plurality of, for example, first to fifteenth sub-back-end packages SBE.PKG (2) to SBE.PKG (16) may be provided. A DRAM device DRAM may be provided in a fourth region of the substrate 871. As shown in FIG. Figure 21A As described above, the front-end chip FE.CHIP can be connected to the back-end chip BE.CHIP and the back-end package BE.PKG (1). The front-end chip FE.CHIP can perform an interface connection operation to the host device through the recessed pin 872. The back-end chip BE.CHIP can perform an interface connection and control operation to the DRAM device DRAM. The back-end package BE.PKG (1) and the sub-back-end packages SBE.PKG (2) to SBE.PKG (16) can be connected to each other in a daisy chain scheme.

[0084] Figure 21B and Figure 21A is a block diagram illustrating a storage architecture 100F according to yet another embodiment of the disclosed technology. Figure 21BA plan view of a storage architecture 100F based on some embodiments of the disclosed technology is shown, Figure 21A A side view of the storage architecture 100F based on some embodiments of the disclosed technology is shown. Referring to Figure 21B and Figure 1 The storage architecture 100F according to the present embodiment can include a front-end chip 910, a plurality of back-end chips 920(1), 920(2), 920(3), 920(4), 920(5), and 920(6), and a plurality of accelerator memory devices 930. Although the storage architecture 100F in the present embodiment includes six back-end chips 920(1), 920(2), 920(3), 920(4), 920(5), and 920(6), this is merely an example, and other embodiments can also exist. For example, the storage architecture 100F can include N back-end chips, N being greater than or equal to 1.

[0085] The front-end chip 910 can communicate with a host device. The front-end chip 910 can include at least part of the configuration of the front-end chip 200 of the storage architecture 100A described with reference to Figure 10 The front-end chip 910 can include at least part of the configuration of the front-end chip 400 of the storage architecture 100B described with reference to Figure 1 The front-end chip 910 can have a different structure from the front-end chips 200 and 400.

[0086] The plurality of back-end chips 920 can communicate with the front-end chip 910. The plurality of back-end chips 920 can communicate with at least part of the plurality of accelerator memory devices 930. The plurality of back-end chips 920 can control at least part of the plurality of accelerator memory devices 930. The plurality of back-end chips 920 can include at least part of the configuration of the back-end chips 310 and 320 of the storage architecture 100A described with reference to Figure 21A The plurality of back-end chips 920 can have a different structure from the back-end chips 310 and 320.

[0087] Each of the plurality of accelerator memory devices 930 can include memory cells that store data. Each of the plurality of accelerator memory devices 930 can include logic circuits that perform operations on the data. In some embodiments, each accelerator memory device includes logic circuits and memory cells grouped in banks. The memory cells and logic circuits included in at least one of the accelerator memory devices 930 can be located in the same bank. Alternatively, the memory cells and logic circuits included in at least one of the accelerator memory devices 930 can not be located in the same bank. In some embodiments, the logic circuits included in each of the accelerator memory devices 930 can be located outside of the banks in which the memory cells are located. Each of the accelerator memory devices 930 can utilize various structural configurations for performing operations on data. In this patent document, each of the accelerator memory devices 930 can also be referred to as an accelerator memory chip or an in-memory processing chip.

[0088] The front-end chip 910, the plurality of back-end chips 920, and the plurality of accelerator memory devices 930 can be configured in a chip set structure. Accordingly, the front-end chip 910, the plurality of back-end chips 920, and the plurality of accelerator memory devices 930 can have a structure physically separated from each other, thereby functioning independently from each other, and can transmit data and signals through buses between chips. The front-end chip 910 can communicate with a host device at a high speed. The back-end chips 920 can communicate with the accelerator memory devices 930 at a low speed. Here, "high speed" and "low speed" indicate relative speeds, i.e., the speed at which the front-end chip 910 communicates with the host device can be higher than the speed at which the back-end chips 920 communicate with the accelerator memory devices 930.

[0089] The front-end chip 910, the plurality of back-end chips 920, and the plurality of accelerator memory devices 930 can be disposed on the package substrate 900. The plurality of connection structures 901 can be located on a lower surface of the package substrate 900. The plurality of connection structures 901 can include various configurations, such as solder balls, although other embodiments are possible.

[0090] The plurality of front-end chip connection structures 911 can be disposed on a lower surface of the front-end chip 910. The plurality of back-end chip connection structures 921 can be disposed on a lower surface of each of the plurality of back-end chips 920. The plurality of accelerator memory device connection structures 931 can be disposed on a lower surface of the plurality of accelerator memory devices 930. The front-end chip connection structures 911, the back-end chip connection structures 921, and the accelerator memory device connection structures 931 can be bumps.

[0091] The front-end chip 910 can be electrically connected to the package substrate 900 through the front-end chip connection structure 911. Each of the back-end chips 920 can be electrically connected to the package substrate 900 through the back-end chip connection structure 921. Each of the accelerator memory devices 930 can be electrically connected to the package substrate 900 through the accelerator memory device connection structure 931. In some cases, an intermediate substrate (e.g., an interposer) can be disposed on the package substrate 900. The intermediate substrate can be located under the front-end chip 910, the back-end chips 920, and the accelerator memory devices 930. Through the intermediate substrate, the package substrate 900 and the front-end chip 910, the back-end chips 920, and the accelerator memory devices 930 can be electrically connected.

[0092] The front-end chip 910 can be electrically connected to at least one back-end chip 920 through the first connection wire(s) 902 of the package substrate 900. The back-end chip 920 can be electrically connected to the accelerator memory device 930 through the third connection wire(s) 904 of the package substrate 900. The plurality of back-end chips 920 can be electrically connected to each other through the second connection wire(s) 903 of the package substrate 900.

[0093] The front-end chip 910 can be electrically connected to a first back-end chip 920(1) among the plurality of back-end chips 920 through the first connection wire(s) 902. The front-end chip 910 can be electrically connected to one of the plurality of back-end chips 920. The front-end chip 910 can not be directly connected to the remaining plurality of back-end chips 920.

[0094] The first back-end chip 920(1) among the plurality of back-end chips 920 can be electrically connected to a second back-end chip 920(2) through the first second connection wire(s) 903(1). The second back-end chip 920(2) can be electrically connected to a third back-end chip 920(3) through the second second connection wire 903(2).

[0095] The first back-end chip 920(1) can be electrically connected to a fourth back-end chip 920(4) through a third second connection wire 903(3). The fourth back-end chip 920(4) can be electrically connected to a fifth back-end chip 920(5) through a fourth second connection wire 903(4). The fifth back-end chip 920(5) can be electrically connected to a sixth back-end chip 920(6) through a fifth second connection wire 903(5).

[0096] The plurality of back-end chips 920 can be linked in a daisy chain scheme. For example, referring to Figure 21A , the back-end chips 920(1), 920(2), 920(3), 920(4), 920(5), 920(6) are connected in series to each other. As Figure 21B and Figure 22In the illustrated embodiment, the plurality of backend chips 920 can be coupled in a structure in which a first backend chip 920(1) communicates with the front-end chip 910, and the remaining backend chips 920(2), 920(3), 920(4), 920(5), and 920(6) communicate through both sides of the first backend chip 920(1). In some embodiments, the plurality of backend chips 920 can be coupled in a linear structure in which the first to sixth backend chips 920(1) to 920(6) sequentially communicate with each other.

[0097] Each of the plurality of backend chips 920 can communicate with at least a portion of the plurality of accelerator memory devices 930. For example, each of the plurality of backend chips 920 can communicate with and control the operation of four accelerator memory devices 930.

[0098] The plurality of backend chips 920 can be disposed on the package substrate 900 to surround the front-end chip 910. For example, the plurality of backend chips 920 can be disposed on different sides of the front-end chip 910. The plurality of accelerator memory devices 930 can be disposed on the package substrate 900 to surround the plurality of backend chips 920. The plurality of backend chips 920 can be located between the front-end chip 910 and the plurality of accelerator memory devices 930. Alternatively, the plurality of backend chips 920 can surround the front-end chip 910, and the plurality of accelerator memory devices 930 can be located in a partial area outside the plurality of backend chips 920.

[0099] Figure 21A is a block diagram illustrating an example of a configuration of a front-end chip of a memory architecture of Figure 21B and Figure 22 According to the front-end chip 910 of the present embodiment, the PCIe fifth generation standard can be used for communication with the host device. However, this communication protocol is merely an example, and the front-end chip 910 can communicate with the host device using a different communication protocol such as the Compute Express Link (CXL) standard.

[0100] Referring to Figure 2 , the front-end chip 910 can include a host interface 912. The front-end chip 910 can include one or more front-end links 913, 914(1), and 914(2). The host interface 912 can include layers and logic circuits required according to a standard for communication of the host interface 912 with the host device. The host interface 912 can include at least a part of the configuration of the host interface 210 included in the front-end chip 200 described with reference to Figure 11 The host interface 912 can include at least a part of the configuration of the host interface 410 included in the front-end chip 400 described with reference to Figure 21A Alternatively, the host interface 912 can have a different structure from the above-described host interfaces 210 and 410.

[0101] The front-end chip 910 may include at least one first front-end link 913. The front-end chip 910 may include one or more second front-end links 914 (1) and 914 (2). The first front-end link 913 may be in an enabled state. The first front-end link 913 may receive a signal through the host interface 912. The first front-end link 913 may communicate with the back-end chip 920. The first front-end link 913 may be directly connected to Figure 21B and Figure 23 The first backend chip 920 (1) among the plurality of backend chips 920 shown in FIG. 1 and communicating with the first backend chip 920 (1). The second frontend links 914 (1) and 914 (2) may be in a disabled state. In this way, at least a portion of the frontend links included in the frontend chip 910 may be in a disabled state.

[0102] In some embodiments, the front-end chip 910 may include only the front-end links in an enabled state. The front-end chip 910 may include only the first front-end link 913. The front-end chip 910 may not include the second front-end links 914(1) and 914(2).

[0103] In some cases, at least one of the second front-end links 914 (1) and 914 (2) may be in an enabled state. The second front-end links 914 (1) and 914 (2) may be directly connected to and communicate with a memory chip. The type of memory chip communicating with the second front-end links 914 (1) and 914 (2) may be different from the type of accelerator memory device 930 communicating with the back-end chip 920, but other embodiments are also possible. In some cases, each of the host interface 912, the first front-end link 913, and the second front-end links 914 (1) and 914 (2) included in the front-end chip 910 may be configured in a chipset structure.

[0104] Figure 21A It shows Figure 21B and Figure 23 A block diagram of an example of a configuration of a back-end chip of a storage architecture. Figure 21A The description of the backend chip 920 shown in FIG can be applied to Figure 21B and Figure 23 Each of the backend chips 920 of the storage architecture 100F. The backend chip 920 can communicate with the frontend chip 910. The backend chip 920 can communicate with another backend chip 920. The backend chip 920 can communicate with the accelerator memory device 930 and control the accelerator memory device 930.

[0105] The backend chip 920 may include a backend link 1001. The backend chip 920 may include a plurality of sub-backend links 1002(1) and 1002(2). Figure 22The number of the plurality of sub-backend links 1002(1) and 1002(2) shown in the middle is an example, but is not limited thereto. The backend chip 920 can include at least one of a first AXI streaming control logic circuit 1003A, a power management logic circuit 1004, an embedded application logic circuit 1005, a system management service logic circuit 1006, a tightly coupled memory (TCM) circuit 1007, a memory management logic circuit 1008, a second AXI streaming control logic circuit 1003B, a crossbar 1009, a memory controller 1010, a memory physical layer 1011, or an operating buffer memory circuit (BUFF) 1012. In some cases, each component included in the backend chip 920 can be configured in a chipset structure.

[0106] The backend link 1001 can be coupled to a first front-end link 913 (see Figure 22 ) of the front-end chip 910 (see Figure 23 ) through an external bus. The backend link 1001 included in one of the plurality of backend chips 920 can be connected to the front-end chip 910. The backend links 1001 included in the remaining plurality of backend chips 920 can not be directly connected to the front-end chip 910.

[0107] The sub-backend links 1002(1) and 1002(2) can be coupled to the sub-backend links 1002 of another backend chip 920 through an external bus. At least one of the plurality of sub-backend links 1002(1) and 1002(2) included in the backend chip 920 can not be connected to another backend chip 920, according to the backend chip 920.

[0108] The first AXI streaming control logic circuit 1003A can be coupled to the backend link 1001 through an internal bus. The internal bus coupled to the first AXI streaming control logic circuit 1003A can include a plurality of lanes, for example, a read lane and a write lane. The first AXI streaming control logic circuit 1003A can provide a data transmission path between the backend link 1001 and the crossbar 1009. The power management logic circuit 1004 can manage power in the backend chip 920. The embedded application logic circuit 1005 can perform operations according to a programmed embedded application. The system management service logic circuit 1006 can perform system management service operations in the backend chip 920. The system management service logic circuit 1006 can be coupled to the crossbar 1009 through an internal bus.

[0109] The tightly coupled memory circuit 1007 can be used as a buffer memory circuit in the back-end chip 920. The memory management logic circuit 1008 can perform a control operation on the tightly coupled memory circuit 1007. The second AXI streaming control logic circuit 1003B can be coupled to the crossbar 1009 through an internal bus. The second AXI streaming control logic circuit 1003B can provide a data transmission path between the memory management logic circuit 1008 and the crossbar 1009. The crossbar 1009 can be coupled to the first AXI streaming control logic circuit 1003A, the second AXI streaming control logic circuit 1003B, the memory controller 1010, the memory physical layer 1011, and the system management service logic circuit 1006 through an internal bus. The crossbar 1009 can be configured to designate various paths of signals and data received through the internal bus. Although Figure 24 not shown in the middle, the memory controller 1010 and the memory physical layer 1011 can be coupled to the crossbar 1009 through a third AXI streaming control logic circuit. The memory controller 1010 and the memory physical layer 1011 can be coupled to the accelerator memory device 930 through an external bus.

[0110] The crossbar 1009 can be coupled to the operation buffer memory circuit 1012 through an internal bus. The operation buffer memory circuit 1012 can store data related to data operations of the plurality of accelerator memory devices 930. For example, the operation buffer memory circuit 1012 can store data required for operations of the accelerator memory device 930. Data to be transmitted to the accelerator memory device 930 can wait in the operation buffer memory circuit 1012. The operation result of the accelerator memory device 930 can be stored in the operation buffer memory circuit 1012 and kept waiting before being transmitted to the host device. The operation result of the accelerator memory device 930 can be collected in the operation buffer memory circuit 1012 and then provided to the host device. The operation buffer memory circuit 1012 can be an SRAM circuit, but is not limited thereto. In this patent document, in some embodiments, the tightly coupled memory circuit 1007 can be referred to as a first buffer memory circuit, and the operation buffer memory circuit 1012 can be referred to as a second buffer memory circuit. In this patent document, in some embodiments, the memory management logic circuit 1008 can be referred to as a first controller, and the memory controller 1010 can be referred to as a second controller.

[0111] Figure 24 is a block diagram illustrating a memory architecture 100G according to still another embodiment of the disclosed technology. Referring to Figure 21AAccording to the present embodiment, the storage architecture 100G may include a front-end chip 910, a plurality of back-end chips 920, and a plurality of accelerator memory devices 930. The front-end chip 910, the plurality of back-end chips 920, and the plurality of accelerator memory devices 930 included in the storage architecture 100G may be connected to the front-end chip 910. Figure 21B and Figure 24 The front-end chip 910, multiple back-end chips 920 and multiple accelerator memory devices 930 of the storage architecture 100F are the same.

[0112] The storage architecture 100G according to this embodiment may include at least one interconnect chip 940. The front-end chip 910, multiple back-end chips 920, multiple accelerator memory devices 930, and the interconnect chip 940 may be configured in a chipset structure. Therefore, the front-end chip 910, multiple back-end chips 920, multiple accelerator memory devices 930, and the interconnect chip 940 may have a physically separate structure, thereby functioning independently of each other, and data and signals may be transmitted via buses between the chips.

[0113] An interconnection chip 940 may be provided on the package substrate 900. The interconnection chip 940 may be provided on the package substrate 900 provided with the front-end chip 910, the plurality of back-end chips 920, and the plurality of accelerator memory devices 930. When the front-end chip 910, the plurality of back-end chips 920, and the plurality of accelerator memory devices 930 are provided on an intermediate substrate on the package substrate 900, the interconnection chip 940 may be provided on the intermediate substrate.

[0114] The interconnection chip 940 may be electrically connected to one of the plurality of backend chips 920. The interconnection chip 940 may communicate with one of the plurality of backend chips 920. The interconnection chip 940 may be connected to a backend chip 920 corresponding to a last node among the plurality of backend chips 920 connected in a daisy chain scheme. Figure 25 In the embodiment shown, the interconnect chip 940 may be coupled to a sixth backend chip 920 ( 6 ) among the plurality of backend chips 920 . In some cases, the interconnect chip 940 may be coupled to a third backend chip 920 ( 3 ) that is another last node among the plurality of backend chips 920 .

[0115] The interconnect chip 940 can include an interconnect chip connection structure 941 on a lower surface of the interconnect chip 940. The back-end chip 920(6) can include a back-end chip connection structure 921 on the lower surface of the interconnect chip 940. The interconnect chip 940 can be electrically connected to the back-end chip 920(6) through the second connection wire 903 of the package substrate 900. The interconnect chip 940 can be electrically connected to the connection structure 901 on the lower surface of the package substrate 900 through the third connection wire(s) 905. The accelerator memory device 930 on the package substrate 900 can not be connected to the connection structure 901 of the package substrate 900. The interconnect chip 940 can be connected to another interconnect chip 940' included in another semiconductor package through the connection structure 901 of the package substrate 900. The other interconnect chip 940' can be located on another package substrate 900' of a semiconductor package that is external to the memory architecture 100G according to the present embodiment. The semiconductor package located externally can be a semiconductor package of the same type as the memory architecture 100G according to the present embodiment, or a semiconductor package of a different type from the memory architecture 100G according to the present embodiment. Through the interconnect chip 940, the memory architecture 100G can communicate with chips within another semiconductor package. Communication between the memory architectures 100G or between the semiconductor packages can be achieved without using the communication bandwidth between the front-end chip 910 and the host device.

[0116] Figure 25 is a block diagram illustrating a memory architecture 100H according to still another embodiment of the disclosed technology. Referring to Figure 21A , the memory architecture 100H according to the present embodiment can include a front-end chip 910, a plurality of back-end chips 920, a plurality of accelerator memory devices 930, and at least one bridge chip 950. At least a portion of the configuration of the front-end chip 910 of the memory architecture 100H can be the same as at least a portion of the configuration of the front-end chip 910 of the memory architecture 100F of Figure 21B and Figure 24 and the memory architecture 100G of Figure 21A . At least a portion of the configuration of the back-end chip 920 of the memory architecture 100H can be the same as at least a portion of the configuration of the back-end chip 920 of the memory architecture 100F of Figure 21B and Figure 24 and the memory architecture 100G of Figure 21A . The accelerator memory device 930 of the memory architecture 100H can be the same as the accelerator memory device 930 of the memory architecture 100F of Figure 21B and Figure 24 and the memory architecture 100G of Figure 24 .

[0117] The front-end chip 910, the plurality of back-end chips 920, the plurality of accelerator memory devices 930, and the bridge chip 950 can be configured in a chipset structure. Accordingly, the front-end chip 910, the plurality of back-end chips 920, the plurality of accelerator memory devices 930, and the bridge chip 950 can have a structure physically separated from each other, thereby functioning independently from each other, and can transmit data and signals through a bus between chips.

[0118] The front-end chip 910, the plurality of back-end chips 920, the plurality of accelerator memory devices 930, and the bridge chip 950 can be disposed on a package substrate. The front-end chip 910 can be electrically connected to the bridge chip 950 through a bridge connection wire 906(1) of the package substrate. The plurality of back-end chips 920(1), 920(2), 920(3), 920(4), 920(5), and 920(6) can be electrically connected to the bridge chip 950 through bridge connection wires 906(2), 906(3), 906(4), 906(5), 906(6), and 906(7), respectively. The bridge chip 950 can include a first bridge link and a second bridge link. The first bridge link can be connected to the front-end link of the front-end chip 910. Communication between the front-end chip 910 and the bridge chip 950 can be performed through the first bridge link. The second bridge link can be connected to the back-end link of the back-end chip 920. Communication between the back-end chip 920 and the bridge chip 950 can be performed through the second bridge link. A communication structure between the front-end chip 910 and the plurality of back-end chips 920 can be provided through the bridge chip 950.

[0119] The memory architecture 100H can include Figure 26 The interconnection chip 940 of the memory architecture 100G. When the interconnection chip 940 is included in the memory architecture 100H, the interconnection chip 940 can be connected to the bridge chip 950. The interconnection chip 940 can not be directly connected to the front-end chip 910, the back-end chip 920, and the accelerator memory device 930. In some embodiments, the interconnection chip 940 can be connected to one of the plurality of back-end chips 920 and communicate with the one back-end chip 920. In this case, the interconnection chip 940 can not be directly connected to the bridge chip 950. Communication can be performed with another memory architecture 100H or a semiconductor package through the interconnection chip 940.

[0120] Figure 26 is a diagram illustrating an example of a memory module 880 employing the memory architecture 100F of FIG. 21. Referring to Figure 27According to the present example, the storage module 880 can include a substrate 881 having sockets provided with socket pins 882. The storage architecture 100F can be provided in a first region of the substrate 881. A power management chip 883 can be provided in a second region of the substrate 881. The first region of the substrate 881 can be a region closest to the socket pins 882. The second region of the substrate 881 can be a region adjacent to the first region. The first region of the substrate 881 can be between the socket pins 882 and the second region.

[0121] The intermediate substrate 960 can be provided on the package substrate 900 in the storage architecture 100F. The front-end chip 910, the plurality of back-end chips 920, and the plurality of accelerator memory devices 930 can be provided on the intermediate substrate 960. The plurality of back-end chips 920 can be provided at different side edges of the front-end chip 910. In some embodiments, the plurality of back-end chips 920 can surround the front-end chip 910. The plurality of accelerator memory devices 930 can be provided at different side edges of the plurality of back-end chips 920. In some embodiments, the plurality of accelerator memory devices 930 can surround the plurality of back-end chips 920. The back-end chips 920 can be between the front-end chip 910 and the accelerator memory devices 930. The plurality of back-end chips 920 can be coupled to each other in a daisy chain scheme. The plurality of accelerator memory devices 930 can communicate with the front-end chip 910 through at least one of the plurality of back-end chips 920. By providing the storage module 880 in the form of a storage architecture 100F provided with a plurality of packages including a front-end chip 910, a plurality of back-end chips 920, and a plurality of accelerator memory devices 930, a module having a computing function can be provided.

[0122] Figure 27 is a diagram illustrating an example of a storage module 890 employing a storage architecture 100I according to yet another embodiment of the disclosed technology. Referring to Figure 21A According to the present example, the storage module 880 can include a substrate 881 having sockets provided with socket pins 882. The storage architecture 100F can be provided in a first region of the substrate 881. A power management chip 883 can be provided in a second region of the substrate 881. The first region of the substrate 881 can be a region closest to the socket pins 882. The second region of the substrate 881 can be a region adjacent to the first region. The first region of the substrate 881 can be between the socket pins 882 and the second region.

[0123] The storage architecture 100I according to this embodiment can be referred to as a controller package. The storage architecture 100I may include a front-end chip 910 and multiple back-end chips 920. The front-end chip 910 and the multiple back-end chips 920 may be configured in a chipset structure. Therefore, the front-end chip 910 and the multiple back-end chips 920 may have a physically separate structure, functioning independently from each other, and data and signals may be transmitted via a bus between the chips.

[0124] At least a portion of the configuration of the front-end chip 910 of the storage architecture 100I may be Figure 21B and Figure 24 Storage architecture 100F and Figure 21A At least a portion of the configuration of the front-end chip 910 of the storage architecture 100G is the same as that of the back-end chip 920 of the storage architecture 100I. Figure 21B and Figure 24 Storage architecture 100F and Figure 25 At least part of the configuration of the back-end chip 920 of the storage architecture 100G is the same.

[0125] The front-end chip 910 can be connected to one of the plurality of back-end chips 920. The plurality of back-end chips 920 can be connected to each other using a daisy chain scheme. Figure 24 The bridge chip 950 of the storage architecture 100H is connected to the front-end chip 910. The storage architecture 100I may include Figure 28 The storage architecture 100G includes an interconnect chip 940 and can communicate with an external semiconductor package via the interconnect chip 940. Thus, the storage architecture 100I can have a structure in which a front-end chip 910 and multiple back-end chips 920 are provided on a package substrate, but without an accelerator memory device 930. Furthermore, the storage architecture 100I can be provided in the form of a controller package that controls the accelerator memory device 930 located outside the package substrate.

[0126] Figures 1-27 1 is a block diagram illustrating a configuration of a front-end link 1100 and a back-end link 2100 of a storage architecture according to an embodiment of the disclosed technology. The configuration of the front-end link 1100 and the back-end link 2100 may be applied to a storage architecture according to an embodiment of the disclosed technology. Figure 28 As with the various examples described so far, the front-end link 1100 and the back-end link 2100 can be used for communication between a front-end chip and a back-end chip.

[0127] Reference Figure 29The front-end link 1100 can include a link layer 1110, a physical layer 1120, and a clock measurement module (CMM). The link layer 1110 can include a flow controller 1111 and a packet decoder 1112. The flow controller 1111 of the link layer 1110 can perform a packet flow control when transmitting a packet to the back-end link 2100. The packet decoder 1112 of the link layer 1110 can perform an error detection function on a packet transmitted from the back-end link 2100. The link layer 1110 can generate and output a lane activation signal LN_A. The lane activation signal LN_A output from the link layer 1110 can be transmitted to the transmitter 1121 of the physical layer 1120 and the back-end link 2100. The link layer 1110 can receive a lane activation signal LN_A transmitted from the back-end link 2100.

[0128] The physical layer 1120 can include a transmitter (TX) 1121 and a receiver (RX) 1122. The transmitter 1121 can transmit a signal transmitted from the link layer 1110 to the back-end link 2100. The receiver 1122 can transmit a signal transmitted from the back-end link 2100 to the link layer 1110. The receiver 1122 can include a phase-locked loop (PLL) and a clock data recovery circuit (CDR). The receiver 1122 can receive a lane activation signal LN_A transmitted from the back-end link 2100. The clock measurement module 1130 can receive a clock signal from a reference clock generator (REF) 3100.

[0129] The back-end link 2100 can include a link layer 2110, a physical layer 2120, and a clock measurement module (CMM) 2130. The link layer 2110 can include a flow controller 2111 and a packet decoder 2112. The flow controller 2111 of the link layer 2110 can perform packet flow control when transmitting a packet to the front-end link 1100. The packet decoder 2112 of the link layer 2110 can perform an error detection function on a packet transmitted from the front-end link 1100. The link layer 2110 can generate and output a lane activation signal LN_A. The lane activation signal LN_A output from the link layer 2110 can be transmitted to the transmitter 2122 of the physical layer 2120 and the front-end link 1100. The link layer 2110 can receive a lane activation signal LN_A transmitted from the front-end link 1100. The physical layer 2120 can include a receiver (RX) 2121 and a transmitter (TX) 2122. The receiver 2121 can transmit a signal transmitted from the front-end link 1100 to the link layer 2110. The receiver 2121 can include a phase-locked loop (PLL) and a clock data recovery circuit (CDR). The receiver 2121 can receive a lane activation signal LN_A transmitted from the front-end link 1100. The transmitter 2122 can transmit a signal transmitted from the link layer 2110 to the front-end link 1100. The clock measurement module 2130 can receive a clock signal from a reference clock generator (REF) 3100.

[0130] Each of the front-end link 1100 and the back-end link 2100 can include a general-purpose input output (GPIO) pin. A lane activation signal LN_A can be sent from the front-end link 1100 to the back-end link 2100 and from the back-end link 2100 to the front-end link 1100 through the GPIO pin. The transmitter 1121 of the front-end link 1100 and the transmitter 2122 of the back-end link 2100 can each include a TXDP pin and a TXDN pin as differential data output pins. Although not shown in the figure, the TXDP pin can be used as a positive output and the TXDN pin can be used as a negative output. The receiver 1122 of the front-end link 1100 and the receiver 2121 of the back-end link 2100 can each include an RXDP pin and an RXDN pin as differential data input pins. Although not shown in the figure, the RXDP pin can be used as a positive input and the RXDN pin can be used as a negative input. Signals from the transmitter 1121 of the front-end link 1100 can be output as a differential data pair from the TXDP pin and the TXDN pin of the front-end link 1100 and can be transmitted to the RXDP pin and the RXDN pin of the back-end link 2100. Similarly, signals from the transmitter 2122 of the back-end link 2100 can be output as a differential data pair from the TXDP pin and the TXDN pin of the back-end link 2100 and can be transmitted to the RXDP pin and the RXDN pin of the front-end link 1100.

[0131] Figures 1-27 FIG. 12 is a block diagram illustrating a configuration of a front-end link 1200 and a back-end link 2200 showing a storage architecture according to another embodiment of the disclosed technology. The configuration of the front-end link 1200 and the back-end link 2200 according to the present example can also be applied to the various examples described with reference to FIGS. 1 through 11. Figure 29 As with the various examples heretofore, the front-end link 1200 and the back-end link 2200 can be used for communication between a front-end chip and a back-end chip.

[0132] Referring to FIG. 12, Figure 28The front-end link 1200 may include a link layer 1210, a physical layer 1220, and a phase-locked loop (PLL) 1230. The link layer 1210 may include a flow controller 1211 and a packet decoder 1212. The flow controller 1211 of the link layer 1210 may perform packet flow control when transmitting packets to the back-end link 2200. The packet decoder 1212 of the link layer 1210 may perform error detection on packets transmitted from the back-end link 2200. The link layer 1210 may generate and output a lane activation signal LN_A. The lane activation signal LN_A output from the link layer 1210 may be transmitted to the transmitter 1121 of the physical layer 1120, the phase-locked loop 1230, and the back-end link 2200. The link layer 1210 may receive the lane activation signal LN_A transmitted from the back-end link 2200.

[0133] The physical layer 1220 may include a transmitter (TX) 1221 and a receiver (RX) 1222. The transmitter 1221 may transmit a signal transmitted from the physical layer 1220 to the backend link 2200. The receiver 1222 may transmit a signal transmitted from the backend link 2200 to the link layer 1210. Figure 28 Front-end link ( Figure 22 Unlike 1100 (of the embodiment shown in FIG1 ), the receiver 1222 of the physical layer 1220 of the front-end link 1200 may include a delay-locked loop (DLL). Receiver 1222 may receive the lane activation signal LN_A transmitted from the back-end link 2200. The phase-locked loop 1230 may receive a clock signal from the reference clock generator (REF) 3200. Based on the lane activation signal LN_A transmitted from the link layer 1210 or the back-end link 2200, the phase-locked loop 1230 may lock onto the clock signal transmitted from the reference clock generator 3200 and then transmit a phase-locked clock signal CKP to the back-end link 2200. The phase-locked loop 1230 may receive the lane activation signal LN_A transmitted from the back-end link 2200.

[0134] The back-end link 2200 can include a link layer 2210 and a physical layer 2220. The link layer 2210 can include a flow controller 2211 and a packet decoder 2212. The flow controller 2211 of the link layer 2210 can control packet flow control when sending a packet to the front-end link 1200. The packet decoder 2212 of the link layer 2210 can perform an error detection function on a packet sent from the front-end link 1200. The link layer 2210 can generate and output a lane activation signal LN A. The lane activation signal LN A output from the link layer 2210 can be sent to the transmitter 2222 of the physical layer 2220 and the front-end link 1200. The link layer 2210 can receive the lane activation signal LN A sent from the front-end link 1200. The physical layer 2220 can include a receiver (RX) 2221 and a transmitter (TX) 2222. The receiver 2221 can send a signal sent from the front-end link 1200 to the link layer 2210. The receiver 2221 can include a delay-locked loop (DLL). The receiver 2221 can receive the lane activation signal LN A sent from the front-end link 1200. The transmitter 2222 can send a signal sent from the link layer 2210 to the front-end link 1200.

[0135] Each of the front-end link 1200 and the back-end link 2200 can include a GPIO pin. The lane activation signal LN A can be sent from the front-end link 1200 to the back-end link 2200 and from the back-end link 2200 to the front-end link 1200 through the GPIO pin. The transmitter 1221 of the front-end link 1200 and the transmitter 2222 of the back-end link 2200 can each include a TXDP pin and a TXDN pin as differential data output pins. Although not shown in FIG. 12, the TXDP pin can function as a positive output terminal and the TXDN pin can function as a negative output terminal. Figure 22 The receiver 1222 of the front-end link 1200 and the receiver 2221 of the back-end link 2200 can each include an RXDP pin and an RXDN pin as differential data input pins. Although not shown in FIG. 12, the RXDP pin can function as a positive input terminal and the RXDN pin can function as a negative input terminal. Figure 30 Signals from the transmitter 1221 of the front-end link 1200 can be output as a differential data pair from the TXDP pin and the TXDN pin of the front-end link 1200 and can be sent to the RXDP pin and the RXDN pin of the back-end link 2200. Signals from the transmitter 2222 of the front-end link 2200 can be output as a differential data pair from the TXDP pin and the TXDN pin of the front-end link 2200 and can be sent to the RXDP pin and the RXDN pin of the front-end link 1200.

[0136] Figures 1-27is a block diagram showing a configuration of a front-end link 1300 and a back-end link 2300 of a storage architecture according to another embodiment of the disclosed technology. The configuration of the front-end link 1300 and the back-end link 2300 according to the present example can also be applied to the front-end link 1000 and the back-end link 2000 with reference to Figure 30 The various examples described. As with the various examples heretofore, the front-end link 1300 and the back-end link 2300 can be used for communication between a front-end chip and a back-end chip.

[0137] With reference to Figure 23 , the front-end link 1300 can include a link layer 1310, a physical layer 1320, and a phase-locked loop (PLL) 1330. The link layer 1310 can include a flow controller 1311 and a packet decoder 1312. The flow controller 1311 of the link layer 1310 can perform packet flow control when transmitting a packet to the back-end link 2300. The packet decoder 1312 of the link layer 1310 can perform an error detection function on a packet transmitted from the back-end link 2300. The link layer 1310 can generate and output a lane activation signal LN_A. The lane activation signal LN_A output from the link layer 1310 can be transmitted to the transmitter 1321 of the physical layer 1320, the phase-locked loop 1330, and the back-end link 2300. The link layer 1310 can receive a lane activation signal LN_A transmitted from the back-end link 2300.

[0138] The physical layer 1320 can include a transmitter (TX) 1321 and a receiver (RX) 1322. The transmitter 1321 can transmit a signal transmitted from the link layer 1310 to the back-end link 2300. The receiver 1322 can transmit a signal transmitted from the back-end link 2300 to the link layer 1310. The receiver 1322 can receive a lane activation signal LN_A transmitted from the back-end link 2300. The phase-locked loop 1330 can receive a clock signal from a reference clock generator (REF) 3300. The phase-locked loop 1330 can lock the clock signal received from the reference clock generator 3300 based on the lane activation signal LN_A transmitted from the link layer 1310 or transmitted from the back-end link 2300, and then can transmit a phase-locked clock signal CKP to the back-end link 2300. The phase-locked loop 1330 can receive a lane activation signal LN_A transmitted from the back-end link 2300.

[0139] The back-end link 2300 can include a link layer 2310 and a physical layer 2320. The link layer 2310 can include a flow controller 2311 and a packet decoder 2312. The flow controller 2311 of the link layer 2310 can perform packet flow control when sending packets to the front-end link 1300. The packet decoder 2312 of the link layer 2310 can perform an error detection function on packets sent from the front-end link 1300. The link layer 2310 can generate and output a lane activation signal LN_A. The lane activation signal LN_A output from the link layer 2310 can be sent to the transmitter 2322 of the physical layer 2320 and the front-end link 1300. The link layer 2310 can receive the lane activation signal LN_A sent from the front-end link 1300. The physical layer 2320 can include a receiver (RX) 2321 and a transmitter (TX) 2322. The receiver 2321 can send signals sent from the front-end link 1300 to the link layer 2310. The receiver 2321 can receive the lane activation signal LN_A sent from the front-end link 1300. The transmitter 2322 can send signals sent from the link layer 2310 to the front-end link 1300.

[0140] Each of the front-end link 1300 and the back-end link 2300 can include a GPIO pin. The lane activation signal LN_A can be sent from the front-end link 1300 to the back-end link 2300 and from the back-end link 2300 to the front-end link 1300 through the GPIO pin. The transmitter 1321 of the front-end link 1300 and the transmitter 2322 of the back-end link 2300 can each include a TXDP pin and a TXDN pin as differential data output pins. Although not shown in Figure 23 the TXDP pin can function as a positive output terminal and the TXDN pin can function as a negative output terminal. The receiver 1322 of the front-end link 1300 and the receiver 2321 of the back-end link 2300 can each include an RXDP pin and an RXDN pin as differential data input pins. Although not shown in Figure 31 the RXDP pin can function as a positive input terminal and the RXDN pin can function as a negative input terminal. Signals from the transmitter 1321 of the front-end link 1300 can be output as a differential data pair from the TXDP pin and the TXDN pin of the front-end link 1300 and can be sent to the RXDP pin and the RXDN pin of the back-end link 2300. Similarly, signals from the transmitter 2322 of the back-end link 2300 can be output as a differential data pair from the TXDP pin and the TXDN pin of the back-end link 2300 and can be sent to the RXDP pin and the RXDN pin of the front-end link 1300.

[0141] Figures 28-30 is shown in Figure 31The packet transmission process in the front-end link and the back-end link can be performed using the same mechanism in the front-end link and the back-end link. Therefore, the following description will be based on the front-end link.

[0142] Reference Figure 24 , a data packet transmitted between the front-end link and the back-end link may be composed of at least one flow control bit (hereinafter referred to as a "flow control unit (Flit)"). In addition, a flow control unit may be composed of at least one physical bit (hereinafter referred to as a "physical unit (Phit)"). In the link layer of the front-end link, the upper layer data F.DATA and the flow control data F.CTRL of a flow control unit may be separated and processed. Figure 24 As shown, in the link layer, upper layer data F.DATA can be configured in a table format with rows consisting of "J" bits ("J" is a natural number) and columns consisting of "W" bits ("W" is a natural number). Flow control data (F.CTRL) can be configured in a table format with rows consisting of 1 bits and columns consisting of "J" bits. Figure 24 Actual data is omitted.

[0143] In an example, the flow control data F.CTRL with a value of "0000" can indicate an idle state. The flow control data F.CTRL with a value of "0001" can indicate that the upper layer data F.DATA corresponds to a first message. The flow control data F.CTRL with a value of "0011" can indicate that the upper layer data F.DATA corresponds to a second message. Similarly, the flow control data F.CTRL with a value of "0111" can indicate that the upper layer data F.DATA corresponds to a third message. In this way, the flow control data F.CTRL can indicate whether there is an idle state and which message the upper layer data F.DATA corresponds to. The size of the data sent to the link layer can be smaller than the size of the flow control unit, which can be determined by merging the flow control data F.CTRL and the upper layer data F.DATA generated by performing packet decoding in the link layer. When the size of the data to be sent from the link layer to the upper layer is smaller than the size of the flow control unit, that is, when the data corresponds to low density, the flow control unit data can be used together in the link layer and the upper layer. On the other hand, when the size of the data to be sent from the link layer to the upper layer is the same as the size of the flow control unit (CFG), that is, when the data corresponds to the maximum density, the link layer can send the CFG data to the upper layer. This method eliminates the need to include a separate header / tail for information other than the data in the packet.

[0144] The upper layer data F.DATA and the flow control data F.CTRL in the link layer can be processed in the form of a control packet part C and a data packet part D respectively at the physical layer and can be sent to the back-end link. Figure 32As shown, a flow control unit sent from the physical layer of the front-end link to the back-end link may include a control packet portion C and a data packet portion D. Each of the control packet portion C and the data packet portion D has a data length of "J" bits. The control packet portion C may have a data width of one bit, while the data packet portion D may have a data width of "W". Assuming that a physical unit consists of a data width of one bit, a physical unit may have a size of "W + 1" bits, including a 1-bit control packet portion C and a "W"-bit data packet portion D. Alternatively, a flow control unit may have a size of "J + (W x J)" bits, including a "J"-bit control packet portion C and a "W x J"-bit data packet portion D. In other words, data packets between the front-end link and the back-end link can be sent in units of "W + 1" bits, which is physically the size of the physical unit. This process can be repeated "J" times until all "J + (W x J)" bits, i.e., the size of the flow control unit, have been sent.

[0145] Figures 28-30 It shows Figure 32 This diagram illustrates an example of a communication process from a front-end link to a back-end link. The following description also applies to the communication process from a back-end link to a front-end link. Furthermore, it is assumed that communication between the front-end link and the back-end link is performed in a peer-to-peer manner. This example illustrates a case where a read command is sent from the front-end link to the back-end link, and read data is sent from the back-end link to the front-end link.

[0146] Reference Figure 25 , the front-end link and the back-end link can exchange their respective credit values ​​in advance. The link layer LINK of the front-end link can send the read command RCMD sent from the upper layer (i.e., the logic circuit in the front-end chip) in the form of a flow control unit TXFlit through the physical layer transmitter TX to the receiver RX of the back-end link. In this case, the link layer LINK of the front-end link can refer to the credit value C of the back-end link to refer to the reception availability of the back-end link. When sending the read command RCMD, the link layer LINK of the front-end link can subtract the number of flow control units sent (i.e., "C-1") from the credit C.

[0147] The receiver RX of the back-end link can receive the transmit flit TX Flit from the front-end link as a receive flit RX Flit. The receiver RX of the back-end link can transmit the credit C equal to the number of normally received flits to the front-end link. The receiver RX of the back-end link can transmit the receive flit RX Flit to the upper layer (i.e., a logic circuit in the back-end chip) through the link layer LINK in the form of a read command RCMD. The upper layer of the back-end link can transmit read data RDATA read from the memory device to the link layer LINK. The link layer LINK of the back-end link can transmit the read data RDATA to the receiver RX of the front-end link in the form of a transmit flit TX Flit through the transmitter TX of the physical layer. In this case, the link layer LINK of the back-end link can encode the read data RDATA with the credit C and transmit the encoded read data RDATA with the credit C to the front-end link. In addition, the link layer LINK of the back-end link can subtract the number of transmitted flits (i.e., "C-1") from the credit C when transmitting the read data RDATA to the front-end link.

[0148] The receiver RX of the front-end link can receive the transmit flit TX Flit from the back-end link as a receive flit RX Flit. The receiver RX of the front-end link that receives the receive flit RX Flit can transmit the receive flit RX Flit to the upper layer through the link layer LINK in the form of read data RDATA. In this case, the link layer of the front-end link can add the number of received flits to the credit C (i.e., "C+1"). Although Figure 33 Although not shown in FIG. 10, when the back-end link has no read data RDATA to be transmitted to the front-end link, a credit-return flit can be generated and immediately returned to the front-end link, or the return can be delayed until the read data RDATA is transmitted to the front-end link.

[0149] Figures 28-30 is a diagram illustrating another example of a communication procedure from the front-end link to the back-end link of Figure 33 The following description is equally applicable to a communication procedure from the back-end link to the front-end link. In addition, it is assumed that communication between the front-end link and the back-end link is performed in a peer-to-peer scheme. In this example, a case in which data is transmitted from the front-end link to the back-end link will be exemplified. The same method can be applied to a case of a transmit command rather than data.

[0150] Referring to Figure 26, the front-end link and the back-end link can exchange respective credit values in advance. The link layer LINK of the front-end link can transmit data DATA sent from an upper layer (i.e., a logic circuit in the front-end chip) to a receiver RX of the back-end link in the form of a transmit flit TX Flit through a transmitter TX of the physical layer. The link layer LINK of the front-end link can subtract the number of transmitted flits (i.e., "C-1") from the credit C when transmitting a read command RCMD. The receiver RX of the back-end link can receive the transmit flit TX Flit from the front-end link as a receive flit RX Flit, and can transmit the transmit flit TX Flit to the link layer LINK. When an error is included in the receive flit RX Flit, the link layer LINK of the back-end link can block data transmission to the upper layer, and can transmit a resume request NACK to the receiver RX of the front-end link through the transmitter TX of the back-end link. In addition, the back-end link can stop all receive operations until the front-end link transmits a resume message RESUME.

[0151] The link layer LINK of the front-end link that has received the received resume RX NACK from the receiver RX of the front-end link can transmit a transmit resume message TX RESUME to the receiver RX of the back-end link in response to the received resume request RX NACK. In this case, the link layer LINK of the front-end link can not perform a credit C add / subtract operation. The point in time at which the link layer LINK of the front-end link transmits the transmit resume message TX RESUME to the back-end link can be set as a non-returned credit. For example, if transmit flits corresponding to 4 credits are transmitted from the front-end link to the back-end link and a third credit is normally returned, the link layer LINK of the front-end link can retransmit transmit flits corresponding to a fourth credit to the back-end link.

[0152] The receiver RX of the back-end link that has received the transmit resume message TX RESUME as a receive resume message RX RESUME from the transmitter TX of the front-end link can transmit the receive resume message RX RESUME to the link layer LINK of the back-end link. After transmitting the resume request TX_RESUME_OK to the receiver RX of the front-end link through the transmitter TX, the link layer LINK of the back-end link can resume the receive operation. The front-end link can transmit data DATA back to the back-end link in response to the resume request RESUME_OK. Although ​ When the transmit resume message TX RESUME is not received by the back-end link or the resume request TX_RESUME_OK is not received by the front-end link, the front-end link can time out, although not shown in FIG. 10.

[0153] Although a number of embodiments have been described above, the disclosure and the examples given are not the only ones that can be resorted to, the disclosed and other embodiments being subject to variations and modifications.

Claims

1. A memory architecture comprising: a plurality of accelerator memory devices located on a package substrate; a front-end chip located on the package substrate and performing communication with a host device; and a plurality of back-end chips performing communication with the front-end chip on the package substrate and controlling at least a portion of the plurality of accelerator memory devices, the plurality of back-end chips being serially coupled to one another based on a daisy chain scheme. each of the plurality of back-end chips comprises:

2. The storage architecture of claim 1, wherein, a back-end link in communication with the front-end chip; and at least one sub-back-end link in communication with at least one other back-end chip among the plurality of back-end chips. the back-end link included in one of the plurality of back-end chips is in communication with the front-end chip, and the back-end links included in the remaining of the plurality of back-end chips are not connected to the front-end chip.

3. The storage architecture of claim 2, wherein, each of the plurality of back-end chips comprises:

4. The storage architecture of claim 1, wherein, an operation buffer memory circuit storing data associated with data operations through the plurality of accelerator memory devices. the front-end chip comprises:

5. The storage architecture of claim 1, wherein, a host interface in communication with the host device; and a plurality of front-end links in communication with at least a portion of the plurality of back-end chips, and at least one of the plurality of front-end links is in a disabled state. the plurality of back-end chips are disposed around the front-end chip and between the front-end chip and the plurality of accelerator memory devices.

6. The storage architecture of claim 1, wherein, the plurality of back-end chips are disposed around the front-end chip and the plurality of accelerator memory devices are disposed around the plurality of back-end chips.

7. The storage architecture of claim 1, wherein, 8. The memory architecture of claim 1, further comprising: an interconnect chip located on the package substrate and in communication with a back-end chip corresponding to a last node of a daisy chain formed by the plurality of back-end chips. the interconnect chip is electrically connected to at least one of a plurality of solder balls located on a lower surface of the package substrate.

9. The storage architecture of claim 8, wherein, the plurality of accelerator memory devices are electrically disconnected from the plurality of solder balls.

10. The storage architecture of claim 9, wherein, the interconnect chip is in communication with another interconnect chip included in a semiconductor package located outside of the memory architecture.

11. The storage architecture of claim 8, wherein, the interconnect chip is not directly connected to the plurality of accelerator memory devices.

12. The storage architecture of claim 8, wherein, 13. A memory architecture comprising: a plurality of accelerator memory devices located on a package substrate; a front-end chip located on the package substrate and in communication with a host device; a bridge chip disposed on the package substrate and in communication with the front-end chip; and a plurality of back-end chips located on the package substrate and in communication with the front-end chip through the bridge chip and controlling at least a portion of the plurality of accelerator memory devices. the bridge chip comprises: a first bridge link in communication with the front-end chip; and 14. The storage architecture of claim 13, wherein, a plurality of second bridge links in communication with the plurality of back-end chips.

15. The memory architecture of claim 13, further comprising: an interconnect chip in communication with the bridge chip and not directly connected to the plurality of back-end chips.

16. A memory architecture comprising: a front-end chip located on a package substrate and in communication with a host device; ​ ​ a plurality of back-end chips disposed on the package substrate and in communication with the front-end chip, and the plurality of back-end chips are serially coupled to one another based on a daisy chain scheme; and a plurality of accelerator memory devices external to the package substrate and in communication with at least one of the plurality of back-end chips.

17. The storage architecture of claim 16, wherein, each of the plurality of back-end chips includes: a first controller to control operation of the back-end chip; a second controller to control at least a portion of the plurality of accelerator memory devices; a first buffer memory circuit to store data in accordance with operation of the first controller; and a second buffer memory circuit to store data associated with data operations of the plurality of accelerator memory devices in response to operation of the second controller.

18. The storage architecture of claim 16, wherein, the front-end chip includes: a first front-end link to communicate with at least one of the plurality of back-end chips; and a second front-end link in a disabled state.

19. The storage architecture of claim 18, wherein, one of the plurality of back-end chips includes a back-end link connected to the front-end chip, and each of the remaining of the plurality of back-end chips includes a back-end link disconnected from the front-end chip.

20. The memory architecture of claim 16, further comprising: an interconnect chip on the package substrate and in communication with a back-end chip corresponding to a last node of a daisy chain formed by the plurality of back-end chips.

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