Three-dimensional stacked NOR type ferroelectric field effect transistor and preparation method thereof

Abstract

The invention provides a three-dimensional stacked NOR type ferroelectric field effect transistor and a preparation method thereof, and belongs to the technical field of micro-nano electronics. In the 3D FeNOR device structure, gate metal electrodes and isolation layers are alternately stacked to form a word line lamination layer of a lamination structure, and the word line lamination layer is located above a silicon dioxide layer; the vertical groove is located in the lamination structure of the word line lamination layer and vertically penetrates through the whole word line lamination layer into the bottom silicon dioxide layer; the ferroelectric layer is attached to the inner wall of the vertical groove and is in contact with the word line lamination layer; the oxide channel layer is attached to the ferroelectric layer; metal materials of the source and the drain are attached to the oxide channel layer, a channel region is arranged between the source and the drain, and a gap exists between the source and the drain at the bottom of the vertical groove; the word line contact hole is located in the word line lamination layer, is parallel to the vertical groove and is used for exposing the gate metal electrode of each layer; and the vertical grooves are circular or rectangular in overlook view. According to the method, the durability and the erasing speed are optimized at the same time, and the method has great potential in the field of in-memory computing facing artificial intelligence acceleration.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of micro-nano electronics, and particularly relates to a novel three-dimensional stacked NOR type ferroelectric field effect transistor (3D FeNOR) and a preparation method thereof. BACKGROUND

[0002] In-memory learning, as a core driving technology of advanced artificial intelligence systems, significantly improves the energy efficiency ratio of data processing by deeply integrating computing and storage functions in physical space. However, this technology puts forward strict requirements for multi-dimensional collaborative optimization of memory device performance: on the one hand, it needs to realize ultra-high storage density to meet the parameter storage needs of large-scale neural network models, and on the other hand, it needs to have ultra-fast operation speed, ultra-high durability and extremely low dynamic power consumption, so as to support real-time weight update and high-frequency inference tasks. Under this background, three-dimensional stacked NOR type ferroelectric field effect transistor (3D FeNOR) is expected to become a breakthrough solution due to its dual advantages of structure and physical properties. Its core advantages are: through the multi-layer vertical stacked NOR array architecture, the integration density is greatly improved compared with traditional planar devices, while the random access characteristics of NOR type memory are retained, effectively adapting to the parallel computing needs of neural networks. In addition, the device uses the inherent non-volatile storage characteristics and field-driven polarization reversal mechanism of ferroelectric materials to complete the storage cell writing and erasing at a small operating voltage and extremely fast speed, providing a physical basis for building a high-energy-efficient storage and computing integrated system.

[0003] However, the existing three-dimensional FeNOR memory technology still has significant defects in engineering application. The most prominent constraint factor is the inherent durability problem of FeNOR storage cells. During the durability cycle, serious interface trap charge trapping and new trap generation effect make the storage window quickly degrade, resulting in that the device durability is limited to 10 8Below, it is difficult to meet the extreme demand of updating neural network weight parameters in the storage-computing integrated architecture every hour more than one million times. The current mainstream durability improvement scheme adopts oxide semiconductor (OS) as the channel material, which can inhibit trap charge capture and new trap generation by reducing the ferroelectric / semiconductor interface stress, but its inherent characteristics cause new technical bottlenecks: the commonly used OS channel is mostly n-type semiconductor material, and due to the lack of p-type minority carriers in the channel, it is difficult to shield the depolarization field in the ferroelectric layer, so that a larger bias voltage needs to be applied on the gate during the erase operation and the time consumption is more than 1us, which is two orders of magnitude lower than the erase speed of the silicon channel FeFET. This slower erase speed will cause the operation timing of the storage array to be disorderly, which restricts the overall performance improvement of the system. Therefore, it is urgent to break through the trade-off between durability and faster erase speed in the 3D FeNOR memory through collaborative design, so as to lay a solid foundation for realizing a high-reliability storage-computing integrated architecture. SUMMARY

[0004] In view of the problems existing in the prior art, the present application provides a novel three-dimensional stacked NOR type ferroelectric field effect transistor (3D FeNOR) and a preparation method thereof, which combines hafnium-zirconium-oxygen ferroelectric layer and oxide channel layer, and simultaneously optimizes the durability and erase speed of the 3D FeNOR.

[0005] The technical scheme of the present application is as follows:

[0006] A three-dimensional stacked NOR type ferroelectric field effect transistor, comprising a silicon substrate, a silicon dioxide layer, a gate metal electrode, an isolation layer, a vertical trench, a ferroelectric layer, an oxide channel layer, a source, a drain, and a word line contact hole, wherein the silicon dioxide layer is located above the silicon substrate, the gate metal electrode and the isolation layer are alternately stacked to form a word line stack, and the word line stack is located above the silicon dioxide layer, the vertical trench is located inside the stack structure of the word line stack and vertically penetrates through the entire word line stack to the bottom silicon dioxide layer, the ferroelectric layer is attached to the inner wall of the vertical trench and contacts the word line stack, the oxide channel layer is attached to the ferroelectric layer, the metal material of the source and the drain is attached to the oxide channel layer, the source and the drain are the channel region, and there is a gap between the source and the drain at the bottom of the vertical trench shape, and the word line contact hole is located in the word line stack and parallel to the vertical trench, and is used to expose the gate metal electrode of each layer.

[0007] In the word line stack, the gate metal electrode material and the isolation layer material are alternately stacked from bottom to top, and each has at least three layers.

[0008] The vertical trench has a circular or rectangular top view shape.

[0009] Further, the gate metal electrode material in the word line stack can be selected from TiN, TaN, W or polysilicon material, which needs to have a small resistivity, certain thermal stability and mechanical strength, and also needs to have a suitable thermal expansion coefficient to induce stable ferroelectricity in the ferroelectric layer, and the thickness of each layer of the gate metal electrode material is 30-70 nm.

[0010] Further, the isolation material in the word line stack can be selected from silicon dioxide or aluminum oxide material, which needs to have a high resistivity and a high breakdown field to form isolation between the two layers of the gate metal electrode, and the thickness of each layer of the isolation layer is 30-70 nm.

[0011] Further, the ferroelectric layer is hafnium oxide doped with zirconium, aluminum or silicon material, which has stable ferroelectric properties, and the thickness is 5-10 nm.

[0012] Further, the oxide channel layer material is an oxide semiconductor material such as indium oxide, zinc oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, etc., and the thickness is 3-10 nm.

[0013] Further, the metal material of the source and the drain can be selected from but not limited to Al, Pt, Cr, Cu, Au, Ti material, which needs to have a low resistivity and form a good ohmic contact with the oxide channel layer to reduce the resistance, and the thickness is 20-100 nm.

[0014] The application also provides a method for preparing the three-dimensional stacked NOR type ferroelectric field effect transistor, which comprises the following steps:

[0015] (1) growing a silicon dioxide layer on a silicon substrate by oxidation or chemical vapor deposition (CVD) method;

[0016] (2) alternately growing gate metal electrode material and isolation layer material on the silicon dioxide layer to form a word line stack, wherein the gate metal electrode material is grown by sputtering or other physical vapor deposition (PVD) method, and the isolation layer material is grown by chemical vapor deposition (CVD) method;

[0017] (3) defining the pattern of the vertical trench by ultraviolet lithography, using photoresist as a barrier layer, and removing the word line stack material in the vertical trench by dry etching until the bottom of the vertical trench reaches the silicon dioxide layer on the silicon substrate;

[0018] (4) growing a hafnium-zirconium-oxygen ferroelectric layer on the entire wafer by atomic layer deposition (ALD) method, and the ferroelectric layer is attached to the inner wall of the vertical trench;

[0019] (5) growing a titanium nitride sacrificial layer on the ferroelectric layer by physical vapor deposition (PVD) method;

[0020] (6) Rapid thermal annealing (RTP) is performed on the whole film to activate the ferroelectricity of the ferroelectric layer;

[0021] (7) The titanium nitride sacrificial layer is removed by using a wet etching method;

[0022] (8) The indium gallium oxide channel layer is grown on the ferroelectric layer by using an atomic layer deposition (ALD) method;

[0023] (9) The pattern of the indium gallium oxide channel region is defined by ultraviolet lithography, and the indium gallium oxide material in the non-channel region is removed by wet etching;

[0024] (10) The metal pattern region of the source and the drain is defined by electron beam lithography, and the metal material of the source and the drain is deposited on the whole film by evaporation or other physical vapor deposition (PVD) methods, and then the metal material in the non-pattern region is removed by a stripping technique to form the source and the drain, and the channel region between the source and the drain;

[0025] (11) The pattern of the word line contact hole is defined layer by layer by ultraviolet lithography, the photoresist is used as a barrier layer, and the dielectric material in the contact hole is removed by dry etching and wet etching, so that the bottom of each layer of the word line contact hole reaches the surface of each layer of the gate metal electrode material.

[0026] Further, the hafnium zirconium oxygen ferroelectric layer in the step (4) is grown by using an atomic layer deposition (ALD) method, and tetrakis(dimethylamino)hafnium (TDMAHf), tetrakis(dimethylamino)zirconium (TDMAZr) and water are used as the precursors of hafnium, zirconium and oxygen respectively, the atomic ratio of the doping is controlled by controlling the cycle ratio of hafnium oxide and zirconium oxide in the atomic layer deposition cycle process, and finally the atomic ratio of hafnium and zirconium in the formed hafnium zirconium oxygen solid solution layer is 1:1, so that good ferroelectricity is ensured.

[0027] Further, the rapid thermal annealing in the step (6) is performed at an annealing temperature of 500-900 ℃ and an annealing time of 10-120 s.

[0028] Further, the titanium nitride sacrificial layer in the step (7) is removed by using a No. 1 cleaning solution, which is a solution formed by mixing ammonia, hydrogen peroxide and water in a volume ratio of 1:1:5.

[0029] Further, the indium gallium oxide channel layer in the step (8) is grown by using an atomic layer deposition method, and indium cyclopentadiene (InCp), triethyl gallium (TEGa) and ozone are used as the precursors of indium, gallium and oxygen respectively, the atomic ratio of the doping is controlled by controlling the cycle ratio of indium oxide and gallium oxide, and finally the atomic ratio of indium and gallium in the formed oxide material is 1:2.

[0030] The technical effects of the present application are as follows:

[0031] I. In the 3D FeNOR device, the direct combination of hafnium zirconium oxide and indium gallium oxide channel avoids the formation of interface layer, inhibits the interface trap charge capture, and thus improves the durability.

[0032] In the conventional silicon channel FeFET device, the direct contact of hafnium zirconium oxide ferroelectric layer with silicon channel will cause oxygen element migration to silicon channel and oxidation reaction during subsequent high temperature process, thereby forming a thin silicon oxide interface layer containing more defects between hafnium zirconium oxide ferroelectric layer and silicon channel. In the cycle process, the thin interface layer has a large electric field intensity and more traps, and will have a strong trap charge capture effect, causing the device to degrade in durability. In the present application, the hafnium zirconium oxide ferroelectric layer is in direct contact with the indium gallium oxide channel. Since both are oxide materials, and the indium gallium oxide channel is grown without undergoing a high temperature process during device preparation, there is no intense oxygen migration and reaction between hafnium zirconium oxide and indium gallium oxide channel, and no oxide interface layer is formed. Since the formation of the interface layer is avoided, the voltage almost completely falls on the ferroelectric layer during the writing process, effectively inhibiting the shielding effect of interface trap charge capture on ferroelectric polarization, thus inhibiting the durability degradation and optimizing the durability. Through the durability test, the 3D FeNOR device proposed in the present application realizes a high durability of 10 11 times, which is 4 orders of magnitude higher than the same structure device reported previously.

[0033] II. In the 3D FeNOR device, the width and length of the channel are reduced, and the principles of hindering channel seepage path and enhancing edge field effect are used to improve the erase speed of the device.

[0034] In a conventional oxide channel FeFET device, since the common oxide channel is an n-type semiconductor, when a negative voltage is applied to the device gate for erasing, the channel lacks p-type minority carriers, making it difficult to shield the depolarization field formed after the ferroelectric layer is polarized and flipped, so a large part of the voltage falls in the channel layer rather than the ferroelectric layer, the ferroelectric layer voltage is reduced, and the ferroelectric polarization needs a longer time to completely flip, resulting in slow erasing speed. In the 3D FeNOR of the present application, the actual device channel width is defined by the thickness of the gate metal electrode material, that is, reduced to below 100 nm. In the device with reduced channel width, the ferroelectric polarization flip during erasing easily leads to the complete depletion of the channel carriers along the channel width direction, at which time the channel is cut off and the device erasing can be achieved without the need for complete polarization flip. In the device with a wider channel, due to the wider channel, the channel carriers along the channel width direction are difficult to be completely depleted, that is, there will be some seepage paths, and the channel is difficult to be cut off, so a longer erasing time is needed to achieve complete polarization flip. Therefore, the reduction of the channel width in the 3D FeNOR effectively speeds up the erasing speed. In addition to the reduction of the channel width, the 3D FeNOR of the present application also adopts electron beam lithography technology to reduce the channel length of the device to 100 nm. The reduction of the channel length makes it easier for the edge electric field from the gate metal electrode to the source and drain metal electrodes to affect the ferroelectric layer between the source and drain metal electrodes, that is, the electric field strength of the ferroelectric layer during erasing is increased, which helps the ferroelectric polarization to complete the flip faster, and speeds up the erasing speed. Through programming and erasing speed test, the 3D FeNOR of the present application shortens the programming and erasing time to 50 ns, which is 3 orders of magnitude shorter than the same structure device reported previously.

[0035] The three-dimensional stacked NOR type ferroelectric field effect transistor of the present application optimizes the durability and erasing speed through the optimization of the gate stack and device size, ensures the integration density while greatly improving the comprehensive performance such as durability and speed, successfully breaks through the trade-off limit between durability and erasing speed, and has great potential in the in-memory computing field facing artificial intelligence acceleration. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 (a) is a cross-sectional view of a three-dimensional stacked NOR type ferroelectric field effect transistor prepared by an embodiment of the present application, and (b) is a three-dimensional schematic view of a three-dimensional stacked NOR type ferroelectric field effect transistor;

[0037] Figure 2 is a schematic diagram of each step of preparing a three-dimensional stacked NOR type ferroelectric field effect transistor by an embodiment of the present application, wherein:

[0038] (a) is a cross-sectional view after growing a 300 nm thick silicon dioxide layer on a silicon substrate by oxidation;

[0039] (b) is a cross-sectional view after forming a word line stack by alternately growing a titanium nitride gate metal electrode material and a silicon dioxide isolation material by sputtering and plasma-enhanced chemical vapor deposition (PECVD), respectively, on the basis of (a);

[0040] (c) is a cross-sectional view after forming a vertical trench by dry etching after defining a vertical trench pattern by ultraviolet lithography on the basis of (b);

[0041] (d) is a cross-sectional view after growing a hafnium-zirconium-oxygen ferroelectric layer by atomic layer deposition on the basis of (c);

[0042] (e) is a cross-sectional view after growing a titanium nitride sacrificial layer by sputtering and activating ferroelectricity by rapid thermal annealing on the basis of (d);

[0043] (f) is a cross-sectional view after growing an indium-gallium-oxide channel layer by atomic layer deposition and patterning by ultraviolet lithography and etching after removing the titanium nitride sacrificial layer by wet etching on the basis of (e);

[0044] (g) is a cross-sectional view after growing metal materials of a source and a drain by electron beam evaporation after defining a pattern of the source and the drain by electron beam lithography on the basis of (f) and peeling off metal materials of non-patterned areas;

[0045] (h) is a cross-sectional view after removing excess dielectric materials in a word line contact hole by dry etching and wet etching after defining a pattern of the word line contact hole layer by layer by ultraviolet lithography on the basis of (g);

[0046] Figure 1 and Figure 2 in which:

[0047] 1 - silicon substrate 2 - silicon dioxide layer

[0048] 3 - titanium nitride gate metal electrode 4 - silicon dioxide isolation layer

[0049] 5 - vertical trench 6 - hafnium-zirconium-oxygen ferroelectric layer

[0050] 7 - indium-gallium-oxide channel layer 8 - source

[0051] 9 - drain 10 - word line contact hole

[0052] Figure 3 is a result of durability test of a three-dimensional stacked NOR-type ferroelectric field effect transistor prepared in an example of the present application, in which the inset is a waveform schematic of the durability test;

[0053] Figure 4(a) and (b) are the results of programming and erasing speed tests of the three-dimensional stacked NOR ferroelectric field effect transistor prepared in an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The present invention will be further described below with reference to specific embodiments in conjunction with the accompanying drawings.

[0055] like Figure 1 As shown, the three-dimensional stacked NOR ferroelectric field-effect transistor prepared in this embodiment includes a silicon substrate 1, a silicon dioxide layer 2, a titanium nitride gate metal electrode 3, a silicon dioxide spacer 4, a vertical trench 5, a hafnium zirconium oxide ferroelectric layer 6, an indium gallium oxide channel layer 7, a source 8, a drain 9, and a wordline contact hole 10. The silicon dioxide layer 2 is located on the silicon substrate, the titanium nitride gate metal electrode 3 and the silicon dioxide spacer 4 are located on the silicon dioxide layer 2, the titanium nitride gate metal electrode 3 and the silicon dioxide spacer 4 are alternately stacked to form a wordline stack, the vertical trench 5 is located in the wordline stack, the hafnium zirconium oxide ferroelectric layer 6 is located on the inner wall of the vertical trench 5 and contacts the wordline stack, the indium gallium oxide channel layer 7 is located on the hafnium zirconium oxide ferroelectric layer 6, the source 8 and the drain 9 are located on the indium gallium oxide channel layer 7, and the wordline contact hole 10 is located in the wordline stack and connected to each layer of the gate metal electrode 3.

[0056] The process steps of the preparation method of the three-dimensional stacked NOR type ferroelectric field effect transistor are as follows: Figure 2 As shown, specifically including:

[0057] 1) A 300 nm thick silicon dioxide layer 2 is grown on a silicon substrate 1 by oxidation, as shown in FIG. Figure 2 As shown in (a);

[0058] 2) Three layers of titanium nitride gate metal electrode 3 and silicon dioxide isolation layer 4 are alternately grown on the silicon dioxide layer 2 by sputtering and plasma enhanced chemical vapor deposition (PECVD), and the thickness of each layer is 70nm. Figure 2 As shown in (b);

[0059] 3) Define the pattern of the vertical trench 5 by ultraviolet lithography, then use photoresist as a barrier layer and remove the gate metal electrode and isolation layer in the vertical trench 5 by dry etching until the bottom of the vertical trench 5 reaches the silicon dioxide layer 2, as shown in FIG. Figure 2 As shown in (c);

[0060] 4) A hafnium zirconium oxide ferroelectric layer 6 is grown on the entire wafer by atomic layer deposition (ALD), with a hafnium to zirconium atomic ratio of 1:1 and a thickness of 10 nm. The ferroelectric layer is attached to the inner wall of the vertical trench, as shown in FIG. Figure 2 As shown in (d);

[0061] 5) A 50nm thick titanium nitride sacrificial layer is grown on the ferroelectric layer by sputtering, and then the entire wafer is subjected to rapid thermal annealing (RTP) to activate the ferroelectricity of the ferroelectric layer. The annealing conditions are 600℃, 90s. The role of the titanium nitride sacrificial layer is to apply stress to the ferroelectric layer during the annealing process to obtain stable ferroelectricity, such as Figure 2 As shown in (e);

[0062] 6) The titanium nitride sacrificial layer is removed by etching with a cleaning solution No. 1. The cleaning solution No. 1 is a solution formed by mixing ammonia, hydrogen peroxide and water in a volume ratio of 1:1:5. It can completely remove the titanium nitride sacrificial layer without damaging the bottom hafnium zirconium oxide ferroelectric layer, thereby protecting the interface; then, an indium gallium oxide channel layer 7 is grown on the ferroelectric layer by atomic layer deposition (ALD), specifically, indium cyclopentadiene (InCp), triethyl gallium (TEGa) and ozone are used as precursors of indium, gallium and oxygen, respectively, and the atomic ratio of doping is controlled by controlling the cyclic rate ratio of indium oxide and gallium oxide. The finally formed oxide material has an indium and gallium atomic ratio of 1:2 and a thickness of 9 nm; then, the indium gallium oxide channel layer 7 pattern is defined by ultraviolet lithography, and the indium gallium oxide material in the non-channel area is removed by etching with a dilute hydrochloric acid solution diluted 1:20, as shown in FIG. Figure 2 As shown in (f);

[0063] 7) Define the source 8 and drain 9 pattern area by electron beam lithography, then grow the metal material Ti / Pt alloy of the source 8 and drain 9 by electron beam evaporation, and then use the lift-off technology to remove the metal material in the non-pattern area to form the source 8 and drain 9, as shown in FIG. Figure 2 As shown in (g), the channel region is between the source and drain;

[0064] 8) Define the pattern of the word line contact hole 10 layer by layer by ultraviolet lithography, then use photoresist as a barrier layer, and remove the excess dielectric material in the contact hole by dry etching and wet etching, so that the bottom of each word line contact hole 10 contacts the corresponding gate metal electrode 3 of each layer, as shown in FIG. Figure 2 As shown in (h).

[0065] At this point, the three-dimensional stacked NOR ferroelectric field effect transistor can be obtained.

[0066] In the steps, the hafnium zirconium oxide ferroelectric layer is preferably grown by atomic layer deposition (ALD), and tetrakis(dimethylamino)hafnium (TDMAHf), tetrakis(dimethylamino)zirconium (TDMAZr) and water are used as precursors of hafnium, zirconium and oxygen, respectively. During the atomic layer deposition cycle, the ratio of the number of cycles of hafnium oxide and zirconium oxide is controlled to control the ratio of hafnium atoms to zirconium atoms. The ratio of hafnium atoms to zirconium atoms in the finally formed hafnium zirconium oxide solid solution layer is 1:1, thereby ensuring good ferroelectricity.

[0067] The temperature and time of the rapid thermal annealing process in the step need to meet the suitable conditions for activating the ferroelectricity, and need to be flexibly adjusted according to the gate metal electrode, the ferroelectric layer material and thickness, and the general range is: the annealing temperature is 500-900 ℃, and the annealing time is 10-120 s.

[0068] Figure 3 is the result of the durability test of the three-dimensional stacked NOR type ferroelectric field effect transistor prepared in the example of the present application, by characterizing the relationship between the threshold voltage of the programmed state and the erased state of the 3D FeNOR and the cycle number, it is found that the storage window of the 3D FeNOR is only slightly degraded after 10 11 cycles, that is, the 3D FeNOR prepared in the example of the present application shows high durability of more than 10 11 cycles, which is 4 orders of magnitude higher than the durability of the similar structure 3D FeNOR device reported previously.

[0069] Figure 4 is the result of the programming and erasing speed test of the three-dimensional stacked NOR type ferroelectric field effect transistor prepared in the example of the present application, by characterizing the change of the storage window under different write pulse voltage amplitude and width, the programming and erasing conditions of the 3D FeNOR are obtained as 4.25 V, 50 ns and-3.25 V, 50 ns, that is, the write time is 50 ns, which is 3 orders of magnitude higher than the write speed of the similar structure 3D FeNOR device reported previously.

[0070] Finally, it should be noted that the purpose of the disclosed examples is to help further understand the present application, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present application and the appended claims. Therefore, the present application should not be limited to the disclosed examples, and the scope of the present application claimed is the scope defined by the claims.

Claims

1. A three-dimensional stacked NOR ferroelectric field-effect transistor, comprising a silicon substrate, a silicon dioxide layer, a gate metal electrode, an isolation layer, a vertical trench, a ferroelectric layer, an oxide channel layer, a source, a drain, and a word line contact hole, wherein the silicon dioxide layer is located above the silicon substrate, characterized in that: The gate metal electrode and the isolation layer are alternately stacked to form a word line stack of a stack structure, and are located above a silicon dioxide layer. The vertical trench is located inside the stack structure of the word line stack and vertically penetrates through the entire word line stack to the bottom silicon dioxide layer. The ferroelectric layer is attached to the inner wall of the vertical trench and contacts the word line stack. The oxide channel layer is attached to the ferroelectric layer. The source and the drain metal material are attached to the oxide channel layer. The source and the drain are separated by a channel region. A gap exists between the source and the drain at the bottom of the vertical trench shape. The word line contact hole is located in the word line stack and is parallel to the vertical trench, and is used to expose the gate metal electrode of each layer. In the word line stack, the gate metal electrode material and the isolation layer material are alternately stacked from bottom to top, and each has at least three layers. The vertical trench has a circular or rectangular shape in plan view.

2. The 3D stacked NOR ferroelectric field effect transistor of claim 1, wherein, The gate metal electrode material in the word line stack is selected from TiN, TaN, W or polysilicon material. The thickness of each layer of gate metal electrode material is 30-70 nm.

3. The 3D stacked-NOR ferroelectric field effect transistor of claim 1, wherein, The isolation material in the word line stack is selected from silicon dioxide or aluminum oxide. The thickness of each layer of isolation layer is 30-70 nm.

4. The 3D stacked-NOR ferroelectric field effect transistor of claim 1, wherein, The ferroelectric layer material is hafnium oxide doped with zirconium, aluminum or silicon, and the thickness is 5-10 nm.

5. The 3D stacked NOR ferroelectric field effect transistor of claim 1, wherein, The oxide channel layer material is an oxide semiconductor material: indium oxide, zinc oxide, indium gallium oxide, indium zinc oxide or indium gallium zinc oxide, and the thickness is 3-10 nm.

6. The 3D stacked NOR ferroelectric field effect transistor of claim 1, wherein, The source and drain metal material is selected from Al, Pt, Cr, Cu, Au or Ti, and the thickness is 20-100 nm.

7. A method for preparing a three-dimensional stacked NOR ferroelectric field effect transistor, characterized in that: The method comprises the following steps: (1) Growing a silicon dioxide layer on a silicon substrate by oxidation or chemical vapor deposition; (2) Alternately growing a gate metal electrode material and an isolation layer material on the silicon dioxide layer to form a word line stack, wherein the gate metal electrode material is grown by sputtering or other physical vapor deposition method, and the isolation layer material is grown by chemical vapor deposition method; (3) Defining the pattern of the vertical trench by ultraviolet lithography, using photoresist as a barrier layer, and removing the word line stack material in the vertical trench by dry etching until the bottom of the vertical trench reaches the silicon dioxide layer on the silicon substrate; (4) Growing a hafnium-zirconium-oxygen ferroelectric layer on the entire wafer by atomic layer deposition, and the ferroelectric layer is attached to the inner wall of the vertical trench; (5) Growing a titanium nitride sacrificial layer on the ferroelectric layer by physical vapor deposition; (6) Activating the ferroelectric property of the ferroelectric layer by rapid thermal annealing treatment; (7) Removing the titanium nitride sacrificial layer by wet etching; (8) Growing an indium gallium oxide channel layer on the ferroelectric layer by atomic layer deposition; (9) Defining the pattern of the indium gallium oxide channel region by ultraviolet lithography, and removing the indium gallium oxide material in the non-channel region by wet etching; (10) Defining the metal pattern region of the source and drain by electron beam lithography, and then depositing the metal material of the source and drain on the entire wafer by evaporation or other physical vapor deposition (PVD) method, and then removing the metal material in the non-pattern region by peeling technology to form the source and drain, and the source and drain are separated by a channel region. (11) The pattern of the word line contact hole is defined layer by layer by ultraviolet lithography, photoresist is used as a barrier layer, dry etching and wet etching are used to remove the dielectric material in the contact hole, so that the bottom of each layer of word line contact hole reaches the surface of each layer of gate metal electrode material.

8. The method of claim 7, wherein, The step (4) uses atomic layer deposition to grow the hafnium-zirconium-oxygen ferroelectric layer, uses tetrakis(dimethylamino)hafnium (TDMAHf), tetrakis(dimethylamino)zirconium (TDMAZr) and water as the precursors of hafnium, zirconium and oxygen respectively, controls the atomic ratio of doping by controlling the cycle ratio of hafnium oxide and zirconium oxide in the atomic layer deposition cycle process, and finally the ratio of hafnium atoms and zirconium atoms in the hafnium-zirconium-oxygen solid solution layer is 1:

1.

9. The method of claim 7, wherein, The step (6) is rapid thermal annealing treatment, the annealing temperature is 500-900℃, and the annealing time is 10-120s.

10. The method of claim 7, wherein, In the step (7), a first cleaning solution, a solution formed by mixing ammonia, hydrogen peroxide and water in a volume ratio of 1:1:5, is used to remove the titanium nitride sacrificial layer; in the step (8), atomic layer deposition is used to grow the indium gallium oxide channel layer, indium cyclopentadiene (InCp), triethyl gallium (TEGa) and ozone are used as the precursors of indium, gallium and oxygen respectively, the atomic ratio of doping is controlled by controlling the cycle ratio of indium oxide and gallium oxide, and finally the atomic ratio of indium and gallium in the oxide material is 1:2.

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