Magnetic memory device

Abstract

The magnetic memory device stabilizes magnetization reversal. A magnetic memory device includes: a first conductor layer extending in a first direction; a second conductor layer extending in the first direction and aligned with the first conductor layer in a second direction intersecting the first direction; a first magnetoresistive effect element electrically connected to the first conductor layer; a second magnetoresistive effect element electrically connected to the second conductor layer; and a third conductor layer extending in the second direction and in contact with the first magnetoresistive effect element. In a write operation for writing data to the first magnetoresistive effect element, a first current is applied to the first conductor layer, a second current is applied to the second conductor layer, and a third current is applied to the third conductor layer independently of the first current and the second current.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a magnetic memory device. BACKGROUND

[0002] A magnetic memory device using a magnetic resistance effect element as a storage element is known. As a method of writing data to a magnetic resistance effect element, various methods have been proposed in the industry. For example, as a method of writing data without causing a current to flow directly through a magnetic resistance effect element, a method using a spin orbit torque (SOT) is known.

[0003] [BACKGROUND ART DOCUMENT]

[0004] [PATENT DOCUMENT]

[0005] Patent Document 1: U.S. Patent Application Publication No. 2021 / 0125654 Specification

[0006] Patent Document 2: U.S. Patent Application Publication No. 2019 / 0051815 Specification

[0007] Patent Document 3: U.S. Patent Application Publication No. 2019 / 0244646 Specification SUMMARY

[0008] [PROBLEMS TO BE SOLVED BY THE INVENTION]

[0009] The magnetic memory device of the present application stabilizes magnetization reversal.

[0010] [TECHNICAL MEANS FOR SOLVING THE PROBLEMS]

[0011] The magnetic memory device of the embodiment includes a first electric conductor layer, a second electric conductor layer, a third electric conductor layer, a first magnetic resistance effect element, and a second magnetic resistance effect element. The first electric conductor layer extends along a first direction. The second electric conductor layer extends along the first direction and is arranged with the first electric conductor layer along a second direction intersecting the first direction. The first magnetic resistance effect element is electrically connected to the first electric conductor layer. The second magnetic resistance effect element is electrically connected to the second electric conductor layer. The third electric conductor layer extends along the second direction and is in contact with the first magnetic resistance effect element. In a write operation of writing data to the first magnetic resistance effect element, a first current is applied to the first electric conductor layer, a second current is applied to the second electric conductor layer, and a third current is applied to the third electric conductor layer independently of the first current and the second current. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a block diagram showing an example of the configuration of the magnetic memory device of the first embodiment.

[0013] Figure 2 is a circuit diagram showing an example of a circuit configuration of the memory cell array of Embodiment 1.

[0014] Figure 3 is a cross-sectional view showing an example of a cross-sectional structure of a part of the memory string of Embodiment 1.

[0015] Figure 4 is a graph showing an example of a voltage applied to the memory cell array in the first example of the write operation of the magnetic memory device of Embodiment 1.

[0016] Figure 5 is a graph showing an example of a current and a magnetic field applied to the memory cell array in the first example of the write operation of the magnetic memory device of Embodiment 1.

[0017] Figure 6 is a graph showing an example of a voltage applied to the memory cell array in the second example of the write operation of the magnetic memory device of Embodiment 1.

[0018] Figure 7 is a graph showing an example of a current and a magnetic field applied to the memory cell array in the second example of the write operation of the magnetic memory device of Embodiment 1.

[0019] Figure 8 is a graph showing a first application example of an application timing of a current applied in the write operation of the magnetic memory device of Embodiment 1.

[0020] Figure 9 is a graph showing a second application example of an application timing of a current applied in the write operation of the magnetic memory device of Embodiment 1.

[0021] Figure 10 is a graph showing a third application example of an application timing of a current applied in the write operation of the magnetic memory device of Embodiment 1.

[0022] Figure 11 is a graph showing a fourth application example of an application timing of a current applied in the write operation of the magnetic memory device of Embodiment 1.

[0023] Figure 12 is a graph showing a fifth application example of an application timing of a current applied in the write operation of the magnetic memory device of Embodiment 1.

[0024] Figure 13 is a graph showing a sixth application example of an application timing of a current applied in the write operation of the magnetic memory device of Embodiment 1.

[0025] Figure 14is a circuit diagram showing an example of a circuit configuration of a memory cell array of Embodiment 2.

[0026] Figure 15 is a cross-sectional view showing an example of a cross-sectional structure of a part of the memory cell array of Embodiment 2.

[0027] Figure 16 is a graph showing an example of a voltage applied to the memory cell array in a first example of a write operation of the magnetic memory device of Embodiment 2.

[0028] Figure 17 is a graph showing an example of a current and a magnetic field applied to the memory cell array in the first example of the write operation of the magnetic memory device of Embodiment 2.

[0029] Figure 18 is a graph showing an example of a voltage applied to the memory cell array in a second example of the write operation of the magnetic memory device of Embodiment 2.

[0030] Figure 19 is a graph showing an example of a current and a magnetic field applied to the memory cell array in the second example of the write operation of the magnetic memory device of Embodiment 2. DETAILED DESCRIPTION

[0031] Hereinafter, several embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are denoted by common reference numerals. In the case where a plurality of components having common reference numerals are distinguished, a suffix is added to the common reference numeral. In the case where a plurality of components do not need to be distinguished in particular, only the common reference numeral is added to the plurality of components, and no suffix is added. The suffix is not limited to a subscript or a superscript, and includes, for example, a lowercase letter added to the end of a reference numeral, a symbol, and an index indicating arrangement, and the like.

[0032] In this specification, the magnetic memory device is, for example, an MRAM (Magnetoresistive Random Access Memory). The magnetic memory device includes a magnetoresistance effect element as a memory element. The magnetoresistance effect element is a resistance change element having a tunnel magnetoresistance effect (Magnetoresistance effect) by a magnetic tunnel junction (MTJ). The magnetoresistance effect element is also referred to as an MTJ element.

[0033] 1. Embodiment 1

[0034] A magnetic memory device of Embodiment 1 will be described.

[0035] 1.1 Configuration

[0036] First, the configuration of the magnetic memory device of the first embodiment will be described.

[0037] 1.1.1 Magnetic memory device

[0038] Figure 1 is a block diagram showing an example of the configuration of the magnetic memory device of the first embodiment. The magnetic memory device 1 includes a memory cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a write circuit 14, a read circuit 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0039] The memory cell array 10 is a storage section of data of the magnetic memory device 1. The memory cell array 10 includes a plurality of memory cells MC. The plurality of memory cells MC each establish a correspondence with a group of a row and a column. The memory cells MC located in the same row establish a correspondence with the same word line WL. The memory cells MC located in the same column establish a correspondence with the same read bit line RBL.

[0040] The row selection circuit 11 is a circuit that selects a row of the memory cell array 10. The row selection circuit 11 is connected to the memory cell array 10 via the word line WL. To the row selection circuit 11, a decoding result (row address) of the address ADD from the decoding circuit 13 is supplied. The row selection circuit 11 selects the word line WL corresponding to the row based on the decoding result of the address ADD. Hereinafter, the selected word line WL is referred to as a selected word line WL. In addition, the word line WL other than the selected word line WL is referred to as a non-selected word line WL.

[0041] The column selection circuit 12 is a circuit that selects a column of the memory cell array 10. The column selection circuit 12 is connected to the memory cell array 10 via the read bit line RBL. To the column selection circuit 12, a decoding result (column address) of the address ADD from the decoding circuit 13 is supplied. The column selection circuit 12 selects the read bit line RBL corresponding to the column based on the decoding result of the address ADD. Hereinafter, the selected read bit line RBL is referred to as a selected bit line RBL. In addition, the read bit line RBL other than the selected bit line RBL is referred to as a non-selected bit line RBL.

[0042] The decoding circuit 13 is a decoder that decodes the address ADD from the input / output circuit 17. The decoding circuit 13 supplies a decoding result of the address ADD to the row selection circuit 11 and the column selection circuit 12. The address ADD includes a column address and a row address.

[0043] The write circuit 14 includes, for example, a write driver (not shown). The write circuit 14 performs writing of data to the memory cell MC.

[0044] The readout circuit 15 includes, for example, a sense amplifier (not shown). The readout circuit 15 reads out data from the memory cell MC.

[0045] The voltage generating circuit 16 generates voltages used for various operations of the memory cell array 10 using a power supply voltage supplied from outside (not shown) of the magnetic memory device 1. For example, the voltage generating circuit 16 generates various voltages required at the time of a write operation, and outputs to the write circuit 14. Further, for example, the voltage generating circuit 16 generates various voltages required at the time of a read operation, and outputs to the readout circuit 15.

[0046] The input / output circuit 17 is responsible for communication with the outside of the magnetic memory device 1. The input / output circuit 17 transfers an address ADD from the outside of the magnetic memory device 1 to the decoding circuit 13. The input / output circuit 17 transfers an instruction CMD from the outside of the magnetic memory device 1 to the control circuit 18. The input / output circuit 17 transmits and receives various control signals CNT between the outside of the magnetic memory device 1 and the control circuit 18. The input / output circuit 17 transfers data DAT from the outside of the magnetic memory device 1 to the write circuit 14, and outputs data DAT transferred from the readout circuit 15 to the outside of the magnetic memory device 1.

[0047] The control circuit 18 includes, for example, a processor such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory). The control circuit 18 controls the operations of the row selection circuit 11, the column selection circuit 12, the decoding circuit 13, the write circuit 14, the readout circuit 15, the voltage generating circuit 16, and the input / output circuit 17 in the magnetic memory device 1 based on the control signals CNT and the instruction CMD.

[0048] 1.1.2 Memory Cell Array

[0049] Next, the configuration of the memory cell array of the magnetic memory device of the first embodiment will be described.

[0050] Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array of the first embodiment. In Figure 2 , various constituent elements are displayed in classification by a suffix including an index ("<>").

[0051] The memory cell array 10 includes a plurality of word lines WL, a plurality of read bit lines RBL, a write bit line WBL, a source line SL, and a plurality of memory strings MS. In addition, the memory cell array 10 includes a plurality of switching elements SEL3. The plurality of word lines WL includes (M+1) word lines WL<0>,..., WL<m>,..., and WL<M>. M is an integer of 2 or more (0 < m < M). In addition, in the example of Figure 2 the example, but is not limited thereto. For example, M can be 0, or 1. The plurality of read bit lines RBL includes (N+1) read bit lines RBL<0>,..., RBL<n>,..., and RBL<N>. N is an integer of 2 or more (0 < n < N). The plurality of switching elements SEL3 includes (N+1) switching elements SEL3<0>,..., and SEL3<N>. The plurality of memory strings MS includes (M+1) memory strings MS<0>,..., MS<m>,..., and MS<M>. The memory strings MS<0> to MS<M> each have a corresponding relationship with the word lines WL<0> to WL<M>. The memory strings MS<0> to MS<M> each have the same configuration. Hereinafter, the memory string MS<m> will be described as an example.

[0052] The memory string MS<m> includes a switching element SEL1<m>, a wiring SOTL<m>, and (N+1) memory cells MC<m,0>,..., MC<m,n>,..., and MC<m,N>.

[0053] The switching element SEL1<m> is a 3-terminal switching element such as a MOSFET. Specifically, the switching element SEL1<m> has a first terminal connected to the wiring SOTL<m>, a second terminal connected to the write bit line WBL, and a control terminal connected to the word line WL<m>.

[0054] The wiring SOTL<m> has a first terminal connected to the first terminal of the switching element SEL1<m>, a second terminal connected to the source line SL, and a central portion between the first and second terminals. In the central portion of the wiring SOTL<m>, the (N+1) memory cells MC<m,0>,..., MC<m,n>,..., and MC<m,N> are connected to each other. Hereinafter, the portion of the central portion of the wiring SOTL<m> connected to any one of the memory cells MC<m,0> to MC<m,N> will be referred to as a "cell portion". In addition, the portion of the central portion of the wiring SOTL<m> between the two adjacent cell portions will be referred to as a "wiring portion". Each cell portion of the wiring SOTL<m> has a first terminal connected to the write bit line WBL via the switching element SEL1<m>, and a second terminal connected to the source line SL.

[0055] The memory cells MC <m, 0> to MC <m, N> are connected to the read bit lines RBL <0> to RBL <N>, respectively. The memory cells MC <m, 0> to MC <m, N> each have the same configuration. Hereinafter, the memory cell MC <m, n> will be described as an example.

[0056] The memory cell MC <m, n> includes a unit portion of the wiring SOTL <m> corresponding to the memory cell MC <m, n>, a switching element SEL2 <m, n>, and a magnetoresistive effect element MTJ <m, n>.

[0057] The switching element SEL2 <m, n> is a 3-terminal type switching element such as a MOSFET. The switching element SEL2 <m, n> has a first terminal connected to the magnetoresistive effect element MTJ <m, n>, a second terminal connected to the read bit line RBL <n>, and a control terminal.

[0058] The magnetoresistive effect element MTJ <m, n> is connected in series between the switching element SEL2 <m, n> and the unit portion of the wiring SOTL <m> corresponding to the memory cell MC <m, n>. The magnetoresistive effect element MTJ <m, n> is a resistance change element. The magnetoresistive effect element MTJ <m, n> functions as a storage element that stores data nonvolatilely according to a change in the resistance state.

[0059] As described above, each memory string MS includes (N + 1) memory cells MC connected to one wiring SOTL. Thus, the memory cell array 10 is configured to include (M + 1) x (N + 1) memory cells MC <0, 0>,..., MC <0, n>,..., MC <0, N>,..., MC <m, 0>,..., MC <m, n>,..., MC <m, N>,..., MC <M, 0>,..., MC <M, n>,..., and MC <M, N> by having (M + 1) memory strings MS.

[0060] The switching elements SEL3 <0> to SEL3 <N> each are a 3-terminal type switching element such as a MOSFET. The switching elements SEL3 <0> to SEL3 <N> each have the same configuration. Hereinafter, the switching element SEL3 <n> will be described as an example. The switching element SEL3 <n> is provided on the path of the read bit line RBL <n>. At a first terminal of the switching element SEL3 <n>, (M + 1) switching elements SEL2 <0, n> to SEL2 <M, n> are commonly connected via the read bit line RBL <n>. Thus, the switching element SEL3 <n> can control whether or not to transmit the voltage applied to the read bit line RBL <n> to the (M + 1) switching elements SEL2 <0, n> to SEL2 <M, n>.

[0061] 1.1.3 Memory String

[0062] Next, the configuration of the memory string of the magnetic memory device of Embodiment 1 is described. Hereinafter, a plane parallel to the surface of the substrate on which the memory cell array 10 is provided is set as the XY plane. The direction in which the memory cell array 10 is provided with respect to the surface of the substrate is set as the Z direction or upward direction. Directions that intersect each other in the XY plane are set as the X direction and the Y direction.

[0063] Figure 3 is a cross-sectional view showing an example of the cross-sectional structure of a portion of the memory string of Embodiment 1. As shown in Figure 3 , the memory string MS <m> includes the conductor layer 30, a plurality of element layers 40, a plurality of conductor layers 50, a plurality of element layers 60, a plurality of conductor layers 70, and a plurality of conductor layers 80. In Figure 3 , as an example, a portion of the wiring SOTL <m> in the memory string MS <m> and three memory cells MC <m, n-1>, MC <m, n>, and MC <m, n+1> connected to the portion of the wiring SOTL <m> are shown.

[0064] (Overall structure)

[0065] First, the overall structure of the memory string MS is described.

[0066] The insulator layer 20 is provided above the substrate (not shown). The conductor layer 30 is provided on the upper surface of the insulator layer 20. The conductor layer 30 extends along the X direction. The conductor layer 30 functions as the wiring SOTL <m>. The portion of the conductor layer 30 that repeatedly overlaps the element layer 40 in the Z direction functions as the cell portion. The portion of the conductor layer 30 that does not repeatedly overlap the element layer 40 in the Z direction functions as the wiring portion.

[0067] The conductor layer 30 is a continuous film containing a heavy metal having non-magnetic and conductive properties. The conductor layer 30 contains, as the heavy metal, at least one element selected from the group consisting of tantalum (Ta), tungsten (W), rhenium (Re), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), copper (Cu), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), manganese (Mn), lead (Pb), bismuth (Bi), antimony (Sb), tellurium (Te), selenium (Se), and polonium (Po), for example. The element contained in the conductor layer 30 as the heavy metal can include an oxide, a nitride, or a sulfide. In the case where tungsten (W) or tantalum (Ta) is contained, the structure of the element is preferably a β structure. The conductor layer 30 can use a conductive oxide such as ruthenium oxide (RuO2) or iridium oxide (IrO2). In addition, the conductor layer 30 can use a transition metal dichalcogenide having a two-dimensional layered structure such as WTe2, WS2, and WSe2. The conductor layer 30 can be configured with a single layer of the material described above, or can be configured with a plurality of layers of the material described above stacked. The conductor layer 30 generates spins mainly caused by the spin Hall effect by the current flowing through the inside. In addition, a spin torque caused by the spin splitter effect, a spin torque caused by the Rashba effect, and the like are sometimes generated. These spin torques are collectively referred to as a spin orbit torque (SOT). The spin orbit torque acts on a portion of the element layer 40 that is in contact with the conductor layer 30.

[0068] A plurality of element layers 40 are provided on the upper surface of the conductor layer 30. The plurality of element layers 40 each have a columnar shape extending in the Z direction. The plurality of element layers 40 each function as a magnetic resistance effect element MTJ. Details of the configuration of the element layer 40 are described later.

[0069] A conductor layer 50 is provided on the upper surface of each of the plurality of element layers 40. The plurality of conductor layers 50 each have a columnar shape extending in the Z direction. The plurality of conductor layers 50 each function as an electrode that electrically connects the element layer 40 and an element layer 60.

[0070] An element layer 60 is provided on the upper surface of each of the plurality of conductor layers 50. The plurality of element layers 60 each have a columnar shape extending in the Z direction. The plurality of element layers 60 each function as a 3-terminal type switching element. Details of the configuration of the element layer 60 are described later.

[0071] A conductor layer 70 is provided on the upper surface of each of the plurality of element layers 60. The plurality of conductor layers 70 each have a columnar shape extending in the Z direction. The plurality of conductor layers 70 each function as an electrode that electrically connects the element layer 60 and a conductor layer 80.

[0072] The plurality of conductor layers 80 are each provided on the upper surface of each of the plurality of conductor layers 70. The plurality of conductor layers 80 each extend along the Y direction. The plurality of conductor layers 80 are arranged along the X direction. The plurality of conductor layers 80 each function as a readout bit line RBL.

[0073] The element layer 40, the conductor layer 50, the element layer 60, the conductor layer 70, and the conductor layer 80 are covered by an insulator layer 90.

[0074] (Magnetoresistive Effect Element MTJ)

[0075] Then, the structure of the magnetoresistive effect element MTJ included in the memory string MS will be described.

[0076] The plurality of element layers 40 each include a ferromagnetic layer 41, a nonmagnetic layer 42, a ferromagnetic layer 43, a nonmagnetic layer 44, and a ferromagnetic layer 45. The ferromagnetic layer 41, the nonmagnetic layer 42, the ferromagnetic layer 43, the nonmagnetic layer 44, and the ferromagnetic layer 45 are laminated in order from the lower side to the upper side.

[0077] The ferromagnetic layer 41 is provided so as to be in contact with the upper surface of the conductor layer 30. The ferromagnetic layer 41 is a conductive film having ferromagnetism. The ferromagnetic layer 41 functions as a storage layer. The ferromagnetic layer 41 has an easy magnetization axis direction in a direction perpendicular to the film surface (Z direction). The spin-orbit torque generated in the conductor layer 30 acts on the ferromagnetic layer 41. In the case where a spin-orbit torque of a prescribed magnitude acts, the magnetization direction of the ferromagnetic layer 41 is configured to be reversed.

[0078] The ferromagnetic layer 41 is generally a ferromagnetic layer using any one element selected from cobalt (Co), iron (Fe), and nickel (Ni). A cobalt iron (CoFe) alloy, iron (Fe), cobalt iron boron (CoFeB), iron boron (FeB), cobalt boron (CoB), and cobalt iron nickel boron (CoFeNiB), and the like become representative ferromagnetic layers of perpendicular magnetization. These have a body-centered cubic structure (BCC structure). In addition, as an element to substitute for boron (B), phosphorus (P), carbon (C), and the like can be mentioned. The magnetic material of CoFeB and the like generates perpendicular magnetic anisotropy at the interface by being in contact with an oxide having a NaCl (001) structure. A MgO (001) / CoFeB laminated film and the like are typical thereof.

[0079] A non-magnetic layer 42 is provided on the upper surface of the ferromagnetic layer 41. The non-magnetic layer 42 is an insulating film having non-magnetic properties. The non-magnetic layer 42 functions as a tunnel barrier layer. The non-magnetic layer 42 is provided between the ferromagnetic layer 41 and a ferromagnetic layer 43, and forms a magnetic tunnel junction together with these two ferromagnetic layers. That is, a magnetoresistance effect is generated in the magnetic tunnel junction portion. In addition, in the case where a cobalt-iron-boron (CoFeB) or the like initial amorphous layer is used as an interface layer of the ferromagnetic layer 41, the non-magnetic layer 42 functions as a seed material for becoming a crystal nucleus for growing a crystalline film from the interface with the ferromagnetic layer 41 during crystallization processing of the ferromagnetic layer 41. Similarly, in the case where cobalt-iron-boron (CoFeB) is used as an interface layer of the ferromagnetic layer 43, the non-magnetic layer 42 also functions as a seed material for the ferromagnetic layer 43. Here, the initial amorphous layer is a layer that is in an amorphous state immediately after film formation and is crystallized after annealing processing. The non-magnetic layer 42 has a structure of a square or cubic crystal system in which the film surface is oriented to a (001) plane. As the oxide used for the non-magnetic layer 42, for example, magnesium oxide (MgO) is representative. As another example of the oxide used for the non-magnetic layer 42, magnesium-aluminum oxide (MgAlOx) or the like can be given. Hereinafter, a case where magnesium oxide (MgO) is used will be described. The magnesium oxide (MgO) has a NaCl structure. In the case where the magnesium oxide (MgO) is used for the non-magnetic layer 42, the (001) interface of the magnesium oxide (MgO) and the (001) interface of the cobalt-iron-boron (CoFeB) are integrated and crystal growth is performed by annealing processing. Thus, the cobalt-iron-boron (CoFeB) has a body-centered cubic structure in which the (001) plane is oriented.

[0080] A ferromagnetic layer 43 is provided on the upper surface of the non-magnetic layer 42. The ferromagnetic layer 43 is a conductive film having ferromagnetic properties. The ferromagnetic layer 43 functions as a reference layer. The ferromagnetic layer 43 has an easy magnetization axis in a direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic layer 43 is fixed. In addition, "magnetization direction fixed" means that the magnetization direction does not change due to a torque of a size that can reverse the magnetization direction of the ferromagnetic layer 41. In the case where the ferromagnetic layer 43 is formed of cobalt-iron-boron (CoFeB), the magnetization direction of the ferromagnetic layer 43 is fixed in the direction of the easy magnetization axis. In the case where the ferromagnetic layer 43 is formed of cobalt-iron-boron (CoFeB), the magnetization direction of the ferromagnetic layer 43 is fixed in the direction of the easy magnetization axis. Figure 3In the example, the magnetization direction of the ferromagnetic layer 43 is oriented toward the direction of the ferromagnetic layer 41. Generally, an interface layer is included in the ferromagnetic layer 43. As the interface layer of the ferromagnetic layer 43, an initial amorphous layer of cobalt iron boron (CoFeB) or the like is used. Further, an auxiliary ferromagnetic layer is provided in a manner to be in contact with the side of the face of the cobalt iron boron (CoFeB) layer opposite to the face in contact with the magnesium oxide (MgO) layer. The auxiliary ferromagnetic layer includes, for example, an alloy film of at least one selected from cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd). In addition, as the auxiliary ferromagnetic layer, a laminated film of a Co / Pt laminated film, a Co / Pd laminated film, or the like can be used. The cobalt iron boron (CoFeB) layer that becomes the initial amorphous layer is used in laminated with the CoPt, CoPd, Co / Pt laminated film, Co / Pd laminated film, or the like. In this case, the interface layer in the ferromagnetic layer 43, for example, the CoFeB layer is formed on the side closer to the nonmagnetic layer 42 than the other layers, and the (001)-oriented MgO is formed.

[0081] The nonmagnetic layer 44 is provided on the upper surface of the ferromagnetic layer 43. The nonmagnetic layer 44 is a conductive film having nonmagnetic properties. The nonmagnetic layer 44 functions as a spacer layer. The nonmagnetic layer 44 is composed of, for example, an element selected from ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), and chromium (Cr), or an alloy thereof.

[0082] The ferromagnetic layer 45 is provided on the upper surface of the nonmagnetic layer 44. The ferromagnetic layer 45 is a conductive film having ferromagnetic properties. The ferromagnetic layer 45 functions as a shift cancelling layer. The ferromagnetic layer 45 has an easy magnetization axis direction in the direction perpendicular to the film surface (Z direction). The ferromagnetic layer 45 includes, for example, an alloy layer of at least one selected from cobalt platinum (CoPt), cobalt palladium (CoPd), cobalt palladium platinum (CoPdPt), and cobalt chromium platinum (CoCrPt). In addition, as the ferromagnetic layer 45, a laminated film of a Co / Pt laminated film, a Co / Pd laminated film, and a Co / Ni laminated film, or the like can be used.

[0083] The ferromagnetic layer 43 and the ferromagnetic layer 45 are antiferromagnetically coupled through the nonmagnetic layer 44. That is, the ferromagnetic layer 43 and the ferromagnetic layer 45 are coupled in a manner to have magnetization directions that are antiparallel to each other. This antiferromagnetic magnetic coupling of the ferromagnetic layer 43, the nonmagnetic layer 44, and the ferromagnetic layer 45 is referred to as a SAF (Synthetic Anti-Ferromagnetic) coupling. By the SAF coupling state, the ferromagnetic layer 45 cancels the influence of the leakage magnetic field of the ferromagnetic layer 43 on the change in the magnetization direction of the ferromagnetic layer 41, and the influence of the leakage magnetic field of the ferromagnetic layer 43 on the ferromagnetic layer 41 can be reduced in substance.

[0084] The magnetoresistive effect element MTJ can take either of a low resistance state and a high resistance state according to whether the relative relationship of the magnetization directions of the storage layer and the reference layer is parallel or anti-parallel. In the magnetic memory device 1, the magnetization direction of the storage layer with respect to the magnetization direction of the reference layer is controlled by not flowing a write current through such a magnetoresistive effect element MTJ. Specifically, a write method using spin-orbit torque generated by flowing a current through a wiring SOTL is employed.

[0085] When a write current Ic0 of a certain magnitude is caused to flow in the wiring SOTL in the X direction, the relative relationship of the magnetization directions of the storage layer and the reference layer becomes parallel. In the case of this parallel state, the resistance value of the magnetoresistive effect element MTJ is the lowest, and the magnetoresistive effect element MTJ is set to a low resistance state. This low resistance state is referred to as a "P (Parallel) state" and is defined as a state of, for example, data "0".

[0086] In addition, when a write current Ic1 is caused to flow in the wiring SOTL in the opposite direction of the write current Ic0, the relative relationship of the magnetization directions of the storage layer and the reference layer becomes anti-parallel. In the case of this anti-parallel state, the resistance value of the magnetoresistive effect element MTJ is the highest, and the magnetoresistive effect element MTJ is set to a high resistance state. This high resistance state is referred to as an "AP (Anti-Parallel) state" and is defined as a state of, for example, data "1".

[0087] In addition, the method of defining data "1" and data "0" is not limited to the above-described example. For example, the P state can be defined as data "1", and the AP state can be defined as data "0".

[0088] (Switching element SEL2)

[0089] Next, the structure of the switching element SEL2 included in the memory string MS will be described.

[0090] The element layer 60 includes a semiconductor film 61, an insulator film 62, and a conductive layer 63. The element layer 60 has, for example, an SGT (Surrounding Gate Transistor) structure.

[0091] The semiconductor film 61 is disposed in the central portion of the element layer 60 in the Z direction. The semiconductor film 61 extends along the Z direction and has a lower end that is in contact with the conductive layer 50 and an upper end that is in contact with the conductive layer 70. The semiconductor film 61 serves as a current path (channel) of the switching element SEL2. The semiconductor film 61 contains, for example, silicon (Si).

[0092] The insulator film 62 covers the side surface of the semiconductor film 61. The insulator film 62 serves as a gate insulating film of the switching element SEL2. The insulator film 62 contains, for example, silicon oxide (SiO2).

[0093] The conductor layer 63 covers a part of the side surface of the insulator film 62. The conductor layer 63 serves as a gate electrode of the switching element SEL2. The conductor layer 63 contains, for example, tungsten (W).

[0094] 1.2 Write Operation

[0095] Next, the write operation of the magnetic memory device of the first embodiment will be described.

[0096] 1.2.1 First Example

[0097] First, the first example of the write operation will be described. The first example of the write operation corresponds to a case where data "0" is written by flowing the write current Ic0 in the wiring SOTL.

[0098] Figure 4 is a view showing an example of the voltage applied to the memory cell array in the first example of the write operation of the magnetic memory device of the first embodiment. In Figure 4 , an example of the voltage applied to the three wirings SOTL Figure 4 , the switching elements SEL2 and SEL3 in the on state are each marked with "O", and the switching elements SEL2 and SEL3 in the off state are each marked with "X". In Figure 4 , the memory cell MC

[0099] In the case of the first example of the write operation with respect to the selected memory cell MC

[0100] In addition, the first end and the second end of the wiring SOTL Figure 4The first and second ends of the other selection bit line RBL <n> are applied with voltages VSS and k2Vw, respectively. The first end of the other selection bit line RBL <n> is the end portion opposite to the switching element SEL3 <n+1> with respect to the memory cell array 10. The second end of the other selection bit line RBL <n> is the end portion sandwiching the memory cell array 10 between the switching element SEL3 <n+1>. The voltage k2Vw is a voltage k2 times the voltage Vw (0 < k2 < 1). The voltage k2Vw is a voltage for flowing the current Iw0 <n+1> in the other selection bit line RBL <n+1>. In addition, k1 and k2 can be different from each other or can be equal.

[0101] In addition, the first and second ends of the selection bit line RBL <n> are applied with voltages VSS and Vw, respectively. The first end of the selection bit line RBL <n> is the end portion opposite to the switching element SEL3 <n> with respect to the memory cell array 10. The second end of the selection bit line RBL <n> is the end portion sandwiching the memory cell array 10 between the switching element SEL3 <n>. The voltage Vw is a voltage for flowing the current Iw0 <n> (not shown) in the selection bit line RBL <n>.

[0102] The first and second ends of the non-selection bit line RBL <n-1> located at one of the two neighbors of the selection bit line RBL <n> are applied with voltages k1Vw and VSS, respectively. The first end of the non-selection bit line RBL <n-1> is the end portion opposite to the switching element SEL3 <n-1> with respect to the memory cell array 10. The second end of the non-selection bit line RBL <n-1> is the end portion sandwiching the memory cell array 10 between the switching element SEL3 <n-1>. The voltage k1Vw is a voltage k1 times the voltage Vw (0 < k1 < 1). The voltage k1Vw is a voltage for flowing the current Iw0 <n-1> in the non-selection bit line RBL <n-1>.

[0103] The first and second ends of the non-selection bit line RBL <n+1> located at the other of the two neighbors of the selection bit line RBL <n> are applied with voltages VSS and k2Vw, respectively. The first end of the non-selection bit line RBL <n+1> is the end portion opposite to the switching element SEL3 <n+1> with respect to the memory cell array 10. The second end of the non-selection bit line RBL <n+1> is the end portion sandwiching the memory cell array 10 between the switching element SEL3 <n+1>. The voltage k2Vw is a voltage k2 times the voltage Vw (0 < k2 < 1). The voltage k2Vw is a voltage for flowing the current Iw0 <n+1> in the non-selection bit line RBL <n+1>. In addition, k1 and k2 can be different from each other or can be equal.

[0104] Figure 5 is a view showing an example of the current and the magnetic field applied in the memory cell array in the first example of the write operation of the magnetic memory device of the first embodiment. In Figure 5 , the current Ic0 <m>, Iw0 <n>, Iw0 <n-1>, and Iw0 <n+1> and the magnetic field Hw0 <n>, Hw0 <n-1>, and Hw0 <n+1> generated by the voltages Vc0, Vw, k1Vw, and k2Vw shown in Figure 4 , respectively, and the change in the magnetization direction of the selected memory cell MC <m, n> are shown.

[0105] As described, voltages Vc0and VSSare applied to both ends of the wiring SOTL<m>, respectively. Thereby, a write current Ic0<m>flows from the paper left side to the paper right side (the +X direction) of the conductive layer 30. By the write current Ic0<m>flowing through the conductive layer 30, a spin orbit torque intended to set the magnetization direction of the ferromagnetic layer 41 to be parallel to the ferromagnetic layer 43 is generated. The spin orbit torque acts on all the ferromagnetic layers 41 that are in contact with the conductive layer 30. Figure 5

[0106] In addition, as described, voltages VSSand Vware applied to both ends of the selected bit line RBL<n>, respectively. Voltages k1Vwand VSSare applied to both ends of the non-selected bit line RBL<n-1>, respectively. Voltages VSSand k2Vware applied to both ends of the non-selected bit line RBL<n+1>, respectively. Thereby, in the conductive layer 80 corresponding to the selected bit line RBL<n>, a current Iw0<n>flows from the paper deep side to the paper near side (the -Y direction) of the conductive layer 80. In the conductive layer 80 corresponding to the non-selected bit line RBL<n-1>, a current Iw0<n-1>flows from the paper near side to the paper deep side (the +Y direction) of the conductive layer 80. In the conductive layer 80 corresponding to the non-selected bit line RBL<n+1>, a current Iw0<n+1>flows from the paper deep side to the paper near side (the -Y direction) of the conductive layer 80. The currents Iw0<n-1>and Iw0<n+1>are each, for example, k1 times and k2 times the size of the current Iw0<n>. Figure 5 Figure 5 Figure 5

[0107] By the currents Iw0<n>, Iw0<n-1>, Iw0<n+1>, magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1>are respectively applied in the vicinity of the interface between the conductive layer 30 and the ferromagnetic layer 41 corresponding to the selected memory cell MC<m,n>. The magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1>respectively take the shape of concentric circles centered on the currents Iw0<n>, Iw0<n-1>, and Iw0<n+1>and are applied in the counterclockwise direction with respect to the directions of the currents Iw0<n>, Iw0<n-1>, and Iw0<n+1>.

[0108] Thereby, in the example of Figure 5 the magnetic field Hw0<n>applied to the selected memory cell MC<m,n>is in the direction (+X direction) in which the current Ic0<m>flows. In addition, in the example of Figure 5 ​​​​In the example, the directions of the magnetic fields Hw0<n-1> and Hw0<n+1> applied to the selected memory cell MC<m,n> are directions inclined in the -Z direction with respect to the direction of the current Ic0<m> flowing. Also, the magnetic fields Hw0<n-1> and Hw0<n+1> applied to the selected memory cell MC<m,n> are applied in directions that mutually reinforce in the -Z direction. Thus, the resultant magnetic field of the magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1> applied to the selected memory cell MC<m,n> is a magnetic field having a component in the +X direction and a component in the -Z direction.

[0109] In addition, the direction of the magnetic field Hw0<n> is determined depending on the material constituting the conductor layer 30. Thus, the direction of the magnetic field Hw0<n> sometimes becomes the opposite direction (-X direction) of the direction of the current Ic0<m> flowing. In addition, the direction of the resultant magnetic field of the magnetic fields Hw0<n-1> and Hw0<n+1> has a component of the magnetization direction (-Z direction) of the ferromagnetic layer 41 determined by the writing operation.

[0110] The component in the X direction of the resultant magnetic field of the magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1> applied to the selected memory cell MC<m,n> assists the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> due to the spin-orbit torque. The component in the Z direction of the resultant magnetic field of the magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1> applied to the selected memory cell MC<m,n> increases the speed of the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> due to the spin-orbit torque and suppresses the kink in the reversal process. Thus, the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> is reversed to a direction parallel with respect to the magnetization direction of the ferromagnetic layer 43.

[0111] By operating as above, data "0" is written to the selected memory cell MC<m,n>.

[0112] 1.2.2 Second Example

[0113] Then, the second example of the writing operation is described. The second example of the writing operation corresponds to a case where data "1" is written by flowing a writing current Ic1 in the wiring SOTL.

[0114] Figure 6 is a view showing an example of the voltage applied to the memory cell array in the second example of the writing operation of the magnetic memory device of the first embodiment. Figure 6 Corresponding to the first example of the writing operation Figure 4 .

[0115] In the second example of performing a column write operation on the selected memory cell MC<m,n>, all switching elements SEL2 are turned off. Switching elements SEL3<n-1>, SEL3<n>, and SEL3<n+1> are turned on. Furthermore, all other switching elements SEL3 are turned off.

[0116] In addition, voltages VSS and Vc1 are applied to the first and second ends of the wiring SOTL<m>, respectively. Voltage Vc1 is a voltage for flowing a write current Ic1<m> (not shown) in the wiring SOTL. In this way, the polarity of the voltage applied to the wiring SOTL<m> in the second example of the write action is reversed from the voltage applied to the wiring SOTL<m> in the first example of the write action, and the magnitude may also be different. Moreover, voltage VSS is applied to the first and second ends of each of the wirings SOTL<m-1> and SOTL<m+1> located on both sides of the wiring SOTL<m>. In addition, although Figure 6 Although not shown in the figure, the voltage VSS is applied to the first end and the second end of each of the other wirings SOTL.

[0117] Voltages VSS and Vw are applied to the first and second ends of the selected bit line RBL<n>, respectively. Voltages VSS and k1Vw are applied to the first and second ends of the unselected bit line RBL<n-1>, respectively. Voltages k2Vw and VSS are applied to the first and second ends of the unselected bit line RBL<n+1>, respectively. In this way, the voltage applied to the selected bit line RBL<n> in the second example of the write operation is the same as the voltage applied to the selected bit line RBL<n> in the first example of the write operation. On the other hand, the polarities of the voltages applied to the unselected bit lines RBL<n-1> and RBL<n+1> in the second example of the write operation are reversed from the polarities of the voltages applied to the unselected bit lines RBL<n-1> and RBL<n+1> in the first example of the write operation.

[0118] Figure 7 This is a diagram showing an example of the current and magnetic field applied to the memory cell array in the second example of the write operation of the magnetic memory device according to the first embodiment. Figure 7 Corresponding to the first example of the write operation Figure 5 .

[0119] As described above, voltages VSS and Vc1 are applied to both ends of the wiring SOTL<m>. Figure 7 A write current Ic1<m> is passed through the conductive layer 30 (in the -X direction). This flow of the write current Ic1<m> generates a spin-orbit moment that tends to set the magnetization direction of the ferromagnetic layer 41 antiparallel to that of the ferromagnetic layer 43. This spin-orbit moment acts on all ferromagnetic layers 41 in contact with the conductive layer 30.

[0120] In addition, as described above, the voltages VSS and Vw are applied to both ends of the selected bit line RBL<n>, respectively. The voltages VSS and k1Vw are applied to both ends of the non-selected bit line RBL<n-1>, respectively. The voltages k2Vw and VSS are applied to both ends of the non-selected bit line RBL<n+1>, respectively. Thus, in the conductor layer 80 corresponding to the selected bit line RBL<n>, the current Iwl<n> flows from the paper-deep side to the paper-near side (-Y direction). In the conductor layer 80 corresponding to the non-selected bit line RBL<n-1>, the current Iwl<n-1> flows from the paper-deep side to the paper-near side (-Y direction). In the conductor layer 80 corresponding to the non-selected bit line RBL<n+1>, the current Iwl<n+1> flows from the paper-near side to the paper-deep side (+Y direction). The currents Iwl<n-1> and Iwl<n+1> are, for example, k1 times and k2 times the size of the current Iwl<n>, respectively. That is, the current values of the currents Iwl<n-1> and Iwl<n+1> are smaller than the current value of the current Iwl<n>. Figure 7 Figure 7 Figure 7

[0121] By the currents Iwl<n>, Iwl<n-1>, and Iwl<n+1>, the magnetic fields Hwl<n>, Hwl<n-1>, and Hwl<n+1> are respectively applied in the vicinity of the interface between the conductor layer 30 and the ferromagnetic layer 41 corresponding to the selected memory cell MC<m,n>. The direction of the magnetic field Hwl<n> applied to the selected memory cell MC<m,n> is opposite (+X direction) to the direction in which the current Icl<m> flows. The directions of the magnetic fields Hwl<n-1> and Hwl<n+1> applied to the selected memory cell MC<m,n> are directions inclined in the +Z direction with respect to the direction in which the current Icl<m> flows. Moreover, the magnetic fields Hwl<n-1> and Hwl<n+1> applied to the selected memory cell MC<m,n> are applied in directions in which they mutually reinforce in the +Z direction. Thus, the resultant magnetic field of the magnetic fields Hwl<n>, Hwl<n-1>, and Hwl<n+1> applied to the selected memory cell MC<m,n> is a magnetic field having a component in the +X direction and a component in the +Z direction.

[0122] In addition, the direction of the magnetic field Hwl<n> is determined in accordance with the material constituting the conductor layer 30, in the same manner as the direction of the magnetic field Hwo<n>. Thus, the direction of the magnetic field Hwl<n> does not change regardless of the data being written. In addition, the direction of the resultant magnetic field of the magnetic fields Hwl<n-1> and Hwl<n+1> has a component of the magnetization direction (+Z direction) of the ferromagnetic layer 41 determined by the write operation.

[0123] ​​​The component of the resultant magnetic field of the magnetic fields Hw1<n>, Hw1<n-1>, and Hw1<n+1> applied to the selected memory cell MC<m,n> in the X direction assists the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> caused by the spin-orbit torque. The component of the resultant magnetic field of the magnetic fields Hw1<n>, Hw1<n-1>, and Hw1<n+1> applied to the selected memory cell MC<m,n> in the Z direction increases the speed of the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> caused by the spin-orbit torque, and suppresses the stagnation during the reversal. Thus, the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC<m,n> is reversed to the direction anti-parallel to the magnetization direction of the ferromagnetic layer 43.

[0124] By acting as above, data "1" is written to the selected memory cell MC<m,n>.

[0125] In addition, the resultant magnetic field of the magnetic fields Hw0<n>, Hw0<n-1>, and Hw0<n+1> applied to the selected memory cell MC<m,n> in the first example of the write operation, and the resultant magnetic field of the magnetic fields Hw1<n>, Hw1<n-1>, and Hw1<n+1> applied to the selected memory cell MC<m,n> in the second example of the write operation also act on the non-selected memory cells MC<m,n-1> and MC<m,n+1>. However, the magnitude of the resultant magnetic field applied to the non-selected memory cells MC<m,n-1> and MC<m,n+1> is sufficiently smaller than the magnitude of the magnetic field for reversing the magnetization direction of the ferromagnetic layer 41. Thus, in either case of the first and second examples of the write operation, data is not written to the non-selected memory cells MC<m,n-1> and MC<m,n+1>.

[0126] 1.2.3 Timing of application of current

[0127] Then, the timing of application of the current applied at the time of the write operation will be described. Hereinafter, six application examples applicable to both the first and second examples of the write operation will be described. Hereinafter, for the convenience of description, the currents Ic0 and Ic1 are simply denoted as the current Ic. Similarly, the currents Iw0<n>, and Iw1<n>, Iw0<n-1>, and Iw1<n-1>, and Iw0<n+1>, and Iw1<n+1> are simply denoted as the currents Iw<n>, Iw<n-1>, and Iw<n+1>, respectively.

[0128] (First application example)

[0129] Figure 8is a diagram of a first application example showing the application timing of the current applied in the write operation of the magnetic memory device of the first embodiment. The first application example corresponds to a case where the application start timing of the current Ic is substantially identical to the application start timing of each of the currents Iw<n>, Iw<n-1>, and Iw<n+1>, and the application end timing of the current Ic is substantially identical to the application end timing of each of the currents Iw<n>, Iw<n-1>, and Iw<n+1>.

[0130] As shown in Figure 8 , the application start timing Tcs of the current Ic can be substantially identical to the application start timing Tws<n> of the current Iw<n>, the application start timing Tws<n-1> of the current Iw<n-1>, and the application start timing Tws<n+1> of the current Iw<n+1>. In addition, the application end timing Tce of the current Ic can be substantially identical to the application end timing Twe<n> of the current Iw<n>, the application end timing Twe<n-1> of the current Iw<n-1>, and the application end timing Twe<n+1> of the current Iw<n+1>.

[0131] (Second application example)

[0132] Figure 9 is a diagram of a second application example showing the application timing of the current applied in the write operation of the magnetic memory device of the first embodiment. The second application example corresponds to a case where the application start timing of the current Ic is substantially identical to the application start timing of each of the currents Iw<n>, Iw<n-1>, and Iw<n+1>, and the application end timing of the current Ic is different from the application end timing of each of the currents Iw<n>, Iw<n-1>, and Iw<n+1>.

[0133] As shown in Figure 9 , the application start timing Tcs of the current Ic can be substantially identical to the application start timing Tws<n> of the current Iw<n>, the application start timing Tws<n-1> of the current Iw<n-1>, and the application start timing Tws<n+1> of the current Iw<n+1>. In addition, the application end timing Tce of the current Ic can be different from the application end timing Twe<n> of the current Iw<n>, the application end timing Twe<n-1> of the current Iw<n-1>, and the application end timing Twe<n+1> of the current Iw<n+1>.

[0134] In addition, in Figure 9In the example, the second application example is shown for the case where the application of currents Iw<n>, Iw<n-1>, and Iw<n+1> ends after the application of current Ic ends. However, the second application example is not limited to this. For example, the second application example may include the case where the application of currents Iw<n>, Iw<n-1>, and Iw<n+1> ends before the application of current Ic ends. However, from the perspective of improving the stability of magnetization reversal in the ferromagnetic layer 41, the case where the application of currents Iw<n>, Iw<n-1>, and Iw<n+1> ends after the application of current Ic ends is more preferable.

[0135] (Third application example)

[0136] Figure 10 This diagram shows a third application example of the timing of current application during the write operation of the magnetic memory device according to the first embodiment. The third application example corresponds to a case where the application start time of the current Ic is different from the application start time of the currents Iw<n>, Iw<n-1>, and Iw<n+1>, and the application end time of the current Ic is different from the application end time of the currents Iw<n>, Iw<n-1>, and Iw<n+1>.

[0137] like Figure 10 As shown, the application start time Tcs of the current Ic may be different from the application start time Tws<n> of the current Iw<n>, the application start time Tws<n-1> of the current Iw<n-1>, and the application start time Tws<n+1> of the current Iw<n+1>. Furthermore, the application end time Tce of the current Ic may be different from the application end time Twe<n> of the current Iw<n>, the application end time Twe<n-1> of the current Iw<n-1>, and the application end time Twe<n+1> of the current Iw<n+1>.

[0138] In addition, Figure 10 In, with Figure 9 Similarly, the case where application of currents Iw<n>, Iw<n-1>, and Iw<n+1> is terminated after application of current Ic is terminated is shown, but the second application example is not limited to this. For example, the third application example may include a case where application of currents Iw<n>, Iw<n-1>, and Iw<n+1> is terminated before application of current Ic is terminated. However, from the perspective of improving the stability of magnetization reversal in the ferromagnetic layer 41, the case where application of currents Iw<n>, Iw<n-1>, and Iw<n+1> is terminated after application of current Ic is terminated is more preferable.

[0139] (Example 4)

[0140] Figure 11is a diagram showing a fourth application example of an application timing of a current applied in a write operation of the magnetic memory device of the first embodiment. The fourth application example corresponds to a case where an application start timing of the current Iw<n> is different from each of application start timings of the currents Iw<n-1> and Iw<n+1>, and an application end timing of the current Iw<n> is substantially identical to each of application end timings of the currents Iw<n-1> and Iw<n+1>.

[0141] As shown in Figure 11 , the application start timing Tws<n> of the current Iw<n> can be different from the application start timing Tws<n-1> of the current Iw<n-1> and the application start timing Tws<n+1> of the current Iw<n+1>. In addition, the application end timing Twe<n> of the current Iw<n> can be substantially identical to each of the application end timing Twe<n-1> of the current Iw<n-1> and the application end timing Twe<n+1> of the current Iw<n+1>.

[0142] In addition, in Figure 11 , a case where the application of the currents Iw<n-1> and Iw<n+1> is started after the application of the current Iw<n> is started is shown, but the fourth application example is not limited thereto. For example, the fourth application example can include a case where the application of the current Iw<n> is started after the application of the currents Iw<n-1> and Iw<n+1> is started.

[0143] (Fifth Application Example)

[0144] Figure 12 is a diagram showing a fifth application example of an application timing of a current applied in a write operation of the magnetic memory device of the first embodiment. The fifth application example corresponds to a case where an application start timing of the current Iw<n> is different from each of application start timings of the currents Iw<n-1> and Iw<n+1>, and an application end timing of the current Iw<n> is different from each of application end timings of the currents Iw<n-1> and Iw<n+1>.

[0145] As shown in Figure 12 , the application start timing Tws<n> of the current Iw<n> can be different from the application start timing Tws<n-1> of the current Iw<n-1> and the application start timing Tws<n+1> of the current Iw<n+1>. In addition, the application end timing Twe<n> of the current Iw<n> can be different from each of the application end timing Twe<n-1> of the current Iw<n-1> and the application end timing Twe<n+1> of the current Iw<n+1>.

[0146] In addition, in Figure 12 , a case where the application of the currents Iw<n-1> and Iw<n+1> is started after the application of the current Iw<n> is started is shown, but the fourth application example is not limited thereto. For example, the fourth application example can include a case where the application of the current Iw<n> is started after the application of the currents Iw<n-1> and Iw<n+1> is started. Figure 11Similarly, the case where the application of currents Iw<n-1> and Iw<n+1> is started after the application of current Iw<n> is started is shown, but the fourth application example is not limited to this. For example, the fourth application example may include the case where the application of current Iw<n-1> and Iw<n+1> is started after the application of currents Iw<n> is started.

[0147] In addition, Figure 12 In the example, the case where the application of currents Iw<n-1> and Iw<n+1> ends after the application of current Iw<n> is completed is shown, but the fifth application example is not limited to this. For example, the fifth application example may include the case where the application of currents Iw<n-1> and Iw<n+1> ends after the application of currents Iw<n> ends.

[0148] (Sixth application example)

[0149] Figure 13 This diagram shows a sixth application example of the application timing of the current applied during the write operation of the magnetic memory device according to the first embodiment. The sixth application example corresponds to a case where the application start time of the current Iw<n> is substantially the same as the application start time of the currents Iw<n-1> and Iw<n+1>, and the application end time of the current Iw<n> is different from the application end time of the currents Iw<n-1> and Iw<n+1>.

[0150] like Figure 13 As shown, the application start time Tws<n> of the current Iw<n> can be substantially the same as the application start time Tws<n-1> of the current Iw<n-1> and the application start time Tws<n+1> of the current Iw<n+1>. Furthermore, the application end time Twe<n> of the current Iw<n> can be different from the application end time Twe<n-1> of the current Iw<n-1> and the application end time Twe<n+1> of the current Iw<n+1>.

[0151] In addition, Figure 13 In, with Figure 12 Similarly, the fifth application example is shown for the case where the application of currents Iw<n-1> and Iw<n+1> ends after the application of current Iw<n> ends. However, the fifth application example is not limited to this. For example, the sixth application example may include the case where the application of currents Iw<n-1> and Iw<n+1> ends after the application of currents Iw<n> ends.

[0152] 1.3 Effects of the First Implementation

[0153] According to the first embodiment, when a write operation to the magnetoresistive effect element MTJ <m,n> is performed, a current Ic <m> is applied to the wiring SOTL <m>. Also, in a manner repeated with the period during which the current Ic <m> is applied, currents Iw <n>, Iw <n-1>, and Iw <n+1> are applied to the read bit lines RBL <n>, RBL <n-1>, and RBL <n+1>, respectively. Thereby, magnetic fields Hw <n>, Hw <n-1>, and Hw <n+1> can be applied near the interface of the ferromagnetic layer 41 corresponding to the magnetoresistive effect element MTJ <m,n> and the wiring SOTL <m>.

[0154] The direction of the magnetic field Hw <n> is parallel to the +X direction. Thus, the magnetic field Hw <n> can assist in the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC <m,n> due to the spin-orbit torque. The magnetic fields Hw <n-1> and Hw <n+1> have a component in the +Z direction in the case where the magnetization direction of the ferromagnetic layer 41 is reversed to the +Z direction, and have a component in the -Z direction in the case where the magnetization direction of the ferromagnetic layer 41 is reversed to the -Z direction. Thus, the magnetic fields Hw <n-1> and Hw <n+1> can improve the stability at the time of the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC <m,n> due to the spin-orbit torque.

[0155] 2. Second Embodiment

[0156] Then, the magnetic memory device of the second embodiment will be described. In the second embodiment, the wiring SOTL is provided at the point of each memory cell MC, unlike the first embodiment. Hereinafter, the configuration and operation that are different from the first embodiment will be mainly described. The configuration and operation that are common to the first embodiment will be appropriately omitted from the description.

[0157] 2.1 Memory Cell Array

[0158] Figure 14 is a circuit diagram showing an example of the circuit configuration of the memory cell array of the second embodiment. Figure 14 Corresponding to the first embodiment Figure 2 .

[0159] The memory cell array 10 includes a plurality of word lines WL, a plurality of read bit lines RBL, a plurality of write bit lines WBL, and a plurality of memory cells MC. In addition, the memory cell array 10 includes a plurality of switching elements SEL3.

[0160] The plurality of switching elements SEL3 have the same configuration as the plurality of switching elements SEL3 of Embodiment 1. The plurality of word lines WL include (M+1) word lines WL<0>,..., WL<m>,..., and WL<M>. The plurality of read bit lines RBL include (N+1) read bit lines RBL<0>,..., RBL<n>,..., and RBL<N>. The plurality of write bit lines WBL include (N+1) write bit lines WBL<0>,..., WBL<n>,..., and WBL<N>. The plurality of switching elements SEL3 include (N+1) switching elements SEL3<0>,..., and SEL3<N>. The plurality of memory cells MC include (M+1) x (N+1) memory cells MC<0,0>,..., MC<0,n>,..., MC<0,N>,..., MC<m,0>,..., MC<m,n>,..., MC<m,N>,..., MC<M,0>,..., MC<M,n>,..., and MC<M,N>. The memory cells MC<0,0> to MC<M,N> have the same configuration. Hereinafter, the memory cell MC<m,n> and the word line WL<m>, the read bit line RBL<n>, and the write bit line WBL<n> connected to the memory cell MC<m,n> are exemplified.

[0161] The memory cell MC<m,n> includes the switching elements SEL1<m,n> and SEL2<m,n>, the wiring SOTL<m,n>, and the magnetoresistive effect element MTJ<m,n>.

[0162] The switching element SEL1<m,n> has a first terminal connected to the wiring SOTL<m,n>, a second terminal connected to the write bit line WBL<n>, and a control terminal.

[0163] The wiring SOTL<m,n> has a first terminal connected to the first terminal of the switching element SEL1<m,n>, a second terminal connected to the word line WL<m>, and a central portion between the first and second terminals. The magnetoresistive effect element MTJ<m,n> is connected to the central portion of the wiring SOTL<m,n>.

[0164] The magnetoresistive effect element MTJ<m,n> has a first terminal connected to the central portion of the wiring SOTL<m,n> and a second terminal connected to the switching element SEL2<m,n>.

[0165] The switching element SEL2<m,n> has a first terminal connected to the second terminal of the magnetoresistive effect element MTJ<m,n>, a second terminal connected to the read bit line RBL<n>, and a control terminal.

[0166] As described above, one memory cell MC includes one wiring SOTL and one magnetoresistive effect element MTJ.

[0167] 2.2 Memory Cell

[0168] Next, the configuration of the memory cell of the magnetic memory device of the second embodiment will be described.

[0169] Figure 15 is a cross-sectional view showing an example of a cross-sectional structure of a portion of the memory cell array of the second embodiment. In Figure 15 , as an example, three memory cells MC<m,n-1>, MC<m,n>, and MC<m,n+1> arranged along the X direction are shown. As shown in Figure 15 , each of the memory cells MC<m,n>, MC<m,n-1>, and MC<m,n+1> includes the conductor layer 30A, the element layer 40, the conductor layer 50, the element layer 60, the conductor layer 70, and the conductor layer 80.

[0170] The cross-sectional structure of the memory cells MC<m,n-1>, MC<m,n>, and MC<m,n+1> of the second embodiment is equivalent to that of the memory cells MC<m,n-1>, MC<m,n>, and MC<m,n+1> of the first embodiment except for the point that the conductor layer 30A to be used as the wiring SOTL is provided separately for each memory cell MC.

[0171] That is, the conductor layer 30A<m,n-1>, the conductor layer 30A<m,n>, and the conductor layer 30A<m,n+1> are arranged in order along the X direction while being separated from each other. Each of the conductor layer 30A<m,n-1>, the conductor layer 30A<m,n>, and the conductor layer 30A<m,n+1> extends along the X direction. The memory cell MC<m,n-1> is provided on the upper surface of the conductor layer 30A<m,n-1>. The memory cell MC<m,n> is provided on the upper surface of the conductor layer 30A<m,n>. The memory cell MC<m,n+1> is provided on the upper surface of the conductor layer 30A<m,n+1>.

[0172] 2.2 Write operation

[0173] Next, the write operation of the magnetic memory device of the second embodiment will be described.

[0174] 2.2.1 First example

[0175] First, the first example of the write operation will be described.

[0176] Figure 16 is a graph showing an example of the voltage applied to the memory cell array in the first example of the write operation of the magnetic memory device of the second embodiment. Figure 16 Corresponding to the memory cells MC<m,n-1>, MC<m,n>, and MC<m,n+1> of the first embodiment Figure 4 In Figure 16In the drawing, an example of voltages applied to 3 read bit lines RBL<n-1>, RBL<n>, and RBL<n+1>, 3 write bit lines WBL<n-1>, WBL<n>, and WBL<n+1>, and 3 word lines WL<m-1>, WL<m>, and WL<m+1> in the memory cell array 10 is shown. In addition, in the drawing, the memory cell MC<m,n> to which writing is performed (that is, the selected state) is shown in a hatched manner. Figure 16 In the drawing, the switch elements SEL1, SEL2, and SEL3 in the on state are each marked with an "O", and the switch elements SEL1, SEL2, and SEL3 in the off state are each marked with an "X". In addition, in the drawing, the memory cell MC<m,n> to which writing is performed (that is, the selected state) is shown in a hatched manner. Figure 16 In the drawing, the memory cell MC<m,n> to which writing is performed (that is, the selected state) is shown in a hatched manner.

[0177] In the case of the first example of the write operation with respect to the selected memory cell MC<m,n>, the switch element SEL1<m,n> is in the on state. In addition, all of the switch elements SEL1 other than the switch element SEL1<m,n> are in the off state. All of the switch elements SEL2 are in the off state. The switch elements SEL3<n-1>, SEL3<n>, and SEL3<n+1> are in the on state. In addition, all of the switch elements SEL3 other than the switch elements SEL3<n-1>, SEL3<n>, and SEL3<n+1> are in the off state.

[0178] The voltage Vc0 is applied to the word line WL<m>. In addition, the voltage VSS is applied to the other word lines WL including the word lines WL<m-1> and WL<m+1>. In addition, the voltage VSS is applied to all of the write bit lines WBL. As a result, the voltages Vc0 and VSS are respectively applied to both ends of the wiring SOTL<m,n>.

[0179] The voltages VSS and Vw are respectively applied to the first end and the second end of the selected bit line RBL<n>. In addition, the voltages k3Vw and VSS are respectively applied to the first end and the second end of the non-selected bit line RBL<n-1> located on one of the two neighbors of the selected bit line RBL<n>. The voltage k3Vw is a voltage that is k3 times the voltage Vw (k3 is a positive real number). The voltages VSS and k4Vw are respectively applied to the first end and the second end of the non-selected bit line RBL<n+1> located on the other of the two neighbors of the selected bit line RBL<n>. The voltage k4Vw is a voltage that is k4 times the voltage Vw (k4 is a positive real number). In addition, k3 and k4 can be different from each other or can be equal.

[0180] Figure 17 is a drawing showing an example of the current and the magnetic field applied to the memory cell array in the first example of the write operation of the magnetic memory device of the second embodiment. Figure 17 Corresponding to the first embodiment Figure 5 .

[0181] As described above, voltages Vc0 and VSS are applied to both ends of the wiring SOTL <m, n>, respectively. Thereby, a write current Ic0 <m> flows from the paper left side to the paper right side (the +X direction) of the conductive layer 30A corresponding to the selected memory cell MC <m, n>. Figure 17 By the write current Ic0 <m> flowing through the conductive layer 30A corresponding to the selected memory cell MC <m, n>, a spin torque intended to make the magnetization direction of the ferromagnetic layer 41 corresponding to the selected memory cell MC <m, n> parallel to the ferromagnetic layer 43 corresponding to the selected memory cell MC <m, n> is generated.

[0182] In addition, as described above, voltages VSS and Vw are applied to both ends of the selected bit line RBL <n>, respectively. Voltages k3Vw and VSS are applied to both ends of the non-selected bit line RBL <n-1>, respectively. Voltages VSS and k4Vw are applied to both ends of the non-selected bit line RBL <n+1>, respectively. Thereby, in the conductive layer 80 corresponding to the selected bit line RBL <n>, a current Iw0 <n> flows from the paper deep side to the paper near side (the -Y direction). Figure 17 In the conductive layer 80 corresponding to the non-selected bit line RBL <n-1>, a current Iw0 <n-1> flows from the paper near side to the paper deep side (the +Y direction). Figure 17 In the conductive layer 80 corresponding to the non-selected bit line RBL <n+1>, a current Iw0 <n+1> flows from the paper deep side to the paper near side (the -Y direction). Figure 17 The currents Iw0 <n-1> and Iw0 <n+1> of the second embodiment are, for example, k3 times and k4 times as large as the current Iw0 <n>, respectively. That is, the current values of the currents Iw0 <n-1> and Iw0 <n+1> of the second embodiment can be smaller than the current value of the current Iw0 <n>, or can be larger than the current value of the current Iw0 <n>.

[0183] By the currents Iw0 <n>, Iw0 <n-1>, and Iw0 <n+1>, magnetic fields Hw0 <n>, Hw0 <n-1>, and Hw0 <n+1> are respectively applied in the vicinity of the interface between the conductive layer 30A corresponding to the selected memory cell MC <m, n> and the ferromagnetic layer 41 corresponding to the selected memory cell MC <m, n>.

[0184] The magnitude and direction of the current Ic0, and the magnitude and direction of each of the magnetic fields Hw0 <n>, Hw0 <n-1>, and Hw0 <n+1> are the same as in the case of the first embodiment. Thus, data "0" is written to the selected memory cell MC <m, n>.

[0185] 2.2.2 Second Example

[0186] Next, a second example of the write operation will be described.

[0187] Figure 18 is a view showing an example of voltages applied to the memory cell array in the second example of the write operation of the magnetic memory device of the second embodiment. Figure 18 corresponding to the first example of the write operation Figure 16 .

[0188] In the case of the second example of the write operation with respect to the selected memory cell MC<m,n>, the switching element SEL1<m,n> becomes the on state. Further, all the switching elements SEL1 except the switching element SEL1<m,n> become the off state. All the switching elements SEL2 become the off state. The switching elements SEL3<n-1>, SEL3<n>, and SEL3<n+1> become the on state. Further, all the other switching elements SEL3 become the off state.

[0189] The voltage Vc1 is applied to the write bit line WBL<n>. Further, the voltage VSS is applied to the other write bit lines WBL including the write bit lines WBL<n-1> and WBL<n+1>. In addition, the voltage VSS is applied to all the word lines WL. Thus, the voltages VSS and Vc1 are respectively applied to both ends of the wiring SOTL<m,n>.

[0190] The voltages VSS and Vw are respectively applied to the first and second ends of the selected bit line RBL<n>. The voltages VSS and k3Vw are respectively applied to the first and second ends of the non-selected bit line RBL<n-1>. The voltages k4Vw and VSS are respectively applied to the first and second ends of the non-selected bit line RBL<n+1>. Thus, the voltages applied to the selected bit line RBL<n> in the second example of the write operation of the second embodiment are the same as the voltages applied to the selected bit line RBL<n> in the first example of the write operation of the second embodiment. On the other hand, the voltages applied to the non-selected bit lines RBL<n-1> and RBL<n+1> in the second example of the write operation of the second embodiment are respectively inverted from the voltages applied to the non-selected bit lines RBL<n-1> and RBL<n+1> in the first example of the write operation of the second embodiment.

[0191] Figure 19 is a view showing an example of currents and magnetic fields applied to the memory cell array in the second example of the write operation of the magnetic memory device of the second embodiment. Figure 19 corresponding to the first example of the write operation Figure 17 .

[0192] As described, the voltages VSS and Vc1 are respectively applied to both ends of the wiring SOTL<m,n>. Thus, the current Ic1 flows from the paper right side of the conductor layer 30A corresponding to the selected memory cell MC<m,n> to the paper left side of the conductor layer 30A corresponding to the selected memory cell MC<m,n> (Figure 19 The write current Icl<m> flows through the conductor layer 30A corresponding to the selected memory cell MC<m,n> from the paper deep side to the paper near side (the -X direction). By the write current Icl<m> flowing through the conductor layer 30A corresponding to the selected memory cell MC<m,n>, a spin orbit torque intended to set the magnetization direction of the ferromagnetic layer 41 corresponding to the selected memory cell MC<m,n> to be antiparallel to the ferromagnetic layer 43 corresponding to the selected memory cell MC<m,n> is generated.

[0193] In addition, as described above, the voltage VSS and Vw are applied to both ends of the selected bit line RBL<n>, respectively. The voltage VSS and k3Vw are applied to both ends of the non-selected bit line RBL<n-1>, respectively. The voltage k4Vw and VSS are applied to both ends of the non-selected bit line RBL<n+1>, respectively. Thus, in the conductor layer 80 corresponding to the selected bit line RBL<n>, the current Iwl<n> flows from the paper deep side to the paper near side (the -Y direction). In the conductor layer 80 corresponding to the non-selected bit line RBL<n-1>, the current Iwl<n-1> flows from the paper deep side to the paper near side (the -Y direction). In the conductor layer 80 corresponding to the non-selected bit line RBL<n+1>, the current Iwl<n+1> flows from the paper near side to the paper deep side (the +Y direction). Figure 19 Figure 19 Figure 19

[0194] By the currents Iwl<n>, Iwl<n-1>, Iwl<n+1>, the magnetic fields Hwl<n>, Hwl<n-1>, and Hwl<n+1> are respectively applied in the vicinity of the interface between the conductor layer 30A corresponding to the selected memory cell MC<m,n> and the ferromagnetic layer 41 corresponding to the selected memory cell MC<m,n>.

[0195] The magnitude and direction of the current Icl and the magnitude and direction of each of the magnetic fields Hwl<n>, Hwl<n-1>, and Hwl<n+1> can be the same as in the case of the first embodiment. Thus, data "1" is written to the selected memory cell MC<m,n>.

[0196] 2.3 Effects of the Second Embodiment

[0197] ​​​According to the second embodiment, when the write operation to the magnetoresistive effect element MTJ <m, n> is performed, the current Ic <m> is applied to the wiring SOTL <m, n>. Also, the currents Iw <n>, Iw <n-1>, and Iw <n+1> are applied to the read bit lines RBL <n>, RBL <n-1>, and RBL <n+1>, respectively, in a manner repeated with the period during which the current Ic <m> is applied. Thereby, the magnetic fields Hw <n>, Hw <n-1>, and Hw <n+1> can be applied in the same direction and with the same magnitude as in the first embodiment, in the vicinity of the interface of the ferromagnetic layer 41 corresponding to the magnetoresistive effect element MTJ <m, n> and the wiring SOTL <m>. Thus, as in the first embodiment, the magnetic field Hw <n> can assist the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC <m, n> caused by the spin-orbit torque. In addition, the magnetic fields Hw <n-1> and Hw <n+1> can improve the stability at the time of the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC <m, n> caused by the spin-orbit torque.

[0198] In addition, in the write operation to the magnetoresistive effect element MTJ <m, n>, no current flows in the wirings SOTL <m, n-1> and SOTL <m, n+1>. Thereby, in the second embodiment, in the write operation to the magnetoresistive effect element MTJ <m, n>, the possibility of erroneous writing of data to the magnetoresistive effect elements MTJ <m, n-1> and MTJ <m, n+1> is low. Thus, the currents Iw <n-1> and Iw <n+1> of the second embodiment can be smaller than the current Iw <n>, or can be larger than it. Thus, the restriction on the write operation can be relaxed.

[0199] 3. Variations

[0200] In addition, the first and second embodiments described above are not limited to the examples described above, and various variations can be applied.

[0201] In the first and second embodiments described above, the case where the current Iw <n-1> is applied to the read bit line RBL <n-1> and the current Iw <n+1> is applied to the read bit line RBL <n+1> in the write operation to the magnetoresistive effect element MTJ <m, n> is described, but is not limited thereto. For example, either one of the currents Iw <n-1> and Iw <n+1> can be applied. In this case, as in the first and second embodiments described above, the stability at the time of the reversal of the magnetization direction of the ferromagnetic layer 41 of the selected memory cell MC <m, n> caused by the spin-orbit torque can be improved.

[0202] In addition, in the first and second embodiments described above, the case where the currents Iw<n-1> and Iw<n+1> are applied in directions opposite to each other has been described, but the present application is not limited to this. For example, if the following condition is satisfied, the currents Iw<n-1> and Iw<n+1> can be applied in directions parallel to each other. The so-called condition includes a case where a resultant magnetic field of the magnetic fields Hw<n-1> and Hw<n+1> has a component in the +Z direction when the magnetization direction of the ferromagnetic layer 41 in the magnetoresistive element MTJ<m,n> is magnetized in the +Z direction, and has a component in the -Z direction when the magnetization direction of the ferromagnetic layer 41 is magnetized in the -Z direction. In this case, as in the first and second embodiments described above, the stability at the time of magnetization direction reversal of the ferromagnetic layer 41 of the selected memory cell MC<m,n> due to the spin-orbit torque can be improved.

[0203] In addition, in the first and second embodiments described above, the case where the magnetoresistive element MTJ has a bottomless structure in which the ferromagnetic layer 41 is disposed below the ferromagnetic layer 43 has been described, but the present application is not limited to this. For example, the magnetoresistive element MTJ can have a topless structure in which the ferromagnetic layer 41 is disposed above the ferromagnetic layer 43. In this case, the conductor layer 30 is disposed above the ferromagnetic layer 41.

[0204] In addition, in the first and second embodiments described above, the case where the ferromagnetic layer 41 is disposed so as to contact the upper surface of the conductor layer 30 has been described, but the present application is not limited to this. The ferromagnetic layer 41 can be disposed above the conductor layer 30 with an intermediate layer interposed therebetween. The intermediate layer can include, for example, a conductive layer of copper (Cu) or the like and an insulating layer of magnesium oxide (MgO) or the like. In a case where the magnetoresistive element MTJ has a bottomless structure, the intermediate layer can function as a base layer of the magnetoresistive element MTJ. In a case where the magnetoresistive element MTJ has a topless structure, the intermediate layer can function as a cover layer of the magnetoresistive element MTJ.

[0205] In addition, in the first and second embodiments described above, the case where a 3-terminal type switching element is applied to the switching elements SEL1, SEL2, and SEL3 has been described, but the present application is not limited to this. For example, a 2-terminal type switching element can be applied to the switching elements SEL1, SEL2, and SEL3.

[0206] The 2-terminal type switching element becomes a "high resistance" state or "off state, for example, an electrically non-conductive state, when the voltage applied between the 2 terminals is lower than the threshold voltage Vth. The 2-terminal type switching element becomes a "low resistance" state or "on state, for example, an electrically conductive state, when the voltage applied between the 2 terminals is equal to or higher than the threshold voltage Vth. The 2-terminal type switching element can switch the current to flow or to be blocked depending on the magnitude of the voltage applied to the corresponding memory cell MC, regardless of the polarity of the voltage applied between the 2 terminals (regardless of the direction of the current to flow).

[0207] Even in the case where the 2-terminal type switching element is applied to the switching elements SEL2 and SEL3, the stability of the write operation can be improved by using the resultant magnetic field of the magnetic fields Hw<n>, Hw<n-1>, and Hw<n+1>, as in the case where the 3-terminal type switching element is applied.

[0208] Although several embodiments of the present application have been described, these embodiments are presented by way of example only, and are not intended to limit the scope of the application. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the application. These embodiments and their variations are included within the scope and spirit of the application, and are included within the scope of the application and its equivalents as recited in the claims.

[0209] [Explanation of Symbols]

[0210] 1... Magnetic memory device

[0211] 10... Memory cell array

[0212] 11... Row selection circuit

[0213] 12... Column selection circuit

[0214] 13... Decoding circuit

[0215] 14... Write circuit

[0216] 15... Readout circuit

[0217] 16... Voltage generation circuit

[0218] 17... Input / output circuit

[0219] 18... Control circuit

[0220] 20, 90... Insulator layer

[0221] 30, 30A, 50, 63, 70, 80... Conductor layer

[0222] 40, 60... Element layer

[0223] 41, 43, 45... ferromagnetic layer

[0224] 42, 44... nonmagnetic layer

[0225] 61... semiconductor film

[0226] 62... insulator film

Claims

1. A magnetic memory device comprising: a first conductor layer extending along a first direction; a second conductor layer extending along the first direction, arranged with the first conductor layer along a second direction intersecting the first direction; a first magnetoresistive effect element electrically connected to the first conductor layer; a second magnetoresistive effect element electrically connected to the second conductor layer; and a third conductor layer extending along the second direction, in contact with the first magnetoresistive effect element; and in a write operation to write data to the first magnetoresistive effect element, a first current is applied to the first conductor layer, a second current is applied to the second conductor layer, a third current is applied to the third conductor layer independently of the first and second currents.

2. The magnetic memory device of claim 1, further comprising: a fourth conductive layer extending along the first direction, arranged along the second direction on the opposite side of the first conductive layer from the second conductive layer; a fourth conductor layer extending along the second direction, in contact with the second magnetoresistive effect element; and a third magnetoresistive effect element connected to the fourth conductor layer; and in the write operation, a fourth current is applied to the fourth conductor layer.

3. The magnetic memory device of claim 2, wherein the second and third magnetoresistive effect elements are adjacent to the first magnetoresistive effect element along the second direction.

4. The magnetic memory device of claim 2, wherein the second current has a direction anti-parallel to a direction of the fourth current.

5. The magnetic memory device of claim 1, wherein a magnetic field applied to the first magnetoresistive effect element based on the first and second currents has a component along the second direction and a component along a third direction intersecting the first and second directions.

6. The magnetic memory device of claim 1, wherein the third conductor layer is further in contact with the second magnetoresistive effect element.

7. The magnetic memory device of claim 1, wherein the second current is less than the first current.

8. The magnetic memory device of claim 1, further comprising a fifth conductor layer extending along the second direction, in contact with the second magnetoresistive effect element.

9. The magnetic memory device of claim 1, wherein the first magnetoresistive effect element comprises: a first ferromagnetic layer in contact with the third conductor layer; a second ferromagnetic layer; and a non-magnetic layer between the first and second ferromagnetic layers.

10. The magnetic memory device of claim 9, wherein by the write operation, a magnetization direction of the first ferromagnetic layer changes from a third direction intersecting the first and second directions to a fourth direction anti-parallel to the third direction; and a magnetic field generated based on the second current has a component anti-parallel to the third direction and parallel to the fourth direction. ​ 11. The magnetic memory device of claim 1, wherein the third electrically conductive layer comprises at least one element selected from the group consisting of tantalum (Ta), tungsten (W), rhenium (Re), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), copper (Cu), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), manganese (Mn), lead (Pb), bismuth (Bi), antimony (Sb), tellurium (Te), selenium (Se), and polonium (Po).

12. The magnetic memory device of claim 1, wherein a first time at which application of the first current is initiated and a second time at which application of the second current is initiated are substantially coincident with a third time at which application of the third current is initiated; and a fourth time at which application of the first current is terminated and a fifth time at which application of the second current is terminated are substantially coincident with a sixth time at which application of the third current is terminated.

13. The magnetic memory device of claim 1, wherein a first time at which application of the first current is initiated and a second time at which application of the second current is initiated are substantially coincident with a third time at which application of the third current is initiated; and a fourth time at which application of the first current is terminated and a fifth time at which application of the second current is terminated are different from a sixth time at which application of the third current is terminated.

14. The magnetic memory device of claim 1, wherein a first time at which application of the first current is initiated and a second time at which application of the second current is initiated are different from a third time at which application of the third current is initiated; and a fourth time at which application of the first current is terminated and a fifth time at which application of the second current is terminated are different from a sixth time at which application of the third current is terminated.

15. The magnetic memory device of claim 1, wherein a first time at which application of the first current is initiated is different from a second time at which application of the second current is initiated; and a fourth time at which application of the first current is terminated is substantially coincident with a fifth time at which application of the second current is terminated.

16. The magnetic memory device of claim 1, wherein a first time at which application of the first current is initiated is different from a second time at which application of the second current is initiated; and a fourth time at which application of the first current is terminated is different from a fifth time at which application of the second current is terminated.

17. The magnetic memory device of claim 1, wherein a first time at which application of the first current is initiated is substantially coincident with a second time at which application of the second current is initiated; and a fourth time at which application of the first current is terminated is different from a fifth time at which application of the second current is terminated.

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