Method for manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device according to an embodiment includes a first film formation step, a second film formation step, and an oxidation step. In the first film formation step, a first coating formed of silicon is formed on the surface of a substrate formed of silicon carbide. In the second film formation step, a second coating film is formed on the surface of the first coating film. In the oxidation step, the first coating film is thermally oxidized from the surface side to form a third coating film. In the second film formation step, the second film is not formed on a portion of the first film and the portion is exposed. Alternatively, in the second film formation step, the film thickness of the second film formed on a part of the first film is smaller than the film thickness of the second film formed on the other part.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a method for manufacturing a semiconductor device.

[0002] This application claims priority from Japanese Patent Application No. 2023-120158 filed on July 24, 2023, the content of which is incorporated herein by reference. BACKGROUND

[0003] In recent years, in the progress of miniaturization of semiconductor devices, a configuration is required in which miniaturization is achieved and voltage resistance is improved by making the insulating film of a portion in a semiconductor device in which insulation breakdown is likely to occur locally thicker. Therefore, a method of forming a locally thick insulating film using a film forming means such as a chemical vapor deposition method (CVD: Chemical Vapor Deposition, hereinafter referred to as CVD) has been proposed, but in this case, there is a problem that impurities are easily mixed into the insulating film.

[0004] PRIOR ART DOCUMENTS

[0005] PATENT DOCUMENTS

[0006] Patent Document 1: Japanese Patent Application Publication No. 2014-56912 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] The present application is to provide a method for manufacturing a semiconductor device capable of forming a locally thick insulating film in which the mixing of impurities is suppressed.

[0009] MEANS FOR SOLVING THE PROBLEMS

[0010] The method for manufacturing a semiconductor device of the embodiment has a first film forming step, a second film forming step, and an oxidation step. In the first film forming step, a first film formed of silicon is formed on a surface of a substrate formed of silicon carbide. In the second film forming step, a second film is formed on a surface of the first film. In the oxidation step, the first film is thermally oxidized from the surface side to form a third film. In the second film forming step, the second film is not formed on a portion of the first film, and the portion is exposed. Alternatively, in the second film forming step, the film thickness of the second film formed on a portion of the first film is smaller than the film thickness of the second film formed on other portions. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a cross-sectional schematic view of a semiconductor device of the first embodiment.

[0012] Figure 2 is a flowchart of a method for manufacturing a semiconductor device of the first embodiment.

[0013] Figure 3 This is a schematic diagram of the base material forming step of the first embodiment.

[0014] Figure 4 This is a schematic diagram of the ion implantation step in the first embodiment.

[0015] Figure 5 This is a schematic diagram of the trench forming step of the first embodiment.

[0016] Figure 6 This is a schematic diagram of the first film forming step in the first embodiment.

[0017] Figure 7 This is a schematic diagram of the inhibitor adsorption step in the second film-forming step of the first embodiment.

[0018] Figure 8 This is a schematic diagram of the precursor adsorption step in the second film-forming step of the first embodiment.

[0019] Figure 9 This is a schematic diagram of the film forming step in the second film forming step of the first embodiment.

[0020] Figure 10 This is a schematic diagram of the first oxidation step in the first embodiment.

[0021] Figure 11 This is a schematic diagram of the etching process in the first embodiment.

[0022] Figure 12 This is a schematic diagram of the second oxidation step in the first embodiment.

[0023] Figure 13 This is a schematic diagram of the electrode forming process of the first embodiment.

[0024] Figure 14 This is a schematic diagram of the interlayer insulating film forming process according to the first embodiment.

[0025] Figure 15 This is a schematic diagram of the first oxidation step of a modification example that can be adopted in the first embodiment.

[0026] Figure 16 This is a schematic diagram of a second film forming step of a modification example that can be adopted in the first embodiment.

[0027] Figure 17 This is a part of a flowchart of a method for manufacturing a semiconductor device according to the second embodiment.

[0028] Figure 18 This is a schematic diagram of the precursor adsorption step in the second film-forming step of the second embodiment.

[0029] Figure 19 is a schematic view of a film formation step in the second film formation step of the second embodiment.

[0030] Figure 20 is a schematic view of the first oxidation step of the second embodiment.

[0031] Figure 21 is a schematic view of the first and second etching steps of the second embodiment.

[0032] Figure 22 is a schematic view of the third etching step of the second embodiment.

[0033] Figure 23 is a schematic view of the third film formation step of the second embodiment.

[0034] Figure 24 is a schematic view of the second oxidation step of the second embodiment. DETAILED DESCRIPTION

[0035] Hereinafter, a manufacturing method of a semiconductor device of an embodiment will be described with reference to the drawings.

[0036] In the present specification, the concepts of "upper" and "lower" are not necessarily terms indicating the relationship with the direction of gravity.

[0037] In the following description, n, n - and p, p - denote the relative levels of impurity concentration in each conductivity type. That is, n - denotes that the impurity concentration of the n-type is relatively lower than n. In addition, p - denotes that the impurity concentration of the p-type is relatively lower than p. Furthermore, n - type is simply denoted as n-type, and p - type is simply denoted as p-type.

[0038] (First Embodiment)

[0039] Figure 1 is a schematic cross-sectional view of a semiconductor device 1 of the first embodiment. The semiconductor device 1 of the present embodiment is a trench-type metal-oxide-semiconductor field-effect transistor (MOSFET: hereinafter referred to as MOSFET).

[0040] The semiconductor device 1 has a substrate 10, an insulating film 30 (gate insulating film), a gate electrode 20, an interlayer insulating film 40, a source electrode 21, a drain electrode 24, a source wiring 22, and a guard electrode 25.

[0041] The base material 10 is formed of silicon carbide (SiC). The silicon carbide constituting the base material 10 preferably has a hexagonal crystal structure, and more preferably has polytype 4H. The base material 10 is formed by epitaxially growing silicon carbide on a single-crystal substrate of silicon carbide. The insulating breakdown electric field of silicon carbide (SiC) is about 10 times larger than that of silicon (Si). Therefore, by using silicon carbide as the base material 10 of the semiconductor device 1, it is possible to maintain the withstand voltage and increase the impurity concentration, and it is possible to constitute a low-resistance, low-loss MOSFET for high power. The base material 10 includes an n - layer 12, a p-type body layer 13, an n-region 14, and a contact region 15.

[0042] n - The n-type layer 12 is formed by adding a donor. The p-type body layer 13 is provided on the n - layer 12. The n-region 14 has an n-type. The n - layer 12 has an n - type. The n-region 14 is provided on the p-type body layer 13. The n-region 14 is separated from the n - layer 12 by the p-type body layer 13. The n-region 14 has a relatively high impurity concentration of the n-type compared to the n - layer 12. The contact region 15 has a p-type. The p-type body layer 13 has a p - type. The contact region 15 is formed on a portion of the p-type body layer 13 in a manner connected to the p-type body layer 13. The contact region 15 has a relatively high impurity concentration of the p-type compared to the p-type body layer 13.

[0043] The base material 10 has a trench 5. The trench 5 is open upward. The inner side surface of the trench 5 includes a bottom surface 5b and a sidewall surface 5a extending upward from the bottom surface 5b. The bottom surface 5b of the trench 5 is disposed at the n - layer 12. The sidewall surface 5a of the trench 5 extends from the upper surface of the n-region 14 to the n - layer 12 through the p-type body layer 13.

[0044] The insulating film 30 covers the inner side surfaces of the trench 5, that is, the side wall surfaces 5a and the bottom surface 5b. The insulating film 30 has a side wall film 31 provided on the side wall surfaces 5a of the trench 5 and a bottom film 32 provided on the bottom surface 5b. The side wall film 31 extends upward from the bottom film 32. The film thickness T2 of the bottom film 32 is larger than the film thickness T1 of the side wall film 31. When the semiconductor device 1 is driven, an electric field is likely to concentrate at a corner portion between the bottom surface 5b and the side wall surface 5a of the trench 5, and the withstand voltage of this portion is likely to become a problem. According to the present embodiment, by relatively thinning the film thickness T1 of the side wall film 31, miniaturization of the semiconductor device 1 can be pursued, and by relatively thickening the film thickness T2 of the bottom film 32, the withstand voltage of the corner portion can be increased to constitute the semiconductor device 1 having excellent insulating properties. The film thickness T2 of the bottom film 32 is, for example, preferably 1 nm or more larger than the film thickness T1 of the side wall film 31 ((T2-T1≥1 nm), more preferably 10 nm or more ((T2-T1≥10 nm).

[0045] The gate electrode 20 is buried in the trench 5. The insulating film 30 is interposed between the gate electrode 20 and the inner side surfaces of the trench 5. That is, the insulating film 30 separates the substrate 10 and the gate electrode 20 within the trench 5. The gate electrode 20 opposes the surface of the p-type body layer 13 through the insulating film 30. The upper surface of the gate electrode 20 and the upper surface of the portion of the insulating film 30 located on the upper surface of the n-region 14 are substantially the same height. The interlayer insulating film 40 is provided in a manner covering the portion of the insulating film 30 extending onto the upper surface of the n-region 14 and the gate electrode 20.

[0046] The source electrode 21 contacts the n-region 14 and the contact region 15 through the interlayer insulating film 40. The source wiring 22 is provided on the source electrode 21 and the interlayer insulating film 40 in a manner contacting the source electrode 21. The drain electrode 24 is provided on the surface of the substrate 10 opposite to the surface on which the trench 5 is provided. The guard electrode 25 covers the drain electrode 24.

[0047] Next, the manufacturing method of the semiconductor device 1 will be described. Figure 2 is a flowchart showing each process of the manufacturing method of the semiconductor device 1 of the present embodiment. The manufacturing method of the semiconductor device 1 of the present embodiment has a substrate forming process S10, an ion implantation process S20, a trench forming process S30, a first film forming process S40, a second film forming process S50, a first oxidation process (oxidation process) S60, an etching process S70, a second oxidation process (oxidation film forming process) S80, a gate electrode forming process S90, an interlayer insulating film forming process S100, a source electrode forming process S110, a source wiring forming process S120, a drain electrode forming process S130, and a guard electrode forming process S140.

[0048] Figure 3is a schematic view of the substrate forming step S10 of the present embodiment. In the substrate forming step S10, for example, an n - layer 12, thereby manufacturing the substrate 10. The single crystal substrate is polished away, for example, in a final process, but the illustration is omitted here.

[0049] Figure 4 is a schematic view of the ion implantation step S20 of the present embodiment. In the ion implantation step S20, the p-type body layer 13, the n region 14, and the contact region 15 are formed. In the ion implantation step S20, in order to form the p-type body layer 13, ion implantation of an acceptor such as aluminum (Al) is performed from the upper surface of the substrate 10. In the ion implantation step S20, next, in order to form the n region 14, ion implantation of a donor such as phosphorus (P) is performed from the upper surface of the substrate 10. Thereby, the n region 14 having a concentration higher than that of the p-type body layer 13 is formed in the n region 14. - layer 12, the p-type body layer 13, and the n region 14 of the substrate 10. In the ion implantation step S20, next, in order to form the contact region 15, ion implantation of an acceptor such as aluminum is performed. In the manufacturing method of the present embodiment, the p-type body layer 13 and the n region 14 can also be formed using epitaxial growth accompanied by addition of impurities instead of the ion implantation step S20.

[0050] Next, activation heat treatment for activating the impurities added by the ion implantation is performed. The temperature of the heat treatment is preferably 1500°C or higher and 1900°C or lower, for example, around 1700°C. The time of the heat treatment is, for example, around 30 minutes. The atmosphere of the heat treatment is preferably a non-active gas atmosphere, for example, an argon (Ar) atmosphere.

[0051] Figure 5 is a schematic view of the trench forming step S30 of the present embodiment. The trench forming step S30 forms a trench 5 in the substrate 10 formed of silicon carbide. In the trench forming step S30, first, a mask 91 having an opening portion 91a that partially exposes the n region 14 is formed on the substrate 10. The opening portion 91a of the mask 91 is formed in correspondence with the position of the trench 5. In the opening 91a of the mask 91, a portion of the n region 14, the p-type body layer 13, and the n - layer 12 is removed by etching. Thereby, the trench 5 is formed in the substrate 10. After the trench 5 is formed, the mask 91 is removed.

[0052] Figure 6 is a schematic view of the first film forming step S40 of the present embodiment. The first film forming step S40 is a step of forming a silicon film (first film) 50 on the inner side surface of the trench 5. The silicon film 50 is formed of silicon. In the first film forming step S40, the silicon film 50 is formed, for example, by a reduced pressure CVD method (LP-CVD).

[0053] Figures 7-9 is a schematic view of each process of the second film forming process S50 of the present embodiment. The second film forming process S50 of the present embodiment has an inhibitor adsorption process S51 ( Figure 7 ), a precursor adsorption process S52 ( Figure 8 ), and a film formation process S53 ( Figure 9 ). The second film forming process S50 is a process of forming a barrier film (second film) 60 on a part of the silicon film 50 provided on the inner side surface of the trench 5 by an atomic layer deposition method (ALD: Atomic Layer Deposition, hereinafter referred to as ALD). In the following description, a region in the silicon film 50 provided on the side wall surface 5a of the trench 5 is referred to as a side wall film 51, and a region provided on the bottom surface 5b of the trench 5 is referred to as a bottom film 52. In the second film forming process S50 of the present embodiment, the barrier film 60 is formed only on the bottom film 52. In the present embodiment, the barrier film 60 is formed of silicon oxide (SiO2). However, the material of the barrier film 60 is not limited to the present embodiment.

[0054] Figure 7 is a schematic view of the inhibitor adsorption process S51 of the present embodiment. The inhibitor adsorption process S51 is a process of adsorbing a factor (hereinafter referred to as inhibitor 71) that hinders adsorption of a precursor 72 (refer to Figure 8 ) described later on the side wall film 51. In the manufacturing method of the semiconductor device 1 of the present embodiment, as the inhibitor 71, for example, surface capping using SAMs (Self-Assembled Monolayers), SIMs (small molecule inhibitors), nitrogen atoms (N), and hydrogen atoms (H) can be exemplified. In the inhibitor adsorption process S51, the inhibitor 71 is formed on the silicon film 50 by CVD. More specifically, a gas containing the inhibitor 71 is introduced into a processing chamber. After the inhibitor 71 is adsorbed, the gas containing the inhibitor 71 is exhausted from the processing chamber.

[0055] In the inhibitor adsorption process S51 of the present embodiment, the pressure of the gas containing the inhibitor 71 and the introduction time of the gas are controlled so that the inhibitor 71 does not reach the innermost part of the inner side surface of the trench 5. Therefore, the inhibitor 71 is adsorbed on a region of the upper part of the side wall film 51 in the inner side surface of the trench 5, and is not adsorbed on a region of the lower part of the side wall film 51 and the bottom film 52.

[0056] Figure 8is a schematic view of the precursor adsorption process S52 of the present embodiment. In the precursor adsorption process S52, a gas containing a precursor 72 is introduced into the processing chamber. In the manufacturing method of the semiconductor device 1 of the present embodiment, as the precursor 72, for example, TDMAS, Orthrus, 3DMAS, SAM24 can be exemplified. The precursor 72 is not adsorbed to the portion of the surface of the silicon film 50 to which the inhibitor 71 is adsorbed. Therefore, the precursor 72 is selectively adsorbed to the region of the lower portion of the side wall film 51 and the bottom film 52 in the inner side surface of the trench 5. After the precursor 72 is adsorbed, the gas containing the precursor 72 is exhausted from the processing chamber. Further, plasma can be generated at the time of adsorbing the precursor 72.

[0057] Figure 9 is a schematic view of the film formation process S53 of the present embodiment. In the film formation process S53, a reaction gas containing a reactant that becomes the basis of the barrier film 60 is introduced into the processing chamber. In the manufacturing method of the semiconductor device 1 of the present embodiment, in the film formation process S53, by causing O3, a radical (for example, O radical) in plasma, or the like to react with the adsorbed molecule (precursor), SiO2 is formed. The reaction gas reacts with the atoms of the precursor 72 only at the position where the precursor 72 is adsorbed, and the barrier film 60 composed of silicon oxide (SiO2) is formed. Therefore, the barrier film 60 is formed only in the region of the lower portion of the side wall film 51 and the bottom film 52. After the barrier film 60 is formed, the reaction gas is exhausted from the processing chamber.

[0058] By the above-described second film formation process S50, the barrier film 60 is formed only in the region of the lower portion of the side wall film 51 and the bottom film 52. That is, in the second film formation process, a part (the bottom film 52) of the silicon film 50 provided to the inner side surface of the trench 5 is covered with the barrier film 60, and the other part (the side wall film 51) of the silicon film 50 is exposed from the barrier film 60. Therefore, the film in which the silicon film 50 and the barrier film 60 are combined is partially thickened in the portion where the barrier film 60 is formed. In the present embodiment, the barrier film 60 is provided to a film thickness TA. In the case where ALD is adopted as the second film formation process S50, in view of the film formation speed of ALD, from the viewpoint of productivity, the film thickness TA of the barrier film 60 is preferably, for example, 300 nm or less.

[0059] According to the present embodiment, ALD is adopted in the second film forming process S50. In ALD, since it is possible to form atomic layers one by one, it is possible to reduce the mixing of impurities and form the barrier film 60 with a stoichiometric composition. Therefore, by adopting ALD as the second film forming process S50, it is possible to selectively form a barrier film 60 having a film thickness that is uniformly and highly precisely controlled on a portion of the inner side surface of the trench 5. In addition, when ALD is adopted in the second film forming process S50, it is possible to partially limit the film formation on the sidewall film 51 using an inhibitor or the like, so that a portion of the silicon film 50 (the sidewall film 51) can be exposed. In addition, in the present embodiment, a case where the barrier film 60 is not formed on the sidewall film 51 in the second film forming process S50 is described. However, as in the modified example ( Figure 16 ), a thin film barrier film 60A may be formed on the sidewall film 51. In this case, the thickness of the barrier film 60A formed on the sidewall film 51 only needs to be smaller than the thickness of the barrier film 60A formed on the bottom film 52.

[0060] Figure 10 This is a schematic diagram of the first oxidation step S60 of this embodiment. The first oxidation step S60 is a step in which the silicon film 50 is thermally oxidized from the surface side to form a first oxide film 80 composed of silicon oxide (SiO2). In the first oxidation step S60, the temperature, time, oxygen concentration, etc. are adjusted to thermally oxidize only a portion of the surface side of the silicon film 50 to form the first oxide film (third film) 80. This thermal oxidation is performed at a temperature at which silicon is thermally oxidized but silicon carbide is substantially not thermally oxidized.

[0061] In the following description, the portion of the first oxide film 80 formed on the sidewall film 51 is referred to as the first portion 80a, and the portion formed on the bottom film 52 is referred to as the second portion 80b. By undergoing the first oxidation step S60, the first portion 80a having a film thickness T3 is formed on the surface of the sidewall film 51. Furthermore, the second portion 80b having a film thickness T4 is formed on the interface side of the bottom film 52 with the barrier film 60. Furthermore, since thermal oxidation of the bottom film 52 proceeds below the first oxide film 80, it proceeds slightly more slowly than thermal oxidation of the sidewall film 51. Therefore, the film thickness T4 of the second portion 80b of the first oxide film 80 is slightly smaller than the film thickness T3 of the first portion 80a.

[0062] By the first oxidation process S60, a film of silicon oxide (SiO2) is formed on the side wall film 51 from only the first oxidation film 80 (first portion 80a) of film thickness T3. On the other hand, on the bottom film 52 after the first oxidation process S60, a laminated film is formed in which the barrier film 60 of film thickness TA and the first oxidation film 80 (second portion 80b) of film thickness T4 are laminated. Here, the sum of the film thicknesses of the barrier film 60 and the first oxidation film 80 on the bottom film 52 (TA+T4) is greater than the film thickness T3 of the first oxidation film 80 on the side wall film 51 (TA+T4>T3). Therefore, the film thickness (TA+T4) of the portion of the oxidation film on the silicon film 50 that is formed on the bottom surface 5b of the trench 5 is greater than the film thickness T3 of the portion that is formed on the side wall surface 5a.

[0063] Figure 11 is a schematic view of the etching process S70 of the present embodiment. The etching process S70 is a process of etching and removing a portion of the barrier film 60 and the first oxidation film 80. The etching process S70 can be performed, for example, by various means such as wet etching using hydrofluoric acid, chemical dry etching, reactive ion etching (RIE), and the like.

[0064] The etching process S70 of the present embodiment removes a prescribed film thickness from the surface side in the oxidation film formed on the surface of the substrate 10. The film thickness TB removed in the etching process S70 is greater than the film thickness T3 of the first portion 80a shown in FIG. 8, and is less than the sum of the film thicknesses of the barrier film 60 and the second portion 80b (TA+T4) (T3<TB<TA+T4). Therefore, on the inner side surface of the trench 5 after the etching process S70, only the second portion 80b of the first oxidation film 80 that is located on the bottom surface 5b remains, and the first portion 80a on the side wall surface 5a is removed. Figure 10

[0065] In addition, the film thickness TB removed in the etching process S70 is preferably greater than the film thickness TA of the barrier film 60 (TB>TA). By this, it is possible to inhibit the oxidation film from the barrier film 60 from remaining on the bottom surface 5b, it is possible to leave only the oxidation film formed by thermal oxidation, and it is possible to improve the uniformity of the crystallization of the insulating film 30. Note that the barrier film 60 does not necessarily need to be completely removed, and can remain.

[0066] Figure 12 ​is a schematic view of the second oxidation step S80 of the present embodiment. The second oxidation step S80 is a step of thermally oxidizing the entire silicon film 50 remaining after the first oxidation step S60 and the etching step S70 to form the insulating film 30. That is, the second oxidation step S80 is a step of forming the insulating film (fourth film) 30 formed of silicon oxide on the inner side surface of the trench 5. This thermal oxidation is performed at a temperature at which silicon is thermally oxidized and silicon carbide is not substantially thermally oxidized.

[0067] By passing through the second oxidation step S80, the side wall film 51 and the bottom film 52 of the silicon film 50 are oxidized, and a second oxidation film 59 from the silicon film 50 is formed on the inner side surface of the trench 5. The second oxidation film 59 from the silicon film 50 and the first oxidation film 80 formed on the second oxidation film 59 combine to constitute the insulating film 30 on the inner side surface of the trench 5. As described above, the first oxidation film 80 remains only on the bottom surface 5b of the trench 5, and thus the bottom film 32 of the insulating film 30 is constituted by the second oxidation film 59 from the silicon film 50 and the first oxidation film 80. On the other hand, the side wall film 31 of the insulating film 30 is constituted only by the second oxidation film 59 from the silicon film 50. Therefore, the film thickness T2 of the bottom film 32 of the insulating film 30 is greater than the film thickness T1 of the side wall film 31.

[0068] Figure 13 is a schematic view of the gate electrode formation step S90 of the present embodiment. In the gate electrode formation step S90, the gate electrode 20 is formed inside the trench 5 and on the insulating film 30. The method of forming the gate electrode 20 can be performed by, for example, film formation of a conductor or doped polysilicon and CMP (Chemical Mechanical Polishing).

[0069] Figure 14 is a schematic view of the interlayer insulating film formation step S100 of the present embodiment. In the interlayer insulating film formation step S100, the interlayer insulating film 40 is formed on the gate electrode 20 and the insulating film 30 in a manner of covering the exposed surface of the gate electrode 20.

[0070] Next, although specific illustrations are omitted, a source electrode formation step, a source wiring formation step, a drain electrode formation step, and a guard electrode formation step are performed, as shown in Figure 1 The source electrode 21, the source wiring 22, the drain electrode 24, and the guard electrode 25 are sequentially formed. Further, the source electrode 21 is formed after the interlayer insulating film 40 and the insulating film 30 are etched to form an opening portion, and the n region 14 and the contact region 15 are exposed.

[0071] By passing through the above steps, the semiconductor device 1 having the insulating film 30 in which the film thickness T2 on the bottom surface 5b of the trench is greater than the film thickness T1 on the side wall surface 5a can be manufactured.

[0072] Next, a first modification that can be employed in the present embodiment will be described.

[0073] In the manufacturing method of the semiconductor device 1 of the present embodiment, only a part of the silicon film 50 is oxidized from the surface side in the first oxidation step S60, and the oxidized part is removed in the etching step S70 of the subsequent step. However, in the first oxidation step S60, the entire silicon film 50 can also be oxidized and directly used as a part of the insulating film 30. Figure 15 is a schematic view of the first oxidation step S60 of the first modification that can be employed in the present embodiment. In the first oxidation step S60 of the present modification, the entire silicon film 50 is thermally oxidized to form a first oxidized film 80A. Further, the film composed of the barrier film 60 and the first oxidized film 80A is provided as the insulating film 30A of the present modification. The insulating film 30A of the present modification is provided with only the first oxidized film 80A on the side wall surface 5a of the trench, and, in contrast, is provided with the barrier film 60 in addition to the first oxidized film 80A on the bottom surface 5b. Therefore, the insulating film 30A can make the film thickness T5b on the bottom surface 5b greater than the film thickness T5a on the side wall surface 5a. After the first oxidation step S60 of the present modification is performed, the etching step S70 and the second oxidation step S80 are not performed, and the steps after the gate electrode formation step S90 are performed in accordance with the above-described procedure. That is, according to the present modification, a part of the process for forming the insulating film 30A can be omitted, and the manufacturing process of the semiconductor device 1 can be simplified. Further, in the above-described embodiment, the barrier film 60 is removed in the etching step S70, and the thickness of the insulating film 30 is ensured by thermal oxidation. Thus, in the above-described embodiment, only the oxidized film formed by thermal oxidation is used as the insulating film 30, and the uniformity of the crystal of the insulating film 30 is improved.

[0074] Further, a second modification that can be employed in the present embodiment will be described.

[0075] Further, in the present embodiment, a case in which only the silicon film 50 that is not oxidized in the first oxidation step S60 Figure 10 is used as the insulating film 30 by being thermally oxidized in the second oxidation step S80 Figure 12 . However, a new film formed of silicon can also be formed on the silicon film 50 and the first oxidized film 80 after the etching step S70 Figure 11 . In this case, the new silicon film is thermally oxidized together with the silicon film 50 in the second oxidation step S80, and constitutes the insulating film 30 together with the first oxidized film 80 remaining after the etching step S70 Figure 11 . In this case, an insulating film 30 thicker than that of the present embodiment can be formed.

[0076] Next, a third modification example that can be adopted in this embodiment will be described.

[0077] In this embodiment, the case where ALD is used in the second film forming step S50 is described. However, as a modification example of the second film forming step S50, a case where CVD is used is also conceivable. Figure 16 : This is a schematic diagram showing the second film forming step S50 of a modified example. Examples of CVD that can be used as the second film forming step S50 of this modified example include HDPCVD (high density plasma Chemical Vapor Deposition), SACVD (Selective Area Chemical Vapor Deposition), and PECVD (Plasma-Enhanced Chemical Vapor Deposition). The barrier film 60A of this modified example is formed not only on the bottom surface 5b of the trench 5, but also on the sidewall surface 5a. However, the film thickness TCa of the barrier film 60A on the sidewall surface 5a is smaller than the film thickness TCb on the bottom surface 5b. That is, in the second film forming step S50, the film thickness TCa of the barrier film 60A formed on a portion of the silicon film 50 (the sidewall film 51) is smaller than the film thickness TCb of the barrier film 60A formed on the other portion (the bottom film 52). In this modification, similarly to the above-described embodiment, the entire barrier film 60A is removed in an etching step S70 after the silicon film 50 is thermally oxidized in a first oxidation step S60 to form a first oxide film 80. Similar to the above-described embodiment, in the etching step S70, the first oxide film 80 can remain on the bottom surface 5 b due to the difference in the film thickness of the barrier film 60A.

[0078] The respective configurations of the first embodiment will be summarized.

[0079] The method for manufacturing the semiconductor device 1 of this embodiment includes a first film forming step S40, a second film forming step S50, and a first oxidation step (oxidation step) S60. The first film forming step S40 is a step of forming a silicon film 50 made of silicon (Si) on the surface of a substrate 10 made of silicon carbide (SiC). The second film forming step S50 is a step of forming a barrier film 60 on a portion of the surface of the silicon film 50. The first oxidation step S60 is a step of thermally oxidizing the silicon film 50 from the surface side to form a first oxide film 80. In the second film forming step S50, the barrier film 60 is not formed on a portion of the silicon film 50 and the portion is exposed, or the thickness of the barrier film 60 formed on a portion of the silicon film 50 is smaller than the thickness of the barrier film 60 formed on other portions.

[0080] According to the above configuration, after the first oxidation process S60 is performed, the thickness of the composite film of the barrier film 60 and the first oxidation film 80 can be locally varied on the surface of the substrate 10. In the above embodiment, by etching the composite film (in the etching process S70), a portion of the first oxidation film 80 is left to form the locally thick insulating film 30. In addition, in the above modification (refer to Figure 15 ), the composite film is directly used as the insulating film 30A to form the locally thick insulating film 30A in which the barrier film 60 and the first oxidation film 80 are stacked. In this way, according to the above configuration, by selectively adjusting the thickness of the barrier film 60, the insulating film 30, 30A whose arrangement and thickness are freely adjusted can be formed. As a result, only the insulating film 30, 30A of the portion in which the insulating properties need to be improved is formed thick, and a semiconductor device 1 that is small and excellent in voltage resistance can be manufactured. According to the above configuration, as the insulating film 30A, an oxidation film formed by thermally oxidizing a film formed of silicon, or an oxidation film formed by ALD can be used to configure the insulating film 30. That is, according to the above configuration, a film formed by CVD is not used as the insulating film 30, 30A. Therefore, compared to the case where the insulating film is formed by CVD, the locally thick insulating film 30, 30A in which the mixing of impurities is suppressed can be formed.

[0081] Further, in the above configuration, the first oxidation process S60 can be a process in which only a portion of the silicon film 50 is thermally oxidized to form the first oxidation film 80 (refer to Figure 10 ), or can be a process in which the entire silicon film 50 is thermally oxidized to form the first oxidation film 80A (refer to Figure 15 ).

[0082] The manufacturing method of the semiconductor device 1 of the present embodiment has an etching process S70 and a second oxidation process (oxidation film forming process) S80. The etching process S70 is a process in which at least a portion of the barrier film 60 and the first oxidation film 80 is etched. The second oxidation process S80 is a process in which an insulating film (fourth film) 30 formed of silicon oxide (SiO2) is formed on the surface of the substrate 10.

[0083] According to the above configuration, the barrier film 60 can be removed by etching in the etching process S70, and then the insulating film 30 can be formed in the second oxidation process S80. Therefore, no film from the barrier film 60 is left in the insulating film 30, and the insulating film 30 can be formed only by thermal oxidation, and the uniformity of the crystallization of the insulating film 30 can be improved.

[0084] The manufacturing method of the semiconductor device 1 of the present embodiment has the trench formation step S30 of forming the trench 5 on the substrate 10 before the first film formation step S40. The portion of the above-mentioned silicon film 50 in which the barrier film 60 is not formed (or only a thin barrier film is formed) is a portion in which the film is formed on the side wall surface 5a of the trench 5. In addition, the other portion of the above-mentioned silicon film 50 in which the barrier film 60 is formed is a portion formed on the bottom surface 5b of the trench 5. According to this configuration, it is possible to form the barrier film 60 only on the bottom surface 5b of the trench 5, or to make the barrier film 60 on the bottom surface 5b thicker than the barrier film 60 on the side wall surface 5a. Thereby, for example, in the insulating film 30, 30A, it is possible to make the insulating property of the bottom film 32 higher than that of the portion in which a thin film is formed (the side wall film 31). In the case where the semiconductor device 1 is a trench type MOSFET, the electric field is easily concentrated around the corner portion of the bottom surface 5b of the trench 5, and the insulating breakdown is easily generated. As shown in the present embodiment, by making the bottom film 32 of the insulating film 30 thicker than the other portion, it is possible to improve the insulating property of the trench type MOSFET.

[0085] In the manufacturing method of the semiconductor device 1 of the present embodiment, the barrier film 60 is silicon oxide (SiO2). According to this configuration, the barrier film 60 and the first oxidation film 80 are both composed of silicon oxide. Therefore, the oxygen diffusion coefficient of the barrier film 60 and the first oxidation film 80 is substantially the same, and in the first oxidation step S60, it is possible to form the oxidation film of a sufficient thickness on the lower side of the barrier film 60. In addition, in the case where the etching step S70 is performed, it is possible to etch the barrier film 60 and the first oxidation film 80 at the same time, and it is possible to seek the simplification of the manufacturing process.

[0086] (Second Embodiment)

[0087] Figure 17 is a flowchart showing a part of the manufacturing method of the semiconductor device 1 of the second embodiment. In addition, in the explanation of each of the embodiments explained below, the same reference numerals are attached to the configuration elements of the same mode as that of the already explained embodiments, and the explanation thereof is omitted.

[0088] As shown in Figure 17 , the second embodiment has the second film formation step S150, the first oxidation step S160, the etching step S170, and the oxidation film formation step S180. In addition, in the manufacturing method of the second embodiment, the explanation of the configuration common to the manufacturing method of the first embodiment is omitted. That is, in the second embodiment, the explanation of the substrate formation step S10, the ion implantation step S20, the trench formation step S30, and the first film formation step S40 performed before each of the steps shown in Figure 17 is omitted. In addition, in the second embodiment, the explanation of the second film formation step S150, the first oxidation step S160, the etching step S170, and the oxidation film formation step S180 is omitted. Figure 17The gate electrode formation process S90, the interlayer insulating film formation process S100, the source electrode formation process S110, the source wiring formation process S120, the drain electrode formation process S130, and the guard electrode formation process S140, which are performed after each of the processes shown, are omitted from the description.

[0089] The second film formation process S150 of the present embodiment has a precursor adsorption process S151 and a film formation process S152. The second film formation process S150 is a process of forming a barrier film (second film) 160 on a portion of the silicon film 50 provided on the inner side surface of the trench 5 by ALD. In the present embodiment, the barrier film 160 is silicon nitride (SiN).

[0090] Figure 18 is a schematic view of the precursor adsorption process S151 of the present embodiment. In the precursor adsorption process S151, a gas containing the precursor 172 is introduced into the processing chamber. As the precursor 172 of the present embodiment, for example, chlorosilane, organosilane, and heterosilane can be exemplified. In addition, the gas containing the precursor 172 is exhausted from the processing chamber before reaching the bottom surface 5b of the trench 5 sufficiently. Thus, in the precursor adsorption process S151 of the present embodiment, the precursor 172 is adsorbed to the side wall film 51 in the inner side surface of the trench 5 and is not adsorbed to the bottom film 52 and the side wall film 51 near the bottom film 52.

[0091] Figure 19 is a schematic view of the film formation process S152 of the present embodiment. In the film formation process S152, a reaction gas containing a reactant that becomes the basis of the barrier film 160 is introduced into the processing chamber. As the reaction gas, for example, NH3plasma or the like can be exemplified. The reaction gas reacts with the atoms of the precursor 172 only at the position where the precursor 172 is adsorbed and forms the barrier film 160. Thus, the barrier film 160 is formed only in the region of the upper portion of the side wall film 51 within the trench 5. After the barrier film 160 is formed, the reaction gas is exhausted from the processing chamber.

[0092] By the second film formation process S150 described above, the barrier film 160 formed of silicon nitride (SiN) is formed only in the region of the upper portion of the side wall film 51 within the trench 5. That is, in the second film formation process S150, the barrier film 160 is not formed on a portion (bottom film 52) of the silicon film 50, and the portion is exposed.

[0093] Further, as a modification of the second film forming step S150, after the barrier film 160 is formed in the entire inner side surface of the trench 5 including the bottom surface 5b with a uniform film thickness by ALD, only the barrier film 160 on the bottom film 52 can be removed by reactive ion etching (RIE). In this case, in the precursor adsorption step, the precursor is adsorbed to the entire inner side surface of the trench 5. Thereby, in the film forming step, the barrier film is formed in the entire inner side surface of the trench 5.

[0094] Figure 20 is a schematic view of the first oxidation step S160 of the present embodiment. The first oxidation step S160 is a step of thermally oxidizing the silicon film 50 from the surface side to form a first oxidation film (third film) 180. The silicon nitride (SiN) constituting the barrier film 160 has a smaller oxygen diffusion coefficient than silicon oxide (SiO2). Therefore, in the first oxidation step S160, the thermal oxidation is slowed down on the lower side of the barrier film 160. Therefore, in the first oxidation step S160, the film thickness T6 of a first portion 180a of the first oxidation film 180 formed on the lower side of the barrier film 160 is smaller than the film thickness T7 of a second portion 180b exposed from the barrier film 160. In the present embodiment, only a portion of the silicon film 50 on the lower side of the barrier film 60 becomes the first oxidation film 180 at the boundary side of the barrier film 60. On the other hand, the entire thickness direction of the silicon film 50 exposed from the barrier film 160 is oxidized to become the first oxidation film 180.

[0095] Further, in the present embodiment, a case where silicon nitride is used as the barrier film 160 is described, but as long as the barrier film 160 has a smaller oxygen diffusion coefficient than silicon oxide, the same first oxidation film 180 can be formed.

[0096] Figure 21 and Figure 22 is a schematic view of the etching step S170 of the present embodiment. The etching step S170 of the present embodiment has a first etching step S171 and a second etching step S172 as shown in Figure 21 , and a third etching step S173 as shown in Figure 22 . As shown in Figure 21 , the first etching step S171 and the second etching step S172 are steps of etching and removing a portion of the barrier film 160 and the first oxidation film 180. Also, as shown in Figure 22 , the third etching step S173 is a step of etching and removing the silicon film 50. That is, in the etching step S170 of the present embodiment, the etching of the barrier film 160 formed of silicon nitride, the etching of the first oxidation film 180 formed of silicon oxide, and the etching of the silicon film 50 formed of silicon are sequentially performed.

[0097] As Figure 21 shown, in the first etching step S171, the entire barrier film 160 is removed. In addition, in the second etching step S172, only the film thickness T6 of the first portion 180a of the first oxide film 180 is etched. Thus, after the second etching step S172, on the inner side surface of the trench 5, only the first oxide film 180 remains on the lower region of the side wall surface 5a and the bottom surface 5b, and only the silicon film 50 remains on the upper region of the side wall surface 5a. As Figure 22 shown, in the third etching step S173, the silicon film 50 is entirely removed. Only the first oxide film 180 remains in the trench 5 after the etching step S170.

[0098] Figure 23 and Figure 24 is a schematic view of the oxide film forming step S180. The oxide film forming step S180 is a step of forming an insulating film (fourth film) 130 formed of silicon oxide (SiO2) on the surface of the substrate 10. The oxide film forming step S180 of the present embodiment has Figure 23 a third film forming step S181 shown in Figure 24 and a second oxidation step S182 shown in

[0099] As Figure 23 shown, the third film forming step S181 is a step of forming a silicon film 155 having a uniform film thickness formed of silicon (Si) on the surface of the substrate 10. In the third film forming step S181, the silicon film 155 is formed, for example, by a reduced pressure CVD method (LP-CVD).

[0100] As Figure 24 shown, the second oxidation step S182 is a step of thermally oxidizing the silicon film 155 formed in the third film forming step S181 to form a second oxide film 159. The second oxidation step S182 is performed at a temperature at which silicon is thermally oxidized and silicon carbide is not substantially thermally oxidized. By passing through the second oxidation step S182, the first oxide film 180 and the second oxide film 159 from the silicon film 155 are arranged on the inner side surface of the trench 5. The first oxide film 180 and the second oxide film 159 constitute the insulating film 130. As described above, the first oxide film 180 remains only on the bottom surface 5b of the trench 5 and the side wall surface 5a in the vicinity of the bottom surface 5b. Thus, on the inner side surface after the oxide film forming step S180, the insulating film 130 is formed to be locally thick on the bottom surface 5b and the lower region of the side wall surface 5a.

[0101] According to the manufacturing method of the semiconductor device 1 of the present embodiment, the insulating film 130 having a locally thick portion can be formed on the inner side surface of the trench 5. Thus, the insulating property of the portion formed thick can be made higher than that of the portion formed thin, and a semiconductor device 1 small in size and excellent in voltage resistance can be manufactured. Further, according to the present embodiment, the insulating film 130 having a locally thick portion in which the mixing of impurities is suppressed can be formed, without using a film formed by CVD as the insulating film 130, as compared with the case where the insulating film is formed by CVD.

[0102] Further, in the manufacturing method of the semiconductor device 1 of the present embodiment, as shown in FIG. 6, the barrier film 160 is provided only to the upper region of the side wall film 51 in the second film forming step S150, and is not provided to the lower region. Thus, as shown in FIG. 7, the insulating film 130 finally formed becomes stepped on the side wall surface 5a of the trench 5, and thus the insulating property of the corner portion of the trench 5 is further improved. However, in the second film forming step S150, the barrier film 160 can be provided to the entire side wall film 51, and thus the insulating film 30 having a uniform film thickness can be formed on the side wall surface 5a. Figure 20 Figure 24 Further, in the manufacturing method of the semiconductor device 1 of the present embodiment, as shown in FIG. 6, the barrier film 160 is provided only to the upper region of the side wall film 51 in the second film forming step S150, and is not provided to the lower region. Thus, as shown in FIG. 7, the insulating film 130 finally formed becomes stepped on the side wall surface 5a of the trench 5, and thus the insulating property of the corner portion of the trench 5 is further improved. However, in the second film forming step S150, the barrier film 160 can be provided to the entire side wall film 51, and thus the insulating film 30 having a uniform film thickness can be formed on the side wall surface 5a.

[0103] The respective configurations of the second embodiment are summarized.

[0104] According to the manufacturing method of the semiconductor device 1 of the present embodiment, in the second film forming step S150, the silicon film 50 provided to the side wall surface 5a of the trench 5 (i.e., the side wall film 51) is covered with the barrier film 160, and the silicon film 50 provided to the bottom surface 5b of the trench 5 (i.e., the bottom film 52) is exposed from the barrier film 160. According to this configuration, the barrier film 160 can be formed on the side wall surface 5a of the trench 5, and as a film in which the silicon film 50 and the barrier film 160 are combined, a locally thick portion can be formed on the side wall surface 5a of the trench 5.

[0105] In the manufacturing method of the semiconductor device 1 of the present embodiment, as in the first embodiment (see Figure 2 ), the trench forming step S30 of forming the trench 5 on the substrate 10 is performed before the first film forming step S40. As shown in FIG. 8, a portion of the silicon film 50 in which the barrier film 160 is not formed (or only a thin barrier film is formed) is a portion formed on the bottom surface 5b of the trench 5. Other portions of the silicon film 50 in which the barrier film 160 is formed are portions formed on the side wall surface 5a of the trench 5. In this way, the region in which the barrier film 160 is formed can be selected so as to locally thicken the film thickness of the insulating film 130. Figure 19

[0106] In the manufacturing method of the semiconductor device 1 of the present embodiment, the barrier film 160 has a smaller oxygen diffusion coefficient than silicon oxide. According to this configuration, as shown in FIG. 9, the barrier film 160 can be formed on the side wall surface 5a of the trench 5, and as a film in which the silicon film 50 and the barrier film 160 are combined, a locally thick portion can be formed on the side wall surface 5a of the trench 5.​​Figure 20 As shown, in the first oxidation step S160, the first oxidation film 180 can be thinned on the lower side of the barrier film 160, and the first oxidation film 180 can be formed thicker on the portion exposed from the barrier film 160.

[0107] Further, in each of the above embodiments and the modified examples thereof, the case where the film thickness of the insulating film 30, 30A, 130 on the bottom surface 5b inside the trench 5 is locally made thicker than other portions is described. However, by using the same method, the insulating film near the opening of the trench 5 can also be locally made thicker. Furthermore, in a configuration not having the trench 5, a locally thicker insulating film can also be formed.

[0108] In addition, each of the above embodiments and the modified examples thereof can be combined with each other. As an example, the barrier film of the material (silicon nitride) described in the second embodiment can be provided at the position of the barrier film described in the first embodiment. In addition, likewise, the barrier film of the material (silicon oxide) described in the first embodiment can be provided at the position of the barrier film described in the second embodiment. In these cases, for example, an insulating film in which the thickness of the bottom portion and the side wall portion is reversed can be formed.

[0109] According to at least one embodiment described above, by the barrier film 60, 60A, 160, a film having a film thickness different from that of the surface of the substrate 10 can be formed, and a locally thicker insulating film 30, 30A in which the mixing of impurities is suppressed can be formed.

[0110] The present application includes the following modes.

[0111] (Mode 1)

[0112] A method of manufacturing a semiconductor device, including the steps of:

[0113] a first film forming step of forming a first film formed of silicon on a surface of a substrate formed of silicon carbide;

[0114] a second film forming step of forming a second film on a surface of the first film; and

[0115] an oxidation step of thermally oxidizing the first film from the surface side to form a third film;

[0116] In the second film forming step, the second film is not formed on a portion of the first film and the portion is exposed, or the film thickness of the second film formed on the portion of the first film is smaller than the film thickness of the second film formed on other portions.

[0117] (Mode 2)

[0118] The method for manufacturing a semiconductor device according to the supplementary note 1, having the following steps:

[0119] an etching step of etching at least a part of the second coating film and the third coating film; and

[0120] an oxidation coating film forming step of forming a fourth coating film of silicon oxide on the surface of the substrate.

[0121] (Supplementary Note 3)

[0122] The method for manufacturing a semiconductor device according to the supplementary note 1 or 2, wherein

[0123] the first film forming step, a trench forming step of forming a trench on the substrate before the first film forming step,

[0124] the part of the first coating film is a part of the first coating film formed on a side wall surface of the trench,

[0125] the other part of the first coating film is a part of the first coating film formed on a bottom surface of the trench.

[0126] (Supplementary Note 4)

[0127] The method for manufacturing a semiconductor device according to the supplementary note 1 or 2, wherein

[0128] the first film forming step, a trench forming step of forming a trench on the substrate before the first film forming step,

[0129] the part of the first coating film is a part of the first coating film formed on a bottom surface of the trench, and the other part of the first coating film is a part of the first coating film formed on a side wall surface of the trench.

[0130] (Supplementary Note 5)

[0131] The method for manufacturing a semiconductor device according to any one of the supplementary notes 1 to 4, wherein the second film forming step is a step of forming the second coating film by an atomic layer deposition method.

[0132] (Supplementary Note 6)

[0133] The method for manufacturing a semiconductor device according to any one of the supplementary notes 1 to 5, wherein the second coating film is silicon oxide.

[0134] (Supplementary Note 7)

[0135] The method for manufacturing a semiconductor device according to any one of the supplementary notes 1 to 5, wherein the second coating film is silicon oxide.

[0136] The present application has been described with reference to several embodiments, but these embodiments are presented by way of example only and are not intended to limit the scope of the application. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the scope of the application. These embodiments and variations thereof are included in the scope and spirit of the application, and are also included in the scope of the application and equivalents thereof as recited in the claims.

[0137] BRIEF DESCRIPTION OF DRAWINGS

[0138] 1 semiconductor device; 5 trench; 5a side surface; 5b bottom surface; 10 substrate; 12 layer; 30, 130 insulating film (fourth film); 50 silicon film (first film); 60, 160 barrier film (second film); 80, 180 first oxide film (third film); S30 trench forming step; S40 first film forming step; S50, S150 second film forming step; S53, S152 film forming step; S60 first oxidation step (oxidation step); S70, S170 etching step; S80 second oxidation step (oxidation film forming step); S180 oxidation film forming step; T1, T2, T3, T4, T6, T7, TA, T5a, T5b, TCa, TCb film thickness.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: a first film forming step of forming a first film formed of silicon on a surface of a substrate formed of silicon carbide; a second film forming step of forming a second film on a surface of the first film; and an oxidizing step of forming a third film by thermally oxidizing the first film from the surface side. In the second film forming step, a portion of the first film is not covered with the second film, or the second film formed on the portion of the first film has a smaller film thickness than the second film formed on other portions.

2. The method for manufacturing a semiconductor device according to claim 1, comprising the steps of: an etching step of etching at least a portion of the second film and the third film; and an oxidized film forming step of forming a fourth film formed of silicon oxide on a surface of the substrate.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: before the first film forming step, a trench forming step of forming a trench on the substrate is included, the portion of the first film is a portion formed on a side wall surface of the trench, and the other portions of the first film are portions formed on a bottom surface of the trench.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: before the first film forming step, a trench forming step of forming a trench on the substrate is included, the portion of the first film is a portion formed on a bottom surface of the trench, and the other portions of the first film are portions formed on a side wall surface of the trench. The second film forming step is a step of forming the second film by an atomic layer deposition method. The second film is silicon oxide. The second film has a smaller oxygen diffusion coefficient than silicon oxide. ​ ​ ​ ​ ​ ​ ​ ​ ​ 5. The method for manufacturing a semiconductor device according to any one of Claims 1 to 4, wherein ​ 6. The method for manufacturing a semiconductor device according to any one of Claims 1 to 4, wherein ​ 7. The method for manufacturing a semiconductor device according to any one of Claims 1 to 4, wherein ​

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