Method for testing transistor

Abstract

The invention relates to a method for testing a transistor. A method may include closing a reset switch electrically coupled to a gate of a transistor such that the gate is at a first voltage to charge the gate, where the transistor includes the gate and a source, and the source is electrically coupled to a first voltage source; placing the gate of the transistor in a high impedance state; turning off the reset switch; closing a comparator switch such that the gate is electrically coupled to a first input terminal of a voltage comparator wherein a second input terminal of the voltage comparator is adapted to receive a detection voltage; and determining whether the transistor has a defect based on an output from the voltage comparator. In one implementation, a defect is detected if excess charge is released from the gate during a detection period after the reset switch is turned off.

Description

Technical Field

[0001] This disclosure relates to methods for testing transistors, and more specifically, to testing defects in transistors. Background Technology

[0002] Power transistors are prone to latent defects due to their large size. Hard defects (such as particles) can be detected and addressed. However, latent defects can be difficult to detect without destructive testing or inspection, and the characteristics of a power transistor with latent defects can be very close to those of a known good device. One indication of a latent defect is an increase in leakage current between the gate and drain, between the gate and source, or between the gate and channel of a power transistor. Leakage current may be 1 nA or less and may be difficult to detect accurately. Leakage current can be an indication of gate damage, but such small leakage currents can be difficult to measure due to various noise sources and parasitic leakage currents toward the substrate. A more accurate and faster test to detect damaged gates is desired. Summary of the Invention

[0003] According to a first aspect, a method is provided, the method comprising: closing a reset switch electrically coupled to the gate of a transistor such that the gate is at a first voltage, wherein the transistor includes a drain, the gate, and a source, and the source is electrically coupled to a first voltage source; opening the reset switch; closing a comparator switch such that the gate is electrically coupled to a first input terminal of a voltage comparator, wherein a second input terminal of the voltage comparator is adapted to receive a detection voltage; and determining whether the transistor is defective based at least in part on the output from the voltage comparator.

[0004] According to a second aspect, a method is provided, the method comprising: charging a gate of a transistor, wherein the transistor includes the gate, a source, and a drain; terminating the charging of the gate of the transistor; comparing a gate voltage of the gate with a detection voltage when or after terminating the charging of the gate of the transistor; and determining whether the transistor is defective based at least in part on the comparison of the gate voltage of the gate with the detection voltage.

[0005] According to a third aspect, a method is provided, the method comprising: closing a reset switch electrically coupled to the gate of a transistor such that the gate is at a first voltage, wherein the transistor includes a drain, the gate, and a source, and the source is electrically coupled to a first voltage source; opening the reset switch; closing a comparator switch such that the gate is electrically coupled to a first input terminal of a voltage comparator, wherein a second input terminal of the voltage comparator is adapted to receive a detection voltage; and determining whether a gate voltage on the gate of the transistor reaches at least the detection voltage at the end of a detection period of at most 0.9 s or during the detection period, wherein: when the transistor is a p-channel transistor: a defect is detected when the gate voltage is at least the detection voltage during the detection period, and no defect is detected when the gate voltage is less than the detection voltage at the end of or after the end of the detection period; and when the transistor is an n-channel transistor: a defect is detected when the gate voltage is at most the detection voltage during the detection period, and no defect is detected when the gate voltage is greater than the detection voltage at the end of or after the end of the detection period. Attached Figure Description

[0006] The accompanying drawings illustrate specific embodiments by way of example, but the embodiments are not limited to the drawings.

[0007] Figure 1 The circuit diagram includes a circuit according to a specific implementation, which includes a p-channel power transistor and electronic components for operating and testing defects in the power transistor.

[0008] Figure 2 The circuit diagram includes a circuit according to another specific embodiment, which includes an n-channel power transistor and electronic components for operating and testing defects in the power transistor.

[0009] Figure 3 include Figure 1 The circuit diagram, in which p-channel power transistors and defects are represented by circuit elements.

[0010] Figure 4 include Figure 2 The circuit diagram, where n-channel power transistors and defects are represented by circuit elements.

[0011] Figure 5 include Figure 1 or Figure 2 A top view of a portion of a power transistor and an illustration of related defects.

[0012] Figure 6 and Figure 7 Including testing and operation Figure 1 The flowchart of the circuit method.

[0013] Figure 8 The graph includes the gate voltage of the p-channel power transistor as a function of time at reset voltage and a specific detection voltage, and the output of the comparator as a function of time, where different resistances represent different degrees of defects.

[0014] Figure 9 Including reset voltage and different detection voltages Figure 8 Some of the images in the document.

[0015] Figure 10 The graph includes the gate voltage of an n-channel power transistor as a function of time at another reset voltage and a specific detection voltage, and the output of a comparator as a function of time, where different resistances represent different degrees of defects.

[0016] Figure 11 Including under another reset voltage and different detection voltages Figure 10 Some of the images in the document.

[0017] Those skilled in the art will recognize that the elements in the accompanying drawings are shown for simplicity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in an understanding of the specific implementation of the invention. Detailed Implementation

[0018] The following description, in conjunction with the accompanying drawings, is provided to aid in understanding the teachings disclosed herein. The following discussion will focus on specific implementations of these teachings. This focus is provided to aid in describing the teachings and should not be construed as a limitation on their scope or applicability. However, other specific implementations may be adopted based on the teachings disclosed herein.

[0019] The terms "horizontal," "lateral," and their variations refer to directions along or parallel to the main surface of the substrate or semiconductor layer, while the term "vertical" and its variations refer to directions perpendicular to the main surface of the substrate or semiconductor layer. Two objects laterally offset may be at the same or different heights.

[0020] The terms "normal operation" and "normal operating conditions" refer to the conditions under which an electronic component or device is designed to operate, not the conditions under which it is in test mode. These conditions can be obtained from datasheets or other information regarding voltage, current, capacitance, resistance, or other electrical conditions. Therefore, normal operation does not include operating an electronic component or device outside its design limits.

[0021] The term "power transistor" is intended to refer to a transistor that is suitable for flowing at least 1A of current when the transistor is in the on state.

[0022] For clarity of the accompanying drawings, certain regions of the device structure, such as doped or dielectric regions, may be shown as having generally straight edges and corners with precise angles. However, those skilled in the art will understand that the edges of such regions may not typically be straight and the corners may not have precise angles due to dopant diffusion and activation or layer formation.

[0023] The terms “on,” “overlay,” and “above” can be used to indicate that two or more elements are in direct physical contact with each other. However, “above” can also mean that two or more elements are not in direct contact with each other. For example, “above” can mean that one element is on top of another element, but the elements are not in contact with each other and there may be another element or one other element between the two elements.

[0024] The terms “comprising,” “including,” “having,” “containing,” or any other variations thereof are intended to cover non-exclusive inclusion. For example, a method, article, or apparatus that includes a list of features is not necessarily limited to those features, but may include other features not expressly listed or inherent to such a method, article, or apparatus. Furthermore, unless expressly stated to the contrary, “or” means inclusive or, not exclusive, or. For example, condition A or B is satisfied by any of the following: A is true (or exists) and B is false (or does not exist); A is false (or does not exist) and B is true (or exists); and both A and B are true (or exist).

[0025] Furthermore, the terms "a" or "an" are used to describe the elements and components described herein. This is merely for convenience and to give a general meaning regarding the scope of the invention. The description should be considered to include one (a), at least one (a), or the singular form includes the plural form and vice versa, unless explicitly stated otherwise. For example, when a single item is described herein, more than one may be used instead of a single item. Similarly, in cases where more than one item is described herein, a single item may be used instead of the more than one item.

[0026] The use of the terms "about," "approximately," or "basically" is intended to indicate that the value of a parameter is close to the specified value or position. However, slight differences can prevent the value or position from being exactly as specified. Such differences can be within manufacturing tolerances. Therefore, from the ideal goal of being exactly as described, a difference of up to ten percent (10%) for the value (and up to twenty percent (20%) for the semiconductor doping concentration) is considered reasonable.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Materials, methods, and examples are illustrative only and are not intended to be limiting. Many details regarding specific materials and processing actions not described herein are conventional and can be found in textbooks and other sources in the semiconductor and electronics fields.

[0028] Methods for testing transistors may include charging the gate to an initial voltage. After charging is terminated, the transistor's gate can be electrically coupled to a comparator to determine whether the gate voltage increased to at least the detection voltage (for p-channel transistors) or decreased to or below the detection voltage (for n-channel transistors) during or at the end of the detection period. This method is more accurate because the current integrates over a period of time across a capacitor including the gate, which serves as one of the electrodes. The resulting signal corresponding to the accumulated charge is more stable and easier to measure than the current itself. This test can be performed on the power transistor itself, rather than on a dedicated test structure. This test can be performed quickly while the power transistor is turned on and is part of a routine to ensure that the power transistor is free of defects before a load or electrical test equipment receives current or a signal from it.

[0029] Figure 1 The circuit diagram includes circuit 100, which includes a power transistor 110 and associated circuit elements. The circuit and method described herein can be used with many different transistors, and are not limited to power transistors. The drain current when the transistor is turned on can be 9 mA, or even lower, because the transistor is smaller. Nevertheless, the circuit and method are still well-suited for power transistors.

[0030] In one embodiment, power transistor 110 is a p-channel insulated-gate field-effect transistor (IGFET). The source and body of power transistor 110 are electrically coupled to a power supply terminal of circuit 100, which is electrically coupled to power supply 126. The drain of power transistor 110 can be electrically floated during testing. In another embodiment, the drain can be electrically connected to the source of power transistor 110 during testing.

[0031] The gate of power transistor 110 is electrically coupled to gate driver 150, which is adapted to provide a potential to the gate of power transistor 110 to turn power transistor 110 on or off. A set of gate switches is configured in a “T-shaped” circuit arrangement, which is an exemplary, non-limiting circuit configuration associated with gate driver 150. Gate switches 152, 154, and 156 are used during normal operation of power transistor 110. When circuit 100 is in normal mode (i.e., non-test mode), switches 152 and 154 are closed, and switch 156 is open. In test mode, switches 152 and 154 are open, and switch 156 is closed.

[0032] Gate driver switch 152 has a gate driver terminal electrically coupled to gate driver 150 and a terminal electrically coupled to node 153; gate access switch 154 has a terminal electrically coupled to node 153 and a gate terminal electrically coupled to the gate of power transistor 110; and gate discharge switch 156 has a power supply terminal electrically coupled to power supply 124 and a switch terminal electrically coupled to node 153. Gate driver 150 is adapted to provide a potential to the gate of power transistor 110, such that the gate-source voltage (Vo) of power transistor 110 is... GS At least the threshold voltage (V) of the power transistor 110. TH The power supply 124 is adapted to provide a potential to the gate of the power transistor 110, so that the V0 of the power transistor 110 is turned on. GS V less than power transistor 110 TH To turn off power transistor 110.

[0033] Gate driver 150 can turn power transistor 110 on and off during normal operation. Gate driver switch 152 and gate access switch 154 are closed, and gate discharge switch 156 is open. When changing from normal mode to test mode, gate driver switch 152 and gate access switch 154 are open, and gate discharge switch 156 is closed to reduce capacitive coupling between gate driver 150 and the gate of power transistor 110. When changing from test mode to normal mode, gate discharge switch 156 is open, and gate driver switch 152 and gate access switch 154 are closed.

[0034] The gate of power transistor 110 is electrically coupled to reset switch 134, which is electrically coupled to reset power supply 132. Reset power supply 132 is adapted to provide a reset voltage (V). RESET Furthermore, the charge on the gate of the power transistor 110 can be changed during testing, thereby changing the gate potential. During the charging portion of the method for testing the power transistor 110, the gate access switch 154 is opened and the reset switch 134 is closed.

[0035] Comparator 140 may include a positive input terminal and a negative input terminal. The positive input terminal may be electrically coupled to a terminal of comparator switch 144, and the other terminal of comparator switch 144 may be electrically coupled to the gate of power transistor 110. The negative input terminal of comparator 140 may be electrically coupled to a gate adapted to provide a detection voltage (V). DETECT The detection power supply 142 of the comparator 140. The output terminal of the comparator 140 can provide an output from the comparator 140. In one embodiment, the comparator 140 is adapted to receive an analog input and output a digital signal. For example, the output terminal of the comparator 140 may be low or have a value of 0 when the potential at the positive terminal of the comparator 140 is less than the potential at the negative terminal, and the output terminal of the comparator 140 may be high or have a value of 1 when the potential at the positive terminal of the comparator 140 is greater than the potential at the negative terminal. The output terminal may be coupled to a circuit element or circuit that can respond appropriately based on the signal from the output terminal.

[0036] During normal operation, no gate defect is detected, and power transistor 110 operates normally. Gate defects can be detected, as will be described in more detail later in this specification. Gate defects associated with the source of power transistor 110 may be adjacent to the source or the body, since the body is electrically connected to the source, and gate defects associated with the drain of power transistor 110 may be adjacent to the drain and may include a drain or drift region (which may exist in power transistor 110). When a gate defect is present, the potential at the positive terminal of comparator 140 will increase relatively rapidly (compared to the absence of a defect), and the comparator output will change from low to high or from 0 to 1 during the detection period. The output terminal of comparator 140 may be coupled to logic that prevents the gate driver 150 from providing a signal to the gate of power transistor 110 to turn on power transistor 110, logic that provides an operator with a signal that a gate defect has been detected, logic that performs another appropriate action in response to a change in the output signal from comparator 140, or a combination thereof.

[0037] The above concepts can be modified to be used with n-channel IGFETs. Figure 2 The circuit diagram includes circuit 200, which includes power transistor 210 and associated circuit elements. Similar to... Figure 1 Circuit 100, described herein, can be used with many different transistors and is not limited to power transistors. The drain current when the transistor is turned on can be 9 mA, or possibly even lower. Nevertheless, the circuit and method are still well-suited for power transistors.

[0038] In one embodiment, power transistor 210 is an n-channel IGFET. The source and body of power transistor 210 are electrically coupled to a power supply terminal of circuit 200, which is electrically coupled to power supply 226. In one embodiment, power supply 226 may be grounded or supply 0V to the source of power transistor 210. The drain of power transistor 210 may be electrically floating during testing. In another embodiment, the drain may be electrically connected to the source of power transistor 210 during testing.

[0039] The gate of power transistor 210 is electrically coupled to gate driver 250, which is adapted to provide a potential to the gate of power transistor 210 to turn power transistor 210 on or off. A set of gate switches is configured in a “T-shaped” circuit arrangement, which is an exemplary, non-limiting circuit configuration associated with gate driver 250. Gate switches 252, 254, and 256 are used during normal operation of power transistor 210. When circuit 200 is in normal mode (i.e., non-test mode), switches 252 and 254 are closed, and switch 256 is open. In test mode, switches 252 and 254 are open, and switch 256 is closed.

[0040] Gate driver switch 252 has a gate driver terminal electrically coupled to gate driver 250 and a terminal electrically coupled to node 253; gate access switch 254 has a terminal electrically coupled to node 253 and a gate terminal electrically coupled to the gate of power transistor 210; and gate discharge switch 256 has a power supply terminal electrically coupled to power supply 224 and a switch terminal electrically coupled to node 253. Gate driver 250 is adapted to provide a potential to the gate of power transistor 210, such that the Vo of power transistor 210... GS At least the V of the power transistor 210 TH This is to turn on power transistor 210. Power supply 224 is adapted to provide a potential to the gate of power transistor 210, such that the V0 of power transistor 210... GS V less than that of power transistor 210 TH This shuts off power transistor 210. In one implementation, power supply 224 may be grounded or supplied with 0V.

[0041] Gate driver 250 turns power transistor 210 on and off during normal operation, with gate driver switch 252 and gate access switch 254 closed and gate discharge switch 256 open. When transitioning from normal mode to test mode, gate driver switch 252 and gate access switch 254 are open, and gate discharge switch 256 is closed to reduce capacitive coupling between gate driver 250 and the gate of power transistor 210. When transitioning from test mode to normal mode, gate discharge switch 256 is open, and gate driver switch 252 and gate access switch 254 are closed.

[0042] The gate of power transistor 210 is electrically coupled to reset switch 234, which is electrically coupled to reset power supply 232. Reset power supply 232 is adapted to provide V RESET Furthermore, the charge on the gate of the power transistor 210 can be changed during testing, thereby altering the gate potential. During the charging portion of the method for testing the power transistor 210, the gate access switch 254 is open, and the reset switch 234 is closed.

[0043] Comparator 240 may include a positive input terminal and a negative input terminal. The positive input terminal of comparator 240 may be electrically coupled to a source suitable for providing V. DETECT The detection power supply 242. The negative input terminal is electrically coupled to a terminal of comparator switch 244, and another terminal of comparator switch 244 is electrically coupled to the gate of power transistor 210. The output terminal of comparator 240 can provide an output from comparator 240. In one embodiment, comparator 240 is adapted to receive an analog input and output a digital signal. For example, when the potential at the positive terminal of comparator 240 is less than the potential at the negative terminal, the output terminal of comparator 240 can be low or have a value of 0, and when the potential at the positive terminal of comparator 240 is greater than the potential at the negative terminal, the output terminal of comparator 240 can be high or have a value of 1. The output terminal can be coupled to a circuit element or circuit that can respond appropriately based on the signal from the output terminal.

[0044] During normal operation, no gate defect is detected, and power transistor 210 operates normally. Gate defects can be detected, as will be described in more detail later in this specification. Gate defects associated with the source of power transistor 210 may be adjacent to the source or the body, since the body is electrically connected to the source, and gate defects associated with the drain of power transistor 210 may be adjacent to the drain and may include a drain or drift region (which may exist in power transistor 210). When a gate defect is present, the potential at the positive terminal of comparator 240 will increase relatively rapidly (compared to the absence of a defect), and the comparator output will change from low to high or from 0 to 1 during the detection period. The output terminal of comparator 240 may be coupled to logic that prevents the gate driver 250 from providing a signal to the gate of power transistor 210 that would turn on power transistor 210, logic that provides an operator with a signal that a gate defect has been detected, logic that performs another appropriate action in response to a change in the output signal from comparator 240, or a combination thereof.

[0045] Figure 3 and Figure 4 This includes circuits 100 and 200, where power transistors are represented by electrical components used to model the behavior of the power transistors, and defects are represented by resistors. Figure 3 In the diagram, power transistor 110 is represented by capacitors 322, 324, and 326, current source 330, and resistor 344, where capacitor 322 corresponds to the gate-drain capacitance (C). GD Capacitor 324 corresponds to the drain-source capacitance (C). DS Capacitor 326 corresponds to the gate-source capacitance (C). GS ), and resistor 344 represents R DSON It is the on-state resistance of the power transistor 110.

[0046] exist Figure 4 In the diagram, power transistor 210 is represented by capacitors 422, 424, and 426, current source 430, and resistor 444, where capacitor 422 corresponds to C. GD Capacitor 424 corresponds to C DS Capacitor 426 corresponds to C GS And resistor 444 represents R DSON It is the on-state resistance of the power transistor 210.

[0047] The more severe the gate defect, the greater the current flowing between the gate and source, the body, or both, or between the gate and drain. After charging the gate of the power transistor under test, the current caused by the defect reduces the potential between the electrodes of capacitors 322 or 326 or both of power transistor 110, or capacitors 422 or 426 or both of power transistor 210. Therefore, as the drain-side gate defect becomes more severe, the current increases and can be modeled by decreasing the resistance value of resistor 372, and as the source-side gate defect becomes more severe, the current increases and can be modeled by decreasing the resistance value of resistor 376. Similarly, as the drain-side gate defect becomes more severe, the current increases and can be modeled by decreasing the resistance value of resistor 472, and as the source-side gate defect becomes more severe, the current increases and can be modeled by decreasing the resistance value of resistor 476.

[0048] In another specific implementation, the connection between the detection power supply and the comparator switch and the comparator can be switched. Regarding... Figure 1 The detection power supply 142 can be electrically coupled to the positive terminal of comparator 140, and the comparator switch 144 can be electrically coupled to the negative terminal of comparator 140. In this specific implementation, the output of comparator 140 will be at V... G Less than V DETECT When it is high or 1, and will be in V G Greater than V DETECT When it is low or 0. Regarding Figure 2 The detection power supply 242 can be electrically coupled to the negative terminal of comparator 240, and the comparator switch 244 can be electrically coupled to the positive terminal of comparator 240. In this specific implementation, the output of comparator 240 will be at V... G Greater than V DETECT When it is high or 1, and will be in V G Less than V DETECT When it is low or 0.

[0049] Before discussing methods for testing gate defects in power transistors, let's first discuss the potential of the power supply. Power supply 126 can provide a potential to power transistor 110. This potential can correspond to the rated voltage of power transistor 110, which can be obtained from the datasheet of power transistor 110. If power transistor 110 does not have a corresponding datasheet, a designed input potential can be used. In the same or different embodiments, the input potential can range from 80% (0.8 times) to 100% (1.0 times) of the rated voltage or the designed input potential. In a non-limiting example, power transistor 110 can have a rated voltage of 45.0V, and in test mode, the potential received by the source of power transistor 110 can be 41.0V. For power transistor 210, power supply 226 can be at a relatively low potential. Power supply 226 can be grounded or can provide 0.0V. In another embodiment, power supply 226 can supply a voltage in the range of -5.0V to 5.0V.

[0050] Reset power supplies 132 and 232 can provide potentials related to the potentials provided by their corresponding power supplies 126 and 226, respectively. Power supplies 126 and 226 provide potentials to the sources of power transistors 110 and 210, respectively. In the specific implementation of the test mode, the relationship between the potential at the source of the power transistor and the potential provided by its corresponding reset power supply is: 0.1V ≤ |(V S -V RESET )|≤9.0V, Equation 1, where: V S It is the source voltage of the power transistor, and V RESET This is the voltage provided by the reset power supply corresponding to the power transistor. Equation 1 includes the absolute value of the difference, making Equation 1 applicable to both p-channel and n-channel power transistors. Voltage differences outside this range can be used if needed or desired.

[0051] When power transistor 110 is a p-channel IGFET, reset power supply 132 will provide a lower potential than power supply 126. In a non-limiting embodiment, V S It can be 41.0V and the reset power supply 132 can provide 38.5V. RESET When power transistor 210 is an n-channel IGFET, reset power supply 232 will provide a higher potential than power supply 226. In a non-limiting embodiment, V S It can be 0.0V and the reset power supply 232 can provide 2.5V. RESET V DD power supply.

[0052] For power transistors, the sense power supply can provide a voltage at V. S and V RESETThe potential between them. Detection power supplies 142 and 242 can provide potentials related to the potentials provided by their corresponding reset power supplies 132 and 232, respectively. Detection power supplies 142 and 242 provide potentials to the terminals of comparators 140 and 240, respectively. In one embodiment, the relationship between the potential provided by the detection power supply and the potential provided by its corresponding reset power supply is: 0.05V ≤ |(V DETECT -V RESET )|≤0.9V, Equation 2, where V DETECT This is the voltage supplied by the detection power supply corresponding to the power transistor. Equation 2 includes the absolute value of the difference, making it applicable to both p-channel and n-channel power transistors. Regarding the lower limit, 0.05V represents a voltage sufficient to distinguish between the voltage difference and voltage fluctuations associated with the parasitic characteristics of the power transistor, noise within the electronic device during testing, or both parasitic characteristics and noise. The upper limit of the difference in Equation 2 is less than the V value for the power transistor in Equation 1. S The difference. With V DETECT The closer to V S The detection period may be long, increasing the time available for test execution. The upper limit should be high enough to provide sufficient confidence that the gate defect was actually detected (i.e., not a false alarm or missed detection). An upper limit of 0.9V provides high confidence in the detection while requiring a short and acceptable test time. Voltage differences outside this range can be used if needed or desired.

[0053] For the p-channel power transistor 110, the reset power supply 132 can provide a lower potential than the power supply 126. In a non-limiting embodiment, the sense power supply 142 can provide a Vf of 38.7V. DETECT Furthermore, the reset power supply 132 can provide 38.5V. RESET The difference is 0.2V. For the n-channel power transistor 210, the reset power supply 232 can provide a higher potential than the power supply 226. In a non-limiting embodiment, V DETECT It can be 2.3V, and the reset power supply 232 can be V. DD Power supply and provides 2.5V. RESET The absolute value of the difference is 0.2V.

[0054] The above discussion covered many power supplies. Each power supply can be an independent power supply or the output of a voltage divider from another power supply. For example, voltage sources 126 and 226 could be step-down voltages from another power supply, and V RESET 、V DETECT Alternatively, both could be step-down voltages from another power source.

[0055] Figure 5 Including power transistor 110 ( Figure 1 A top view of a portion of power transistor 110. The description of power transistor 210 can also be made for power transistor 210. Figure 2 This is achieved through [the following]. The power transistor 110 includes multiple transistor structures 510, wherein three transistors are [in...]. Figure 5 As shown in the diagram. Each transistor structure 510 may include a drain region 512, a gate electrode 514, and a source region 516. Figure 5 In this configuration, the drift region can be a portion of the drain region 512. As shown, the transistor structure 510 is oriented such that when in the on state, current flows laterally within the transistor structure 510 (from the source region 516 through the channel region below the gate electrode 514 into the drain region 512).

[0056] exist Figure 5 In the diagram, gate defects 572 and 576 are shown in a lightning bolt shape. Gate defect 572 is associated with drain region 512 or drift region, and gate defect 576 is associated with source region 516, body region (below the corresponding gate electrode 514), or a combination of at least one source region 516 and at least one body region of transistor structure 510. Figure 5 Show the closest Figure 5 Gate defects 572 and 576 in the transistor structure on the left. Any one or more other transistor structures may include gate defects 572 or 576, or both gate defects 572 and 576. In the same or another specific embodiment, the transistor structure 510 of the power transistor 110 may not have any detectable gate defects, the left transistor structure 510 may not have either gate defects 572 or 576 or have one of them, or one or more other transistor structures 510 (including...) Figure 5 The central transistor structure 510 or the right transistor structure 510 may be without either of the gate defects 572 and 576, have one of them, or have both.

[0057] In another specific implementation of another physical design, the drain may be made of back metal. Figure 5 The drain region 512 can be replaced by another source region 516. The gate electrode 514 is located on the main surface of the substrate, and the active region of the transistor structure is located in this main surface. When in the on state, the current initially flows laterally from the source region 516 into the channel region, and then vertically through most of the drift region of the power transistor 110 (inflow). Figure 5 (The drawings).

[0058] In another specific implementation of another physical design, the gate electrode 514 may be within a gate trench, and the drain may be made of back metal. Figure 5The drain region 512 can be replaced by another source region 516. When in the ON state, the current flows vertically from the source region 516 through the channel region (adjacent to the gate trench of the gate electrode 514) and the drift region (entering the back metal) of the power transistor 110 before reaching the back metal. Figure 5 (The drawings).

[0059] For power transistor 210, the physical design can be the same as that of the power transistor. When in the on state, current flows from the drain to the source, instead of from the source to the drain as described with respect to power transistor 110.

[0060] Another physical design using power transistors 110 or 120 is possible. Therefore, the physical design is exemplary and does not limit the concepts described herein. Any physical design may have the features previously discussed... Figure 5 The gate defect described.

[0061] Many components have already been described regarding electrical coupling. In an alternative embodiment, any or all of the electrical couplings may be electrical connections. For example, any one or more switches may be electrically connected to the gate of power transistor 110 or 120. Resistors (not shown) may be along any one or more conduction paths between the power supply and power transistor 110 or 210, comparator 140 or 240, or power transistor 110 or 210 and its corresponding comparator.

[0062] Figure 6 and Figure 7 The flowchart includes a method for using a power transistor. The power transistor may be electrically coupled to a load, whereby the power transistor supplies current to the load or electrical test equipment. If the power transistor has a gate defect, the load or electrical test equipment may be damaged or malfunction. This method can be used to ensure the functional safety of the power transistor before it is turned on. This method is exemplary, and not all actions are necessary, or other actions may be part of the method. This method is described with respect to power transistor 110 and may be modified for power transistor 210.

[0063] This method may include in Figure 6 The signal to turn on the power transistor is received at box 602. In one embodiment, this method can be used to perform a safety test before turning on the power transistor. This embodiment can significantly reduce the likelihood of damage or adverse effects on loads or electrical test equipment coupled to the drain of the power transistor. This test can be performed separately from turning on the power transistor, so the action associated with box 602 is not required in all embodiments.

[0064] This method may include in Figure 6At block 622, the gate of the power transistor is placed in a high-impedance state. The gate of the power transistor 110 can be placed in a high-impedance state by disconnecting the gate access switch 154. The gate driver switch 152 can be opened, and the gate discharge switch 156 can be closed to reduce the capacitive coupling between the gate driver 150 and the gate of the power transistor 110. The reset switch 134 and the comparator switch 144 can be opened. If the switches are in the correct positions (open or closed), no further action is required, and therefore the actions in block 622 do not need to be performed for all specific implementations.

[0065] During testing, there may be little or no current (less than 1 nA) flowing between the source and drain of power transistor 110. The drain of power transistor 110 may be electrically floating or may be at substantially the same potential as the source of the power transistor (e.g., |(V)). S -V D ()|<0.05V).

[0066] This method may include in Figure 6 At points 642 and 644, the reset switch is closed, and the gate of the power transistor is charged. Reset switch 134 is closed, causing reset power supply 132 to charge the gate of power transistor 110 to substantially reach the potential of reset power supply 132. The potential of reset power supply 132 is comparable to the V0 of power transistor 110. S The voltage ranges from 0.1V to 9.0V. In one specific implementation, the reset power supply 132 can provide the V of the specific power transistor 110. S A potential of 1.5V to 4.0V is applied. The gate potential of power transistor 110 is charged so that it is substantially the same as that of reset power supply 132. This charging can be performed within a charging time period ranging from 1μs to 1ms.

[0067] This method may include in Figure 6 The reset switch is disconnected and the comparator switch is closed at points 662 and 664 in the middle, and at... Figure 7 Compare V at position 722 in the box. G and V DETECT This method can be transformed from charging the gate of power transistor 110 to comparing the potential V on the gate of power transistor 110. G and V DETECTReset switch 134 can be opened before comparator switch 144 is closed. During the detection period, current can flow through either defective resistor 372 or 376, changing the potential between the corresponding capacitors 324 and 326. Therefore, capacitors 324 and 326, which are charged when reset switch 134 is closed, can begin to discharge after reset switch 134 is opened. When and after comparator switch 144 is closed, the potential of the gate of power transistor 110 can be sent to and received by comparator 140. Detection power supply 142 can provide a potential in the range of 0.05V to 0.9V higher than the potential of reset power supply 132. In a particular implementation, V DETECT Comparable V RESET 0.1V to 0.5V.

[0068] The method may also include Figure 7 The decision diamond at point 742 determines whether the power transistor has a defect. Different techniques can be used to determine whether a defect has been detected. When V G At least V DETECT When the output from comparator 140 changes from low level or 0 to high level or 1, this is referred to herein as an output state change.

[0069] The detection period can be used for this determination. The detection period can have a duration sufficient to ensure that parasitic characteristics or noise do not cause either a missed detection (an actual defect exists but is not detected) or a false alarm (a defect is detected when it does not exist). If the detection period is too short, missed detections are more likely, and if the detection period is too long, false alarms are more likely. In one implementation, the detection period can be at least 1 ms. As the detection period increases, performing the method may require a longer time. In the same or different implementations, the detection period can be at most 900 ms. In a specific implementation, the detection period can range from 1.1 ms to 99 ms.

[0070] One technique may involve accessing a signal from comparator 140 immediately after the end of the detection period or within a few milliseconds (e.g., up to 5 milliseconds). If the state of the output of comparator 140 remains unchanged at the end of the detection period, no defect is detected; if the state of the output of comparator 140 changes, a defect is detected. Another technique may be to detect a change in the output state of comparator 140 and determine whether the change occurred before the end of the detection period. If the change occurred before the end of the detection period, a defect is detected, and no further comparison is required. If the detection period ends and no change in output state is detected, no defect is detected. This technique is faster than existing techniques because the method can be terminated more quickly when a defect is detected. However, the implementation of this technique may be more complex or resource-intensive because accessing the signal at the output and monitoring the detection period (how much time has elapsed) may consume more processing resources. Other methods for monitoring V may be used without departing from the concepts described herein. G The technology is used to detect the presence of defects.

[0071] This method can be performed after a determination is completed in decision diamond 742. When no defect is detected (from the "No" branch of decision diamond 742), the method can be included in... Figure 7 At boxes 762 and 764, the comparator switch is disconnected and the gate driver and access switch are closed. Comparator switch 144 can be disconnected after the detection period ends, and can be disconnected or not disconnected after the detection action in decision diamond 742 is completed. When no defect is detected, power transistor 110 can be turned on and can provide current to a load coupled to the drain of the power transistor or provide a signal to electrical test equipment. Power transistor 110 can be turned on or after the gate driver switch 152 and gate access switch 154 are closed and the gate discharge switch 156 is opened. The method can be repeated or not repeated before power transistor 110 is turned on. The method can be performed based on the usage frequency (e.g., once every 100, 1000, or 1 million times the power transistor is turned on) or based on a time period (e.g., once daily, weekly, or monthly) each time power transistor 110 is turned on.

[0072] When a defect is detected (from the "Yes" branch of decision diamond 742), the method may include in Figure 7The comparator switch is disconnected at blocks 782 and 788, and a signal indicating a defect has been detected is sent. Comparator switch 144 may be disconnected after the detection period ends, and may or may not be disconnected after the detection action in decision diamond 742 is completed. Power transistor 110 should not be turned on when a defect is detected. A signal may be sent to make the system or operator aware that power transistor 110 is defective. The system may repeat this method to confirm the presence of a defect. When repeating this method, the system may shut down or complete, or may not shut down or complete, pending tasks (e.g., stopping the instruction queue from sending further instructions to the processor, completing pending data write commands for writing data to memory, etc.) to reduce noise levels. In another embodiment, the system or operator may send a message to a technician to inspect or replace power transistor 110. Other actions regarding the system may be performed, such as checking the voltage of the power supply electrically coupled to power transistor 110 or comparator 140. The user of this method may determine one or more actions to be taken when a defect is detected, where these actions are tailored to a specific application. Therefore, it is not necessary to send a signal in block 788 in all embodiments.

[0073] The method described above for the p-channel power transistor 110 can also be used for the n-channel power transistor 210. Except for the polarity of the power supply potential and the potential difference, the method and operation for the n-channel transistor 210 are essentially the same as those for the p-channel power transistor 110. Figure 2 In circuit 200, the power supply potential may differ from that in circuit 100, and the polarity of the potential difference may be opposite. For example, the potential of the reset power supply 232 may be greater than that of the power transistor 110. S The voltage ranges from 0.1V to 9.0V. In one specific implementation, the reset power supply 232 can provide the V of the specific power transistor 210. S A potential ranging from 1.5V to 4.0V. The sensing power supply 242 can provide a voltage higher than V. RESET Potential in the range of 0.05V to 0.9V. In a specific implementation, V DETECT Comparable V RESET From 0.1V to 0.5V. When V G Reduce to V DETECT When the voltage is low or lower, the output from comparator 240 changes from low or 0 to high or 1.

[0074] Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. Upon reading this specification, those skilled in the art will recognize that those aspects and embodiments are merely illustrative and do not limit the scope of the inventive concept. Embodiments may be made according to any one or more of the embodiments listed below.

[0075] Specific implementation 1: A method may include closing a reset switch electrically coupled to the gate of a transistor such that the gate is at a first voltage, wherein the transistor includes a drain, the gate, and a source, and the source is electrically coupled to a first voltage source; opening the reset switch; closing a comparator switch such that the gate is electrically coupled to a first input terminal of a voltage comparator, wherein a second input terminal of the voltage comparator is adapted to receive a detection voltage; and determining whether the transistor is defective based at least in part on the output from the voltage comparator.

[0076] Specific implementation 2. According to the method of specific implementation 1, the method further includes placing the gate of the transistor in a high-impedance state before closing the reset switch.

[0077] Specific implementation 3. According to the method of specific implementation 2, placing the gate of the transistor in the high impedance state includes disconnecting the gate access switch between the gate driver and the gate of the transistor.

[0078] Specific Implementation 4. According to the method described in Specific Implementation 1, the method further includes:

[0079] A closed gate access switch is used to enable the transistor by receiving a signal from the gate driver at the gate of the transistor.

[0080] Specific implementation 5. According to the method of specific implementation 4, after the gate access switch is closed, the voltage of the drain of the transistor is substantially the same as the voltage of the source of the transistor.

[0081] Specific implementation 6. According to the method of specific implementation 4, wherein the result of determining whether the transistor has a defect is that no defect is detected, and in response to the absence of a defect detection, the gate access switch is closed.

[0082] Specific implementation 7. The method according to specific implementation 6, wherein the load or test equipment is electrically coupled to the transistor.

[0083] Specific Implementation 8. According to the method of Specific Implementation 6, determining whether the transistor has a defect includes determining whether the gate voltage on the gate of the transistor reaches at least the detection voltage during or within the detection time period.

[0084] Specific implementation 9. The method according to specific implementation 8, wherein the transistor is determined to be defective in such a way that the detection time period is at most 0.9s.

[0085] Specific implementation 10. According to the method of specific implementation 1, the result of determining whether the transistor has a defect is that a defect is detected, and the gate access switch is kept open in response to the detection of the defect.

[0086] Specific implementation 11. A method may include charging the gate of a transistor, wherein the transistor includes the gate, source, and drain; terminating the charging of the gate of the transistor; comparing a gate voltage of the gate with a detection voltage when or after terminating the charging of the gate of the transistor; and determining whether the transistor is defective based at least in part on the comparison of the gate voltage of the gate with the detection voltage.

[0087] Specific implementation 12. According to the method of specific implementation 11, determining whether the transistor has the defect includes determining whether the gate voltage on the gate of the transistor reaches at least the detection voltage during or within the detection time period.

[0088] Specific implementation 13. According to the method of specific implementation 12, the method further includes placing the source of the transistor at a source voltage, wherein when the charging of the gate of the transistor is terminated, the detection voltage is between the source voltage and the gate voltage.

[0089] Specific Implementation 14. A method may include closing a reset switch electrically coupled to the gate of a transistor, such that the gate is at a first voltage, wherein the transistor includes a drain, the gate, and a source, and the source is electrically coupled to a first voltage source; opening the reset switch; closing a comparator switch, such that the gate is electrically coupled to a first input terminal of a voltage comparator, wherein a second input terminal of the voltage comparator is adapted to receive a detection voltage; and determining whether a gate voltage on the gate of the transistor reaches at least the detection voltage during a detection period of at most 0.9 s or during the detection period. When the transistor is a p-channel transistor: a defect is detected when the gate voltage is at least the detection voltage at the end of the detection period or during the detection period, and no defect is detected when the gate voltage is less than the detection voltage at the end of or after the end of the detection period. When the transistor is an n-channel transistor: a defect is detected when the gate voltage is at most the detection voltage at the end of the detection period or during the detection period, and no defect is detected when the gate voltage is greater than the detection voltage at the end of or after the end of the detection period.

[0090] Specific Implementation 15. According to the method described in Specific Implementation 14, where 0.05V≤|(V DETECT -V RESET)|≤0.9V, where V DETECT It is the detection voltage, and V RESET It is the reset voltage.

[0091] Specific Implementation 16. According to the method of Specific Implementation 14, wherein the source of the transistor is adapted to receive a source voltage, 0.1V ≤ |(V S -V RESET )|≤9.0V, where V S It is the source voltage, and V RESET It is the reset voltage.

[0092] Specific implementation 17. According to the method of specific implementation 16, wherein the drain of the transistor is adapted to receive the source voltage when the comparator switch is closed.

[0093] Specific implementation 18. According to the method of specific implementation 14, wherein the method further includes completing the current path between the transistor and the load, wherein the gate voltage does not reach the detection voltage during or within the detection time period, and the current path is completed after the gate voltage on the gate of the transistor does not reach the detection voltage during or within the detection time period.

[0094] Specific Implementation 19. According to the method of Specific Implementation 14, the method further includes sending a signal to the test equipment, wherein the gate voltage on the gate of the transistor does not reach the detection voltage during or within the detection time period, and the signal is sent after the gate voltage on the gate of the transistor does not reach the detection voltage during or within the detection time period.

[0095] Specific implementation 20. According to the method of specific implementation 14, the method further includes sending a signal, wherein the gate voltage on the gate of the transistor reaches the detection voltage during or within the detection time period, the sending of the signal corresponds to the detection of the defect, and is performed after the gate voltage on the gate of the transistor reaches the detection voltage during or within the detection time period.

[0096] Example

[0097] The following examples illustrate how defects of varying degrees can affect how quickly the charge on the gate of a power transistor can change, and whether a defect is detected depends on V. RESET 、V DETECT and the testing period.

[0098] Example 1 is a simulation based on a p-channel transistor, which uses circuit 100 for reset and then charging of the transistor's gate. This transistor is a p-channel laterally diffused metal-oxide-semiconductor (pLDMOS) power transistor with a rated input voltage of 45V. The transistor's C... GD Approximately 41pF, and the transistor's C GS Approximately 67 pF. V S It is 41.0V, V DETECT It is 38.7V, and V RESET It is 38.5V.

[0099] Figure 8 Including the V of power transistor 110 G Graphs showing the change over time with resistances of 50MΩ, 100MΩ, 200MΩ, 300MΩ, 400MΩ, 500MΩ, and 1GΩ. Figure 8 It also includes a graph showing the output of comparator 140 changing over time at 300 MΩ, illustrating when the output state of comparator 140 changes. Other graphs of comparator 140 may be shown in the comparator output signal response, but are not shown here to simplify the interpretation of V. G Crossing V DETECT Understanding how the output state of time comparator 140 changes.

[0100] Lower resistance corresponds to a gate with more defects, and higher resistance corresponds to a gate with fewer defects. For a detection time period of 6ms, gate defects corresponding to 300MΩ and lower resistances will result in detected defects, while no gate defects or gate defects corresponding to resistances higher than 300MΩ will result in undetected defects.

[0101] In another specific implementation, V DETECT The voltage can be changed to 39.0V, resulting in a 0.5V difference between the potentials of the reset power supply 132 and the detection power supply 142. This detection period can be set to 20ms. Figure 9 Including the V of power transistor 110 G Graphs showing the changes over time at resistances of 200MΩ, 300MΩ, 400MΩ, and 500MΩ. Figure 9 It also includes a graph showing the output of comparator 140 changing over time at 400 MΩ, illustrating when the output state of comparator 140 changes. Other graphs of comparator 140 may be shown in the comparator output signal response, but are not shown here to simplify the interpretation of V. G Crossing V DETECT Understanding how the output state of time comparator 140 changes.

[0102] In this specific implementation, a gate defect corresponding to a resistance of 410 MΩ or lower will result in a detected defect, while the absence of a gate defect or a gate defect corresponding to a resistance higher than 410 MΩ will result in an undetected defect. A resistance of 400 MΩ is reached within 19 ms (less than 20 ms). Therefore, a gate defect will be detected in power transistor 110 because V0 is higher at 20 ms. G Greater than 39.0V.

[0103] Example 2 is a simulation based on an n-channel transistor, which uses circuit 200 to charge the transistor's gate. This transistor is an n-channel laterally diffused metal-oxide-semiconductor (nLDMOS) power transistor with a rated input voltage of 45V. The transistor's C... GD Approximately 47pF, and the transistor's C GS Approximately 55 pF. V S 0.0V, V DETECT It is 2.3V, and V RESET It is 2.5V.

[0104] Figure 10 Including the V of power transistor 210 G Graphs showing the change over time with resistances of 50MΩ, 100MΩ, 200MΩ, 300MΩ, 400MΩ, 500MΩ, and 1GΩ. Figure 9 It also includes a graph showing the output of comparator 240 changing over time at 300 MΩ, to illustrate when the output state of comparator 240 changes.

[0105] Lower resistance corresponds to a gate with more defects, and higher resistance corresponds to a gate with fewer defects. For a detection time period of 6ms, gate defects corresponding to 320MΩ and lower resistances will result in detected defects, while no gate defects or gate defects corresponding to resistances higher than 320MΩ will result in undetected defects.

[0106] In another specific implementation, V DETECT The voltage can be changed to 2.0V, so that the potential difference between the reset power supply 232 and the detection power supply 242 is 0.5V. The detection period can be set to 20ms. Figure 11 Including the V of power transistor 210 G Graphs showing the changes over time at resistances of 200MΩ, 300MΩ, 400MΩ, and 500MΩ. Figure 11 It also includes a graph showing the output of comparator 240 changing over time at 400 MΩ, illustrating when the output state of comparator 240 changes. Other graphs of comparator 240 may be shown in the comparator output signal response, but are not shown here to simplify the interpretation of V. G Crossing V DETECTUnderstanding how the output state of time comparator 240 changes.

[0107] In this specific implementation, a gate defect corresponding to a resistance of 410 MΩ or lower will result in a detected defect, while the absence of a gate defect or a gate defect corresponding to a resistance higher than 410 MΩ will result in an undetected defect. A resistance of 400 MΩ is reached within 19 ms (less than 20 ms). Therefore, a gate defect will be detected in the power transistor 210 because V0 is higher at 20 ms. G Less than 2.0V.

[0108] These examples are based on power transistors with a rated voltage of 45V. The concepts of this invention can be used with circuits that have power transistors with significantly lower rated voltages, such as 12V for energy converters in personal computers, laptops, etc., or significantly higher rated voltages, such as at least 100V or more than 1000V for use in electric vehicles. These rated voltages are exemplary, and power transistors with other rated voltages can be used.

[0109] The specific implementation described herein provides benefits for testing power transistors. The circuit can be used to charge the gate of a power transistor and then use a comparator to determine if the power transistor has defects. After charging, when a defect is present, the voltage on the gate can be closer to the voltage on the source of the power transistor. For a p-channel power transistor, V G Can be directed to V DETECT Increase. If V increases during, before, or at the end of the detection period. G At least V DETECT If V0 = 0, a defect is detected. Otherwise, no defect is detected. For an n-channel power transistor, V0 G Can be directed to V DETECT Decrease. If V decreases during or before the detection period, or at the end of the detection period. G Reaching or falling below V DETECT If the test is successful, a defect is detected. Otherwise, no defect is detected. Testing can be performed before the power transistor is turned on to ensure that the power transistor operates correctly and does not damage downstream loads or cause incorrect operation of electrical test equipment.

[0110] During the comparison portion of this test, current can flow into or out of the gate of the power transistor, and the current can affect the gate voltage. Testing by monitoring the current may not be sensitive enough to detect some defects, especially small defects or those in their early stages of development. In contrast, the current integrates over a period of time across a capacitor, including the gate which serves as one of the capacitor's electrodes. The resulting signal corresponding to the accumulated charge is more stable and easier to measure than the current itself.

[0111] Compared to dedicated test structures, power transistors can be tested directly. Therefore, no area of ​​the substrate (e.g., a wafer) is lost due to a dedicated test structure. Furthermore, since no dedicated test structure is required, the discrepancies between power transistors and dedicated test structures are avoided.

[0112] It's possible that, aside from the power supply, the power transistor and all other circuit components can be on the same die. Therefore, the test circuitry can be part of a built-in self-test circuit. This test can be performed quickly, taking less than a second. If needed or desired, a portion of the circuitry can be external to the die. This design may result in tests taking longer to perform. Those skilled in the art will be able to determine the design of the test circuitry that meets the application's needs or expectations.

[0113] It should be noted that not all activities described in the general description or examples above are required; some specific activities may not be necessary, and one or more additional activities may be performed in addition to those described. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed.

[0114] The beneficial effects, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, these beneficial effects, advantages, solutions to problems, and any features that may lead to or make more apparent any beneficial effect, advantage, or solution should not be construed as critical, necessary, or essential features of any or all claims.

[0115] The description and illustrations of the specific embodiments described herein are intended to provide a general understanding of the structure of various embodiments. The description and illustrations are not intended to be an exhaustive and comprehensive description of all elements and features of devices and systems using the structures or methods described herein. Individual embodiments may also be provided in combination within a single embodiment; conversely, various features described in the context of a single embodiment for simplicity may also be provided individually or in any sub-combination. Furthermore, references to values ​​expressed as ranges include all values ​​within that range. Many other embodiments will be apparent only to those skilled in the art upon reading this specification. Other embodiments may be used and derived from this disclosure, such that structural substitutions, logical substitutions, or other changes can be made without departing from the scope of this disclosure. Therefore, this disclosure should be considered exemplary and not restrictive.

Claims

1. A method, the method comprising: A reset switch electrically coupled to the gate of a transistor is closed, such that the gate is at a first voltage, wherein the transistor includes a drain, the gate, and a source, and the source is electrically coupled to a first voltage source; Disconnect the reset switch; Close the comparator switch so that the gate is electrically coupled to the first input terminal of the voltage comparator, wherein the second input terminal of the voltage comparator is adapted to receive the detected voltage; as well as Whether the transistor is defective is determined at least in part based on the output from the voltage comparator.

2. The method according to claim 1, further comprising: The gate of the transistor is placed in a high-impedance state before the reset switch is closed.

3. The method according to claim 2, wherein, Placing the gate of the transistor in a high-impedance state includes: disconnecting the gate access switch between the gate driver and the gate of the transistor.

4. The method according to claim 1, further comprising: A closed gate access switch is used to enable the transistor by receiving a signal from the gate driver at the gate of the transistor.

5. The method according to claim 4, wherein, After the gate access switch is closed, the voltage at the drain of the transistor is substantially the same as the voltage at the source of the transistor.

6. The method according to claim 4, wherein: The result of determining whether the transistor has a defect is that no defect was detected, and The gate access switch is closed in response to the absence of a detected defect.

7. The method according to claim 6, wherein, The load or test equipment is electrically coupled to the transistor.

8. The method according to claim 6, wherein, Determining whether the transistor has a defect includes: Determine whether the gate voltage on the gate of the transistor reaches at least the detection voltage during the detection time period.

9. The method according to claim 8, wherein, The operation of determining whether the transistor is defective is performed during the detection period of up to 0.9 seconds.

10. The method according to claim 1, wherein: The result of determining whether the transistor has a defect is that a defect is detected, and The gate access switch remains open in response to the detection of the defect.

11. A method, the method comprising: The gate of a transistor is charged, wherein the transistor includes the gate, source, and drain. Terminate charging of the gate of the transistor; When or after terminating charging of the gate of the transistor, the gate voltage is compared with the detection voltage. as well as Whether the transistor is defective is determined at least in part based on comparing the gate voltage of the gate with the detection voltage.

12. The method according to claim 11, wherein, Determining whether the transistor has the defect includes determining whether the gate voltage on the gate of the transistor reaches at least the detection voltage during the detection time period.

13. The method according to claim 12, further comprising: The source of the transistor is placed at a source voltage, wherein the detection voltage is between the source voltage and the gate voltage when charging of the gate of the transistor is terminated.

14. A method, the method comprising: A reset switch electrically coupled to the gate of a transistor is closed, such that the gate is at a first voltage, wherein the transistor includes a drain, the gate, and a source, and the source is electrically coupled to a first voltage source; Disconnect the reset switch; Close the comparator switch such that the gate is electrically coupled to a first input terminal of the voltage comparator, wherein a second input terminal of the voltage comparator is adapted to receive a detected voltage; and Determine whether the gate voltage on the gate of the transistor reaches at least the detection voltage within a detection time period of at most 0.9 s, wherein: When the transistor is a p-channel transistor: A defect is detected when the gate voltage reaches the detection voltage at the end of the detection period or when the detection period is at least the detection voltage. No defect was detected when the gate voltage was less than the detection voltage at the end of or after the detection time period. When the transistor is an n-channel transistor: A defect is detected when the gate voltage reaches the detection voltage at the end of the detection period or at most the detection voltage during the detection period. No defect was detected when the gate voltage was greater than the detection voltage at the end of or after the detection period.

15. The method of claim 14, wherein: 0.05V≤|(V DETECT -V RESET )|≤0.9V, Where V DETECT It is the detection voltage, and V RESET It is the reset voltage.

16. The method of claim 14, wherein: The source of the transistor is adapted to receive a source voltage. 0.1V≤|(V S -V RESET )|≤9.0V, Where V S It is the source voltage, and V RESET It is the reset voltage.

17. The method of claim 16, wherein: The drain of the transistor is adapted to receive the source voltage when the comparator switch is closed.

18. The method of claim 14, further comprising completing a current path between the transistor and the load, wherein: The gate voltage did not reach the detection voltage during the detection time period, and The operation of completing the current path is performed after the gate voltage on the gate of the transistor does not reach the detection voltage during the detection time period.

19. The method of claim 14, further comprising sending a signal to the test equipment, wherein: The gate voltage on the gate of the transistor did not reach the detection voltage during the detection time period, and The operation of sending the signal is performed after the gate voltage on the gate of the transistor does not reach the detection voltage during the detection time period.

20. The method of claim 14, further comprising transmitting a signal, wherein: The gate voltage on the gate of the transistor reaches the detection voltage during the detection time period, and Sending the signal corresponds to detecting the defect, and is performed after the gate voltage on the gate of the transistor reaches the detection voltage during the detection time period.

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