Preparation method of on-chip magnetic core power inductor
By forming silicon trenches of a specific depth on a wafer and fabricating magnetic cores, the size and compatibility issues of traditional inductors have been solved, enabling miniaturized and highly integrated inductors that meet the high-performance requirements of advanced electronic devices.
Patent Information
- Application Number
- CN202510992947.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-18
- Publication Date
- 2025-10-28
Smart Images
Figure CN120857516A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of inductive devices, and in particular relates to a method for fabricating an on-chip magnetic core power inductor. Background Art
[0002] With the increasing demand for miniaturization of power electronic systems in wearable devices, flexible electronics, microrobots, and self-driven wireless sensor networks, power supplies based on traditional inductor designs have become a technological bottleneck for the rapid iteration of advanced electronic devices. The core materials of traditional inductors limit operating frequencies and prevent the reduction of the size of filter inductors and capacitors, resulting in high material costs and failing to meet the requirements of advanced electronic devices for fast transient response and low power transmission loss. Furthermore, traditional inductor processes are incompatible with CMOS processes, thus limiting the application of advanced packaging technologies and preventing the realization of chip-level fully integrated power supply products with high integration packaging efficiency.
[0003] The on-chip magnetic core power inductor uses soft magnetic materials with excellent high-frequency characteristics and is realized on the wafer through CMOS compatible technology, which can effectively solve the problems of large size, high difficulty in heterogeneous integration, and low packaging efficiency of current power magnetic devices. Summary of the Invention
[0004] The purpose of this invention is to provide a method for fabricating an on-chip magnetic core power inductor, which solves the challenges of traditional inductors, such as large size, high material cost, incompatibility with CMOS processes, and inability to achieve high-efficiency chip-level fully integrated power products.
[0005] To achieve the above-mentioned technical objectives, the present invention provides the following technical solution:
[0006] A method for fabricating an on-chip magnetic core power inductor includes:
[0007] S1: Silicon trenches for the inductor terminal windings and the inductor intermediate windings are formed on the upper surface of the wafer using photolithography and deep reactive ion etching (DRIE); wherein, the depth of the silicon trenches for the inductor terminal windings after etching is greater than the depth of the silicon trenches for the inductor intermediate windings.
[0008] S2: Sequentially form an insulating thin film layer, a titanium barrier layer, and a copper seed layer on the walls of the silicon trenches of the inductor terminal winding and the intermediate winding of the inductor; and fully plate copper in the silicon trenches of the inductor terminal winding and the intermediate winding of the inductor by electroplating.
[0009] S3: On the upper surface of the wafer, the bulk silicon of the inductor terminal winding silicon trench and the upper periphery of the inductor intermediate winding silicon trench is etched by photolithography and deep reactive ion etching, and a fluid magnetic material composed of soft magnetic powder and epoxy resin is coated to form a partial magnetic core.
[0010] S4: Polish the lower surface of the wafer using a chemical and mechanical polishing (CMP) process until the lower end of the inductor terminal winding is exposed, and form a solder joint at the exposed lower end of the inductor terminal winding.
[0011] S5: On the lower surface of the wafer, the bulk silicon of the inductor terminal winding silicon trench and the lower periphery of the inductor intermediate winding silicon trench is etched by photolithography and deep reactive ion etching, and coated with a fluid magnetic material composed of soft magnetic powder and epoxy resin to form another part of the magnetic core.
[0012] S6: Polish the lower surface of the magnetic core using CMP process to expose the solder joints of the inductor terminal winding, thus obtaining the prepared on-chip magnetic core power inductor.
[0013] Preferably, the wafer is first cleaned to remove contaminants before performing step S1.
[0014] Preferably, step S1 includes:
[0015] S11: Photoresist is coated on the upper surface of the wafer, and the pattern of the inductor terminal winding is patterned through photolithography exposure and development processes.
[0016] S12: The silicon trench corresponding to the inductor terminal winding is formed by deep reactive ion etching to form the initial silicon trench and remove the photoresist.
[0017] S13: The pattern of the inductor's central winding is patterned through photolithography exposure and development processes;
[0018] S14: Continue using the DRIE process to cyclically etch the inductor's intermediate winding area and the inductor's terminal winding area that has been initially etched, ultimately forming the silicon trenches of the inductor's terminal winding and the inductor's intermediate winding.
[0019] Preferably, step 3 includes:
[0020] S21: The silicon trench walls of the inductor terminal winding and the inductor intermediate winding are thermally oxidized using a dry and wet oxygen process to form a silicon dioxide insulating film layer; then the photoresist generated in step S14 is removed.
[0021] S22: Using magnetron sputtering technology, titanium target material is sputtered onto the wall of silicon tank in a vacuum environment to form a titanium barrier layer on the surface of the insulating thin film layer.
[0022] S23: A thin copper layer is deposited on the surface of the barrier layer by physical vapor deposition as a copper seed layer for electroplating;
[0023] S24: Using the seed layer as the conductive layer, copper is electroplated in the silicon trench of the inductor terminal winding and the silicon trench of the inductor intermediate winding to form the inductor terminal winding and the inductor intermediate winding; during the electroplating process, an over-plated copper layer will be formed on the upper surface of the wafer.
[0024] S25: Chemical mechanical polishing is used to remove the over-plated copper layer formed on the upper surface of the wafer during the electroplating process.
[0025] Preferably, step S3 includes:
[0026] S31: Coating a polyimide film on the upper surface of the wafer as a first polyimide insulating layer;
[0027] S32: Photoresist is coated on the upper surface of the first polyimide insulating layer, and the bulk silicon pattern to be etched is patterned by photolithography exposure and development process.
[0028] S33: The bulk silicon of the inductor terminal winding silicon trench and the upper periphery of the inductor intermediate winding silicon trench is etched by deep reactive ion etching.
[0029] S34: After etching, a fluid magnetic material composed of soft magnetic powder and epoxy resin is coated from the upper surface of the wafer to form a partial magnetic core;
[0030] S35: After forming part of the magnetic core, the upper surface of the magnetic core is polished using a chemical mechanical polishing process.
[0031] Preferably, forming a solder joint at the exposed lower end of the inductor terminal winding includes: pre-treating the exposed copper surface of the terminal winding with nickel and gold plating, applying flux to the wafer surface, then placing solder balls in the nickel-gold plated area of the inductor terminal winding using a fixture and a stencil, and then using reflow soldering to bond the solder balls to the terminal to form a solder joint.
[0032] Preferably, step S5 includes:
[0033] S51: Coating a polyimide film on the lower surface of the wafer as a second polyimide insulating layer;
[0034] S52: Photoresist is coated on the lower surface of the second polyimide insulating layer, and the bulk silicon pattern to be etched is patterned through photolithography exposure and development process;
[0035] S53: The bulk silicon of the inductor terminal winding silicon trench and the lower periphery of the inductor intermediate winding silicon trench is etched by deep reactive ion etching.
[0036] S54: After etching, a fluid magnetic material composed of soft magnetic powder and epoxy resin is coated from the lower surface of the wafer to form another part of the magnetic core.
[0037] The present invention has at least the following beneficial effects
[0038] This fabrication method addresses the challenges of traditional inductors, such as large size, high material costs, incompatibility with CMOS processes, and the inability to achieve high-efficiency chip-level fully integrated power products. It also addresses issues related to core materials limiting operating frequency, difficulty in reducing filter component size, and the inability to meet fast transient response and low power transmission loss requirements. By using photolithography and deep reactive ion etching to form silicon trenches of specific depths on the wafer's upper surface, an insulating layer, a barrier layer, and a seed layer are sequentially formed and fully plated with copper. Combined with etching excess bulk silicon on both the upper and lower surfaces and coating with a fluid magnetic material, a complete magnetic core is formed. Polishing then exposes the solder joints. This process achieves inductor miniaturization, reduces material costs, and ensures CMOS compatibility, enabling high-efficiency chip-level fully integrated power products. Simultaneously, the high-permeability soft magnetic material increases the operating frequency, and the high aspect ratio winding reduces winding losses to meet low power transmission loss requirements. This satisfies the miniaturization and high-performance demands of power electronic systems in wearable devices, flexible electronics, and other fields. Attached Figure Description
[0039] Figure 1 This is a schematic diagram of the on-chip magnetic core power inductor described in this invention;
[0040] Figures 2 to 18 This is a process flow diagram of the on-chip magnetic core power inductor described in this invention;
[0041] Figure 19 This is a practical application example diagram of the on-chip magnetic core power inductor described in this invention;
[0042] The figures are labeled as follows: 1. Magnetic core; 2. Inductor intermediate winding; 3. Inductor terminal winding; 4. Inductor terminal winding solder joint; 5. Silicon dioxide thin film insulating layer; 6. First polyimide insulating layer; 7. Second polyimide insulating layer; 8. Silicon-based wafer; 9. First surface of wafer; 10. Second surface of wafer; 11 and 13. Patterned inductor winding photoresist; 12. Silicon trench of inductor terminal winding; 14. Silicon trench of inductor intermediate winding; 15. Barrier layer; 16. Seed layer; 17. Copper overplating layer on the first surface of wafer; 18. Copper surface of inductor terminal winding; 19. Polyimide thin film on the second surface of wafer; 20. Substrate; 21. Bonding wire; 22. Solder ball. Detailed Implementation
[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0044] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.
[0045] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.
[0046] Please see Figure 1 This invention provides a method for fabricating an on-chip magnetic core power inductor, comprising:
[0047] S1: Photolithography and deep reactive ion etching are used on the upper surface of the wafer to etch the silicon trenches of the inductor terminal winding and the silicon trenches of the inductor intermediate winding; wherein, the depth of the silicon trenches of the inductor terminal winding after etching is greater than the depth of the silicon trenches of the inductor intermediate winding.
[0048] Preferably, the wafer is first cleaned to remove contaminants before performing step S1.
[0049] like Figure 1 As shown, as a method for fabricating an on-chip magnetic core power inductor according to the present invention, the on-chip magnetic core power inductor includes: a magnetic core 1, an inductor intermediate winding 2, an inductor terminal winding 3, an inductor terminal winding solder joint 4, a silicon dioxide insulating layer 5, a first polyimide insulating layer 6, and a second polyimide insulating layer 7.
[0050] like Figure 2As shown, in this embodiment, the silicon-based wafer 8, with a thickness of 380 μm, is used for bulk silicon molds. The first surface 9 (the upper surface of the wafer is used as the first surface) and the second surface 10 (the lower surface of the wafer is used as the second surface) of the wafer are cleaned using standard cleaning processes (such as RCA cleaning) to remove contaminants such as organic and inorganic substances.
[0051] Preferably, step S1 includes:
[0052] S11: Photoresist is coated on the upper surface of the wafer, and the pattern of the inductor terminal winding is patterned through photolithography exposure and development processes.
[0053] like Figure 3 In this embodiment, the inductor terminal winding 3 is patterned by photolithography using photoresist 11 (such as AZ4620) on the first surface 9 of the wafer, with a photolithography depth of 5μm to 10μm. The position of the inductor terminal winding is determined by the winding width, spacing, and number of turns, according to the designer's design. In this example, the winding width and spacing can both be 50μm.
[0054] S12: The silicon trench corresponding to the inductor terminal winding is formed by deep reactive ion etching to form the initial silicon trench and remove the photoresist.
[0055] like Figure 4 As shown, in this embodiment, the silicon trench 12 of the inductor terminal winding 3 is etched using a deep reactive ion etching (DRIE) process. Process parameters such as the flow rates of SF6, C4F8, and O2, the etching-to-passivation time ratio, the bias voltage of the upper and lower electrodes, and the cavity pressure are optimized. Through multiple rounds of cyclic etching, a silicon trench 12 of the inductor terminal winding 3 with a depth of approximately 50 μm, a trench wall steepness close to 90°, a sidewall roughness of less than 500 nm, and an opening width of 50 μm is achieved. This optimization process is based on the experience of those skilled in the art.
[0056] S13: The pattern of the inductor's central winding is patterned through photolithography exposure and development processes;
[0057] like Figure 5 As shown, in this embodiment, the intermediate winding 2 of the inductor is patterned by photolithography on the photoresist 11 (e.g., AZ4620), and the photolithography depth is 5μm to 10μm.
[0058] S14: Continue using the DRIE process to cyclically etch the inductor's intermediate winding area and the inductor's terminal winding area that has been initially etched, ultimately forming the silicon trenches of the inductor's terminal winding and the inductor's intermediate winding.
[0059] like Figure 6As shown, in this embodiment, the silicon trenches 12 and 14 of the intermediate winding 2 and the terminal winding 3 of the inductor are etched using the DRIE process. Through multiple rounds of cyclic etching, the etching depth of the silicon trench 12 of the terminal winding of the inductor is approximately 250 μm, and the etching depth of the silicon trench 14 of the intermediate winding of the inductor is approximately 190 μm.
[0060] S2: Sequentially form an insulating thin film layer, a titanium barrier layer, and a copper seed layer on the walls of the silicon trenches of the inductor terminal winding and the intermediate winding of the inductor; and fully plate copper in the silicon trenches of the inductor terminal winding and the intermediate winding of the inductor by electroplating.
[0061] Preferably, step 3 includes:
[0062] S21: The silicon trench walls of the inductor terminal winding and the inductor intermediate winding are thermally oxidized using a dry and wet oxygen process to form a silicon dioxide insulating film layer; then the photoresist generated in step S14 is removed.
[0063] like Figure 7 As shown, in this embodiment, an insulating thin film layer is formed on the silicon trench wall of the inductor winding. A silicon dioxide thin film insulating layer 5 with a thickness of 300nm to 700nm is formed on the surface of the silicon trenches 12 and 14 of the inductor winding by thermal oxidation using a dry and wet oxidation process to avoid the formation of a leakage current path between the inductor winding and the magnetic core. Then, the photoresist 11 is removed by wet method + oxygen plasma.
[0064] S22: Using magnetron sputtering technology, titanium target material is sputtered onto the wall of silicon tank in a vacuum environment to form a titanium barrier layer on the surface of the insulating thin film layer.
[0065] like Figure 8 As shown, in this embodiment, a barrier layer and a seed layer are formed on the silicon trench wall of the inductor winding. First, a barrier layer 15 is formed by magnetron sputtering of 20nm to 40nm titanium (Ti) to prevent copper ions in the winding from diffusing in silicon and silicon dioxide and forming a low-impedance current path between the windings.
[0066] S23: A thin copper layer is deposited on the surface of the barrier layer by physical vapor deposition as a copper seed layer for electroplating;
[0067] In this embodiment, a thin copper (Cu) layer is deposited on the barrier layer 15 by physical vapor deposition (PVD) as a seed layer 16 for electroplating the inductor winding, with a thickness of approximately 1 μm.
[0068] S24: Using the seed layer as the conductive layer, copper is electroplated in the silicon trench of the inductor terminal winding and the silicon trench of the inductor intermediate winding to form the inductor terminal winding and the inductor intermediate winding; during the electroplating process, an over-plated copper layer will be formed on the upper surface of the wafer.
[0069] like Figure 9 As shown, in this embodiment, the inductor winding is electroplated by optimizing the electroplating time and electroplating solution ratio to fully plate the silicon tanks 12 and 14 of the inductor winding with copper, thereby achieving a high aspect ratio winding and reducing winding resistance and power loss. During the electroplating process, a copper layer 17 is also plated on the first surface 9 of the wafer. In this embodiment, the optimization of the electroplating time and electroplating solution ratio is based on the experience of those skilled in the art.
[0070] S25: Chemical mechanical polishing is used to remove the over-plated copper layer formed on the upper surface of the wafer during the electroplating process.
[0071] like Figure 10 As shown, in this embodiment, the copper plating layer 17 on the upper surface of the wafer is removed by chemical and mechanical polishing (CMP) using fine sandpaper as the polishing pad.
[0072] S3: On the upper surface of the wafer, the bulk silicon of the inductor terminal winding silicon trench and the upper periphery of the inductor intermediate winding silicon trench is etched by photolithography and deep reactive ion etching, and a fluid magnetic material composed of soft magnetic powder and epoxy resin is coated to form a partial magnetic core.
[0073] Preferably, step S3 includes:
[0074] S31: Coating a polyimide film on the upper surface of the wafer as a first polyimide insulating layer;
[0075] like Figure 11 As shown, in this embodiment, a first polyimide insulating layer is formed, and a polyimide film 6 is coated on the first surface 9 of the wafer to prevent leakage current channels from forming between the inductor winding and the magnetic core. A photosensitive material is used, and high-speed spin coating is employed to uniformly coat the first surface 9 of the wafer with a polyimide film 6, with a thickness of 3μm to 6μm, and then cured.
[0076] S32: Photoresist AZ4620 is coated on the upper surface of the first polyimide insulating layer, and the bulk silicon pattern to be etched is patterned through photolithography exposure and development process;
[0077] S33: The bulk silicon of the inductor terminal winding silicon trench and the upper periphery of the inductor intermediate winding silicon trench is etched by deep reactive ion etching.
[0078] like Figure 12 As shown, in this embodiment, the wafer bulk silicon is etched for the first time, and the photolithography exposure time is controlled. Photolithography is performed from the first surface 9 of the wafer to remove the bulk silicon outside the inductor windings 2 and 3, while retaining part of the bulk silicon on the second surface 10 of the wafer to ensure the rigidity and strength of the wafer.
[0079] S34: After etching, a fluid magnetic material composed of soft magnetic powder and epoxy resin is coated from the upper surface of the wafer to form a partial magnetic core;
[0080] like Figure 13 As shown, in this embodiment, the first-stage molded magnetic core uses a composite soft magnetic powder with high permeability. The mass ratio of the magnetic powder to epoxy resin is optimized to achieve a balance between permeability, fluid flowability, and the rigidity of the cured magnetic core. The fluid is thoroughly stirred to defoam, ensuring the magnetic powder is uniformly dispersed in the epoxy resin and preventing hollow air bubbles from remaining in the core after curing. After coating the first surface of the disc with the fluid magnetic material resulting from the fusion of soft magnetic powder and epoxy resin, it is placed in a vacuum environment for curing at approximately 150°C for about 1.5 hours. The above steps of coating the fluid magnetic material and curing should be repeated multiple times. In this embodiment, the optimization process was determined by those skilled in the art based on experience.
[0081] S35: After forming part of the magnetic core, the upper surface of the magnetic core is polished using a chemical mechanical polishing process.
[0082] In this embodiment, after the first core forming is completed, the core surface is polished using CMP process to finally form a core layer 1 with a thickness greater than 400μm.
[0083] S4: Polish the lower surface of the wafer using chemical mechanical polishing (CMP) until the lower end of the inductor terminal winding is exposed, and form a solder joint at the exposed lower end of the inductor terminal winding.
[0084] Preferably, forming a solder joint at the exposed lower end of the inductor terminal winding includes: pre-treating the exposed copper surface of the terminal winding with nickel and gold plating, applying flux to the wafer surface, then placing solder balls in the nickel-gold plated area of the inductor terminal winding using a fixture and a stencil, and then using reflow soldering to bond the solder balls to the terminal to form a solder joint.
[0085] like Figure 14 As shown, in this embodiment, the thinning of the second surface of the wafer is achieved by polishing the second surface 10 of the wafer using a CMP process until the copper surface 18 of the inductor terminal winding 3 is exposed. Under the premise of meeting the inductor thickness requirements, the middle winding 2 of the inductor must not be exposed.
[0086] like Figure 15 As shown, in this embodiment, the inductor terminals are treated with solder bumps. Different types of solder bumps are selected based on factors such as the spacing of the inductor windings, cost, and application. For example, if solder bumps are used, the terminals need to undergo pretreatment with electroless nickel plating and gold plating, with thicknesses of 3μm to 8μm and 0.05μm to 1μm, respectively. Flux is applied to the wafer surface, and then the solder ball is placed at the inductor terminal winding plane 18 using a fixture and a stencil. Reflow soldering is then used to bond the solder ball to the terminal to form solder bump 4.
[0087] S5: On the lower surface of the wafer, the bulk silicon of the inductor terminal winding silicon trench and the lower periphery of the inductor intermediate winding silicon trench is etched by photolithography and deep reactive ion etching, and coated with a fluid magnetic material composed of soft magnetic powder and epoxy resin to form another part of the magnetic core.
[0088] Preferably, step S5 includes:
[0089] S51: Coating a polyimide film on the lower surface of the wafer as a second polyimide insulating layer;
[0090] like Figure 16 As shown, in this embodiment, the coating of the second surface 10 of the wafer with a polyimide film is carried out using a photosensitive material and high-speed spin coating, so that a layer of polyimide film 19 is uniformly coated on the second surface 10 of the wafer as a second polyimide insulating layer 7 to avoid the inductor winding and the magnetic core forming a leakage channel. The thickness is 3μm to 6μm, and then cured.
[0091] S52: Photoresist AZ4620 is coated on the lower surface of the second polyimide insulating layer, and the bulk silicon pattern to be etched is patterned through photolithography exposure and development process;
[0092] S53: The bulk silicon of the inductor terminal winding silicon trench and the lower periphery of the inductor intermediate winding silicon trench is etched by deep reactive ion etching.
[0093] like Figure 17 As shown, in this embodiment, the second etching of the wafer silicon involves controlling the photolithography exposure time and photolithography from the second surface of the wafer to remove all remaining bulk silicon.
[0094] S54: After etching, a fluid magnetic material composed of soft magnetic powder and epoxy resin is coated from the lower surface of the wafer to form another part of the magnetic core.
[0095] like Figure 18 As shown, in this embodiment, the second-formed magnetic core uses the same materials and processes as the first-formed magnetic core, and is formed from the direction of the second surface of the wafer, so that the magnetic core 1 completely covers the inductor windings 2 and 3.
[0096] S6: Polish the lower surface of the magnetic core using CMP process to expose the solder joints of the inductor terminal winding, thus obtaining the prepared on-chip magnetic core power inductor.
[0097] like Figure 1 As shown, in this embodiment, the thinning of the second-formed magnetic core is polished using CMP process until the surface of the end winding solder joint 4 is exposed.
[0098] like Figure 19In this embodiment, the surface treatment of the solder joints varies depending on the integration method of the inductor. If the inductor is interconnected with the substrate 20 via bonding wire 21, the surface of the solder joint 4 can be electroplated with titanium-nickel-gold; if the inductor is flip-chip bonded to the substrate 21, the surface of the solder joint 4 can be treated with solder balls 22.
[0099] This fabrication method addresses the challenges of traditional inductors, such as large size, high material costs, incompatibility with CMOS processes, and the inability to achieve high-efficiency chip-level fully integrated power products. It also addresses issues related to core materials limiting operating frequency, difficulty in reducing filter component size, and the inability to meet fast transient response and low power transmission loss requirements. By using photolithography and deep reactive ion etching to form silicon trenches of specific depths on the wafer's upper surface, an insulating layer, a barrier layer, and a seed layer are sequentially formed and fully plated with copper. Combined with etching excess bulk silicon on both the upper and lower surfaces and coating with a fluid magnetic material, a complete magnetic core is formed. Polishing then exposes the solder joints. This process achieves inductor miniaturization, reduces material costs, and ensures CMOS compatibility, enabling high-efficiency chip-level fully integrated power products. Simultaneously, the high-permeability soft magnetic material increases the operating frequency, and the high aspect ratio winding reduces winding losses to meet low power transmission loss requirements. This satisfies the miniaturization and high-performance demands of power electronic systems in wearable devices, flexible electronics, and other fields.
[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A method for fabricating an on-chip magnetic core power inductor, characterized in that, include: S1: Photolithography and deep reactive ion etching are used on the upper surface of the wafer to etch the silicon trenches of the inductor terminal winding and the silicon trenches of the inductor intermediate winding; wherein, the depth of the silicon trenches of the inductor terminal winding after etching is greater than the depth of the silicon trenches of the inductor intermediate winding. S2: Sequentially form an insulating thin film layer, a titanium barrier layer, and a copper seed layer on the walls of the silicon trenches of the inductor terminal winding and the intermediate winding of the inductor; and fully plate copper in the silicon trenches of the inductor terminal winding and the intermediate winding of the inductor by electroplating. S3: On the upper surface of the wafer, the bulk silicon of the inductor terminal winding silicon trench and the upper periphery of the inductor intermediate winding silicon trench is etched by photolithography and deep reactive ion etching, and a fluid magnetic material composed of soft magnetic powder and epoxy resin is coated to form a partial magnetic core. S4: Polish the lower surface of the wafer using chemical mechanical polishing (CMP) until the lower end of the inductor terminal winding is exposed, and form a solder joint at the exposed lower end of the inductor terminal winding. S5: On the lower surface of the wafer, the bulk silicon of the inductor terminal winding silicon trench and the lower periphery of the inductor intermediate winding silicon trench is etched by photolithography and deep reactive ion etching, and coated with a fluid magnetic material composed of soft magnetic powder and epoxy resin to form another part of the magnetic core. S6: Polish the lower surface of the magnetic core using CMP process to expose the solder joints of the inductor terminal winding, thus obtaining the prepared on-chip magnetic core power inductor.
2. The method for fabricating an on-chip magnetic core power inductor according to claim 1, characterized in that, Before performing step S1, the wafer is first cleaned to remove contaminants.
3. The method for fabricating an on-chip magnetic core power inductor according to claim 1, characterized in that, Step S1 includes: S11: Photoresist is coated on the upper surface of the wafer, and the pattern of the inductor terminal winding is patterned through photolithography exposure and development processes. S12: The silicon trench corresponding to the inductor terminal winding is formed by deep reactive ion etching to form the initial silicon trench and remove the photoresist. S13: The pattern of the inductor's central winding is patterned through photolithography exposure and development processes; S14: Continue using the DRIE process to cyclically etch the inductor's intermediate winding area and the inductor's terminal winding area that has been initially etched, ultimately forming the silicon trenches of the inductor's terminal winding and the inductor's intermediate winding.
4. The method for fabricating an on-chip magnetic core power inductor according to claim 1, characterized in that, Step S2 includes: S21: The silicon trench walls of the inductor terminal winding and the inductor intermediate winding are thermally oxidized using a dry and wet oxygen process to form a silicon dioxide insulating film layer; then the photoresist generated in step S14 is removed. S22: Using magnetron sputtering technology, titanium target material is sputtered onto the wall of silicon tank in a vacuum environment to form a titanium barrier layer on the surface of the insulating thin film layer. S23: A thin copper layer is deposited on the surface of the barrier layer by physical vapor deposition as a copper seed layer for electroplating; S24: Using the seed layer as the conductive layer, copper is electroplated in the silicon trench of the inductor terminal winding and the silicon trench of the inductor intermediate winding to form the inductor terminal winding and the inductor intermediate winding; during the electroplating process, an over-plated copper layer will be formed on the upper surface of the wafer. S25: Chemical mechanical polishing is used to remove the over-plated copper layer formed on the upper surface of the wafer during the electroplating process.
5. The method for fabricating an on-chip magnetic core power inductor according to claim 1, characterized in that, Step S3 includes: S31: Coating a polyimide film on the upper surface of the wafer as a first polyimide insulating layer; S32: Photoresist is coated on the upper surface of the first polyimide insulating layer, and the bulk silicon pattern to be etched is patterned by photolithography exposure and development process. S33: The bulk silicon of the inductor terminal winding silicon trench and the upper periphery of the inductor intermediate winding silicon trench is etched by deep reactive ion etching. S34: After etching, a fluid magnetic material composed of soft magnetic powder and epoxy resin is coated from the upper surface of the wafer to form a partial magnetic core; S35: After forming part of the magnetic core, the upper surface of the magnetic core is polished using a chemical mechanical polishing process.
6. The method for fabricating an on-chip magnetic core power inductor according to claim 1, characterized in that, The process of forming a solder joint at the exposed lower end of the inductor terminal winding includes: pre-treating the exposed copper surface of the terminal winding with nickel and gold plating, applying flux to the wafer surface, then placing solder balls in the nickel-gold plated area of the inductor terminal winding using a fixture and a stencil, and then using reflow soldering to bond the solder balls to the terminal to form a solder joint.
7. The method for fabricating an on-chip magnetic core power inductor according to claim 1, characterized in that, Step S5 includes: S51: Coating a polyimide film on the lower surface of the wafer as a second polyimide insulating layer; S52: Photoresist is coated on the lower surface of the second polyimide insulating layer, and the bulk silicon pattern to be etched is patterned through photolithography exposure and development process; S53: The bulk silicon of the inductor terminal winding silicon trench and the lower periphery of the inductor intermediate winding silicon trench is etched by deep reactive ion etching. S54: After etching, a fluid magnetic material composed of soft magnetic powder and epoxy resin is coated from the lower surface of the wafer to form another part of the magnetic core.