Write buffer and logic unit management in data storage device

Abstract

Aspects of the present disclosure provide various techniques, apparatuses, and methods that may improve memory resource utilization of a data storage device that stores data using a non-volatile memory (NVM). In some aspects, a data storage device may be provided with multiple write buffers to improve write throughput of the device. In some aspects, a data storage device may track utilization information for each write buffer using a utilization array. In some aspects, a data storage device may vary the use of a memory with a low utilization write buffer to serve full active logic units to preserve the functionality of the write buffer of the active logic units.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 296,319, filed April 5, 2023, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0003] The technologies discussed below generally relate to data storage devices, and more specifically to technologies used for writing buffers and logical unit management in data storage devices. Background Technology

[0004] Data storage devices may include volatile memory and / or non-volatile memory for storing data. Volatile memory cannot retain the data stored therein when power is lost, but non-volatile memory can retain the data stored therein when power is lost. Some examples of volatile memory include static random access memory (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Some examples of non-volatile memory include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0005] Flash memory is widely used in computing devices, mobile devices, and wireless communication devices to store large amounts of data. In some aspects, host devices can communicate with flash memory-based storage devices using the Universal Flash Memory (UFS) interface defined by the JEDEC (Joint Electron Device Engineering Committee) standard. Flash memory-based storage devices can use write buffers to improve performance, such as write throughput. A write buffer is a temporary storage device used to store incoming write data before it is written to the main storage device, such as NAND flash memory. Write buffers can optimize the write performance of storage devices by allowing more efficient write operations to the NAND flash memory of the data storage device. Furthermore, by using write buffers, data storage devices can increase write performance by reducing the number of write operations required to store incoming data, which can also help extend the lifespan of the main storage device. In some aspects, write buffers can be implemented using single-cell (SLC) memory. SLC buffers store a single data bit per cell, resulting in higher write performance and greater durability compared to multi-cell (MLC) and triple-cell (TLC) memories that store two or more data bits per cell. Summary of the Invention

[0006] The following provides an overview of one or more embodiments to offer a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a form as a prelude to the more detailed descriptions that follow.

[0007] One aspect of this disclosure provides a data storage device including a plurality of logical units (LUs) and a plurality of write buffers, each write buffer being associated with a corresponding LU among the plurality of LUs. The data storage device also includes a controller configured to receive data to be stored in a first LU associated with a first write buffer among the plurality of logical units (LUs), the first LU having insufficient space to store the data. The controller is further configured to identify a second write buffer associated with a second LU among the plurality of LUs, the second write buffer being underutilized to buffer data in the second LU. The controller is also configured to repurpose the memory resources of the second write buffer to increase the storage capacity of the first LU. The controller is further configured to transfer data to the first LU having a capacity expanded using the memory resources of the second write buffer.

[0008] One aspect of this disclosure provides a method of using a data storage device. The method includes: receiving data in a first logical unit (LU) associated with a first write buffer among a plurality of write buffers, the first LU having insufficient space to store the data. The method further includes: identifying a second write buffer associated with a second LU among the plurality of write buffers, the second write buffer being underutilized to buffer data in the second LU. The method further includes: repurposing memory resources of the second write buffer to increase the storage capacity of the first LU. The method further includes: transferring data to the first LU having an expanded capacity using the memory resources of the second write buffer.

[0009] One aspect of this disclosure provides a data storage device. The data storage device includes means for receiving data to be stored in a first LU associated with a first write buffer among a plurality of write buffers, the first LU having insufficient space to store the data. The data storage device also includes means for identifying a second write buffer associated with a second LU among the plurality of write buffers, the second write buffer being underutilized to buffer data in the second LU. The data storage device also includes means for repurposing memory resources of the second write buffer to increase the storage capacity of the first LU. The data storage device further includes means for transferring data to the first LU having a capacity expanded using the memory resources of the second write buffer.

[0010] To achieve the foregoing and related objectives, one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and accompanying figures illustrate certain exemplary aspects of one or more embodiments in detail. However, these aspects are merely indications of a number of ways in which the principles of the various embodiments may be employed, and the described embodiments are intended to cover all such aspects and their equivalents. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a data storage system according to some aspects of this disclosure.

[0012] Figure 2 This is a block diagram illustrating a dedicated write buffer configuration according to some aspects of this disclosure.

[0013] Figure 3 This is a block diagram illustrating a shared write buffer configuration according to some aspects of this disclosure.

[0014] Figure 4 This is a block diagram illustrating a first mapping between a write buffer and a logical unit of a data storage device according to some aspects of this disclosure.

[0015] Figure 5 This is a diagram illustrating some exemplary utilization factors according to some aspects of this disclosure.

[0016] Figure 6 This is a block diagram illustrating a process of changing the use of the write buffer according to some aspects of this disclosure to improve the resource utilization of the data storage device.

[0017] Figure 7 This is a flowchart illustrating the process of selecting single-level cell (SLC) blocks to increase the storage capacity of logical units (LUs) according to some aspects of this disclosure.

[0018] Figure 8 This is a block diagram illustrating an exemplary mapping table between SLC blocks and LUs of a data storage device according to some aspects of this disclosure.

[0019] Figure 9 This is a flowchart of a method for changing the purpose of the write buffer of a data storage device, according to some aspects of this disclosure. Detailed Implementation

[0020] The detailed descriptions following, illustrated with reference to the accompanying drawings, are intended as descriptions of various configurations and are not intended to represent the only configurations in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed descriptions include specific details. However, these concepts can be practiced without these specific details. In some instances, to avoid ambiguity regarding such concepts, well-known structures and components are shown in block diagram form.

[0021] The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising,” “having,” “including,” and / or “containing” as used herein indicate the presence of the stated features, integers, processes, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, processes, operations, elements, components, and / or groups thereof.

[0022] Furthermore, many examples are described in the form of sequences of actions to be performed by elements such as computing devices. It will be appreciated that the various actions described herein can be performed by specific circuitry (e.g., an application-specific integrated circuit (ASIC)), by program instructions executed by one or more processors, or by a combination of both. Additionally, these sequences of actions described herein can be considered to be fully embodied in any form of computer-readable storage medium having a corresponding set of computer instructions stored therein, which, when executed, will cause the associated processor to perform the functions described herein. Thus, various aspects can be embodied in several different forms, all of which are contemplated to fall within the scope of the claimed subject matter. Furthermore, for each example described herein, the corresponding form of any such example can be described herein as, for example, "a logical component configured to perform the described actions."

[0023] This disclosure provides various techniques, apparatuses, and methods for improving the utilization of memory resources in data storage devices. Data storage devices may use non-volatile memory (NVM) to store data. Examples of non-volatile memory are flash memory (e.g., NAND-based flash memory). Flash memory may be accessed or represented as multiple logical cells. Each logical cell may be identified by a unique logical cell number (LUN). In some aspects, the data storage device may be configured with multiple write buffers to improve the write throughput of the device. In some aspects, the write buffers may be implemented using single-level cell (SLC) memory, and the main storage device may be implemented using multi-level cell (MLC) or triple-level cell (TLC) memory. In some aspects, the storage device may use a utilization array to track the utilization information of each write buffer. In some aspects, the data storage device may repurpose memory with low-utilization write buffers to serve full active logical cells, thereby preserving the functionality of the write buffers for active logical cells.

[0024] Figure 1 This is a block diagram illustrating a data storage system 100 according to some aspects of the present disclosure. The data storage system 100 may include a host 102 and a data storage device 104. In some examples, the data storage system 100 may be implemented in a portable computer, tablet computer, smartphone, wearable device, wireless communication device, base station, Internet of Things (IoT) device, etc. In some aspects, the host 102 may be a processor, such as a central processing unit (CPU), graphics processing unit (GPU), digital signal processor (DSP), controller, microcontroller, application processor (AP), neural processing unit (NPU), field-programmable gate array (FPGA), etc. In other aspects, the host 102 may be any device that needs to store data in the data storage device.

[0025] Host 102 may use data storage device 104 to store data for various operations. In some aspects, data storage device 104 may use non-volatile memory 106 to store data. In one example, non-volatile memory 106 may include NAND flash memory that can be configured as SLC, MLC, and / or TLC memory. In one example, data storage device 104 and non-volatile memory 106 may conform to the Universal Flash Storage (UFS) specification defined by JEDEC (Joint Electron Device Engineering Committee). In one example, host 102 may use storage interface 108 (e.g., a UFS interface) to write data to and read data from data storage device 104. In some aspects, storage interface 108 may be implemented using various interface standards, such as Peripheral Component Interconnect Fast (PCIe) interface, Serial Advanced Technology Annex (ATA), etc.

[0026] Host 102 can transmit write commands (with write data) to data storage device 104 to store data in the storage device. To read data from data storage device 104, host 102 can transmit read commands to data storage device 104 and receive data from the storage device. In one example, host 102 and data storage device 104 can exchange information in the form of Universal Flash Storage Protocol Information Units (UPIUs). A UPIU can include various information transmitted via an interface (e.g., interface 108) between host 102 and data storage device 104. For example, a UPIU can include commands, data read from or written to data storage device 104, and various status or control information. For example, status information in a UPIU can provide information about the status of data storage device 104 or the progress of a specific operation (e.g., writing or reading data from data storage device 104). Status information can provide details about whether the operation was successful, whether an error occurred, and what type of error occurred. Control information in a UPIU can be used to manage communication between data storage device 104 (e.g., a UFS device) and host 102. In one example, control information may include information about the device's configuration, power management, and other parameters related to data transfer between the host and data storage devices.

[0027] In some aspects, data storage device 104 may include a memory controller 110 for controlling access to non-volatile memory 106. The memory controller 110 may manage the data flow between non-volatile memory 106 and host 102. In some aspects, the memory controller 110 is responsible for performing various tasks such as error correction, wear leveling, garbage collection, and power management. For example, the memory controller 110 may write data to or read data from non-volatile memory 106 in response to commands received from host 102 (e.g., UFS read or write commands). In some aspects, the memory controller 110 may be a processor, such as a microprocessor, microcontroller, FPGA, etc. In one example, when the memory controller 110 receives a write command and data from host 102, the memory controller 110 may store the received data in non-volatile memory 106 according to the write command. In one example, when the memory controller 110 receives a read command from host 102, the memory controller 110 may read the data stored in non-volatile memory 106 according to the read command. The memory controller 110 may then provide the read data to the host 102, for example, via interface 108. The data storage device 104 may include a command queue 112 (e.g., one or more command queues) for storing commands (e.g., write commands and read commands) and data (e.g., write data) from the host 102. The command queue 112 can help improve the performance of the data storage device by allowing it to process multiple commands concurrently and / or optimizing the order in which commands are executed.

[0028] In some aspects, data storage device 104 may include a write buffer 114 to support enhanced write capabilities (e.g., turbo write operations), thereby increasing the write speed or throughput of data storage device 104 / non-volatile memory 106. The write buffer 114 is configured to have a higher write speed than the main storage device (e.g., non-volatile memory 106). The memory controller may temporarily store data received from the host in the write buffer 114 before storing it in the main storage device. In some aspects, host 102 may transmit commands to memory controller 110 via interface 108 to control / configure the write buffer 114. In one example, the host may control the size of the write buffer, enable or disable the write buffer, and manage data transfer between the write buffer (e.g., write buffer 114) and the main storage device (e.g., non-volatile memory 106). For example, the host may transmit various commands to enable the write buffer, specify the size of the write buffer, and transfer data to the write buffer. The host may then transmit commands to flush the write buffer and store the data in the main storage device. When enhanced write functionality is enabled, data storage device 104 can perform enhanced write operations, thereby writing data to write buffer 114 at a higher write speed than when enhanced write functionality is not used (i.e., using normal or non-enhanced write functionality). Enhanced write operations can provide improved performance (e.g., increased write speed or throughput) compared to writing data that is directed to main storage device (e.g., non-volatile memory 106).

[0029] In some aspects, the write buffer 114 and the non-volatile memory 106 may be included in the same physical flash memory (e.g., NAND flash memory). A first portion of the flash memory may be configured as SLC memory to provide the write buffer 114, and a second portion of the flash memory may be configured as MLC / TLC memory to provide the non-volatile memory 106 (main storage device). The SLC memory may store one bit of information per cell, and the MLC / TLC memory may store more than one bit of information per cell (e.g., the MLC memory stores two bits and the TLC memory stores three bits). In other aspects, the non-volatile memory 106 may support other configurations that allow more than three bits of information per cell.

[0030] In some respects, except Figure 1 In addition to the write buffer 114, command queue 112, and non-volatile memory 106 illustrated herein, storage device 104 may also include any other storage space, such as cache memory, reserved areas, and meta-areas for storing metadata. However, for ease of description, additional descriptions associated with other storage spaces will be omitted (or minimized), and the description will focus on the non-volatile memory storing user data.

[0031] Figure 2 A dedicated write buffer configuration 200 according to some aspects of this disclosure is illustrated. The main storage device 202 of the data storage device may be configured to provide multiple logical units (LUs), such as LU-0, LU-1, LU-2, LU-3, LU-4, LU-5, and LU-6. In some aspects, one or more LUs may be assigned to data partitions. In one aspect, each LU may be associated with a dedicated write buffer, such as write buffers 204, 206, 208, 210, 212, 214, and 216. In one example, the main storage device and write buffers may be implemented using non-volatile memory 106. In some aspects, SLC memory is used to configure the write buffers, and MLC or TLC memory is used to configure the main storage device 202. Each write buffer may use one or more SLC blocks to support enhanced write operations of the associated LU. In enhanced write operations, when the host transfers data to one LU, the data may first be stored in the associated write buffer that has a higher throughput or write speed than the LU.

[0032] Figure 3 A shared write buffer configuration 300 according to some aspects of this disclosure is illustrated. The main storage device 302 may be configured to provide multiple logical units (LUs), such as LU-0, LU-1, LU-2, LU-3, LU-4, LU-5, and LU-6. A second write buffer configuration 300 may use a write buffer 304 shared by the multiple LUs. In one example, the main storage device 302 and the write buffer 304 may use... Figure 1 The non-volatile memory 106 is used for implementation. In some aspects, the write buffer 304 is configured with SLC memory, and the main storage device 302 is configured with MLC or TLC memory. The write buffer 304 can provide one or more SLC blocks to each associated LU for enhanced write operations.

[0033] Figure 4 This illustration shows the mapping between write buffers and logical units (LUs) in a data storage device according to some aspects of this disclosure. In one aspect, the write buffer and the LU can be... Figure 1 The data storage device 104 is implemented. In one aspect, non-volatile memory 106 ( Figure 1 ) can be configured to provide multiple LU 402 (e.g., in Figure 4The LUs are shown as LU-0, LU-1, ..., LU-n. Each LU may correspond to a physical memory portion of the main storage device. In one example, the size of each LU may be 50 gigabytes (GB) or any suitable size. Write buffers may include one or more write buffers that enable enhanced write operations for the LUs. For example, a write buffer may provide multiple SLC blocks 404 (e.g., SLC0, SLC1, ..., SLCn). In one example, the size of each SLC block may be 2GB or any suitable size. Each SLC block may be associated with a specific LU. For example, SLC0 is associated with LU-0, SLC1 with LU-1, LU-n with SLCn, and so on. Using enhanced write operations, when the host (e.g., ...) enables enhanced write operations, ... Figure 1 When host 102 writes data to the LU, it first writes the data to the associated SLC block, which has a faster write throughput than the LU. The write buffer can improve the write performance of the main storage device by caching the written data before writing it to the LU.

[0034] In some respects, some LUs (e.g., LUs allocated to user data partitions) may be used more frequently (e.g., for read / write operations) compared to other LUs (e.g., LUs allocated to backup data partitions). When an LU (e.g., LU-n) becomes full or there is insufficient space for new data, the data storage device can use associated SLC blocks (e.g., SLCn) to store new data written to the LU. In this case, the SLC block loses its function as a write buffer to enhance write operations. However, for LUs that are not frequently used or are underutilized, the associated SLC block may be idle or infrequently used for buffering data.

[0035] Various aspects of this disclosure provide techniques for more efficiently repurposing the memory resources of underutilized SLC blocks. In some aspects, the data storage device may track the utilization of SLC block 404 to promote more efficient use of the SLC block's resources (e.g., physical memory). For example, the data storage device may include a utilization array 406 to store utilization information for each SLC block. The utilization information (e.g., U-0, U-1, ..., Un) may characterize the utilization or availability of each SLC block based on various factors. Figure 5Various exemplary utilization information 500 are illustrated according to several aspects. In one aspect, utilization information 500 may indicate the percentage of storage capacity currently used for each SLC block to store data. In another aspect, utilization information 500 may indicate the read / write ratio of each SLC block. The read / write ratio indicates the ratio of read operations to write operations. A high read / write ratio may indicate that the SLC block is used more for reading than for writing. A low read / write ratio may indicate that the SLC block is not frequently used for boosted write operations. In one aspect, utilization information 500 may indicate the response time of each SLC block. Response time refers to the time it takes for the SLC block to respond to a read or write command. A slow response time may indicate that the SLC block is experiencing high utilization. In another aspect, utilization information 500 may indicate the lifetime estimate of each SLC block. A low lifetime estimate may indicate that the buffer has experienced high utilization (e.g., boosted write operations). By monitoring utilization information, data storage devices (e.g., memory controller 110) can determine which SLC blocks may be underutilized.

[0036] Figure 6 This is a diagram illustrating a process of changing the use of the write buffer according to some aspects of this disclosure to improve the resource utilization of a data storage device. The data storage device may have multiple LUs 602 (e.g., LU-0, LU-1, ..., LU-n) and multiple SLC blocks 604, which can be used to perform enhanced write operations on the LUs. In some aspects, the LUs 602 may be... Figure 4 The same applies to LU 402. In one example, when an LU (e.g., LU-n) becomes full or lacks sufficient space for new data, the data storage device can use the associated SLC block (e.g., SLC-n) or its memory resources to store the new data for the LU. Effectively, the SLC resources are used to increase the storage capacity of the LU. However, when an SLC block is used to increase the capacity of an associated LU to store more data, the SLC block may no longer support enhanced write operations. Therefore, without an SLC block capable of performing enhanced write operations, the throughput of the LU may decrease.

[0037] In some respects, data storage devices can be used with different LUs (e.g., Figure 6 The memory resources of the SLC block (SLC1) associated with LU-1 are used to expand the LU (e.g., Figure 6 The storage capacity of (LU-n). Reference Figure 6 For example, when LU-n becomes full or there is insufficient space for new data, the data storage device can repurpose the memory resources of SLC1 to expand the storage capacity of LU-n. Therefore, the data storage device can retain the originally associated SLCn of LU-n for enhanced write operations.

[0038] Figure 7 This is a flowchart illustrating a process 700 for selecting SLC blocks to increase the storage capacity of a LU according to some aspects of this disclosure. In one example, this process may be performed by... Figure 1 The data storage device 104 performs this operation. In one example, the data storage device can use process 700 to select underutilized SLC blocks, which can be repurposed to increase LUs that are full or do not have enough space for new data (e.g., Figure 6 The storage capacity of LU-n).

[0039] At 710, the data storage device can compare multiple SLC blocks (e.g., Figure 4 SLC block 404 and Figure 6 The data storage device can calculate the utilization rate of SLC blocks (604) and generate utilization information based on comparisons. The data storage device can then use the utilization information of the SLC blocks (e.g., ...) Figure 5 The utilization information (500) is stored in the utilization array (e.g., Figure 4 Utilization array 406 and / or Figure 6 In the utilization array 606), at 720, the data storage device can select the SLC block that is not fully utilized (e.g., has the lowest utilization) among all SLC blocks. In one example, the data storage device can select the SLC block with the lowest storage capacity in use. In one example, the data storage device can select the SLC block with the highest read / write ratio. In one example, the data storage device can select the SLC block with the fastest response time. In one example, the data storage device can select the SLC block with the longest estimated lifetime. In other respects, the data storage device can select SLC blocks based on any combination of the above factors that indicate the SLC block with the lowest utilization.

[0040] At point 730, the data storage device can change the use of memory resources of a selected SLC block to increase the storage capacity of a LU that is full (i.e., has no free space) or does not have enough space to store new data received from the host. The selected SLC block (e.g., SLC1) may initially be associated with a different LU (e.g., LU-1) before being reallocated to increase the storage capacity of another LU (e.g., LU-n). In some aspects, the data storage device can update the mapping or association between the selected SLC block and the LUs of the storage device (e.g., Logical Block Addressing (LBA)).

[0041] Figure 8An exemplary mapping table between SLC blocks and LUs of a data storage device according to some aspects of this disclosure is illustrated. A first table 800 shows a first mapping between SLC blocks and LUs of the data storage device. For example, SLC0 is mapped to LU-0, SLC1 is mapped to LU-1, SLCn is mapped to LU-n, and so on. (As stated above regarding...) Figures 4 to 7 As described, the data storage device can change the use of an SLC block to expand the storage capacity of a LU. In one example, a second table 802 illustrates a second mapping between the SLC block and the LU after the SLC1 block is repurposed to expand the storage capacity of LU-n. In this case, the second table 802 can be updated to show that the SLC1 block is no longer allocated to LU-1 as a write buffer. For example, the mapping table 802 can use "empty" (or any suitable label) to indicate that the SLC1 block is not mapped to any LU as a write buffer. In one aspect, the data storage device can use Logical Block Addressing (LBA) to map the physical memory of the repurposed SLC1 block to LU-n to expand the storage capacity of LU-n. For example, the original capacity of LU-n can be expanded from X to X+Y, where X is the original capacity of LU-n and Y is the capacity of SLC1 or its corresponding physical memory.

[0042] Figure 9 A flowchart illustrating a method 900 for changing the use of a write buffer of a storage device according to various aspects of this disclosure is shown. In one example, method 900 may use... Figure 1 The method is executed using data storage device 104. In other respects, the method can be adapted to other data storage devices. In some respects, data storage device 104 can change the use of resources of the SLC block to expand the storage capacity of a full LU, allowing the original write buffer of the LU to continue to support enhanced write operations.

[0043] In one aspect, the data storage device includes non-volatile memory (NVM) configured to provide a plurality of logical units including a first logical unit (LU) and a second LU. The non-volatile memory also includes a plurality of write buffers, including a first write buffer associated with the first LU and a second write buffer associated with the second LU.

[0044] At 902, the method includes: receiving data to be stored in a first LU associated with a first write buffer. The first LU may not have enough space to store the data. In one example, a data storage device 104 may be provided for receiving data to be stored in the first LU (e.g., Figure 4 and Figure 6The data in the LU-n (e.g., memory controller 110). In one example, memory controller 110 may receive data from host 102 via storage interface 108. In one example, memory controller 110 may receive write commands with data from the host.

[0045] At 904, the method includes: identifying a second write buffer associated with a second LU, the second write buffer being underutilized to buffer data of the second LU. In one aspect, data storage device 104 may provide a second write buffer (e.g., LU-1) for identifying data underutilized to buffer the second LU (e.g., LU-1). Figure 4 and Figure 6 Components of SLC1 (e.g., memory controller 110). For example, data storage device 104 can use Figure 5 One or more of the utilization information in 500 are used to identify underutilized write buffers.

[0046] At 906, the method includes: changing the use of memory resources of the second write buffer to increase the storage capacity of the first LU. In one aspect, the data storage device 104 may provide components (e.g., a memory controller 110) for changing the use of memory resources of the second write buffer to increase the storage capacity of the first LU. In one example, the memory resources may include SLC, MLC, or TLC memory.

[0047] At 908, the method further includes transferring data to a first LU having a capacity expanded using memory resources with a second write buffer. In one aspect, the memory controller 110 may provide components for transferring data to the first LU. For example, the capacity of the first LU may be expanded from X to X+Y, where X is the original capacity of the first LU and Y is the added capacity using memory resources with a second write buffer.

[0048] In some respects, data storage devices can utilize arrays (e.g., Figure 4 Array 406 and Figure 6The data storage device maintains utilization information for multiple write buffers in an array 606. In some aspects, the data storage device may identify underutilized second write buffers based on the utilization information. In some aspects, the data storage device may identify the underutilized second write buffer with the lowest utilization among the multiple write buffers based on the utilization information. In some aspects, the utilization array may include multiple entries, each entry including utilization information for a corresponding write buffer among the multiple write buffers. In some aspects, the utilization information may include at least one of the following: the storage capacity in use for each write buffer among the multiple write buffers; the read / write ratio for each write buffer among the multiple write buffers; the response time for each write buffer among the multiple write buffers; or the lifetime estimate for each write buffer among the multiple write buffers. In some aspects, when the amount of data stored in the first LU is less than a predetermined threshold, the data storage device may restore the second write buffer to buffer data in the second LU. In some aspects, the data storage device may map the logical address of the first LU to the physical memory of the second write buffer whose purpose has been changed.

[0049] The following provides an overview of various embodiments of this disclosure.

[0050] A first aspect of this disclosure provides a data storage device comprising: a plurality of logical units (LUs); a plurality of write buffers, each write buffer being associated with a corresponding LU among the plurality of LUs; and a controller configured to: receive data to be stored in a first LU associated with a first write buffer among the plurality of logical units (LUs), the first LU having insufficient space to store the data; identify a second write buffer associated with a second LU among the plurality of LUs, the second write buffer being underutilized to buffer data in the second LU; change the use of memory resources of the second write buffer to increase the storage capacity of the first LU; and transfer the data to the first LU having a capacity expanded using the memory resources of the second write buffer.

[0051] In a second aspect, either alone or in combination with the first aspect, the controller is further configured to: maintain utilization information of the plurality of write buffers in a utilization array; and identify a second write buffer that is not being fully utilized based on the utilization information.

[0052] In a third aspect, either alone or in combination with the second aspect, the controller is further configured to: identify, based on the utilization information, a second, underutilized write buffer with the lowest utilization among the plurality of write buffers.

[0053] In the fourth aspect, either alone or in combination with any of the second and third aspects, the utilization array comprises a plurality of entries, each entry comprising the utilization information for a corresponding write buffer among the plurality of write buffers.

[0054] In a fifth aspect, either alone or in combination with the second aspect, the utilization information includes at least one of the following: the storage capacity of each of the plurality of write buffers; the read / write ratio of each of the plurality of write buffers; the response time of each of the plurality of write buffers; or the lifetime estimate of each of the plurality of write buffers.

[0055] In a sixth aspect, either alone or in combination with any of the first, second, third, and fifth aspects, wherein the controller is further configured to: use the first write buffer to buffer the data transmitted to the first LU having the extended capacity.

[0056] In a seventh aspect, either alone or in combination with any of the first, second, third, and fifth aspects, wherein the controller is further configured to: restore the second write buffer to buffer the data of the second LU when the amount of data stored in the first LU is less than a predetermined threshold.

[0057] In the eighth aspect, either alone or in combination with any of the first, second, third, and fifth aspects, wherein the controller is further configured to map the logical address of the first LU to the physical memory of the second write buffer whose purpose has been changed.

[0058] In a ninth aspect, alone or in combination with any of the first, second, third, and fifth aspects, the data storage device further includes: a non-volatile memory configured to provide the plurality of LUs and the plurality of write buffers, wherein the plurality of LUs are configured to store more bits per cell compared to the plurality of write buffers.

[0059] A tenth aspect of this disclosure provides a method of using a data storage device, the method comprising: receiving data in a first logical unit (LU) associated with a first write buffer among a plurality of write buffers, the first LU having insufficient space to store the data; identifying a second write buffer associated with a second LU among the plurality of write buffers, the second write buffer being underutilized to buffer data in the second LU; repurposing the memory resources of the second write buffer to increase the storage capacity of the first LU; and transferring the data to the first LU having a capacity expanded using the memory resources of the second write buffer.

[0060] In the eleventh aspect, alone or in combination with the tenth aspect, the method further includes: maintaining utilization information of the plurality of write buffers in a utilization array; and identifying a second write buffer that is not being fully utilized based on the utilization information.

[0061] In a twelfth aspect, either alone or in combination with the eleventh aspect, the method further includes: identifying a second, underutilized write buffer among the plurality of write buffers with the lowest utilization rate based on the utilization information.

[0062] In the thirteenth aspect, either alone or in combination with any of the eleventh and twelfth aspects, the utilization array comprises a plurality of entries, each entry comprising the utilization information for a corresponding write buffer among the plurality of write buffers.

[0063] In the fourteenth aspect, either alone or in combination with the eleventh aspect, the utilization information includes at least one of the following: the storage capacity of each of the plurality of write buffers; the read / write ratio of each of the plurality of write buffers; the response time of each of the plurality of write buffers; or the lifetime estimate of each of the plurality of write buffers.

[0064] In the fifteenth aspect, alone or in combination with any of the tenth, eleventh, twelfth and fourteenth aspects, the method further includes: using the first write buffer to buffer the data transferred to the first LU having the extended capacity.

[0065] In a sixteenth aspect, either alone or in combination with any of the tenth, eleventh, twelfth, and fourteenth aspects, the method further includes: restoring the second write buffer to buffer data in the second LU when the amount of data stored in the first LU is less than a predetermined threshold.

[0066] In the seventeenth aspect, alone or in combination with any of the tenth, eleventh, twelfth and fourteenth aspects, the method further includes: mapping the logical address of the first LU to the physical memory of the second write buffer whose purpose has been changed.

[0067] The eighteenth aspect of this disclosure provides a data storage device. The data storage device includes: means for receiving data to be stored in a first LU associated with a first write buffer among a plurality of write buffers, the first LU having insufficient space to store the data; means for identifying a second write buffer associated with a second LU among the plurality of write buffers, the second write buffer being underutilized to buffer data in the second LU; means for changing the use of memory resources of the second write buffer to increase the storage capacity of the first LU; and means for transferring the data to the first LU having a capacity expanded using the memory resources of the second write buffer.

[0068] In a nineteenth aspect, either alone or in combination with the eighteenth aspect, the data storage device further includes: components for maintaining utilization information of the plurality of write buffers in a utilization array; and components for identifying a second write buffer that is not being fully utilized based on the utilization information.

[0069] In the twentieth aspect, alone or in combination with the nineteenth aspect, the data storage device further includes: a component for identifying, based on the utilization information, a second, underutilized write buffer among the plurality of write buffers that has the lowest utilization rate.

[0070] In the twenty-first aspect, either alone or in combination with any of the nineteenth and twentieth aspects, the utilization array comprises a plurality of entries, each entry comprising the utilization information for a corresponding write buffer among the plurality of write buffers.

[0071] In the twenty-second aspect, either alone or in combination with the nineteenth aspect, the utilization information includes at least one of the following: the storage capacity of each of the plurality of write buffers; the read / write ratio of each of the plurality of write buffers; the response time of each of the plurality of write buffers; or the lifetime estimate of each of the plurality of write buffers.

[0072] In the twenty-third aspect, alone or in combination with any of the eighteenth, nineteenth, twentieth and twenty-second aspects, the data storage device further includes: a component for using the first write buffer to buffer the data transferred to the first LU having the extended capacity.

[0073] In the twenty-fourth aspect, alone or in combination with any of the eighteenth, nineteenth, twentieth and twenty-second aspects, the data storage device further includes: a component for restoring the second write buffer to buffer data of the second LU when the amount of data stored in the first LU is less than a predetermined threshold.

[0074] In the twenty-fifth aspect, alone or in combination with any of the eighteenth, nineteenth, twentieth, and twenty-second aspects, the data storage device further includes: a component for mapping the logical address of the first LU to a physical memory of a second write buffer with a changed purpose.

[0075] It should be understood that this disclosure is not limited to the exemplary terms used above to describe various aspects of this disclosure. For example, bandwidth may also be referred to as throughput, data rate, or another term.

[0076] The use of designations such as "first," "second," etc., to refer to elements in this document generally does not limit the number or order of those elements. Rather, these designations are used here as a convenient way to distinguish two or more elements or instances of elements. Thus, a reference to the first element and the second element does not imply that only two elements can be used, or that the first element must precede the second element.

[0077] In this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect electrical coupling or other communication coupling between two structures. Furthermore, the term "about" means within ten percent of the stated value.

[0078] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data storage device, the data storage device comprising: Multiple logic units (LUs); Multiple write buffers, each write buffer being associated with a corresponding LU among the multiple LUs; and The controller is configured to: Receive data in a first LU associated with a first write buffer among the plurality of write buffers, which is to be stored in the plurality of logical units (LUs), and the first LU does not have enough space to store the data; A second write buffer is identified among the plurality of write buffers and associated with a second LU among the plurality of LUs, the second write buffer being underutilized to buffer data of the second LU; Change the use of memory resources in the second write buffer to increase the storage capacity of the first LU; as well as The data is transferred to the first LU, which has a capacity expanded using the memory resources extended by the second write buffer.

2. The data storage device according to claim 1, wherein the controller is further configured to: Maintain utilization information of the plurality of write buffers in the utilization array; and The utilization information is used to identify the underutilized second write buffer.

3. The data storage device according to claim 2, wherein the controller is further configured to: The utilization information is used to identify the underutilized second write buffer among the plurality of write buffers, which has the lowest utilization rate.

4. The data storage device according to claim 2, wherein the utilization array comprises a plurality of entries, each entry comprising the utilization information corresponding to one of the plurality of write buffers.

5. The data storage device according to claim 2, wherein the utilization information includes at least one of the following: The storage capacity of each of the plurality of write buffers; The read / write ratio of each of the plurality of write buffers; The response time of each of the plurality of write buffers; or Lifetime estimate for each of the plurality of write buffers.

6. The data storage device according to claim 1, wherein the controller is further configured to: The first write buffer is used to buffer the data transmitted to the first LU with the expanded capacity.

7. The data storage device according to claim 1, wherein the controller is further configured to: When the amount of data stored in the first LU is less than a predetermined threshold, the second write buffer is restored to buffer the data of the second LU.

8. The data storage device according to claim 1, wherein the controller is further configured to: The logical address of the first LU is mapped to the physical memory of the second write buffer whose purpose has been changed.

9. The data storage device according to claim 1, further comprising: A non-volatile memory configured to provide the plurality of LUs and the plurality of write buffers, wherein the plurality of LUs are configured to store more bits per cell compared to the plurality of write buffers.

10. A method of using a data storage device, the method comprising: Data is received from a first logical unit (LU) associated with a first write buffer among multiple write buffers, which is to be stored in multiple logical units (LUs), and the first LU does not have enough space to store the data; A second write buffer associated with a second LU is identified among the plurality of write buffers, and the second write buffer is not fully utilized to buffer data of the second LU; Change the use of memory resources in the second write buffer to increase the storage capacity of the first LU; as well as The data is transferred to the first LU, which has a capacity expanded using the memory resources extended by the second write buffer.

11. The method according to claim 10, further comprising: The utilization information of the multiple write buffers is maintained in the utilization array; as well as The utilization information is used to identify the underutilized second write buffer.

12. The method according to claim 11, further comprising: The utilization information is used to identify the underutilized second write buffer among the plurality of write buffers, which has the lowest utilization rate.

13. The method of claim 11, wherein the utilization array comprises a plurality of entries, each entry comprising the utilization information corresponding to one of the plurality of write buffers.

14. The method of claim 11, wherein the utilization information includes at least one of the following: The storage capacity of each of the plurality of write buffers; The read / write ratio of each of the plurality of write buffers; The response time of each of the plurality of write buffers; or Lifetime estimate for each of the plurality of write buffers.

15. The method according to claim 10, further comprising: The first write buffer is used to buffer the data transmitted to the first LU with the expanded capacity.

16. The method according to claim 10, further comprising: When the amount of data stored in the first LU is less than a predetermined threshold, the second write buffer is restored to buffer the data of the second LU.

17. The method according to claim 10, further comprising: The logical address of the first LU is mapped to the physical memory of the second write buffer whose purpose has been changed.

18. A data storage device, the data storage device comprising: A component for receiving data in a first LU associated with a first write buffer among a plurality of write buffers to be stored in a plurality of logical units (LUs), wherein the first LU has insufficient space to store the data; A component for identifying a second write buffer associated with a second LU among the plurality of write buffers, the second write buffer being underutilized to buffer data of the second LU; A component for changing the use of memory resources in the second write buffer to increase the storage capacity of the first LU; and A component for transmitting the data to the first LU having a capacity extended by the memory resources using the second write buffer.

19. The data storage device according to claim 18, further comprising: A component for maintaining utilization information of the plurality of write buffers in the utilization array; and A component used to identify a second write buffer that is not being fully utilized based on the utilization information.

20. The data storage device according to claim 19, further comprising: A component for identifying, based on the utilization information, the underutilized second write buffer among the plurality of write buffers that has the lowest utilization rate.

21. The data storage device of claim 19, wherein the utilization array comprises a plurality of entries, each entry comprising the utilization information corresponding to one of the plurality of write buffers.

22. The data storage device of claim 19, wherein the utilization information includes at least one of the following: The storage capacity of each of the plurality of write buffers; The read / write ratio of each of the plurality of write buffers; The response time of each of the plurality of write buffers; or Lifetime estimate for each of the plurality of write buffers.

23. The data storage device according to claim 18, further comprising: A component for using the first write buffer to buffer the data transmitted to the first LU having the extended capacity.

24. The data storage device according to claim 18, further comprising: A component for restoring the second write buffer to buffer data in the second LU when the amount of data stored in the first LU is less than a predetermined threshold.

25. The data storage device according to claim 18, further comprising: A component for mapping the logical address of the first LU to the physical memory of a second write buffer whose purpose has been changed.

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