Wafer graph processing method, device and equipment

Abstract

The invention provides a wafer graph processing method, device and equipment, and relates to the technical field of ultrasonic detection. The method comprises the steps that a plurality of echo signals of a plurality of ultrasonic signals sequentially transmitted to a wafer to be detected by target ultrasonic equipment are received, the target ultrasonic equipment comprises a plurality of transducer units which are annularly arranged, and the transducer units are independently and obliquely installed; establishing a reference reflection signal of the cavity structure on the to-be-detected wafer according to the preset reflection characteristics of the cavity structure on the to-be-detected wafer; and generating and displaying a bubble distribution diagram of the wafer to be detected according to the reference reflection signal and the plurality of echo signals. According to the invention, high-precision identification and visual presentation of the bubble defect of the wafer to be detected are realized.

Description

Technical Field

[0001] This application relates to the field of ultrasonic testing technology, and more specifically, to a wafer pattern processing method, apparatus, and device. Background Technology

[0002] In the field of MEMS (Micro-Electro-Mechanical Systems) device manufacturing, two or more wafers are typically bonded together to form MEMS products. However, bubbles generated during the bonding process can directly weaken the bonding strength, severely affecting the reliability and lifespan of the device. Therefore, defect detection near the cavity location of the product has become a critical step in ensuring product quality.

[0003] In existing technologies, ultrasonic equipment is commonly used to inspect the bonding quality of bonded MEMS products. However, this inspection technology has significant drawbacks. The inherent cavity structure of the MEMS product itself can cause confusion with the signals generated by bubble areas, making it impossible for ultrasonic equipment to effectively distinguish between the product's original normal cavity structure and bubble defect areas.

[0004] The aforementioned problems severely restrict the accuracy and effectiveness of ultrasonic testing technology in the bonding quality inspection of MEMS products, and there is an urgent need for an improved testing method to achieve accurate identification and location of bonding defects in MEMS products. Summary of the Invention

[0005] This application addresses the shortcomings of the prior art by providing a wafer pattern processing method, apparatus, and device to solve the problems existing in the prior art.

[0006] The technical solution adopted in the embodiments of this application is as follows: In a first aspect, embodiments of this application provide a wafer pattern processing method, including: The device receives multiple echo signals from multiple ultrasonic signals sequentially emitted by a target ultrasonic device to a wafer under test. The target ultrasonic device includes multiple transducer units arranged in a ring, and the multiple transducer units are independently tilted. Based on the preset reflection characteristics of the cavity structure on the wafer under test, a reference reflection signal of the cavity structure on the wafer under test is established; Based on the reference reflection signal and the plurality of echo signals, a bubble distribution map of the wafer under test is generated and displayed.

[0007] In one embodiment, before generating and displaying the bubble distribution pattern of the wafer under test based on the reference reflection signal and the plurality of echo signals, the method further includes: Based on the multiple echo signals, the actual reflection signal of the cavity structure is obtained; The reference reflection signal is calibrated based on the actual reflection signal to obtain the calibrated reference reflection signal; The step of generating and displaying a bubble distribution map of the wafer under test based on the reference reflection signal and the plurality of echo signals includes: Based on the calibrated reference reflection signal and the multiple echo signals, a bubble distribution map of the wafer under test is generated and displayed.

[0008] In one embodiment, generating and displaying a bubble distribution map of the wafer under test based on the calibrated reference reflection signal and the plurality of echo signals includes: Based on the actual reflection signal and the calibrated reference reflection signal, the bubble reflection signal of the wafer under test is obtained from the plurality of echo signals; Based on the bubble reflection signal, a bubble distribution map of the wafer under test is generated and displayed.

[0009] In one embodiment, the method further includes: The reflection signal deviation of the cavity structure is obtained based on the actual reflection signal and the calibrated reference reflection signal. If the deviation of the reflected signal is greater than or equal to the preset signal deviation, an alarm signal is output for the wafer under test. The alarm signal is used to indicate that there is an etching abnormality in the cavity structure.

[0010] In one embodiment, the method further includes: If the deviation of the reflected signal is greater than or equal to the preset signal deviation, the coordinates of the etching anomaly position are obtained from the real reflected signal and output.

[0011] In one embodiment, before establishing a reference reflection signal on the cavity structure of the wafer under test based on a preset reflection characteristic of the cavity structure, the method further includes: Based on the product information of the wafer under test, the preset reflection features of the cavity structure on the wafer under test are obtained from the preset ultrasonic reflection feature database. The preset ultrasonic reflection feature database stores product information of at least two wafers and corresponding preset reflection features.

[0012] In one embodiment, before obtaining the preset reflection features of the cavity structure on the wafer under test from a preset ultrasonic reflection feature database based on the product information of the wafer under test, the method further includes: Obtain cavity configuration information for each wafer, wherein the cavity configuration information includes: geometric parameters of the cavity structure in each wafer and material properties of the cavity structure; Based on the geometric parameters of the cavity structure and the material properties of the cavity structure, a preset reflection feature of the cavity structure is generated; Establish the association between the preset reflection characteristics of the cavity structure and the product information of the wafer under test, and store it in the preset ultrasonic reflection characteristic database.

[0013] In one embodiment, generating and displaying a bubble distribution map of the wafer under test based on the reference reflection signal and the plurality of ultrasonic signals includes: In the first mode, a bubble distribution map of the wafer under test is generated and displayed based on the reference reflection signal and the plurality of echo signals; Alternatively, in the second mode, the actual scan map corresponding to the plurality of echo signals is displayed.

[0014] Secondly, embodiments of this application also provide a wafer pattern processing apparatus, comprising: A control module is used to control a target ultrasonic device to sequentially transmit multiple ultrasonic signals to the wafer under test. The target ultrasonic device includes multiple transducer units arranged in a ring, and the multiple transducer units are independently tilted. A module is established to establish a reference reflection signal on the cavity structure of the wafer under test based on the preset reflection characteristics of the cavity structure on the wafer under test; The display module is used to generate and display a bubble distribution map of the wafer under test based on the reference reflection signal and the plurality of ultrasonic signals.

[0015] Thirdly, embodiments of this application also provide an electronic device, including: a processor, a storage medium, and a bus. The storage medium stores program instructions executable by the processor. When the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the wafer pattern processing method described in any of the above embodiments.

[0016] The beneficial effects of this application are as follows: This application provides a wafer pattern processing method, including receiving multiple echo information from multiple ultrasonic signals sequentially emitted by a target ultrasonic device to a wafer under test, wherein the target ultrasonic device includes: multiple transducer units arranged in a ring, and the multiple transducer units are independently tilted; establishing a reference reflection signal of the cavity structure on the wafer under test based on a preset reflection characteristic of the cavity structure on the wafer under test; and generating and displaying a bubble distribution pattern of the wafer under test based on the reference reflection signal and the multiple echo signals. The method of this application has the following advantages: 1. Multiple transducer units arranged in a ring are installed at an independent tilt angle to construct a three-dimensional scanning field. This design breaks through the detection blind zone limitation of traditional vertical incidence and provides high-density data support for defect feature extraction through multi-directional acoustic wave refraction and reflection coupling.

[0017] 2. The preset reflection characteristics of the cavity structure on the wafer under test are used to establish a reference reflection signal on the cavity structure on the wafer under test, thus establishing a precise reference system for the identification of bubble defects.

[0018] 3. Based on the reference reflection signal and multiple echo signals, a bubble distribution map of the wafer under test is generated and displayed, achieving high-precision differentiation between normal cavity structures and bubble defect areas, and visualizing the bubble defects. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of ultrasonic scanning after wafer bonding provided in this application. Figure 2 This is one of the schematic flowcharts of the wafer pattern processing method provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of the ultrasonic device provided in the embodiments of this application; Figure 4 This is a second schematic flowchart of the wafer pattern processing method provided in the embodiments of this application; Figure 5 This is the third schematic flowchart of the wafer pattern processing method provided in the embodiments of this application; Figure 6 This is the fourth flowchart illustrating the wafer pattern processing method provided in the embodiments of this application. Figure 7 Fifth schematic flowchart of the wafer pattern processing method provided in the embodiments of this application; Figure 8 A schematic diagram illustrating the two display modes provided in this application; Figure 9 This is a schematic diagram of the structure of the wafer pattern processing apparatus provided in the embodiments of this application; Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0022] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0023] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0025] Figure 1 This is a schematic diagram of ultrasonic scanning after wafer bonding provided in this application, as shown below. Figure 1 As shown, in the field of MEMS device manufacturing, when manufacturing MEMS products, two wafers need to be bonded together. After that, ultrasonic scanning is required to obtain information on the bubble defect area on the bonded wafer. However, since the wafer has a normal cavity structure, ultrasonic scanning cannot distinguish between the normal cavity structure and the bubble defect area.

[0026] To address the problems in the prior art, this application provides a wafer pattern processing method. This method can be generated by any electronic device with computing and processing capabilities. The electronic device can be, for example, a terminal-facing computer device or a backend server.

[0027] The wafer pattern processing method provided in this application is illustrated below with reference to the accompanying drawings and several examples.

[0028] Figure 2 This is one of the schematic flowcharts of the wafer pattern processing method provided in the embodiments of this application, such as... Figure 2 As shown, the method may include: S101, Receive multiple echo signals from multiple ultrasonic signals sequentially emitted by the target ultrasonic device to the wafer under test.

[0029] In this embodiment, the target ultrasonic device may include at least a control unit and an ultrasonic probe.

[0030] The control unit and the ultrasonic probe are communicatively connected. Optionally, the control unit can be an FPGA (Field Programmable Gate Array) controller. The control unit is used to implement the wafer pattern processing method provided in the embodiments of this application.

[0031] In this embodiment, the ultrasonic probe is equipped with multiple transducer units. The transducer units can be miniature transducer units.

[0032] In this embodiment, the multiple transducer units may include at least two transducer units with different detection angles.

[0033] In this embodiment, the control unit is connected to multiple transducer units, enabling the control unit to control the multiple transducer units to transmit and receive ultrasonic signals.

[0034] In some implementations, the control unit can control each transducer unit to independently transmit and receive ultrasonic signals, and independently control the phase of the ultrasonic signals transmitted by each transducer unit.

[0035] Specifically, the control unit can switch the control of each transducer unit to emit ultrasonic signals by switching electronic switches. The control unit controls each transducer unit to emit ultrasonic signals to the bonding wafer interface in a time-division manner according to a preset timing sequence, ensuring that the ultrasonic signals do not overlap when propagating in space. Each transducer unit can also receive ultrasonic reflected signals.

[0036] Optionally, the ultrasonic probe may also include: a substrate, on which multiple transducer units are arranged in a ring.

[0037] Specifically, each transducer unit is mounted on the substrate at a tilt angle, and each tilt angle is the angle between the normal direction of each transducer unit and the normal direction of the substrate.

[0038] The substrate can be a ring-shaped substrate. Multiple transducer units arranged in a ring on the ring-shaped substrate can also be called a ring-shaped miniature ultrasonic transducer array. The ring-shaped multi-angle ultrasonic transducer array probes are distributed in an umbrella-like structure.

[0039] It is worth noting that the normal direction of the substrate is perpendicular to the plane on which the substrate lies. When the normal direction of the transducer unit is perpendicular to the substrate, the angle between the normal direction of the transducer unit and the normal direction of the substrate is 0. Each transducer unit is independently tilted on the substrate, and the normal direction of each transducer unit radiates outward at multiple tilt angles. That is, each transducer unit emits ultrasonic signals and receives ultrasonic reflected signals towards the bonding wafer interface at different tilt angles, achieving multi-angle scanning coverage.

[0040] In this embodiment, the number of tilt angles may include at least two to achieve more comprehensive coverage. For example, the number of tilt angles may be three: 0 degrees, 10 degrees, and 30 degrees. The two transducer units symmetrically distributed around the normal direction of the substrate have the same mounting tilt angle.

[0041] In practice, the target ultrasonic device is aligned with the wafer to be tested, such as... Figure 3 As shown, multiple transducer units of the target ultrasonic device emit ultrasonic signals towards the wafer interface at different tilt angles (0, 10, 30 degrees) and receive the echo signals of the ultrasonic signals reflected back from the wafer, achieving multi-angle scanning coverage of the wafer under test. The controller controls each transducer unit to sequentially emit multiple ultrasonic signals towards the wafer under test (e.g., with microsecond-level delays) to ensure that the sound waves do not overlap during spatial propagation.

[0042] During the emission process, the transducer unit converts the electrical signal into an ultrasonic signal. Specifically, for each position (X,Y) to be scanned on the bonded wafer, multiple transducer units (0°, 10°, 30°, etc.) sequentially emit ultrasonic signals at each position (X,Y) to be scanned and collect echo signals in the corresponding directions to achieve multi-angle scanning coverage. This allows the wafer to be scanned from different angles and obtain more comprehensive test data.

[0043] S102. Based on the preset reflection characteristics of the cavity structure on the wafer under test, establish the reference reflection signal of the cavity structure on the wafer under test.

[0044] In this embodiment, preset reflection features of the cavity structure on the wafer under test can be obtained from a preset ultrasonic reflection feature database based on the product information of the wafer under test. The preset ultrasonic reflection feature database stores product information for at least two wafers and their corresponding preset reflection features. Then, based on the preset reflection features of the cavity structure on the wafer under test, a reference reflection signal on the cavity structure is established, providing a comparison standard for subsequent testing.

[0045] S103. Based on the reference reflection signal and multiple echo signals, generate and display the bubble distribution map of the wafer under test.

[0046] The bubble distribution diagram includes the bubble structure in the wafer under test.

[0047] In this embodiment, based on the established reference reflection signal and the multiple echo signals obtained in step S101, a bubble distribution map of the wafer under test can be generated and displayed using a specific data processing algorithm and analysis model, so that the inspection personnel can intuitively obtain the distribution of bubbles on the wafer.

[0048] In one embodiment, a machine learning model can be used to compare and analyze the reference reflection signal and the echo signal to generate and display a bubble distribution map of the wafer under test. For example, by extracting features (such as size features, position features, etc.) of the cavity structure and bubble structure from the reference reflection signal and the echo signal, and based on the extracted feature data, the bubble structure and cavity structure in the wafer under test can be determined and then displayed.

[0049] In summary, this application provides a wafer image processing method that employs multiple transducer units arranged in a ring, each installed at an independent tilt angle, to construct a three-dimensional scanning field. This design overcomes the limitations of traditional vertically incident detection blind zones and provides high-density data support for defect feature extraction through multi-directional acoustic refraction and reflection coupling. Secondly, based on the preset reflection characteristics of the cavity structure on the wafer under test, a reference reflection signal on the cavity structure of the wafer under test is established, providing a precise reference system for identifying bubble defects. Finally, based on the reference reflection signal and multiple echo signals, a bubble distribution map of the wafer under test is generated and displayed, achieving high-precision differentiation between normal cavity structures and bubble defect areas, and visualizing the bubble defects.

[0050] Figure 4 This is a second schematic flowchart of the wafer pattern processing method provided in the embodiments of this application, as shown below. Figure 4 As shown, before performing S103, the method of this application may further include: S201. Obtain the true reflection signal of the cavity structure based on multiple echo signals.

[0051] In this embodiment, the multiple echo signals acquired in S101 are preprocessed, for example, by removing noise interference and then optimizing the echo signals using filtering algorithms and signal enhancement algorithms to complete the preprocessing. Then, signal processing techniques, such as spectrum analysis and time-domain analysis, are used to extract the actual reflection signal corresponding to the cavity structure from the optimized echo signals.

[0052] S202. Based on the actual reflection signal, calibrate the reference reflection signal to obtain the calibrated reference reflection signal.

[0053] In this embodiment, the acquired real reflection signal is compared and analyzed with the reference reflection signal established in step S102 to identify the differences between the two. Based on the difference data, a calibration algorithm is used to adjust the reference reflection signal, such as correcting parameters like the signal amplitude and phase, to obtain a calibrated reference reflection signal that better reflects the actual detection conditions.

[0054] In this embodiment, the step of S103, which generates and displays a bubble distribution map of the wafer under test based on a reference reflection signal and multiple ultrasonic signals, may include: S203. Based on the calibrated reference reflection signal and multiple echo signals, generate and display the bubble distribution map of the wafer under test.

[0055] Specifically, the calibrated reference reflection signal and multiple pre-processed echo signals can be input into a specific data processing algorithm and analysis model. This algorithm and model calculate the location and size of the bubbles in the wafer by comparing and analyzing the signal characteristics of the two signals, such as reflection intensity and reflection time. Based on the calculation results, a graphical bubble distribution map of the wafer is generated and displayed on a display device, allowing inspection personnel to intuitively understand the bubble distribution on the wafer.

[0056] In one embodiment, such as Figure 5 As shown, before obtaining the preset reflection features of the cavity structure on the wafer under test from the preset ultrasonic reflection feature database based on the product information of the wafer under test, the method of this application further includes: S301. Obtain the cavity configuration information of each wafer.

[0057] In this embodiment, the geometric parameters of the cavity structure in each wafer can be read and recorded by a wafer manufacturing system or a dedicated testing device. These parameters include, but are not limited to, the shape (e.g., circular, elliptical, irregular shape), dimensions (length, width, height, diameter, etc.), and position coordinates of the cavity. At the same time, the material properties of the cavity structure can be obtained, such as acoustic impedance Z, attenuation coefficient μ, material type (silicon-based, compound semiconductor, etc.), and density.

[0058] In this embodiment, during the acquisition of cavity configuration information, the system can also perform integrity checks and anomaly checks on the wafer's cavity configuration information. If data is missing or abnormal, the system automatically issues an alarm and prompts the operator to supplement or correct it.

[0059] In one embodiment, integrity checks and information anomaly checks can be performed based on a pre-trained neural network model.

[0060] Specifically, multiple models can be used for integrity checks and information anomaly checks. For example, one model can be used for integrity checks, and another model can be used for anomaly detection. During model training, both models can be trained simultaneously, reducing the need for training data preparation and improving training efficiency.

[0061] In this embodiment, the computer or server can also automatically supplement and correct missing or abnormal data. For example, for missing data, interpolation can be used to supplement the missing data; for abnormal data, the abnormal data can be deleted first, and then the missing data can be supplemented on the deleted data.

[0062] S302. Generate the preset reflection features of the cavity structure based on the geometric parameters and material properties of the cavity structure.

[0063] In this embodiment, the acquired geometric parameters and material properties can be input into a pre-established acoustic simulation model. Based on the acoustic wave equation and material mechanical properties, this model simulates the propagation process of ultrasonic waves in different cavity structures using numerical calculation methods such as finite element analysis and boundary element analysis, generating corresponding preset reflection characteristics. These preset reflection characteristics are a set of characteristic attributes of the reflected signal that the cavity structure should produce under the action of ultrasonic waves, and may include, but are not limited to, the morphological characteristics, temporal characteristics, amplitude characteristics, and phase characteristics of the reflected wave.

[0064] In this embodiment, during the generation process, the simulation parameters of the preset reflection features, such as ultrasonic frequency and incident angle, can be adjusted according to actual needs to improve the accuracy and applicability of the preset reflection features.

[0065] S303. Establish the association between the preset reflection characteristics of the cavity structure and the product information of the wafer under test, and store it in the preset ultrasonic reflection characteristic database.

[0066] In this embodiment, the generated preset reflection features are associated with the product information of the wafer under test (such as wafer model, batch number, manufacturing process, etc.). A database management system (such as MySQL, Oracle, etc.) is used to store the associated information in a preset ultrasonic reflection feature database according to a specific data structure (such as relational data tables). During storage, the data is encrypted to ensure data security and integrity. At the same time, an indexing mechanism is established to facilitate quick querying and retrieval of relevant data later.

[0067] In one embodiment, such as Figure 6 As shown, based on the reference reflection signal and multiple ultrasonic signals, a bubble distribution map of the wafer under test is generated and displayed, which may include: S401. Based on the real reflection signal and the calibrated reference reflection signal, obtain the bubble reflection signal of the wafer under test from multiple echo signals.

[0068] In this embodiment, the real reflection signal is compared and analyzed with the calibrated reference reflection signal. Specifically, through signal difference calculation, feature recognition and other processing methods, the parts of the real reflection signal that are the same as or similar to the calibrated reference reflection signal are removed. These parts represent the reflection information of the normal cavity structure of the wafer, while the remaining difference signal part is the bubble reflection signal of the wafer under test.

[0069] S402. Generate and display the bubble distribution map of the wafer under test based on the bubble reflection signal.

[0070] In this embodiment, after acquiring the bubble reflection signal, the signal can be further processed. For example, based on parameters such as the time delay and amplitude of the bubble reflection signal, combined with physical characteristics such as the propagation speed of ultrasound in the wafer material, the specific position coordinates (x, y, z) of the bubble inside the wafer can be calculated, where x and y represent the position of the bubble on the wafer plane, and z represents the depth of the bubble in the wafer thickness direction. Simultaneously, the approximate size of the bubble can be estimated based on the amplitude of the bubble reflection signal.

[0071] In this embodiment, the calculated bubble position coordinates and size information can be imported into graphics generation software. This software can be dedicated to image drawing and display, or it can be a drawing module integrated into the signal processing system of the ultrasonic testing equipment. In the graphics generation software, based on a planar view of the wafer, graphic symbols representing the bubbles, such as circles, are drawn at the corresponding positions according to the bubble position coordinates. The size of the graphic symbols is adjusted according to the estimated bubble size, thereby generating a bubble distribution map of the wafer under test.

[0072] Furthermore, the generated bubble distribution map can be displayed on a monitor, allowing staff to visually observe the distribution of bubbles inside the wafer under test, including the number, location, and approximate size of the bubbles, in order to assess and analyze the quality of the wafer.

[0073] In one embodiment, such as Figure 7 As shown, the method of this application may further include: S501. Obtain the reflection signal deviation of the cavity structure based on the actual reflection signal and the calibrated reference reflection signal.

[0074] In this embodiment, the real reflected signal and the calibrated reference reflected signal are subjected to another in-depth comparative analysis. Signal analysis algorithms are used to compare the real reflected signal and the calibrated reference reflected signal point by point from multiple dimensions such as the time domain and frequency domain, and to calculate the amplitude difference, phase difference, etc. between the two at each time point or frequency point.

[0075] In this embodiment, by integrating these differences, a value is obtained that can comprehensively reflect the degree of difference between the real reflected signal and the calibrated reference reflected signal, and this value is used as the reflection signal deviation of the cavity structure.

[0076] S502. If the reflected signal deviation is greater than or equal to the preset signal deviation, an alarm signal is output for the wafer under test. The alarm signal is used to indicate that there is an etching abnormality in the cavity structure.

[0077] In this embodiment, a reasonable preset signal deviation threshold is pre-set in the signal processing module. This threshold is determined based on wafer manufacturing process standards and a large amount of experimental data, and can accurately reflect the difference between the wafer reflection signal under normal conditions and the reflection signal when there is an etching anomaly. When the calculated reflection signal deviation is greater than or equal to the preset signal deviation, the signal processing module immediately triggers an alarm program, emitting a clear audible and visual alarm signal through the audible and visual alarm device equipped on the ultrasonic testing equipment. At the same time, it prominently alerts the testing personnel on the display screen that there is an etching anomaly in the cavity structure of the wafer under test, so that the testing personnel can take timely measures to deal with it.

[0078] For example, when the signal difference is greater than 10%, it is determined that the corresponding cavity has an abnormality during etching, and an alarm message is output.

[0079] In this embodiment, if the reflected signal deviation is greater than or equal to the preset signal deviation, the coordinates of the etching abnormal position can also be obtained from the real reflected signal and output.

[0080] Specifically, the signal processing module, based on the signal differences recorded at each location point during the calculation of the reflected signal deviation, and combined with the calculation method based on ultrasonic propagation characteristics used in step S402 to determine the bubble position coordinates, accurately locates the signal feature positions related to the etching anomaly from the actual reflected signal. That is, based on parameters such as time delay and amplitude in the actual reflected signal, and signals in the actual reflected signal whose reflected signal deviation is greater than or equal to a preset signal deviation, combined with physical characteristics such as the propagation speed of ultrasonic waves in the wafer material, the module calculates the specific position coordinates (x, y, z) of the etching anomaly location inside the wafer.

[0081] Then, following the same coordinate calculation logic, the position is converted into specific coordinate values ​​(x', y', z') and displayed on the screen along with the alarm signal. Alternatively, the coordinates of the etching abnormal position can be transmitted to other related devices or systems via the data output interface, facilitating further analysis and repair of the etching abnormal position.

[0082] In one embodiment, such as Figure 8 As shown, this application can output the final result in two modes. For example, in the first mode, a bubble distribution map of the wafer under test is generated and displayed based on the reference reflection signal and multiple echo signals. Alternatively, in the second mode, the actual scan map corresponding to the multiple echo signals is displayed.

[0083] Specifically, operators can select to execute either the first mode or the second mode through the system's user interface. In the first mode, the system combines the reference reflection signal and multiple echo signals, and uses image synthesis algorithms, such as pixel-based image synthesis algorithms or feature-matching image synthesis algorithms, to integrate and process the data. Then, through a display device, such as an LCD monitor or a projection device, the bubble distribution map of the wafer under test is visualized at a preset display resolution and color mode, facilitating intuitive viewing and analysis by technicians.

[0084] In the second mode, the system directly generates a real scan image based on multiple echo signals, and then transmits the real scan image data to the display device for display at the original scan resolution and color mode, enabling technicians to directly observe the actual shape and position of the cavity structure on each target grain on the wafer under test.

[0085] This embodiment provides technicians with flexible data viewing methods through the two modes described above. In the first mode, a bubble distribution map (showing only bubbles) of the wafer under test can be generated and displayed based on the reference reflection signal and multiple echo signals, providing intuitive and accurate data support for wafer quality inspection and manufacturing process improvement. In the second mode, the actual scan image (including cavities and bubbles) can be directly displayed, meeting the technicians' needs for viewing the original scan data, helping to promptly identify problems in the production process and improve wafer product quality.

[0086] The following will continue to explain the apparatus, device and storage medium for performing the wafer pattern processing method provided in any of the above embodiments of this application. The specific implementation process and the resulting technical effects are the same as those in the corresponding method embodiments. For the sake of brevity, the parts not mentioned in the following embodiments can be referred to the corresponding content in the method embodiments.

[0087] like Figure 9 As shown, this application also provides a wafer pattern processing apparatus, which may include: The control module 10 is used to receive multiple echo signals from multiple ultrasonic signals sequentially emitted by the target ultrasonic device to the wafer under test. The target ultrasonic device includes multiple transducer units arranged in a ring, and the multiple transducer units are independently tilted.

[0088] The module 20 is used to establish a reference reflection signal on the cavity structure of the wafer under test based on the preset reflection characteristics of the cavity structure on the wafer under test.

[0089] Display module 30 is used to generate and display a bubble distribution map of the wafer under test based on the reference reflection signal and the plurality of echo signals.

[0090] Optionally, the device further includes an acquisition module, configured to acquire the actual reflection signal of the cavity structure based on the plurality of echo signals; and to calibrate the reference reflection signal based on the actual reflection signal to obtain a calibrated reference reflection signal.

[0091] The display module 30 is also used to generate and display a bubble distribution map of the wafer under test based on the calibrated reference reflection signal and the plurality of echo signals.

[0092] Optionally, the acquisition module is further configured to acquire, based on the product information of the wafer under test, preset reflection features of the cavity structure on the wafer under test from a preset ultrasonic reflection feature database, wherein the preset ultrasonic reflection feature database stores product information of at least two wafers and corresponding preset reflection features.

[0093] Optionally, the acquisition module is further configured to acquire cavity configuration information for each wafer, the cavity configuration information including: geometric parameters of the cavity structure in each wafer, and material properties of the cavity structure; and to generate a preset reflection feature of the cavity structure based on the geometric parameters of the cavity structure and the material properties of the cavity structure.

[0094] In one embodiment, the wafer pattern processing apparatus may further include a creation module for creating a correlation between the preset reflection features of the cavity structure and the product information of the wafer under test, and storing it in the preset ultrasonic reflection feature database.

[0095] Optionally, the display module 30 is further configured to obtain the bubble reflection signal of the wafer under test from the plurality of echo signals based on the real reflection signal and the calibrated reference reflection signal; and generate and display the bubble distribution map of the wafer under test based on the bubble reflection signal.

[0096] Optionally, the device further includes an alarm module, used to obtain the reflection signal deviation of the cavity structure based on the actual reflection signal and the calibrated reference reflection signal; if the reflection signal deviation is greater than or equal to a preset signal deviation, an alarm signal is output for the wafer under test, the alarm signal being used to indicate that there is an etching abnormality in the cavity structure.

[0097] Optionally, the alarm module is further configured to obtain and output the coordinates of the etching abnormality position from the real reflected signal if the reflected signal deviation is greater than or equal to the preset signal deviation.

[0098] Optionally, the display module 30 is further configured to generate and display a bubble distribution map of the wafer under test based on the reference reflection signal and the plurality of echo signals in a first mode; or, in a second mode, display the actual scan map corresponding to the plurality of echo signals.

[0099] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.

[0100] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more microprocessors, or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a system-on-a-chip (SOC).

[0101] like Figure 10 As shown, this application also provides an electronic device, including: a processor 100, a storage medium 200 and a bus 300. The storage medium stores program instructions executable by the processor. When the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the wafer pattern processing method described in any of the above embodiments.

[0102] Optionally, this application also provides a readable storage medium storing program instructions, which, when executed by a processor, implement the wafer pattern processing method described in any of the above embodiments.

[0103] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0104] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0105] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0106] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0107] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A wafer pattern processing method, characterized in that, include: The device receives multiple echo signals from multiple ultrasonic signals sequentially emitted by a target ultrasonic device to a wafer under test. The target ultrasonic device includes multiple transducer units arranged in a ring, and the multiple transducer units are independently tilted. Based on the preset reflection characteristics of the cavity structure on the wafer under test, a reference reflection signal of the cavity structure on the wafer under test is established; Based on the reference reflection signal and the plurality of echo signals, a bubble distribution map of the wafer under test is generated and displayed.

2. The method according to claim 1, characterized in that, Before generating and displaying the bubble distribution pattern of the wafer under test based on the reference reflection signal and the plurality of echo signals, the method further includes: Based on the multiple echo signals, the actual reflection signal of the cavity structure is obtained; The reference reflection signal is calibrated based on the actual reflection signal to obtain the calibrated reference reflection signal; The step of generating and displaying a bubble distribution map of the wafer under test based on the reference reflection signal and the plurality of echo signals includes: Based on the calibrated reference reflection signal and the multiple echo signals, a bubble distribution map of the wafer under test is generated and displayed.

3. The method according to claim 2, characterized in that, The step of generating and displaying a bubble distribution map of the wafer under test based on the calibrated reference reflection signal and the plurality of echo signals includes: Based on the actual reflection signal and the calibrated reference reflection signal, the bubble reflection signal of the wafer under test is obtained from the plurality of echo signals; Based on the bubble reflection signal, a bubble distribution map of the wafer under test is generated and displayed.

4. The method according to claim 2, characterized in that, The method further includes: The reflection signal deviation of the cavity structure is obtained based on the actual reflection signal and the calibrated reference reflection signal. If the deviation of the reflected signal is greater than or equal to the preset signal deviation, an alarm signal is output for the wafer under test. The alarm signal is used to indicate that there is an etching abnormality in the cavity structure.

5. The method according to claim 4, characterized in that, The method further includes: If the deviation of the reflected signal is greater than or equal to the preset signal deviation, the coordinates of the etching anomaly position are obtained from the real reflected signal and output.

6. The method according to claim 1, characterized in that, Before establishing the reference reflection signal on the cavity structure of the wafer under test based on the preset reflection characteristics of the cavity structure on the wafer under test, the method further includes: Based on the product information of the wafer under test, the preset reflection features of the cavity structure on the wafer under test are obtained from the preset ultrasonic reflection feature database. The preset ultrasonic reflection feature database stores product information of at least two wafers and corresponding preset reflection features.

7. The method according to claim 6, characterized in that, Before obtaining the preset reflection features of the cavity structure on the wafer under test from the preset ultrasonic reflection feature database based on the product information of the wafer under test, the method further includes: Obtain cavity configuration information for each wafer, wherein the cavity configuration information includes: geometric parameters of the cavity structure in each wafer and material properties of the cavity structure; Based on the geometric parameters of the cavity structure and the material properties of the cavity structure, a preset reflection feature of the cavity structure is generated; Establish the association between the preset reflection characteristics of the cavity structure and the product information of the wafer under test, and store it in the preset ultrasonic reflection characteristic database.

8. The method according to claim 1, characterized in that, The step of generating and displaying a bubble distribution map of the wafer under test based on the reference reflection signal and the plurality of echo signals includes: In the first mode, a bubble distribution map of the wafer under test is generated and displayed based on the reference reflection signal and the plurality of echo signals; Alternatively, in the second mode, the actual scan map corresponding to the plurality of echo signals is displayed.

9. A wafer pattern processing apparatus, characterized in that, include: The control module is used to receive multiple echo signals from multiple ultrasonic signals sequentially emitted by the target ultrasonic device to the wafer under test, wherein the target ultrasonic device includes multiple transducer units arranged in a ring, and the multiple transducer units are independently tilted. A module is established to establish a reference reflection signal on the cavity structure of the wafer under test based on the preset reflection characteristics of the cavity structure on the wafer under test; The display module is used to generate and display a bubble distribution map of the wafer under test based on the reference reflection signal and the plurality of echo signals.

10. An electronic device, characterized in that, include: The device includes a processor, a storage medium, and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the wafer pattern processing method according to any one of claims 1 to 8.

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