Root mean square value RMS detection method and system

Abstract

The invention discloses a root mean square value RMS detection method and system, and belongs to the technical field of measurement and control. Wherein a to-be-detected voltage signal is preprocessed by the filter amplification circuit, a square wave signal synchronous with a sine wave zero crossing point is generated through the zero crossing comparison circuit, a signal period boundary is identified, and an integral number of complete and continuous signal periods are extracted in real time through the period detection module; the cycle information identified by the cycle detection module is transmitted to the data storage and processing module, meanwhile, the sampling signal of the high-speed ADC module is transmitted to the data storage and processing module, and sine wave data sampled by the high-speed ADC module is subjected to point-by-point square operation; the square values in a complete period are accumulated and summed, and an original sampling sequence is not stored; fIR digital filtering is carried out on the RMS values of continuous C periods through a digital filtering module; and the dynamic response performance of the system under different frequency bands is remarkably enhanced while the measurement precision is improved.

Description

Technical Field

[0001] This invention belongs to the field of measurement and control technology, specifically relating to a root mean square (RMS) value detection method and system. Background Technology

[0002] The effective value (RMS) of AC voltage, also known as the root mean square (RMS), refers to the equivalent thermal effect of an AC voltage (or current) applied to a resistive load within the same time period as a DC voltage (or current). It is widely used in industrial measurement and control. AC voltage RMS detection mainly employs two technical solutions: a closed-loop feedback calculation method based on analog circuits and a sampling calculation method based on digital signal processing.

[0003] (1) In analog circuit solutions, the industry often uses ADI's AD637 series dedicated AC voltage RMS detection chip. This type of chip not only increases hardware costs, but also requires adjusting the external capacitor of the integrating amplifier through peripheral circuits to change the calculation time and filtering coefficient, resulting in poor system flexibility. In addition, the calculation error is inconsistent for input waveforms with different bandwidths and amplitudes, and the output results are easily affected by ripple interference, thus affecting the measurement accuracy and making it difficult to meet the application scenarios with multi-frequency signals and high precision requirements.

[0004] (2) In digital circuit implementation schemes, the traditional sliding window sampling method cannot adaptively adjust the sampling window depth according to the input signal frequency. In the low frequency band, the insufficient sampling depth can easily introduce large errors; while in the high frequency band, the overall sampling and calculation time is long, making it difficult to meet the response requirements of real-time control. Summary of the Invention

[0005] To address the shortcomings of the aforementioned background technology, this invention provides a root mean square (RMS) detection method. This method is highly efficient, possessing adaptive sampling depth adjustment capabilities and the ability to calculate the effective value of the current signal period in real time. While improving measurement accuracy, this method significantly enhances the dynamic response performance of the system across different frequency bands.

[0006] The technical solution is as follows: Firstly, a root mean square (RMS) detection method is provided, comprising: Signal period synchronization detection: The voltage signal under test is preprocessed by the filtering and amplification circuit, and a square wave signal synchronized with the zero-crossing point of the sine wave is generated by the zero-crossing comparison circuit. The signal period boundary is identified and transmitted to the period detection module inside the FPGA. The period detection module extracts complete and continuous integer signal periods in real time. The entire cycle square accumulation calculation: The cycle information identified by the cycle detection module is transmitted to the data storage and processing module inside the FPGA. At the same time, the sampling signal of the high-speed ADC module is transmitted to the data storage and processing module through the ADC driver module inside the FPGA. The RMS calculation module inside the FPGA performs point-by-point square operation on the sine wave data sampled by the high-speed ADC module, and accumulates the square values ​​within a complete cycle without storing the original sampling sequence, and calculates the RMS value. Dynamic filtering: The RMS value of C consecutive cycles is subjected to FIR digital filtering by the digital filtering module inside the FPGA. The value of C is dynamically configured by the parameter control module inside the FPGA according to the signal frequency.

[0007] Preferably, the period detection module has a built-in cycle_cnt counter register. The period detection module uses the high-frequency master clock in the FPGA to drive the cycle_cnt counter register and clears the counter register at the instant when the sine wave signal crosses zero from the negative half-cycle to the positive half-cycle.

[0008] Preferably, the high-frequency master clock frequency inside the FPGA is greater than the sampling clock frequency in the high-speed ADC module.

[0009] Preferably, the rising edge signal indicates the rising edge of the square wave signal, corresponding to the instant when the original sine wave signal crosses zero from the negative half-cycle to the positive half-cycle, and characterizes the starting boundary of a complete signal cycle.

[0010] Preferably, the ADC sampled values ​​are squared in real time, the result is stored in a 20-bit wide multi_data register, and the result is accumulated and stored in a 32-bit wide sum_data accumulator register.

[0011] Preferably, the zero-crossing comparator circuit includes a high-speed voltage comparator and a reference voltage source. The non-inverting input of the high-speed voltage comparator is connected to the AC signal to be measured after signal preprocessing, and its inverting input is connected to the reference voltage for real-time comparison of the input signal with the zero-level output transition signal. The output of the high-speed voltage comparator is connected to the digital processing module FPGA.

[0012] Preferably, the RMS value is calculated and its square root is taken according to the following formula, which yields the RMS value for the current period. In the formula, X i For the first i Second ADC sample value; N The cycle length is obtained by accumulating counts in the cycle_cnt register.

[0013] Preferably, the filtered RMS value is transmitted to the parameter control module and then to the host computer via the PCIe interface.

[0014] Preferably, the C value is dynamically configured according to the signal frequency: In the low-frequency band, configure C=1; At high frequencies, configure C=3.

[0015] On the other hand, a root mean square (RMS) detection system is provided, employing the aforementioned RMS detection method. The RMS detection system includes: Signal preprocessing unit: includes a voltage detection circuit, a filter amplification circuit and a zero-crossing comparison circuit connected in sequence. It is used to preprocess the voltage signal to be measured through the filter amplification circuit and the zero-crossing comparison circuit in sequence, generate a square wave signal synchronized with the zero-crossing point of the sine wave, identify the signal period boundary, and transmit it to the FPGA unit to identify a complete and continuous integer number of signal periods. FPGA unit: includes period detection module, data storage and processing module, ADC driver module, RMS calculation module, parameter control module and digital filtering module; The period detection module is used to transmit the identified complete and continuous integer number of signal periods to the data storage and processing module; The ADC driver module is used to transmit the sampled signal from the high-speed ADC module to the data storage and processing module; The RMS calculation module is used to perform square accumulation operation on the sampled signal of the ADC module in the data storage and processing module based on the whole cycle to obtain the RMS value; The digital filtering module is used to perform FIR filtering on the RMS values ​​of C consecutive periods; The parameter control module is used to dynamically configure the C value according to the signal frequency and transmit it to the host computer through the PCIe interface.

[0016] The technical solution includes at least the following technical effects: (1) During the data acquisition stage, the system combines the filter amplifier circuit and the zero-crossing comparison circuit to realize the real-time identification and synchronization of the input sinusoidal signal period; the identified period information is transmitted to the calculation and data storage module in real time to ensure that the voltage data involved in the calculation is a complete and continuous integer number of signal periods, thereby avoiding errors caused by non-integer period sampling.

[0017] (2) In terms of computational implementation, the traditional RMS sliding window calculation method has a long period of time and a lot of sampling data when the input signal is in the low frequency band, which consumes a lot of storage resources. However, due to the regularity of the sampling data, the present invention can simply perform square accumulation and summation of the ADC sampling data during the calculation process and store the calculation results, without having to completely store all the original data in the entire sampling window. This significantly reduces the occupation of internal storage resources and improves the system resource utilization and processing efficiency.

[0018] (3) In terms of result processing, to further improve measurement accuracy, this invention introduces a configurable digital filtering module to perform dynamic error compensation on the calculation results. The filtering parameters can be adjusted online in real time via the PCIE interface, thereby flexibly optimizing filtering performance across different frequency ranges, balancing calculation speed and measurement accuracy. This mechanism effectively solves the problems of slow response in the low-frequency band and decreased accuracy in the high-frequency band of traditional methods, ensuring high-precision, low-latency RMS measurement across the entire frequency range.

[0019] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit the invention. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0021] Figure 1 This is a flowchart of a root mean square (RMS) detection method according to the present invention. Figure 2 This is a schematic diagram of the structure of a root mean square (RMS) detection system according to the present invention; Figure 3 for Figure 1 The schematic diagram of the zero-crossing comparator circuit in the image; Figure 4 The image shows the RMS calculation results of the root mean square (RMS) value detection method of the present invention. Figure 5 The graph shows the RMS calculation results under the traditional sliding window sampling method. Figure 6 The key signal waveforms and timing relationships of the periodic detection module are shown. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0023] As attached Figure 1 As shown, a root mean square (RMS) detection method, taking RMS calculation in ultrasonic signal measurement as an example, includes the following steps: Step S1, Signal periodic synchronization detection: The input voltage signal to be measured is detected in real time by an external analog circuit. After preprocessing by a filtering and amplification circuit, a square wave signal synchronized with the zero-crossing point of the sine wave is generated by a zero-crossing comparator circuit. The zero-crossing point information of the sine wave signal is extracted to identify the signal period boundary. This zero-crossing signal is sent to the period detection module inside the FPGA to identify the periodic characteristics of the signal in real time. That is, it extracts a complete and continuous integer number of signal periods in real time, thereby achieving precise synchronization and segmentation of the input signal period.

[0024] Step S2, cumulative square summation and RMS calculation for the entire period: The period information identified by the period detection module is transmitted to the data storage and processing module inside the FPGA. Simultaneously, the sampled signal from the high-speed ADC module is transmitted to the data storage and processing module via the FPGA's internal ADC driver module. The FPGA's internal RMS calculation module performs point-by-point squaring on the sinusoidal data sampled by the high-speed ADC module and sums the squared values ​​over a complete period, without storing the original sampling sequence. Because this method processes only the data over the entire period, it avoids the integration error caused by the mismatch between sampling depth and signal period in the traditional sliding window method, significantly improving computational accuracy.

[0025] The RMS calculation module has performed the sum of squares for each signal cycle. The RMS value of the current cycle can be calculated according to the following formula. After detecting the instantaneous point where the negative half-cycle of the sine signal crosses zero into the positive half-cycle, the sum of the squares of that cycle and the cycle length signal are sent to the divider module for further square root processing.

[0026] In the formula, X i For the first i Second ADC sample value; N The period length is determined by... Figure 6 The count is obtained by accumulating the count in the cycle_cnt register.

[0027] Step S3, Dynamic Filtering: This invention incorporates an adjustable digital filtering module for error compensation to address noise issues in practical applications. The RMS value for C consecutive cycles is subjected to FIR digital filtering by the FPGA's internal digital filtering module. The filtered RMS value is then transmitted to the host computer via a PCIe interface through the parameter control module. The value of C is dynamically configured by the FPGA's internal parameter control module based on the signal frequency. In the low-frequency range, C=1; in the high-frequency range, C=3.

[0028] In one embodiment, to improve measurement stability and anti-interference capability, the system caches the continuously calculated RMS values ​​for C cycles and performs an FIR digital filtering process after reaching a set number of cycles to further suppress calculation errors and noise disturbances. Parameter C is a configurable variable, and the system can dynamically adjust its value according to the signal frequency: setting it to 1 in the low-frequency band to improve response speed; and appropriately increasing the value of C in the high-frequency band to suppress the influence of quantization noise during ADC sampling. Because the duration of a single cycle is significantly shortened, the cumulative processing delay can still be maintained within the time limit allowed by the system's real-time control, meeting the dynamic response requirements of closed-loop control, thereby achieving high-precision, low-latency RMS measurement of signals across the entire frequency band.

[0029] Based on the analysis of system performance and error sources, this invention further quantifies and evaluates the timing characteristics and accuracy of RMS calculation from the perspective of hardware parameters. If the ADC chip used has a resolution of N bits and a sampling rate of BMhz, and its sampling clock is consistent with the main frequency of the RMS calculation module, the sampling clock period is... If the input signal frequency is AKhz, then the total sampling and calculation time is... for: In the formula, the first term This represents the number of cycles required for the sampling phase, relative to the input signal frequency. A Inversely proportional; the second term is 6 N The clock cycle overhead during the computation phase mainly comes from the divider and square root operation modules, and its complexity is related to the ADC bit width. N Positive correlation; The sampling clock period.

[0030] The RMS calculation of this invention maintains high accuracy from low frequency to high frequency of 200kHz.

[0031] Taking a typical configuration as an example, when using an ADC chip with a 10-bit width and a 50 MHz sampling rate, an input signal frequency of 100 kHz, and C=1, the system requires approximately 11.2 µs to complete one full RMS calculation. As the input signal frequency decreases and the sampling period increases, the computational delay percentage decreases, further improving measurement accuracy. ADC quantization error is the main source of measurement error in the low-frequency band, while ADC sampling speed is the main source of measurement error in the high-frequency band. The sampling signal period is... When the minimum peak-to-peak value of the input signal is 50% of the maximum input range of the ADC, during the sampling clock cycle Sampling signal period When the ADC resolution and other three factors satisfy the following relationship, The maximum measurement error of the system is 1 / 2 N To improve measurement accuracy, an ADC chip with a higher sampling rate and higher resolution (such as 12-bit or 14-bit) can be selected. The sampling clock is 50MHz. When the signal frequency is below 50kHz, a 10-bit high-speed ADC is used, and the maximum measurement error is within 0.1%.

[0032] like Figure 2 As shown, a root mean square (RMS) value detection system is provided, the system comprising: Signal preprocessing unit: includes a voltage detection circuit, a filter amplification circuit and a zero-crossing comparison circuit connected in sequence. It is used to preprocess the voltage signal to be measured through the filter amplification circuit and the zero-crossing comparison circuit in sequence, generate a square wave signal synchronized with the zero-crossing point of the sine wave, identify the signal period boundary, and transmit it to the FPGA unit to identify a complete and continuous integer number of signal periods. FPGA unit: includes period detection module, data storage and processing module, ADC driver module, RMS calculation module, parameter control module and digital filtering module; The period detection module is used to transmit the identified complete and continuous integer number of signal periods to the data storage and processing module. The input of the period detection module is connected to the output of the zero-crossing comparison circuit, and the output of the period detection module is connected to the data storage preprocessing module. The ADC driver module is used to transmit the sampling signal of the high-speed ADC module to the data storage and processing module. The input of the ADC driver module is connected to the high-speed ADC module, and its output is connected to the data storage and processing module. The RMS calculation module is used to perform square accumulation operation on the sampled signal of the ADC module in the data storage and processing module based on an integer cycle to obtain the RMS value; the input terminal of the RMS calculation module is connected to the parameter control module and the data storage and processing module, and the output terminal of the RMS calculation module is connected to the input terminal of the digital filtering module. The digital filtering module is used to perform FIR filtering on the RMS values ​​of C consecutive periods; the output of the digital filtering module is connected to the parameter control module. The parameter control module is used to dynamically configure the C value according to the signal frequency and transmit it to the host computer through the PCIe interface. The PCIe interface enables online real-time adjustment of the filter parameters, thereby flexibly optimizing the filter performance in different frequency ranges while balancing calculation speed and measurement accuracy.

[0033] The period detection module has a built-in cycle_cnt counter register. The period detection module uses the high-frequency master clock in the FPGA to drive the cycle_cnt counter register. At the instant when the sine wave signal crosses zero from the negative half cycle to the positive half cycle, the counter register is cleared. The rising edge signal indicates the rising edge of the square wave signal, which corresponds to the instant when the original sine wave signal crosses zero from the negative half cycle to the positive half cycle, and represents the starting boundary of a complete signal cycle.

[0034] The periodic detection module has the following functions: Detection of period boundary: By identifying the rising edge of the square wave signal output by the zero-crossing comparator circuit (corresponding to the zero-crossing point from the negative half-cycle to the positive half-cycle of the sine wave), the starting point of a complete sine wave cycle is accurately determined.

[0035] High-precision period measurement: Utilizing the high-frequency master clock inside the FPGA, which is much higher than the ADC sampling rate and the input signal frequency, sub-sampling resolution counting measurement is performed on the time interval between the rising edge (level_flip) of the square wave signal.

[0036] Provides a time base: Provides an accurate, full-cycle-based time base (cycle_cnt value) for subsequent RMS calculations. This base ensures that RMS calculations always begin at the end of an integer number of full cycles, and that the data processed is fully aligned periodic data.

[0037] Figure 6The key signal waveforms and timing relationships of the period detection module are demonstrated. The period detection module utilizes the `cycle_cnt` counter register to perform high-precision period measurement of the square wave signal output from the zero-crossing comparator circuit. Since the ADC sampling rate is limited by the chip's sampling rate, it is difficult to accurately capture the zero-crossing moment of the signal. This invention uses a high-frequency master clock inside the FPGA, much higher than the ADC sampling clock, to count the rising edges of the square wave signal at a sub-sampling time resolution, thereby achieving high-precision dynamic measurement of the input sine wave signal period. The rising edge signal `level_flip` identifies the rising edge of the square wave signal, corresponding to the instantaneous point when the original sine wave signal crosses zero from the negative half-cycle to the positive half-cycle, accurately representing the starting boundary of a complete signal cycle. This signal is used as a synchronous trigger node for RMS calculation, ensuring that each RMS operation is based on a complete and aligned integer number of signal cycle data. Through this mechanism, the system can achieve a rapid response to changes in the input signal frequency and provide an accurate time reference for subsequent integer-cycle-based square accumulation and RMS calculation, effectively eliminating leakage errors caused by non-integer-cycle sampling and significantly improving the measurement accuracy and dynamic performance across the entire frequency band.

[0038] like Figure 3 As shown, the zero-crossing comparator circuit includes a high-speed voltage comparator and a reference voltage source. The non-inverting input of the high-speed voltage comparator is connected to the AC signal to be measured after signal preprocessing, and its inverting input is connected to the reference voltage. It is used to compare the input signal with the zero-level output transition signal in real time. The output of the high-speed voltage comparator is connected to the digital processing module FPGA.

[0039] The zero-crossing comparator circuit, based on a high-speed voltage comparator, is used to accurately detect the moment when the AC input signal crosses the zero level. It is a key front-end circuit for achieving signal period synchronization and phase reference extraction. The core of the circuit consists of a high-response, low-propagation-delay voltage comparator and a high-precision, low-noise reference voltage source. The AC signal under test is processed by the pre-filter circuit and then connected to the input terminal TP13 of the comparator, where it is compared with a stable reference voltage in real time. When the input signal rises from the negative half-cycle and crosses the reference voltage threshold, the comparator output jumps to a positive level; when the input signal falls from the positive half-cycle and falls below the reference voltage, the output jumps to a low level. As a result, a square wave signal with a duty cycle close to 50% and synchronized with the fundamental frequency of the input sine wave signal is generated at the output terminal TP14. Its rising and falling edges correspond to the positive and negative zero-crossing moments of the original signal, respectively. This square wave signal has good timing resolution and anti-interference capability, and can be directly used as a trigger reference for subsequent FPGA internal period detection, frequency calculation and RMS synchronization calculation, ensuring that the digital processing module is precisely aligned with the analog input signal in time, and providing a reliable time-domain synchronization signal for high-precision AC parameter measurement.

[0040] like Figure 4 and Figure 5 As shown, the system clock is 50MHz, and RMS calculations are performed on sinusoidal signals with frequencies below 200kHz and 100kHz for verification. The input signal is sampled by a 10-bit resolution ADC and then sent to the RMS calculation module, with a theoretical standard RMS output value of 625.427.

[0041] Figure 4 The RMS calculation result in a preferred embodiment of the present invention is shown. With parameter C configured as 3, the RMS value of 625 is calculated 19.1us after system reset, with an error of 0.07%. Except for a slight fluctuation at the moment of signal frequency switching, the output result has basically no ripple error in the entire calculation process, showing good stability and accuracy consistency.

[0042] Figure 5 The results are RMS calculations using the traditional sliding window sampling method. Due to the long fixed window length, the system requires 33.7 µs to complete one full calculation, which is significantly slower than the method proposed in this invention. Furthermore, significant ripple errors appear in the output signal below 80 kHz, while the overall measurement error reaches 0.4% in the high-frequency range, indicating that it is inferior to the method proposed in this invention in both dynamic response and measurement accuracy.

[0043] Taking the storage resources consumed by a sampling frequency of 100Hz as an example, if the sampling signal period is 10ms, then the traditional method requires 610KB of direct sampled data to be stored, which requires calling 1MB of RAM, as well as registers for the square result and the accumulated result.

[0044] This invention employs a computational architecture based on full-cycle synchronization. A zero-crossing detection mechanism accurately identifies signal cycle boundaries, ensuring that each RMS calculation applies to the sampled data of the entire cycle. Based on this, the algorithm only needs to perform real-time squaring of the ADC sampled values ​​and store the result in a 20-bit wide register, multi_data (e.g., ...). Figure 6 As shown), and the result is accumulated into a 32-bit wide accumulation register sum_data (as shown). Figure 6 As shown in the diagram, there is no need to store the original sampling sequence or retain the intermediate computation states of multiple sliding windows. This directly reduces the on-chip storage resource usage by 1MB. In contrast, the traditional sliding window method lacks the ability to perceive the periodic phase of the signal and cannot accurately identify the critical points of the period. Therefore, it must continuously cache a large amount of historical sampling data and maintain independent sum-of-squares intermediate values ​​for each sliding window. This mechanism leads to the need to use a large number of shift register chains or RAM modules to store the sampling sequence and intermediate results in its RTL implementation, significantly increasing the consumption of logic resources and circuit area.

[0045] In summary, this invention eliminates non-integer-cycle sampling errors by using a zero-crossing comparison circuit and synchronizing with the sub-sampling period. It calculates in real time without storing intermediate sample values ​​and results, thus overcoming resource bottlenecks. Combined with dynamically adjustable FIR filtering, it achieves low-frequency unfiltered operation and high-frequency enhanced noise reduction by configuring parameter C through the PCIE interface. This systematically solves the industry problem of the incompatibility between high and low frequency accuracy and response speed in traditional RMS detection technology. Ultimately, it achieves groundbreaking technical effects such as full-band detection error ≤0.1%, high-frequency response delay as low as 19.1μs, and hardware resource consumption reduced by >99%.

[0046] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0047] The above are merely optional embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for detecting the root mean square (RMS) value, characterized in that, include: Signal period synchronization detection: The voltage signal under test is preprocessed by the filtering and amplification circuit, and a square wave signal synchronized with the zero-crossing point of the sine wave is generated by the zero-crossing comparison circuit. The signal period boundary is identified and transmitted to the period detection module inside the FPGA. The period detection module extracts complete and continuous integer signal periods in real time. The entire cycle square accumulation calculation: The cycle information identified by the cycle detection module is transmitted to the data storage and processing module inside the FPGA. At the same time, the sampling signal of the high-speed ADC module is transmitted to the data storage and processing module through the ADC driver module inside the FPGA. The RMS calculation module inside the FPGA performs point-by-point square operation on the sine wave data sampled by the high-speed ADC module, and accumulates the square values ​​within a complete cycle to calculate the RMS value. Dynamic filtering: The RMS value for C consecutive cycles is subjected to FIR digital filtering by the digital filtering module inside the FPGA. The value of C is dynamically configured by the parameter control module inside the FPGA according to the signal frequency.

2. The root mean square (RMS) detection method according to claim 1, characterized in that, The cycle detection module has a built-in cycle_cnt counter register. The cycle detection module uses the high-frequency master clock in the FPGA to drive the cycle_cnt counter register and clears the counter register at the instant when the sine wave signal crosses zero from the negative half-cycle to the positive half-cycle.

3. The root mean square (RMS) detection method according to claim 2, characterized in that, The high-frequency master clock frequency inside the FPGA is greater than the sampling clock frequency in the high-speed ADC module.

4. The root mean square (RMS) detection method according to claim 2, characterized in that, The rising edge signal indicates the rising edge of the square wave signal, corresponding to the instant when the original sine wave signal crosses zero from the negative half-cycle to the positive half-cycle, and represents the starting boundary of a complete signal cycle.

5. The root mean square (RMS) detection method according to claim 1, characterized in that, The ADC sampled values ​​are squared in real time, and the result is stored in a 20-bit wide multi_data register. The result is then accumulated and stored in a 32-bit wide sum_data accumulator register.

6. The root mean square (RMS) detection method according to claim 1, characterized in that, The zero-crossing comparator circuit includes a high-speed voltage comparator and a reference voltage source. The non-inverting input of the high-speed voltage comparator is connected to the AC signal to be measured after signal preprocessing, and its inverting input is connected to the reference voltage. It is used to compare the input signal with the zero-level output transition signal in real time. The output of the high-speed voltage comparator is connected to the digital processing module FPGA.

7. The root mean square (RMS) detection method according to claim 1, characterized in that, The RMS value is calculated and its square root is applied using the following formula to determine the RMS value for the current period. In the formula, X i The value is the i-th ADC sample; N is the period length, obtained by accumulating the count in the cycle_cnt register.

8. The root mean square (RMS) detection method according to claim 1, characterized in that, The filtered RMS value is transmitted to the parameter control module and then to the host computer via the PCIe interface.

9. The root mean square (RMS) detection method according to claim 1, characterized in that, The C value is dynamically configured based on the signal frequency. In the low-frequency band, configure C=1; At high frequencies, configure C=3.

10. A root mean square (RMS) value detection system, employing the RMS value detection method according to any one of claims 1-9, characterized in that, The RMS testing system includes: The signal preprocessing unit includes a voltage detection circuit, a filter amplification circuit, and a zero-crossing comparison circuit connected in sequence. It is used to preprocess the voltage signal to be measured through the filter amplification circuit and the zero-crossing comparison circuit in sequence, generate a square wave signal synchronized with the zero-crossing point of the sine wave, identify the signal period boundary, and transmit it to the FPGA unit to identify a complete and continuous integer number of signal periods. The FPGA unit includes a periodic detection module, a data storage and processing module, an ADC driver module, an RMS calculation module, a parameter control module, and a digital filtering module; The period detection module is used to transmit the identified complete and continuous integer number of signal periods to the data storage and processing module. The ADC driver module is used to transmit the sampled signal from the high-speed ADC module to the data storage and processing module; The RMS calculation module is used to perform square accumulation operation on the sampled signal of the ADC module in the data storage and processing module based on the whole cycle to obtain the RMS value; The digital filtering module is used to perform FIR filtering on the RMS values ​​of C consecutive periods; The parameter control module is used to dynamically configure the C value according to the signal frequency and transmit it to the host computer through the PCIe interface.

Images