Floating-point number in-memory calculation method and system based on time domain index processing, and medium

Abstract

The invention relates to a floating-point number in-memory calculation method and system based on time domain index processing, and a medium. The floating-point number in-memory calculation method based on time domain index processing comprises the steps that the weight part of the data type of an FP8 is converted into the type of an FP9 to be processed, input indexes and weight indexes are converted into pulse widths to be combined to solve the index sum, and then the number of pulse edges contained under the indexes and the pulse widths is calculated according to the number of the pulse edges contained under the pulse widths to obtain the floating-point number in-memory calculation. And synchronously completing mantissa shift control as a control signal, and synchronously starting subsequent operation by utilizing a maximum delay signal so as to adaptively control a calculation period. The bit widths of the weight index and the input index which need to be operated can be reduced by one bit, the bit width of the weight mantissa is increased by one bit, meanwhile, an index processing module in a digital domain in the prior art is omitted, mantissa shifting is synchronously controlled by utilizing a time domain processing index part, and the operation efficiency is improved. Therefore, the bottleneck problems of multiple cycles and high hardware cost caused by the fact that calculation in the floating-point number memory depends on a digital device are obviously reduced.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing technology, and in particular to an in-memory computing method for floating-point numbers based on time-domain exponential processing, an in-memory computing system for floating-point numbers based on time-domain exponential processing, and a readable storage medium. Background Technology

[0002] In-memory computing designs can be divided into analog-domain in-memory computing and digital-domain in-memory computing. Digital in-memory computing schemes utilize all-digital circuits to perform calculations, integrating digital logic onto the memory array through bit-by-bit multiplication and addition operations to achieve high precision, but also resulting in higher power consumption. Using digital in-memory computing for floating-point calculations contradicts the initial goal of reducing power consumption through an integrated in-memory architecture. Traditional FP data types cannot be directly implemented in the digital domain because the data classification characteristics of FP complicate the calculation logic of digital domain FP MAC, ultimately leading to a decrease in storage density and computing circuit density. Therefore, exponent pre-alignment is commonly used for floating-point calculations. The general principle is: first, align the exponents in the same data set with the largest exponent; then, shift the mantissa and directly perform an INT MAC on the mantissa. This type of calculation mostly uses an all-digital architecture, while digital-domain in-memory computing circuits supporting FP data types contain a large number of digital logic devices. For example, an adder is used to sum the exponent parts, a comparator is used to find the maximum exponent, and a subtraction operation is used to extract the exponent difference. After obtaining the exponent difference, the difference is passed to the mantissa processing module for mantissa product shifting. This process uses a large number of digital logic devices, and the time separation of each operation results in a large number of devices in the circuit being idle for a long time, which leads to problems such as multiple cycles, high area consumption, and high hardware cost. Summary of the Invention

[0003] Therefore, it is necessary to address the problems of existing floating-point in-memory computations, which heavily utilize digital logic devices and have time-separated operations, resulting in a large number of devices in the circuit being idle for extended periods. This leads to problems such as multiple cycles, high area consumption, and high hardware costs. To address these issues, a floating-point in-memory computation method, system, and medium based on time-domain exponential processing should be provided.

[0004] Firstly, this invention proposes a floating-point in-memory computation method based on time-domain exponent processing, which is used for floating-point in-memory computation of K groups of computational objects; the k-th group of computational objects includes: one input exponent E in,k 1 input mantissa M in,k 1 weighted index E w,k 1 weighted mantissa M w,k ;k∈[1,K]; it includes:

[0005] Ew,k The least significant bit is used as M w,k The extension bits, and stored according to E w,k The least significant bit controls M w,k Whether to shift left to the extension bit; according to E in,k The value of the least significant bit controls M w,k To move right; via M w,k The movement operation to E w,k and E in,k Pre-align the least significant bit; after pre-alignment, make M w,k and M in,k The product of the last digits M is obtained through multiplication logic. WIN,k E w,k and E in,k The input digital time converter obtains the corresponding two delayed signals, and their pulse widths are combined to obtain the total delay signal E representing the sum of the exponents. WIN，k Based on E WIN，k and enable signal EN k M is controlled by a shift register. WIN，k Shift right until the maximum delay signal E is encountered. MAX The mantissa MO is output after the falling edge. MO is then accumulated and added to obtain the final mantissa value. MAX The corresponding exponent value is output as the final exponent value; the final mantissa output and the final exponent value output are combined to form the floating-point in-memory calculation result.

[0006] Secondly, the present invention also proposes a floating-point in-memory computation system based on time-domain exponentiation processing, which uses the floating-point in-memory computation method based on time-domain exponentiation processing as described in the first aspect. The floating-point in-memory computation system includes a pre-alignment module, a time-domain conversion module, and a mantissa shifting module.

[0007] The pre-alignment module is used to align E w,k The least significant bit is used as M w,k The extension bits, and stored according to E w,k The least significant bit controls M w,k Whether to shift left to the extension bit; according to E in,k The value of the least significant bit controls M w,k To move right; via M w,k The movement operation to E w,k and E in,k The least significant bit is pre-aligned. The time domain conversion module is used to convert E... w,k and E in,k The input digital time converter obtains the corresponding two delayed signals, and their pulse widths are combined to obtain the total delay signal E representing the sum of the exponents. WIN，k The mantissa shifting module is used for E-based...WIN，k and enable signal EN k M is controlled by a shift register. WIN，k Shift right until the maximum delay signal E is encountered. MAX The mantissa MO is output after the falling edge; MO is then accumulated and added to obtain the final mantissa value. MAX The corresponding exponent value is output as the final exponent value; the final mantissa output and the final exponent value output are combined to form the floating-point in-memory calculation result.

[0008] Thirdly, the present invention also proposes a readable storage medium on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the floating-point in-memory calculation method based on time-domain exponential processing as described in the first aspect.

[0009] The beneficial effects of this invention are:

[0010] 1. This invention reduces the bit width of both the weight exponent and the input exponent by one bit, simplifying exponent calculations. The bit width of the mantissa is increased by one bit to expand the mantissa precision range. Simultaneously, by utilizing DTC for exponent processing, the use of adders, comparators, and subtractors in the digital domain exponent processing module of existing technologies is eliminated. Furthermore, by synchronously controlling the mantissa shift during exponent processing in the time domain, this significantly reduces the bottleneck problem of multi-cycle and high hardware cost inherent in floating-point in-memory calculations that rely on digital devices.

[0011] 2. This invention can adaptively enable the adder tree accumulation operation and subsequent normalization processing by adjusting the arrival time of the maximum delay signal. During training, since the maximum exponent sum generally does not appear near the maximum value, the required calculation cycle is often small. Due to the advantage of this invention in adaptively enabling subsequent operations, the calculation can be completed in a shorter time. Even when the maximum delay signal = 1, the exponent summation, comparison for finding the maximum value, and mantissa shifting operations can be completed in one cycle. In contrast, when using a comparator to compare the exponent sum, regardless of the input data, it is necessary to compare step by step to obtain the maximum value, which cannot be changed periodically. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram illustrating the conversion between the exponent and mantissa bit widths in this embodiment;

[0014] Figure 2 This is a flowchart of the mantissa shift in this embodiment;

[0015] Figure 3 This is a schematic diagram of the structure of the weighted mantissa storage unit in this embodiment;

[0016] Figure 4 This is a schematic diagram of DTC and pulse width conversion in this embodiment;

[0017] Figure 5 This is a schematic diagram comparing the exponential pulse width in this embodiment. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0020] Traditional exponent alignment schemes can lead to precision loss due to right shifting of the mantissa when aligning to the maximum exponent, especially for floating-point types like FP8 with smaller mantissa bit widths, where the precision loss from shifting is even greater. The adders and comparators required for exponent processing are idle during the MAC process, resulting in wasted resources. This embodiment proposes a floating-point in-memory calculation method based on time-domain exponent processing, using FP8 (E4M3) floating-point format as an example. Its core design involves converting the weight portion of the FP8 (E4M3) data type to FP9 (E4M4) for processing. The exponent sum is obtained by converting the exponents of the input and weights into pulse widths and merging them. The number of pulse edges contained in the exponent and pulse width is then used as a control signal to synchronously control the mantissa shift, and the maximum delay signal is used to synchronously initiate subsequent operations to adaptively control the calculation cycle. The following detailed explanation uses the floating-point in-memory calculation of eight sets of calculation objects as an example.

[0021] Floating-point numbers calculated in memory include input floating-point numbers and weighted floating-point numbers. Input floating-point numbers include the input exponent and the input mantissa. Weighted floating-point numbers include the weight exponent and the weight mantissa. First, for the weight portion (weighted floating-point numbers), of the 8 columns of memory used to store FP8, besides the one-bit sign bit, 7 columns are used to store the weight exponent (its bit length is represented as E). w 3E w 2E w 1E w 0) and mantissa (its number of digits is represented as M) w 2M w 1M w 0). For example Figure 1 As shown, this invention preprocesses the weight index and input index: the least significant bit E of the weight index is... w 0 is used as the extension bit of the most significant bit of the weight mantissa (i.e., the least significant bit E of the weight exponent). w 0, expanded to M w 3) Reduce the bit width of the weight exponent to be calculated to 3 bits (E). w 3E w 2E w 1) to expand the mantissa of the weight to 4 bits (M) w 3M w 2M w 1M w 0). Specifically, in this embodiment, the high-order three bits of the weight index are directly stored in a bit depth of E. w 3E w 2E w In the storage unit of 1, then through the least significant bit E of the weighted exponent w Whether E is zero or not determines the location of the weight mantissa: if E w If 0 = 0, then the weighted mantissa is stored in the original mantissa M. w 2M w 1M w 0, the extension bits are padded with 0s at the high bits. If E w If 0 = 1, then shift the weight's last digit one position to the left and store it in M. w 3M w 2M w 1st position, and in the original M w Bit 0 is padded with 0s at the lowest bit level. After the weighted floating-point number is stored, in calculation mode, the same process is performed by inputting the exponent (whose bit value is represented as E). in 3E in 2E in 1E in The least significant bit E of 0) in Whether E is 0 or 1 determines whether the mantissa of the weight is shifted to the right. in If 0 = 1, the weighted mantissa remains in its original position; if E inIf 0 = 0, the weight mantissa is shifted right and padded with 0s in the high-order bits of the extension bit. The above operations are performed by directly reading E. w 0E in The value of 0 controls the shift of the weight mantissa. Since the least significant bit of the input exponent also controls the shift of the weight mantissa, the bit width of both the input exponent and the weight exponent is reduced by one bit during subsequent time-domain transformation operations. Left and right shifts of the weight mantissa are used to pre-align and sum the least significant bits of the weight exponent and the input exponent, effectively performing the calculations in advance. Furthermore, the FP8 (1-4-3) weight floating-point number is converted to FP9 (1-4-4) type for calculation without adding extra storage units, increasing the calculation precision. Simultaneously, the bit width of the weight exponent and the input exponent required for the operation is reduced to 3 bits, facilitating the next time-domain transformation.

[0022] Please refer to Figure 2 After pre-alignment, the weighted mantissa and the input mantissa are multiplied to obtain the mantissa product M. WIN The weighted exponent and the input exponent are input to a digital-to-time converter to obtain the corresponding delayed signals. Their pulse widths are then combined to obtain the total delayed signal E, representing the sum of the exponents. WIN Based on E WIN The enable signal EN is transmitted through a shift register ( Figure 2 SHIFT control in M WIN Shift right until the maximum delay signal E is encountered. MAX The mantissa MO is output after the falling edge. MO is input to the adder tree for mantissa accumulation and addition. MAX The corresponding exponent value is output as the final exponent value, thus obtaining the floating-point in-memory calculation result. The specific processing procedure will be explained in detail below with reference to the accompanying diagram:

[0023] like Figure 3 As shown, M WIN The computational circuitry includes: a memory cell group and AND gates. The memory cell group comprises four columns of 6T SRAM cells (Static Random Access Memory), which are used to store the weighted mantissa bits (including the extended M). w 3) An AND gate has two inputs. One input is connected to the storage node of the memory cell, and the other input is used to input the exponent. The output is used to output M. WINThe calculation circuit uses AND gates to implement the multiplication logic of input and weight. In this embodiment, the 4-bit weight mantissa is stored in 4 columns of 6T SRAM cells. The 3-bit mantissa input is serially input in three cycles starting from the least significant bit. In each cycle, the multiplication operation of 1 bit input and 4 bits weight is completed, and the multiplication result is passed to the lower four bits in the subsequent seven-bit shift register. In each cycle, the shift register is used for shift accumulation operation. After three cycles, the INT type (4×3) multiplication result of all mantissa parts is obtained.

[0024] To transfer exponential processing to the time domain, a Digital Time Converter (DTC) is used to convert the values ​​of the weighted exponent and the input exponent into the length of time, i.e., the pulse width. These pulse widths are then combined to implement the exponential addition logic. This eliminates the need for adders and comparators in the exponential processing module, significantly reducing hardware costs. Furthermore, since the bit width of the weighted exponent and the input exponent is reduced to 3 bits in the preprocessing, when the DTC performs pulse width conversion on the input and weighted exponents (the number of delay units in the DTC corresponds to the bit width of the exponent), taking the 8 sets of calculation objects in this embodiment as an example, reducing the exponent from 4 bits to 3 bits reduces the number of delay units per DTC from 15 to 7, saving over 50% of hardware consumption. Specifically, as... Figure 4 As shown, the DTC in this embodiment can be composed of seven equal delay units connected in series. Each delay unit outputs a delay signal with a pulse width of ΔT. During exponentiation calculation, the DTC reads the weighted exponent and uses the read weighted exponent value to control the selector to select the corresponding delay unit to output the weighted portion delay signal S. W Then S W This information is then passed to the next-level DTC (i.e., the DTC that processes the input exponent). Similarly, the input exponent value also controls the corresponding input delay signal S at the output. IN This way, S w and S in The combined result of these two parts is the total delay signal E representing the sum of the input weight exponents. WIN Iterate through each input exponent to obtain multiple sets of E. WIN And select the maximum value of E. WIN As the maximum delay signal E MAX .like Figure 5 As shown, this embodiment takes 8 sets of input indices and weight indices as an example. When the weight index is 111, S with a value of 7Δt is selected. W Pass it to the next DTC. Select S again with 7Δt when the exponent is 111. IN The final output is the E of the combined 14Δt pulse width. WIN The 14Δt pulse width signal represents the largest exponential sum generated in this embodiment, namely E.MAX When the weight exponent is 0.01, choose S with a weight of 1Δt. W Pass it to the next DTC. Select S again for 1Δt when the exponent is 001. IN The final output is the E of the combined 2Δt pulse width. WIN The 2Δt pulse width signal represents the minimum exponential sum generated in this embodiment. Similarly, in other cases, the generated E... WIN The length of each pulse is determined by the corresponding input index and weight index. Furthermore, in this embodiment, since the combined total pulse width has the same starting edge, the eight weight indices in the first stage can share a single DTC output S. W The falling edge of the pulse width selected by the first DTC will serve as the start of the second delay segment. Since the falling edges of the pulse widths output by the DTC are asynchronous, a separate DTC needs to be set up in the second stage for each group of computational objects to extend the pulse width from the first stage, thus merging the two pulse widths. That is, the eight input exponents will each use their corresponding DTC output S. IN .

[0025] Please refer to this again. Figure 5 E MAX Find all E using an OR gate. WIN The maximum value in E is obtained. MAX The final output will be converted to a digital output via a counter. Because E WIN The length of the exponent represents the magnitude of the sum of the exponents, so the E in each group... WIN The falling edge and E MAX The time interval between the falling edges represents the difference between the sum of the exponents and the maximum sum of exponents. This time interval can then be used as the enable signal EN to control the shift of the mantissa product stored in the shift register. When EN = 1, the data in the shift register will be shifted two bits to the right (the least significant bit of the exponent after pre-alignment is actually the second least significant bit of the original exponent, with a weight of 2 (binary). Therefore, a difference of one in the exponent value corresponds to a shift of two bits in the mantissa). When EN = 0, the data in the shift register will remain unchanged. Figure 4 As shown, when E WIN =2Δt, E MAX When = 14Δt, the time difference between the two delayed signals, 14 - 2 = 12Δt, represents the difference in the exponential sums, which is 12. Therefore, the EN group will contain the 12 falling edges of the pulse CLK. Here, EN is E WIN E MAX Generated via an XOR gate (general-purpose logic circuit). CLK originates from a pulse generation module in the external circuitry. During the period when EN is high, each of the 12 falling edges of CLK will trigger a right shift register by two bits. In summary, in M...WIN Simultaneously with the input shift register, the first-stage DTC (processing the weighted exponent) begins operation, and the second-stage DTC (processing the input exponent) automatically starts operation after the first-stage pulse width output. During the pulse width conversion between the two DTCs, an XOR gate generates EN, synchronously controlling the mantissa shift during the pulse width delay. For hardware details, please refer to [link to relevant documentation]. Figure 2 First, the 4-bit mantissa read from the weight part and the 3-bit mantissa of the input part are processed by an AND gate to form a calculation circuit and multiplication logic to obtain a 7-bit (4b×3b) M. WIN The 7-bit M WIN The data is input into a shift register (in this embodiment, the shift register includes seven edge-triggered flip-flops, the output of each flip-flop is connected to the input of the flip-flop to its right, and the data is input and output in parallel). Then, when each group of E... WIN (In this embodiment, 7 bits correspond to 7 total delay signals E) WIN0 ~E WIN6 Before the falling edge of ) arrives, EN remains low, allowing the shift register to retain the product result, i.e., M. WIN Unchanged. When E WIN When the falling edge of the signal arrives (EN signal goes high to enable), E... WIN EN will be multiplied by the mantissa M in the shift register. WIN To prepare for the right shift, each cell has a falling edge of pulse CLK within its pulse width Δt. Upon each falling edge, the shift register will cause M to... WIN Move two units to the right, eventually reaching E. MAX When the falling edge arrives, all ENs will be turned off, at which point all mantissa products M will be... WIN They have all been shifted by the corresponding number of bits. E MAX The falling edge of the synchronous control register will pass the shifted 7-bit mantissa output MO (corresponding to the parallel output of 7 mantissa outputs MO0 to MO6) to the adder tree for subsequent mantissa accumulation. MAX The corresponding exponent value is converted into the final exponent value output, thus obtaining the floating-point in-memory calculation result. During the DTC conversion process, the smallest E... WIN When the falling edge of the exponent arrives, the corresponding mantissa product shift operation is initiated. Different exponents of different magnitudes complete their corresponding mantissa shift control in sequence during this process. When the falling edge of the maximum pulse width appears (i.e., when E is encountered), the shift operation is initiated. MAX The mantissa shift operation is completed on the falling edge of the exponent, without waiting for the exponent difference to be extracted and then passed to the mantissa module.

[0026] Combination Figure 2 Figure 5The best case study can be analyzed in E MAX In smaller cases, for example, E. MAX When = 1, E for each group WIN There are only two possibilities: 0 and 1. When E WIN When E = 0, only one right shift is needed. WIN =1 (E) WIN =E MAX In this case, no shifting is required. The exponentiation and mantissa shifting operations can be completed in a single pulse, and the subsequent adder tree accumulation operation can be adaptively and synchronously initiated. The worst-case scenario occurs in E... MAX＝ In the case of 14, 14 pulses are required to complete the exponent comparison and mantissa shift control. Furthermore, with the maximum exponent, more shift operations will result in greater dynamic power consumption.

[0027] In summary, compared to traditional digital schemes, pulse width delay merging eliminates the need for adders, while traditional adders require waiting for carry-in from the lower bit, and carry-lookahead adders require more complex structures. Furthermore, pulse width comparison eliminates the need for comparators and reduces the number of cycles required for step-by-step comparisons in large-scale multi-row parallel comparisons. Utilizing the falling edge of the pulse width as a shift control signal eliminates the need for subtractors to extract the exponent difference. This embodiment significantly improves upon the high resource consumption and multiple cycle limitations of in-memory computation for floating-point numbers in the digital domain. On the other hand, this embodiment achieves the addition of input and weight exponents through pulse width merging, applicable to computational scenarios where weights are constantly updated. By reducing the exponent width of the operation and sharing the first DTC, it does not consume excessive additional hardware. Furthermore, this embodiment can be adapted to training requirements with different bit widths by adding mantissa storage column units. Specifically, in terms of hardware for exponentiation processing, each group of computational objects requires only one DTC in the second stage (the first-stage DTC can be shared), and each DTC can be implemented with 7 delay units, totaling 28 MOSFETs. In contrast, traditional digital in-memory computing schemes require a 4-bit adder (a basic serial carry 4-bit adder requires at least 50 MOSFETs) and a 4-bit subtractor (approximately 100 MOSFETs) per group of exponentiation operations to achieve the same logic. Furthermore, multiple 5-bit comparators are needed when comparing multiple exponentiation results. In this case, implementing the same logic for each group of exponentiation operations saves approximately 80% of MOSFET consumption, and traditional comparators require step-by-step comparisons under any data conditions, while the DTC's pulse width operation time is adaptive.

[0028] In another embodiment, a floating-point in-memory computation system based on time-domain exponentiation processing is also proposed, which uses the floating-point in-memory computation method based on time-domain exponentiation processing as described in the above embodiment. This floating-point in-memory computation system is used for floating-point in-memory computation of K groups of computational objects. The k-th group of computational objects includes: one input exponent E. in,k 1 input mantissa M in,k 1 weighted index E w,k 1 weighted mantissa M w,k , k∈[1,K]. It includes: pre-alignment module, time domain transformation module, and mantissa shift module.

[0029] The pre-alignment module is used to align E w,k The least significant bit is used as M w,k The extension bits, and stored according to E w,k The least significant bit controls M w,k Whether to shift left to the extension bit. According to E in,k The value of the least significant bit controls M w,k Should we move right? (via M) w,k The movement operation to E w,k and E in,k The least significant bit is pre-aligned. The time domain conversion module is used to convert E... w,k and E in,k The input digital time converter obtains the corresponding two delayed signals, and their pulse widths are combined to obtain the total delay signal E representing the sum of the exponents. WIN，k The mantissa shifting module is used for E-based... WIN，k and enable signal EN k M is controlled by a shift register. WIN，k Shift right until the maximum delay signal E is encountered. MAX The mantissa MO is output after the falling edge. MO is then accumulated and added to obtain the final mantissa value. E MAX The corresponding exponent value is output as the final exponent value. The final mantissa output and the final exponent value output are combined to form the floating-point number calculation result.

[0030] In another embodiment, a readable storage medium storing a computer program is also proposed. When executed by a processor, this computer program implements the steps of the floating-point in-memory calculation method based on time-domain exponential processing as described in the above embodiment. It should be noted that, as those skilled in the art will understand, the readable storage medium provided by this invention can be any combination of one or more computer-readable media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable computer hard disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, apparatus, or device.

[0031] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0032] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A floating-point in-memory calculation method based on time-domain exponential processing, characterized in that, It is used for in-memory floating-point calculations of K groups of computational objects; the k-th group of computational objects includes: 1 input exponent E in,k 1 input mantissa M in,k 1 weighted index E w,k 1 weighted mantissa M w,k ;k∈[1,K];It includes: E w,k The least significant bit is used as M w,k The extension bits, and stored according to E w,k The least significant bit controls M w,k Whether to shift left to the extension bit; according to E in,k The value of the least significant bit controls M w,k To move right; via M w,k The movement operation to E w,k and E in,k Pre-align the least significant bit; after pre-alignment, make M w,k and M in,k The product of the last digits M is obtained through multiplication logic. WIN,k E w,k and E in,k The input digital time converter obtains the corresponding two delayed signals, and their pulse widths are combined to obtain the total delay signal E representing the sum of the exponents. WIN，k ; Based on E WIN，k and enable signal EN k M is controlled by a shift register. WIN，k Shift right until the maximum delay signal E is encountered. MAX Output the mantissa MO after the falling edge; The final mantissa value is output by accumulating and adding the mantissas of MO; E MAX The corresponding exponent value is output as the final exponent value; the final mantissa output and the final exponent value output are combined to form the floating-point in-memory calculation result.

2. The floating-point in-memory calculation method based on time-domain exponential processing according to claim 1, characterized in that, If E w,k If the least significant bit is 0, then M w,k If E remains unchanged, pad with 0s in the extension bits; w,k If the least significant bit is 1, then M will be... w,k Shift left by one bit so that M w,k The high-order bit is in the extension bit, and in M w,k Fill the lower digits with 0; If E in,k If the least significant bit is 1, then M w,k Unchanged; if E in,k If the least significant bit is 0, then M w,k Shift right by one bit and fill the extension bit with 0.

3. The floating-point in-memory calculation method based on time-domain exponential processing according to claim 1, characterized in that, E MAX The acquisition methods include: traversing K input exponents to obtain K total delay signals E. WIN,0～ E WIN,K-1 And select the maximum value as E. MAX ; EN k The methods for obtaining E include: WIN，k The falling edge and E MAX The time interval between the falling edges is used as EN k .

4. The floating-point in-memory calculation method based on time-domain exponential processing according to claim 1, characterized in that, M WIN，k The computing circuit includes: A group of storage cells, comprising multiple SRAM cells, is used to store data for extended bits and weighted mantissa bits; An AND gate, with one input connected to the storage node of the memory cell, and the other input used for E. in,k The input terminal is used to output M. WIN，k .

5. The floating-point in-memory calculation method based on time-domain exponential processing according to claim 1, characterized in that, The digital time converter comprises N cascaded delay units; each of the N delay units outputs a delay signal with a pulse width of ΔT; the nth delay unit outputs a delay signal with a pulse width of nΔT; n∈[1,N]; According to E w,k The value controls the output weighted delay signal S of the nth delay unit. W According to E in,k The value controls the output input delay signal S of the q-th delay unit. IN ;S w and S in The total delay signal E is obtained by combining the signals. WIN，k ; q∈[1,N].

6. The floating-point in-memory calculation method based on time-domain exponential processing according to claim 5, characterized in that, Multiple E w,k Shared digital time converter output S W Multiple E in,k Output S using the corresponding digital time converters respectively IN .

7. The floating-point in-memory calculation method based on time-domain exponential processing according to claim 5, characterized in that, Control M WIN，k The method for moving to the right includes the following steps: Get E WIN，k The falling edge and E MAX The number of falling edges of the pulse CLK between the falling edges; where the period length of CLK is ΔT; M is encountered at each falling edge of CLK WIN，k Move two units to the right until you encounter E. MAX The mantissa MO is output after the falling edge.

8. The floating-point in-memory calculation method based on time-domain exponential processing according to claim 1, characterized in that, When each group's E WIN，k Before the falling edge arrives, EN k Keep it low, the shift register holds M WIN，k constant; When E WIN，k When the falling edge arrives, EN k When it becomes high, E WIN，k EN k M in the control shift register WIN，k Move right until E MAX When the falling edge arrives, EN k Close, M WIN，k The shift is complete.

9. A floating-point in-memory computing system based on time-domain exponential processing, characterized in that, It uses the in-memory floating-point calculation method based on time-domain exponential processing as described in any one of claims 1 to 8; It includes: Pre-alignment module, which is used to align E w,k The least significant bit is used as M w,k The extension bits, and stored according to E w,k The least significant bit controls M w,k Whether to shift left to the extension bit; according to E in,k The value of the least significant bit controls M w,k To move right; via M w,k The movement operation to E w,k and E in,k Pre-align the least significant bit; The time domain transformation module is used to convert E... w,k and E in,k The input digital time converter obtains the corresponding two delayed signals, and their pulse widths are combined to obtain the total delay signal E representing the sum of the exponents. WIN，k ; The mantissa shift module is used for E-based... WIN，k and enable signal EN k M is controlled by a shift register. WIN，k Shift right until the maximum delay signal E is encountered. MAX The mantissa MO is output after the falling edge; MO is then accumulated and added to obtain the final mantissa value. MAX The corresponding exponent value is output as the final exponent value; the final mantissa output and the final exponent value output are combined to form the floating-point in-memory calculation result.

10. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the floating-point in-memory calculation method based on time-domain exponential processing as described in any one of claims 1 to 8.

Images