A cache line priority resetting method and an artificial intelligence chip

Abstract

The application provides a cache line priority resetting method and an artificial intelligence chip, and relates to the technical field of artificial intelligence chips.The method comprises the following steps: when it is detected that a cache group contains a cache line in a first priority state (i.e., the priority is greater than a preset level) and a target time length (i.e., an interval time length from the last time the cache group is accessed by a data request carrying a priority prompt) is greater than a preset time length, the request state between a processing core and a cache is detected; when the request state is that no data request sent by the processing core is detected, a priority resetting process is spontaneously initiated, and the priority of the cache line in the first priority state in the cache group is adjusted to the preset level; in this way, the priority of the cache line is reset by the hardware itself, the cache space is prevented from being occupied by the cache line with a high priority for a long time, the cache space reserved for non-important data access is improved, the overall performance of the cache is improved, and meanwhile, the processing of the data request (i.e., normal access) of the processing core is not affected.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence chip technology, and in particular to a method for resetting the priority of cache lines and an artificial intelligence chip. Background Technology

[0002] In caching, cache lines are typically divided into multiple priority levels. Higher-priority cache lines are less likely to be replaced. In practice, the priority of the cache line containing the data is configured according to its importance. The more important the data in the cache line, the higher its priority. For data that will be used immediately or frequently over a long period (i.e., important data), the corresponding cache line is configured with a high priority, allowing this data to remain in the cache. For data that will not be used for a long time or will never be used again (i.e., unimportant data), the corresponding cache line is configured with a low priority, making this data more likely to be replaced, thus freeing up more cache space for other data.

[0003] However, the above approach can cause high-priority cache lines to occupy cache space for a long time, resulting in less cache space reserved for accessing non-critical data, which in turn affects the overall performance of the cache. Summary of the Invention

[0004] This application provides a method for resetting the priority of cache lines and an artificial intelligence chip, which avoids high-priority cache lines from occupying cache space for a long time, thereby increasing the cache space reserved for accessing non-critical data and thus improving the overall performance of the cache.

[0005] On one hand, embodiments of this application provide a method for resetting the priority of cache lines, the method comprising:

[0006] The status information of multiple cache groups in the cache is detected. The status information includes priority status and target duration. The target duration represents the time interval since the cache group was last accessed by a data request carrying a priority hint.

[0007] For each cache group, if the priority status of the cache group is a cache line containing a first priority status, and the target duration is greater than a preset duration, then the request status between the processing core and the cache is detected, where the first priority status indicates that the priority is greater than a preset level.

[0008] If the request status is "no data request sent by the processing core is detected", then at least one cache line in the cache group with the first priority status is determined, and the priority of each of the at least one cache line is adjusted to the preset level.

[0009] Optionally, determining at least one cache line in the cache group with the first priority state includes:

[0010] Read the tag information for each cache line in the cache group from the tag memory;

[0011] For each cache line's tagging information, if the tagging information contains a priority hint and the priority hint indicates the first priority state, then the cache line is determined to be in the first priority state.

[0012] Optionally, adjusting the priority of each of the at least one cached line to the preset level includes:

[0013] For each of the at least one cached lines, execute:

[0014] Update the priority hint included in the tagging information of the cached line so that the priority hint indicates that the priority is the preset level.

[0015] Optionally, after adjusting the priority of each of the at least one cached line to the preset level, the method further includes:

[0016] Update the priority status of the cache group to: cache lines that do not contain the first priority status;

[0017] Set the target duration to zero.

[0018] Optionally, it also includes:

[0019] Receive a data request sent by the processing core, the data request carrying a priority indication, the priority indication indicating the first priority state;

[0020] When the data request hits or is assigned a cache line, the priority hint is added to the tagging information of the cache line.

[0021] Optionally, after adding the priority hint to the tagging information of the cache line when the data request hits or is allocated a cache line, the method further includes:

[0022] If the priority status of the cache group to which the cache line belongs is: not containing cache lines with the first priority status, then the priority status of the cache group is updated to: containing cache lines with the first priority status.

[0023] Optionally, the data request further includes: a cache group index; after receiving the data request sent by the processing core, it further includes:

[0024] When the cache group index hits a cache group, the target duration corresponding to the cache group is set to zero.

[0025] Optionally, the data request can be a read request or a write request.

[0026] On one hand, embodiments of this application provide an artificial intelligence chip, including:

[0027] Processes the core, cache, and main memory;

[0028] The cache is used to execute the steps of the above-mentioned cache line priority reset method.

[0029] On one hand, embodiments of this application provide a computer device, including a memory, an artificial intelligence chip, and a computer program stored in the memory and executable on the artificial intelligence chip. When the artificial intelligence chip executes the computer program, it implements the steps of the above-mentioned cache line priority reset method.

[0030] In this embodiment of the application, when a cache group is detected to contain cache lines in the first priority state (i.e., priority greater than a preset level), and the target duration (i.e., the interval between the last access to the cache group by a data request carrying a priority indicator) is greater than the preset duration, it indicates that the cache group has not been accessed by high-priority requests for a long time. Therefore, a priority reset process is initiated spontaneously to reduce the priority of the cache lines in the first priority state in the cache group, effectively preventing high-priority cache lines from occupying cache space for a long time, thereby increasing the cache space reserved for non-important data access and thus improving the overall performance of the cache.

[0031] Secondly, before initiating the priority reset process for the cache group, the request status between the processing core and the cache is checked; when the request status is that no data request sent by the processing core is detected, the priority reset process is initiated spontaneously, and the priority of the cache line in the first priority status in the cache group is adjusted to the preset level; in this way, not only can the hardware spontaneously reset the cache line priority, but it will not affect the processing of data requests (i.e., normal access) of the processing core. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A schematic diagram of the structure of an artificial intelligence chip provided in this application embodiment. Figure 1 ;

[0034] Figure 2 A schematic diagram of the structure of an artificial intelligence chip provided in this application embodiment. Figure 2 ;

[0035] Figure 3 This application provides a schematic diagram of the structure of an automatic high-priority engine reset according to an embodiment of the present application.

[0036] Figure 4 A flowchart illustrating a method for resetting the priority of cache lines provided in this application embodiment. Figure 1 ;

[0037] Figure 5 A flowchart illustrating a status information update method provided in an embodiment of this application;

[0038] Figure 6 A flowchart illustrating a method for resetting the priority of cache lines provided in this application embodiment. Figure 2 ;

[0039] Figure 7 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0041] refer to Figure 1 The diagram shows the structure of an artificial intelligence chip applicable to the embodiments of this application. The artificial intelligence chip 100 includes at least a processing core 101, a cache 102, and main memory 103. The processing core 101 has the ability to perform artificial intelligence-related calculations, such as matrix multiplication and convolution operations, which are common calculation operations in artificial intelligence models.

[0042] Cache 102 is a small, fast storage area located between processing core 101 and main memory 103. It is used to temporarily store data or instructions that processing core 101 or other hardware devices may frequently access in the near future, with the aim of speeding up access and reducing access latency.

[0043] Main memory 103 is the next level below cache 102. Main memory 103 is the main memory device directly accessed by processing core 101. Compared to cache 102, main memory 103 generally has a larger capacity but is slower. When processing core 101 accesses data, if the data is not in cache 102 (i.e., cache miss), it loads the data from main memory 103 into cache 102 (usually loaded line by line), and subsequent accesses can directly read from cache 102.

[0044] In this embodiment, cache 102 detects the status information of multiple cache groups, including priority status and target duration. The target duration represents the interval since the cache group was last accessed by a data request carrying a priority indicator. For each cache group, if the priority status of the cache group includes cache lines with a first priority status (i.e., priority greater than a preset level) and the target duration is greater than the preset duration, the request status between processing core 101 and cache 102 is detected. If the request status is that no data request sent by processing core 101 is detected, at least one cache line with a first priority status in the cache group is identified, and the priority of each of the at least one cache line is adjusted to the preset level.

[0045] In some embodiments, see Figure 2 The cache 102 includes: a selector 201, a tag ram 202, a hit-miss check unit 203, a cache ram 204, and an auto reset-high-priority engine 205.

[0046] Specifically, the tag memory 202 is used to store tag information for each cache line in multiple cache sets, where a cache set is a logical group consisting of multiple cache lines. A cache line is the smallest unit of data stored in cache 102, and the size of a cache line may vary under different hardware architectures; for example, 32 bytes, 64 bytes, 128 bytes, etc.

[0047] The cache line is also the smallest unit of operation in cache 102; when reading data (such as an integer or floating-point number) from cache 102, not only this one piece of data is read, but the entire cache line containing that data (e.g., 64 bytes) is read together.

[0048] For a cache line, the cache line includes: data and tagging information. The tagging information includes: tag, valid bit, and dirty bit. The tag is used to identify the address range of the data in main memory; the valid bit indicates whether the data is valid; the dirty bit indicates whether the data has been modified, that is, whether it is consistent with main memory.

[0049] The cache memory 204 stores the data in each cache line. The tag information stored in the tag memory 202 has a one-to-one correspondence with the data stored in the cache memory 204.

[0050] In this embodiment, cache 102 receives data requests sent by processing core 101, which are either read or write requests. The data request carries a priority hint, indicating the first priority state. The size of the priority hint is determined based on the number of priorities that need to be represented.

[0051] For example, if there are two priorities, namely high priority and low priority, the priority hint size is 1 bit, where 1 represents high priority and 0 represents low priority. As another example, if there are three priorities, namely high priority, medium priority, and low priority, the priority hint size is 2 bits, where 00 represents low priority, 01 represents medium priority, and 10 represents high priority.

[0052] The priority hint carried in the data request defaults to the highest priority; however, the preset level can be set according to actual needs. For example, when the priority hint is 1 bit, the preset level is low priority, and the priority hint carried in the data request defaults to 1, indicating high priority.

[0053] For example, when the priority hint is 2 bits, the default level is medium priority, and the priority hint carried in the data request is 10 by default, indicating high priority.

[0054] After receiving a data request sent by the processing core 101, the selector 201 prioritizes processing the data request; thus, the hit checking unit 203 reads the tag information of each cache line from the tag memory 202; and then performs a hit check on the data request based on the read tag information.

[0055] Specifically, data requests also include: memory addresses; during hit checks, the corresponding cache group is first queried based on the cache group index in the memory address; when the cache group index hits a cache group, the high-priority engine 205 is automatically reset to set the target duration corresponding to that cache group to zero.

[0056] Next, the tag in the memory address is compared one by one with the tag information of each cache line under the cache group to obtain the check result. When a data request hits or is allocated a cache line, a priority hint is added to the tag information of that cache line, and the updated tag information is updated in the tag memory 202.

[0057] At the same time, the automatic reset of the high-priority engine 205 is triggered to update; specifically, if the priority status of the cache group to which the cache line belongs is: cache lines that do not contain the first priority status, then the automatic reset of the high-priority engine 205 will update the priority status of the cache group to: cache lines that contain the first priority status.

[0058] When a data request hits or is allocated a cache line, if the data request is a read request, the data of the cache line is read from cache memory 204, which may have been previously read from main memory 103; then, a request response is returned to processing core 101, which carries the read data.

[0059] If the data request is a write request, the target data carried by the write request will be written to the storage area corresponding to the cache line in the cache memory 204, and a request response will be returned to the processing core 101, which indicates that the write is complete.

[0060] In some embodiments, see Figure 3 The automatic high-priority engine 205 includes: a cache group status detection unit 301, an occupancy status detection unit 302, and a decision unit 303.

[0061] The cache group status detection unit 301 is used to detect the status information of each cache group, including priority status and target duration. The occupancy status detection unit 302 is used to detect the request status between the processing core 101 and the cache 102.

[0062] The request status between processing core 101 and cache 102 includes: currently receiving a data request from processing core 101 and currently not receiving a data request from processing core 101.

[0063] If the cache group status detection unit 301 determines that the priority status of a cache group is: a cache line containing the first priority status and the target duration is greater than the preset duration; and the occupancy status detection unit 302 determines that the request status is: no data request has been received from the processing core 101, then the decision unit 303 initiates a priority reset request for the cache group.

[0064] At this time, selector 201 selects to process the priority reset request, so that hit check unit 203 reads the tag information of each cache line in the corresponding cache group from tag memory 202 according to the cache group index carried in the priority reset request.

[0065] For the tagging information of each cache line in the cache group, if the tagging information contains a priority hint and the priority hint indicates the first priority state, then in the tagging memory 202, the priority hint is adjusted to indicate a preset level (i.e., the priority of the cache line is reduced).

[0066] When the priority of each cache line in the cache group is not greater than the preset level, the cache group status detection unit 301 updates the status information of the cache group, specifically by updating the priority status of the cache group to: cache lines that do not contain the first priority status; and at the same time, setting the target duration corresponding to the cache group to zero.

[0067] In this embodiment of the application, when it is detected that the cache group contains cache lines in the first priority state, and the target duration (i.e., the interval between the last access of the cache group by a data request carrying a priority indication) is greater than the preset duration, it indicates that the cache group has not been accessed by high priority for a long time. Therefore, a priority reset process is initiated spontaneously to reduce the priority of the cache lines in the first priority state (i.e., high priority) in the cache group, effectively preventing high priority cache lines from occupying cache space for a long time, thereby increasing the cache space reserved for non-important data access, and thus improving the overall performance of the cache.

[0068] Secondly, before initiating the priority reset process for the cache group, the request status between the processing core 101 and the cache 102 is checked; when the request status is that no data request sent by the processing core 101 is detected, the priority reset process is initiated spontaneously, and the priority of the cache line in the first priority status in the cache group is adjusted to the preset level; in this way, not only can the hardware spontaneously reset the cache line priority, but it will not affect the processing of data requests (i.e., normal access) of the processing core.

[0069] In addition to the structure described above, the artificial intelligence chip 100 in this application may also include other structures, and this application does not specifically limit such structures.

[0070] Artificial intelligence chips 100 can be: Graphics Processing Unit (GPU), General-Purpose Graphics Processing Units (GPGPU), Domain Specific Architecture (DSA), etc.

[0071] The following is based on Figure 1 The diagram shown illustrates the architecture of an AI chip and details the process of a method for resetting the priority of cache lines. (See also...) Figure 4 This method is executed by a cache in an artificial intelligence chip and includes the following steps:

[0072] Step 401: Detect the status information of each of the multiple cache groups in the cache.

[0073] Specifically, the status information includes: priority status and target duration. Priority status indicates whether the cache group contains cache lines with a first-priority status; a first-priority status means the priority is higher than a preset level. The priority status of a cache group can correspond to different values, and the meaning of the priority status varies depending on the value.

[0074] For example, the priority status of a cache group is represented by 1 bit. When the priority status value is 0, it means that the cache group does not contain cache lines with the first priority status; when the priority status value is 1, it means that the cache group contains cache lines with the first priority status.

[0075] The target duration represents the time elapsed since the last access to the cache group by a data request carrying a priority indicator. The priority indicator carried by the data request defaults to first priority; that is, when a data request carries a priority indicator, it means that the data request is a high-priority access request. A longer target duration indicates a longer interval between high-priority accesses to the cache group.

[0076] In some embodiments, a data request sent by the processing core is received, the data request including: a cache group index; when the cache group index hits a cache group, the target duration corresponding to the cache group is set to zero.

[0077] The corresponding cache group is queried based on the cache group index; when the cache group index hits a cache group, the target duration corresponding to that cache group is set to zero.

[0078] In some embodiments, the data request also carries a tag and a priority hint, whereby the priority hint indicates a first priority state. When a data request hits or is allocated a cache line, the priority hint is added to the tagging information of that cache line.

[0079] Specifically, when a cache group index hits a cache group, the tag carried by the data request is compared one by one with the tag information of each cache line under the cache group to obtain the check result.

[0080] When the check result is that the data request hits the tag information of a cache line, that is, there exists a cache line whose tag information contains the tag carried by the data request and the cache line is valid, then a priority hint is added to the tag information of the cache line to indicate that the cache line is in the first priority state (i.e., a high priority cache line).

[0081] When the check result is that the data request does not hit the tag information of any cache line, that is, no cache line's tag information contains the tag carried by the data request, a cache line is allocated for the data request, and a priority hint is added to the tag information of the cache line to indicate that the cache line is in the first priority state.

[0082] In some embodiments, if the priority status of the cache group to which the cache line belongs is: cache lines that do not contain the first priority status, then the priority status of the cache group is updated to: cache lines that contain the first priority status.

[0083] Of course, if the priority status of the cache group already indicates that it contains cache lines with the first priority status (that is, in the cache group, in addition to the cache line that the data request hit or was allocated, there are other cache lines with the first priority status), then there is no need to update the priority status of the cache group.

[0084] For example, see Figure 5 The priority hint size is set to 1 bit, where 1 represents high priority and 0 represents low priority; the default priority level is low. The tag memory stores the tag information for six cache lines: tag information 1 for cache line 1, tag information 2 for cache line 2, tag information 3 for cache line 3, tag information 4 for cache line 4, tag information 5 for cache line 5, and tag information 6 for cache line 6. Cache lines 1, 2, and 3 are located in cache group A; cache lines 4, 5, and 6 are located in cache group B.

[0085] The system receives and processes data requests sent by the core. The data requests carry a cache group index, a tag, and a priority hint. The cache group index is set to "A", the tag is set to "0x12", and the priority hint is set to "1".

[0086] First, locate cache group A based on the cache group index, and then read the tag information of each cache line in cache group A from the tag memory, namely tag information 1, tag information 2 and tag information 3.

[0087] The tag carried in the data request is compared one by one with tag information 1, tag information 2 and tag information 3; assuming that the tag carried in the data request matches tag information 1, the priority hint carried in the data request is added to tag information 1, and then the updated tag information 1 is saved to the tag memory.

[0088] Next, the priority state of cache group A is set to 1, indicating that cache group A contains high-priority cache lines; at the same time, the target duration of cache group A is set to 0.

[0089] In this embodiment of the application, after performing a hit check on the data request, when the data request hits or is allocated a cache line, the tag information of the cache line is updated accordingly; at the same time, the current cache group is recorded at the granularity of the cache group to see whether it contains a cache line with the first priority state, instead of recording whether the priority of each cache line is greater than the preset level. This reduces the number of priority states, thereby reducing the consumption of trigger resources.

[0090] Step 402: For each cache group, if the priority status of the cache group is a cache line containing the first priority status, and the target duration is greater than the preset duration, then check the request status between the processing core and the cache.

[0091] Specifically, when a cache group contains cache lines in the first priority state and the target duration is longer than the preset duration, it means that the cache group has not been accessed by high priority for a long time. In other words, the high priority cache lines contained in the cache group will not be accessed for a long time. Therefore, the priority of these cache lines can be reduced accordingly, i.e., a priority reset process can be initiated.

[0092] Before initiating a priority reset process for this cache group, the request status between the processing core and the cache is checked; if the request status is that no data request sent by the processing core is detected, the priority reset process is initiated automatically; if the request status is that a data request sent by the processing core is detected, the data request sent by the processing core is executed first.

[0093] Step 403: If the request status is "no data request sent by the processing core is detected", then determine at least one cache line in the cache group with the first priority status, and adjust the priority of each of the at least one cache line to the preset level.

[0094] Specifically, priority reset requests have a lower priority than data requests to the processing core. Therefore, before initiating a priority reset request, the request status between the processing core and the cache is checked; when a data request to the processing core is received, a priority reset request cannot be initiated.

[0095] When no data request is received from the processing core, and the cache group is determined to contain cache lines in the first priority state using the method described above, and the target duration is greater than the preset duration, a priority reset request is initiated; then at least one cache line in the first priority state in the cache group is determined, and the priority of each of the at least one cache line is adjusted to the preset level.

[0096] In this embodiment of the application, when it is detected that the cache group contains cache lines in the first priority state, and the target duration (i.e., the interval between the last access of the cache group by a data request carrying a priority indication) is greater than the preset duration, it indicates that the cache group has not been accessed by high priority for a long time. Therefore, a priority reset process is initiated spontaneously to reduce the priority of the cache lines in the first priority state (i.e., high priority) in the cache group, effectively preventing high priority cache lines from occupying cache space for a long time, thereby increasing the cache space reserved for non-important data access, and thus improving the overall performance of the cache.

[0097] Secondly, before initiating the priority reset process for the cache group, the request status between the processing core and the cache is checked; when the request status is that no data request sent by the processing core is detected, the priority reset process is initiated spontaneously, and the priority of the cache line in the first priority status in the cache group is adjusted to the preset level; in this way, not only can the hardware spontaneously reset the cache line priority, but it will not affect the processing of data requests (i.e., normal access) of the processing core.

[0098] In some embodiments, tag information for each cache line in the cache group is read from the tag memory. For each cache line's tag information, if the tag information contains a priority hint indicating a first priority state, then the cache line is determined to be in a first priority state.

[0099] If the tagging information includes a priority hint, and the priority hint indicates that the priority is not greater than the preset level, then the priority of the cached line is determined to be no greater than the preset level. If the tagging information does not include a priority hint, then the priority of the cached line is also determined to be no greater than the preset level.

[0100] After determining at least one cache line in the cache group that is in the first priority state, the priority of each cache line is adjusted to the preset level, that is, the priority of each cache line is reduced; then, the priority hint contained in the tag information of each cache line is updated so that the priority hint indicates the priority is the preset level.

[0101] In some embodiments, after adjusting the priority of each of the above at least one cache line to a preset level, the priority status of the cache group is updated to: cache lines that do not contain the first priority status; and the target duration is set to zero.

[0102] For example, see Figure 6 The priority hint size is set to 1 bit, where 1 represents high priority and 0 represents low priority. The tag memory stores the tag information of 6 cache lines, namely: tag information 1 for cache line 1, tag information 2 for cache line 2, tag information 3 for cache line 3, tag information 4 for cache line 4, tag information 5 for cache line 5, and tag information 6 for cache line 6.

[0103] Among them, cache line 1, cache line 2 and cache line 3 are located in cache group A, and cache line 4, cache line 5 and cache line 6 are located in cache group B.

[0104] When initiating a priority reset request, the priority reset request is set to carry the cache group index "A"; then the tag information of each cache line in cache group A is read from the tag memory, namely tag information 1, tag information 2 and tag information 3.

[0105] First, check the tag information 1. Since the tag information 1 contains a priority hint and the corresponding value is "1", set the priority hint to "0" to obtain the updated tag information 1. Then, save the updated tag information 1 to the tag memory.

[0106] Next, check tag information 2. Since tag information 2 does not contain priority hints, tag information 2 does not need to be updated.

[0107] Next, check the tag information 3. Since tag information 3 contains a priority hint and the corresponding value is "0", there is no need to update tag information 3.

[0108] At this point, cache group A does not contain any high-priority cache lines. Therefore, the priority status of cache group A is set to 0, indicating that cache group A does not contain any high-priority cache lines; at the same time, the target duration of cache group A is set to 0.

[0109] In this embodiment, when the cache communicates with the processing core, it detects in real time whether each cache group contains cache lines in the first priority state. If the cache group contains cache lines in the first priority state and there is no high-priority access for a long time, it automatically initiates a priority reset request to reset the priority of high-priority cache lines in the cache group, effectively preventing high-priority cache lines from occupying cache space for a long time, thereby improving the overall performance of the cache.

[0110] Secondly, by recording at the granularity of cache groups whether there has been no high-priority access for a long time and whether there are high-priority cache lines, the resource consumption of triggers can be reduced.

[0111] Based on the same technical concept, embodiments of this application provide a computer device, such as... Figure 7 As shown, it includes at least one artificial intelligence chip 100 and a memory 701 connected to at least one artificial intelligence chip 100. In this embodiment, the specific connection medium between the artificial intelligence chip 100 and the memory 701 is not limited. Figure 7 Taking the connection between the AI ​​chip 100 and the memory 701 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0112] In this embodiment of the application, the memory 701 stores instructions that can be executed by at least one artificial intelligence chip 100. By executing the instructions stored in the memory 701, at least one artificial intelligence chip 100 can perform the steps of the above-mentioned cache line priority reset method.

[0113] The artificial intelligence chip 100 serves as the control center of the computer device. It connects to various parts of the computer device via various interfaces and lines, and resets cache line priorities by running or executing instructions stored in the memory 701 and accessing data stored in the memory 701. Optionally, the artificial intelligence chip 100 may include one or more processing units. The artificial intelligence chip 100 may integrate an application processor and a modem processor. The application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may not be integrated into the artificial intelligence chip 100. In some embodiments, the artificial intelligence chip 100 and the memory 701 may be implemented on the same chip; in other embodiments, they may be implemented on separate chips.

[0114] The artificial intelligence chip 100 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0115] Memory 701, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 701 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 701 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer device, but is not limited thereto. Memory 701 in the embodiments of this application may also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0116] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the above-described cache line priority reset method.

[0117] Those skilled in the art will understand that embodiments of the present invention can be provided as methods or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0118] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer apparatus or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0119] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer device or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0120] These computer program instructions may also be loaded onto a computer device or other programmable data processing equipment to cause a series of operational steps to be performed on the computer device or other programmable equipment to produce a process implemented by the computer device, thereby providing instructions that execute on the computer device or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0121] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0122] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for resetting the priority of cache lines, characterized in that, include: The status information of multiple cache groups in the cache is detected. The status information includes: priority status and target duration; the target duration represents the interval since the cache group was last accessed by a data request with a priority hint; the priority hint represents the first priority status. For each cache group, if the priority status of the cache group is: a cache line containing a first priority status, and the target duration is greater than a preset duration, then the request status between the processing core and the cache is detected. The first priority status indicates that the priority is greater than a preset level. If the request status is that no data request sent by the processing core is detected, the hardware automatically initiates a priority reset process to determine at least one cache line in the cache group with the first priority status, and adjusts the priority of each of the at least one cache line to the preset level. When a data request including a memory address is received from the processing core, if the cache group index in the memory address matches a cache group, the target duration corresponding to the cache group is set to zero. The marker in the memory address is compared one by one with the marker information of each cache line under the cache group to obtain the inspection result; When the check result is that the data request does not hit the tag information of any cache line, a cache line is allocated for the data request, and the priority hint is added to the tag information of the cache line to indicate that the cache line is in the first priority state.

2. The method as described in claim 1, characterized in that, Determining at least one cache line in the cache group with the first priority state includes: Read the tag information for each cache line in the cache group from the tag memory; For each cache line's tagging information, if the tagging information contains a priority hint and the priority hint indicates the first priority state, then the cache line is determined to be in the first priority state.

3. The method as described in claim 2, characterized in that, Adjusting the priority of each of the at least one cached line to the preset level includes: For each of the at least one cached lines, execute: Update the priority hint included in the tagging information of the cached line so that the priority hint indicates that the priority is the preset level.

4. The method as described in claim 1, characterized in that, After adjusting the priority of each of the at least one cached line to the preset level, the method further includes: Update the priority status of the cache group to: cache lines that do not contain the first priority status; Set the target duration to zero.

5. The method according to any one of claims 1 to 4, characterized in that, Also includes: When the data request hits a cache line, the priority hint is added to the tagging information of the cache line.

6. The method as described in claim 5, characterized in that, After adding the priority hint to the tagging information of the cache line when the data request hits a cache line, the method further includes: If the priority status of the cache group to which the cache line belongs is: not containing cache lines with the first priority status, then the priority status of the cache group is updated to: containing cache lines with the first priority status.

7. The method as described in claim 5, characterized in that, The data request can be a read request or a write request.

8. An artificial intelligence chip, characterized in that, include: Processes the core, cache, and main memory; The cache is used to perform the method according to any one of claims 1 to 7.

9. A computer device comprising a memory, an artificial intelligence chip, and a computer program stored in the memory and running on the artificial intelligence chip, characterized in that, When the artificial intelligence chip executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

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