Clock tree error positioning method and device

Abstract

The invention provides a clock tree error positioning method and device. The clock tree error positioning method comprises the following steps: performing first clock tree synthesis on a target chip, and obtaining clock delay jumps corresponding to a plurality of clock trees in the first clock tree synthesis process; determining the clock tree of which the clock delay jump meets a first preset condition in the plurality of clock trees as a to-be-optimized clock tree; and performing error positioning on the to-be-optimized clock tree according to the clock delay reports corresponding to the to-be-optimized clock tree at the plurality of integrated nodes. Through the clock tree error positioning method, the problem that the research and development period of the chip is prolonged due to the fact that abnormal nodes in the chip are difficult to position is solved.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and in particular to a clock tree error localization method and apparatus. Background Technology

[0002] In the field of integrated circuit design, Clock Tree Synthesis (CTS) is a key technology for building clock distribution networks. Its core objective is to form a clock transmission path with low latency, low skew, low power consumption, and high stability by rationally arranging buffers and clock connections, so as to ensure that all functional modules of the chip operate synchronously under the drive of a unified clock signal.

[0003] In related technologies, when there is a problem with the clock transmission path in the clock tree, traditional design methods rely on designers to adjust the buffer drive capability or manually optimize local interconnects based on their experience. However, since clock synthesis tools do not provide a systematic diagnostic approach, designers find it difficult to quickly locate the key nodes or clock tree elements that cause the clock tree to malfunction. This requires designers to make repeated trial and error adjustments, which significantly prolongs the chip development cycle.

[0004] Therefore, the relevant technologies suffer from the problem of difficulty in locating abnormal nodes in the chip, which leads to an extended chip development cycle. Summary of the Invention

[0005] To address the aforementioned technical problems, this application proposes a clock tree error localization method and apparatus.

[0006] To address the aforementioned technical problems, this application proposes a clock tree error localization method, which includes:

[0007] Perform first clock tree synthesis on the target chip and obtain the clock delay transitions corresponding to multiple clock trees during the first clock tree synthesis process;

[0008] The clock tree whose clock delay transition satisfies the first preset condition among multiple clock trees is identified as the clock tree to be optimized.

[0009] Error location of the clock tree to be optimized is performed based on the clock delay reports corresponding to multiple synthesis nodes.

[0010] The step of determining the clock tree whose clock delay transitions satisfy a first preset condition as the clock tree to be optimized includes:

[0011] The clock tree whose clock delay jump is greater than a first preset value among the multiple clock trees is the first clock tree to be optimized;

[0012] Based on the first clock tree to be optimized, a second clock tree to be optimized associated with the first clock tree is selected from the remaining clock trees.

[0013] In the above embodiments, by identifying clock trees associated with abnormal clock trees in advance, designers can optimize clock trees in conjunction with the second clock tree to be optimized during subsequent adjustments. This avoids ignoring the impact of adjusting the first clock tree to be optimized alone on the associated clock trees, thus enabling the location of potential anomalies in the clock trees of the chip and further shortening the R&D cycle.

[0014] Specifically, based on the first clock tree to be optimized, a second clock tree to be optimized associated with the first clock unit is selected from the remaining clock trees, including:

[0015] Candidate clock trees are selected from the remaining clock trees, wherein the difference between the clock delay time of the candidate clock tree and the clock delay time of the first clock tree to be optimized is less than a second preset value.

[0016] Determine the common logic length between the first clock tree to be optimized and the candidate clock trees;

[0017] If the common logic length is greater than a preset threshold, the candidate clock tree is determined as the second clock tree to be optimized.

[0018] In the above embodiments, due to the similar delay characteristics of the two associated clock trees, clock trees associated with the first clock tree to be optimized are initially screened based on the fact that the difference in clock delay time is less than a second preset value. Further screening of clock trees associated with the first clock tree to be optimized, based on the common logic length between them to determine if there is a shared path or path element, allows for more precise location of the second clock tree to be optimized, thus improving the location accuracy of the second clock tree to be optimized.

[0019] The step of determining the common logic length of the first clock tree to be optimized and the candidate clock trees includes:

[0020] Determine the common receiving end of the first clock tree to be optimized and the candidate clock trees;

[0021] Obtain the first clock delay path from the first clock source of the first clock tree to be optimized to the common receiver;

[0022] Obtain the second clock delay path from the second clock source of the candidate clock tree to the common receiver;

[0023] Based on the first clock delay path and the second clock delay path, determine the common standard unit set of the first clock tree to be optimized and the candidate clock trees;

[0024] The common logic length is determined based on the common standard unit set and the common receiver.

[0025] In the above embodiments, the common logic length can be accurately determined by traversing the logic length from the common receiver to each common standard unit, avoiding errors in the determination of the clock tree to be optimized due to calculation errors in the common logic length, thereby improving the determination accuracy of the clock tree to be optimized.

[0026] The step of locating errors in the clock tree to be optimized based on clock delay reports corresponding to multiple synthesis nodes includes:

[0027] The clock tree to be optimized is subjected to a second clock tree synthesis, wherein the second clock tree synthesis includes multiple synthesis nodes;

[0028] During the second clock tree synthesis process, for each synthesis node, after the current synthesis node has finished running, the first clock delay report corresponding to the current synthesis node is obtained;

[0029] Based on the first clock delay report, determine the first clock delay transition of the clock tree to be optimized at the current synthesis node;

[0030] If the first clock delay transition satisfies the second preset condition, the next synthesis node of the current synthesis node is run;

[0031] If the first clock delay transition does not meet the second preset condition, the current synthesis node is determined to be an error node.

[0032] In the above embodiments, since clock delay transitions can intuitively reflect whether the clock tree is abnormal, the clock delay transitions formed before and after the synthesis node can accurately determine whether the synthesis node is an error node, thereby improving the error positioning accuracy of the target chip.

[0033] After determining that the current synthesis node is an error node, the method further includes:

[0034] Obtain the receiver delay set from the first clock delay report;

[0035] The error receiver in the clock tree to be optimized is determined based on the receiver delay set.

[0036] Obtain the set of element delays in the error delay path corresponding to the error receiver;

[0037] The error elements in the error delay path are determined based on the set of element delays.

[0038] In the above embodiments, after determining the error nodes, the error elements that cause the clock tree to be optimized to become abnormal are further identified, enabling designers to accurately locate the error elements that cause the error nodes to become abnormal, quickly adjust the clock tree to be optimized, and further shorten the research and development cycle.

[0039] Prior to performing the first clock tree synthesis on the target chip, the method further includes:

[0040] For each clock tree in the target chip, obtain the set of positions corresponding to all receivers for the current clock tree;

[0041] The center position is determined based on the set of positions;

[0042] The placement area is determined based on the sum of the areas of the center position and the standard units in the current clock tree;

[0043] Each of the standard units is placed in the placement area.

[0044] In the above embodiments, the placement area of ​​the standard unit in the clock tree is determined to avoid the clock length and delay path of the clock tree from increasing due to poor physical placement of the standard unit, thereby reducing the delay time of the clock tree.

[0045] To address the aforementioned technical problems, this application also proposes a clock tree error positioning device, which includes:

[0046] The acquisition module is used to perform a first clock tree synthesis on the target chip and acquire the clock delay transitions corresponding to multiple clock trees during the first clock tree synthesis process.

[0047] The determination module is used to determine the clock tree whose clock delay transition meets the first preset condition from multiple clock trees as the clock tree to be optimized.

[0048] The positioning module is used to locate the error of the clock tree to be optimized based on the clock delay reports corresponding to multiple synthesis nodes.

[0049] To address the aforementioned technical problems, this application also proposes another clock tree error localization device, which includes a memory and a processor coupled to the memory; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the clock tree error localization method as described above.

[0050] To address the aforementioned technical problems, this application also proposes a computer storage medium / computer program product, wherein the computer storage medium is used to store a computer program, and the computer program product includes a computer program, which, when executed by a computer, is used to implement the clock tree error localization method described above.

[0051] Compared with existing technologies, the beneficial effects of this application are: by diagnosing abnormal clock trees, i.e. clock trees to be optimized, through clock delay jumps, designers can accurately locate the clock tree that causes timing problems in the target chip, shortening the R&D cycle; and by analyzing clock delay reports from different synthesis nodes, the error location of the clock tree to be optimized can be completed, determining at which node the clock tree to be optimized is abnormal, helping designers to accurately locate the synthesis node that causes timing problems in the clock tree to be optimized, further shortening the R&D cycle. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] in:

[0054] Figure 1 This is a flowchart illustrating an embodiment of the clock tree error localization method provided in this application;

[0055] Figure 2 This is a schematic diagram illustrating the association between a first clock tree to be optimized and a second clock tree to be optimized in one embodiment provided in this application;

[0056] Figure 3 This is a flowchart illustrating the synthesis process of the second clock tree in one embodiment provided in this application;

[0057] Figure 4 This is a schematic diagram of a clock delay report in one embodiment provided in this application;

[0058] Figure 5 This is a flowchart of the first clock tree synthesis process provided in this application;

[0059] Figure 6 This is a schematic diagram of the random arrangement of standard units in one embodiment provided in this application;

[0060] Figure 7 This is a schematic diagram of a standard unit being placed in a placement area according to one embodiment provided in this application;

[0061] Figure 8This is a schematic diagram of an embodiment of the clock tree error positioning device provided in this application;

[0062] Figure 9 This is a schematic diagram of another embodiment of the clock tree error positioning device provided in this application;

[0063] Figure 10 This is a schematic diagram of the structure of an embodiment of the computer storage medium / computer program product provided in this application. Detailed Implementation

[0064] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0065] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0066] In the clock tree optimization process of related technologies, the clock tree synthesis of a chip can be completed with a single command. This single command implicitly encapsulates complex steps such as aggregation, clock equalization, routing, and post-adjustment. The details of the intermediate steps are hidden, which means that designers can only know that there is a delay problem in the overall result, but cannot identify which specific nodes or clock trees are causing the problem. In other words, it is difficult to locate the specific problem node or the abnormal clock tree. Designers can only make adjustments through repeated trial and error, which increases the cost of trial and error and prolongs the chip development cycle.

[0067] To address the problems in related technologies, this application provides a clock tree error localization method, for details please refer to [link / reference needed]. Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the clock tree error localization method provided in this application.

[0068] like Figure 1As shown, the specific steps are as follows:

[0069] Step S11: Perform first clock tree synthesis on the target chip and obtain the clock delay transitions corresponding to multiple clock trees during the first clock tree synthesis process.

[0070] In the embodiments of this application, the goal of clock tree synthesis is to build a clock allocation network that meets the delay and offset requirements for the target chip. Generally, multiple clock tree synthesis iterations are required to obtain the final clock allocation network that meets the requirements.

[0071] The first clock tree synthesis is a single clock tree synthesis step in the iterative process. This process involves multiple synthesis nodes, which, upon completion, form a clock allocation network containing multiple clock trees. If the clock allocation network formed by the first clock tree synthesis fails to meet requirements, it is necessary to locate the synthesis node, clock tree, or element in the clock path that causes this failure—this is called error localization—to guide subsequent clock tree synthesis processes and prevent blind iteration.

[0072] During the first clock tree synthesis process, a script is provided to generate a clock delay report after each synthesis node is completed. One synthesis node corresponds to one clock delay report, and each clock delay report includes at least the delay time of the target chip at each clock tree at the corresponding synthesis node.

[0073] The clock delay transition for each clock tree in the first clock tree synthesis process is determined based on the delay time of the clock tree at the first synthesis node and the delay time at the last synthesis node.

[0074] Optionally, a clock tree analysis report is generated after the first clock tree synthesis, and clock delay transitions are obtained from the clock tree analysis report.

[0075] The clock delay reports corresponding to multiple synthesis nodes in the first clock tree synthesis are traversed and extracted to obtain the delay time of each clock tree in the target chip at each synthesis node. After analysis, a clock tree analysis report is obtained. Please refer to Table 1. Table 1 shows a clock tree analysis report in one embodiment. The target chip includes N clock trees numbered from 1 to N. The table includes the delay time of each clock tree at each synthesis node in the first clock tree synthesis, as well as the clock delay jump calculated based on the clock tree at the focus node and the post-adjustment node, and the diagnostic priority determined based on the clock delay jump. For each clock tree, the delay time corresponding to the last synthesis node is subtracted from the delay time corresponding to the aggregation node (first synthesis node). The difference is then divided by the delay time corresponding to the aggregation node to obtain the clock delay jump in the first clock synthesis process. For clock trees whose clock delay jump falls within the first range, the diagnostic priority of the clock tree is determined to be high. For clock trees whose clock delay jump falls within the second range, the diagnostic priority of the clock tree is determined to be medium. For clock trees whose clock delay jump falls within the third range, the diagnostic priority of the clock tree is determined to be low. For example, clock trees with a clock delay jump greater than 50% (corresponding to the first range) have a high diagnostic priority; clock trees with a clock delay jump between 50% and 20% (corresponding to the second range) have a medium diagnostic priority; and clock trees with a clock delay jump less than 20% (corresponding to the third range) have a low diagnostic priority.

[0076] Table 1

[0077]

[0078] Taking clock tree 1 as an example, the delay time of the focus node in the first clock tree synthesis process is 2.181, the delay time of the focus node in the first clock tree synthesis process is 2.483, the delay time of the focus node in the first clock tree synthesis process is 2.399, the delay time of the focus node in the first clock tree synthesis process is 2.399, the delay time of the focus node in the second clock tree 1 is 2.399 minus the delay time of the aggregation node is 2.181, the difference is divided by the delay time of the aggregation node, and finally the clock delay adjustment table corresponding to this clock tree is calculated to be 9.995%, which falls into the third range, and the diagnostic priority corresponding to this clock tree is low.

[0079] The delay times, clock delay transitions, and diagnostic priorities of other clock trees at each synthesis node are similar to those of clock tree 1 above, and will not be repeated here.

[0080] The clock tree analysis report includes the delay times of all clock trees at multiple synthesis nodes, clock delay jumps during the synthesis process of the first clock tree, and diagnostic priorities.

[0081] Alternatively, the clock delay transition can also be represented by the ratio of the delay time corresponding to the last synthesis node to the delay time corresponding to the first synthesis node.

[0082] Step S12: Determine the clock tree whose clock delay transition meets the first preset condition from among multiple clock trees as the clock tree to be optimized.

[0083] In this embodiment of the application, after obtaining the clock delay transitions of multiple clocks during the first clock tree synthesis process, abnormal clock trees are selected based on the clock delay transitions, that is, clock trees whose clock delay transitions meet the first preset condition, and the selected clock trees are determined as clock trees to be optimized.

[0084] In this embodiment, by diagnosing the abnormal clock tree, i.e. the clock tree to be optimized, designers can accurately locate the clock tree that causes timing problems in the target chip, thus shortening the development cycle.

[0085] In an optional embodiment, determining a clock tree whose clock delay transition meets a first preset condition among multiple clock trees as a clock tree to be optimized includes: identifying a clock tree whose clock delay transition is greater than a first preset value among the multiple clock trees as a first clock tree to be optimized; and, based on the first clock tree to be optimized, selecting a second clock tree associated with the first clock tree to be optimized from the remaining clock trees.

[0086] In this embodiment, a first clock tree to be optimized is first selected, and then a second clock tree to be optimized associated with the first clock tree to be optimized is selected based on the first clock tree to be optimized.

[0087] A clock tree whose clock delay jump is greater than the first preset value is a direct manifestation of clock tree abnormality. Based on the clock delay jump corresponding to each clock tree, the abnormal clock tree is selected from multiple clock trees, which is the first clock tree to be optimized.

[0088] In chip design, there are cases where two clock trees are associated. This means that the two clock trees share some logic, such as a clock buffer or data selector being shared by two clock trees. If the two clock trees share some logic, such as a buffer or data selector, then a change in one clock tree may cause a change in the other clock tree.

[0089] If one of the clock trees is identified as an abnormal clock tree, the clock trees associated with it are also highly likely to be abnormal. Alternatively, the associated clock trees may not be abnormal, but subsequent adjustments to the abnormal clock tree will cause changes in the associated clock trees, making them abnormal as well. Therefore, when a clock tree is identified as an abnormal clock tree (the first clock tree to be optimized), the clock trees associated with it also need to be prioritized for adjustment. Thus, the clock trees associated with the first clock tree to be optimized are designated as the second clock trees to be optimized.

[0090] The clock tree to be optimized includes a first clock tree to be optimized and a second clock tree to be optimized. The clock tree that meets the first preset condition is the first clock tree to be optimized with a clock delay jump greater than the first preset value, and the second clock tree to be optimized associated with the first clock tree to be optimized.

[0091] In the above embodiments, by identifying clock trees associated with abnormal clock trees in advance, designers can optimize clock trees in conjunction with the second clock tree to be optimized during subsequent adjustments. This avoids ignoring the impact of adjusting the first clock tree to be optimized alone on the clock trees associated with it, thus enabling the location of potential anomalies in the clock trees in the chip and further shortening the R&D cycle.

[0092] Furthermore, after determining the first clock tree to be optimized, the difference between the delay time of each clock tree in the remaining clock trees and the clock delay time of the first clock tree to be optimized is determined. Clock trees whose difference is less than a second preset value are determined as candidate clock trees, that is, candidate clock trees are selected from the remaining clock trees, wherein the difference between the clock delay time of the candidate clock tree and the clock delay time of the first clock tree to be optimized is less than the second preset value.

[0093] A second clock tree to be optimized is further selected from the candidate clock trees. Based on the common logic length between each clock tree in the candidate clock trees and the first clock tree to be optimized, the candidate clock trees whose common logic length is greater than a preset threshold are determined as the second clock tree to be optimized, that is, the common logic length between the first clock tree to be optimized and the candidate clock trees is determined. If the common logic length is greater than the preset threshold, the candidate clock tree is determined as the second clock tree to be optimized.

[0094] In this embodiment, since the two associated clock trees have similar delay characteristics, the clock trees associated with the first clock tree to be optimized are initially screened based on the fact that the difference in clock delay time is less than a second preset value. Based on the common logical length between the clock trees, it is determined that there is a shared path or path element between them, and the clock trees associated with the first clock tree to be optimized are further screened. This can accurately locate the second clock tree to be optimized associated with the first clock tree to be optimized, thereby improving the positioning accuracy of the second clock tree to be optimized.

[0095] Furthermore, the common logic length of the two clock trees can be determined using the following method, taking the determination of the common logic length between the candidate clock tree and the first clock tree to be optimized as an example:

[0096] A common receiving end is determined between two clock trees, namely, the common receiving end between the first clock tree to be optimized and the candidate clock tree. The clock source of the first clock tree to be optimized is the first clock source, and the clock source of the candidate clock tree is the second clock source. The clock path from the first clock source to the common receiving end is the first clock delay path, and the clock path from the second clock source to the common receiving end is the second clock delay path. That is, the first clock delay path from the first clock source of the first clock tree to be optimized to the common receiving end is obtained, and the second clock delay path from the second clock source of the candidate clock tree to the common receiving end is obtained. The common standard units of the first clock delay path and the second clock delay path are filtered out to obtain a common standard unit set. That is, based on the first clock delay path and the second clock delay path, the common standard unit set of the first clock tree to be optimized and the candidate clock tree is determined, and the common logic length between the first clock tree to be optimized and the candidate clock tree is determined based on the common standard unit set.

[0097] Specifically, each standard unit in the first clock delay path of the first clock tree to be optimized is traversed, and it is checked whether the standard unit is in the second clock delay path of the candidate clock tree. If it is, it means that the standard unit is a common standard unit and is added to the common standard unit set.

[0098] The logic length from each standard unit in the common standard unit set to the common receiver is calculated, and the maximum value of the logic length is obtained. The maximum value is determined as the common logic length of the first clock tree to be optimized and the candidate clock trees.

[0099] Please see Figure 2 , Figure 2 This is a schematic diagram illustrating the association between the first clock tree to be optimized and the second clock tree to be optimized in one embodiment provided in this application, as shown below. Figure 2 As shown, the first clock source of the first clock tree to be optimized is clock1, and the second clock source of the second clock tree to be optimized is clock2. The clock signal of clock source clock1 is connected to the standard cells (including) in the three branches. Figure 2 The buffers and / or data selectors shown in the diagram are transmitted to the receiving end, where triangles represent buffers, trapezoids represent data selectors, and rectangles represent the receiving end.

[0100] The clock signal of clock1 may reach three receiving ends: sinkA, sinkB, and sinkC. Therefore, the receiving ends of the first clock tree to be optimized are sinkA, sinkB, and sinkC. The clock signal of clock2 may reach three receiving ends: sinkB, sinkC, and sinkD. Therefore, the receiving ends of the second clock tree to be optimized are sinkB, sinkC, and sinkD.

[0101] SinkB and SinkC can receive clock signals from both clock1 and clock2. Therefore, sinkB and SinkC are the common receivers of the first and second clock trees to be optimized. The clock path from the first clock source to the common receiver is the first clock delay path, which includes the clock path from clock1 to sinkB (denoted as the first path) and the clock path from clock1 to sinkC (denoted as the second path). The clock path from the second clock source to the common receiver is the second clock delay path, which includes the clock path from clock2 to sinkB (denoted as the third path) and the clock path from clock2 to sinkC (denoted as the fourth path).

[0102] When there are multiple common receivers, there are multiple first clock delay paths and multiple second clock delay paths. The common standard unit set is divided into a first subset and a second subset. The first subset includes the common standard units of the first path and the third path, and the second subset includes the common standard units of the second path and the fourth path. The logic length from each standard unit in the first subset to sinkB and the logic length from each standard unit in the second subset to sinkC are calculated, and the maximum value of all the above logic lengths is obtained. The maximum value is determined as the common logic length of the first clock tree to be optimized and the candidate clock tree.

[0103] Figure 2 The buffer represented by the triangle and the data selector represented by the trapezoid are standard cells. Figure 2 The longest logical length between the common standard unit and the common receiver is the length of the data selector mux1 and the common receiver sinkB. The logical lengths corresponding to mux1 and sinkB are defined as the common logical length.

[0104] It should be noted that the standard unit of the clock tree is a pre-designed and reusable circuit unit, such as a clock inverter and a clock data selector.

[0105] Optionally, the common logic lengths can also be sorted and output to a logic length report. Please refer to Table 2. Table 2 is... Figure 2The report includes the logic lengths of the first and second clock trees to be optimized. These reports contain the common receivers between the two clock trees (sinkB and sinkC) and the length of the common logic corresponding to each receiver, arranged in descending order of length. The length value at the top of the list is the length of the common logic corresponding to sinkB. Figure 2 The common logic between the data selector mux1 and sinkB includes four standard units (corresponding to...) Figure 2 The four buffers between mux1 and sinkB represent the length of the common logic by the number of standard cells. Therefore, the length of the common logic corresponding to sinkB is 4; the length of the common logic corresponding to sinkC is... Figure 2 The common logic between the data selector mux2 and sinkC includes two standard units (corresponding to...) Figure 2 The length of the common logic is represented by the number of standard cells (two buffers between mux1 and sinkB). Therefore, the length of the common logic corresponding to sinkC is 4.

[0106] Table 2

[0107] Public receiver Length value of public logic sinkB 4 sinkC 2

[0108] In the above embodiments, the common logic length can be accurately determined by traversing the logic length from the common receiver to each common standard unit, avoiding errors in the determination of the clock tree to be optimized due to calculation errors in the common logic length, thereby improving the determination accuracy of the clock tree to be optimized.

[0109] Step S13: Perform error localization on the clock tree to be optimized based on the clock delay reports corresponding to multiple synthesis nodes.

[0110] In this embodiment, the clock synthesis process includes multiple synthesis nodes, each of which generates a clock delay report. By analyzing the clock delay reports of different synthesis nodes, the error location of the clock tree to be optimized is completed, and it is determined at which node the clock tree to be optimized is abnormal. This helps designers accurately locate the synthesis node that causes timing problems in the clock tree to be optimized, and further shortens the development cycle.

[0111] In this embodiment, the clock delay reports corresponding to multiple synthesis nodes can be generated during the first clock tree synthesis process, or during the second clock tree synthesis process performed after the first clock tree synthesis process.

[0112] In an optional embodiment, the step of error localization of the clock tree to be optimized based on the clock delay reports corresponding to multiple synthesis nodes includes: performing a second clock tree synthesis on the clock tree to be optimized, wherein the second clock tree synthesis includes multiple synthesis nodes; during the second clock tree synthesis process, for each synthesis node, after the current synthesis node has finished running, obtaining the first clock delay report corresponding to the current synthesis node, and determining the first clock delay transition of the clock tree to be optimized at the current synthesis node based on the first clock delay report; if the first clock delay transition meets a second preset condition, running the next synthesis node of the current synthesis node; if the first clock delay transition does not meet the second preset condition, determining the current synthesis node as an error node.

[0113] In this embodiment, after determining the clock tree to be optimized, a second clock tree synthesis is performed on the target chip. The second clock tree synthesis includes multiple synthesis nodes. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a flowchart illustrating the synthesis process of the second clock tree in one embodiment provided in this application, as shown below. Figure 3 As shown, the second clock tree synthesis process includes multiple nodes, namely the aggregation node, clock equalization node, routing node, and post-adjustment node; after the operation of each node, a clock delay report corresponding to that node is generated.

[0114] The process of generating a clock delay report at each node is specifically divided into two parts: First, determining the clock delay value corresponding to each receiver. That is, for each clock tree in the target chip, using commands to obtain all receivers corresponding to that clock tree, traversing each receiver, obtaining the clock delay value of each receiver, and putting the obtained "clock delay value" and "receiver" into a list (the first list), and outputting them to the clock delay report in a certain order; Second, traversing each receiver, and using commands to obtain the specific clock path of that receiver in the clock tree, traversing the clock path... For each element, use commands to obtain the clock delay value from the clock source to each element. Put the obtained "clock delay value" and "element" into a list (second list) and output them to the clock delay report in a certain order. Thirdly, traverse each receiver and use commands to obtain its specific clock path list. The first element in the clock path list is the clock source. Use commands to open the clock diagnostic interface built into the clock synthesis tool. Use commands to trace the physical path from the clock source to the receiver. Output the physical screenshot path obtained in the previous step to the clock delay report.

[0115] The elements in the clock path refer to the various functional units or components that constitute the clock signal transmission path, including standard units such as data selectors and buffers.

[0116] Optionally, the maximum clock delay value among the multiple receivers of any clock tree is determined as the delay time of the clock tree, or the average value of the clock delay values ​​among the multiple receivers of any clock tree is determined as the delay time of the clock tree.

[0117] Please see Figure 4 , Figure 4 This is a schematic diagram of a clock delay report in one embodiment provided in this application. The clock delay report includes a first list, a second list, and a physical screenshot path. The first list includes the clock delay value corresponding to each receiver in each clock tree. The second list includes the clock delay value corresponding to each element in each clock tree. The physical screenshot path visually shows the path from the clock source to the register clock pin (i.e., the receiver).

[0118] Optionally, multiple delay reports generated by clock tree synthesis are read, and each line is traversed to obtain a clock tree analysis report. Specifically, regular expressions are used to match keywords of the main nodes of clock tree synthesis in multiple delay reports, node names are extracted and stored in variables, and regular expressions are used to match keywords related to clock trees and their delay times to extract clock tree names and clock tree delay times respectively. A hash data structure is created, with the node name as the hash name, the clock tree name as the hash key, and the clock tree delay time as the value corresponding to the key. The hash keys and values ​​are traversed, and the delay time of each clock tree at each node is output to a specified file.

[0119] Please see Figure 5 , Figure 5 This is a flowchart of the first clock tree synthesis process provided in this application, such as... Figure 5 As shown, a script program is provided that automatically outputs clock path, timing information, etc. during the operation of the aggregation node, clock equalization node, and cabling node, and generates a clock delay report after the node receives the information.

[0120] In the second clock tree synthesis process, multiple synthesis nodes refer to aggregation nodes, clock balancing nodes, and routing nodes. For each synthesis node, after the synthesis node completes its operation, it is determined whether the clock delay transition (first clock delay transition) of the clock tree to be optimized at the current synthesis node meets the second preset condition. If it does, the next synthesis node is run. If it does not meet the condition, the current synthesis node is an error node, i.e., there is an abnormal node. The clock tree to be optimized needs to be adjusted and the current synthesis node is run again until the clock delay transition of the current synthesis node meets the second preset condition.

[0121] like Figure 3As shown, after layout optimization design, a second clock tree synthesis is performed. Further optimization follows the second clock tree synthesis, which includes: clustering (grouping logic units); determining if the clustering meets a second preset condition; if not, re-clustering; if it does, clock balancing is performed to optimize clock path delay and skew; if clock balancing meets the second preset condition, it is re-balanced; if so, routing is performed; if routing meets the second preset condition, it is re-routed; if so, post-adjustment is performed, i.e., static timing analysis is conducted on the post-routing design to verify timing convergence.

[0122] In this embodiment, the first clock delay jump corresponding to each synthesis node can be determined by the first clock delay report (determined based on the delay time of the clock tree after the synthesis node and the delay time of the clock tree before the synthesis node). Based on whether the first clock delay jump meets the second preset condition, such as being greater than the third preset value, it can be determined whether the current synthesis node is an error node. The clock delay jump can intuitively reflect whether the clock tree is abnormal. By accurately judging whether the synthesis node is an error node through the clock delay jump formed before and after the synthesis node, the error positioning accuracy of the target chip is improved.

[0123] Optionally, after determining that the current synthesis node is an error node, the receiver delay set in the first clock delay report is obtained; the error receiver in the clock tree to be optimized is determined according to the receiver delay set; the element delay set in the error delay path corresponding to the error receiver is obtained; and the error element in the error delay path is determined according to the element delay set.

[0124] In this embodiment, after determining the error node, it is further determined which specific elements in the error node have unreasonable settings that cause the clock tree to be optimized to malfunction. Specifically, the receiver delay set is obtained, which is the clock delay value corresponding to each receiver in the clock tree to be optimized. The error receiver is determined based on the receiver delay set. For example, the receiver with a clock delay value greater than a fourth preset value in the receiver delay set is determined as the error receiver. The clock path corresponding to the error receiver in the clock tree to be optimized is the error delay path. The clock delay values ​​corresponding to all elements involved in the error delay path constitute the element delay set. The error element is determined based on the element delay set. For example, the element with a delay greater than a fifth preset value in the element delay set is determined as the error element.

[0125] After identifying the error nodes, the error elements that cause the clock tree to be optimized to malfunction are further identified. This allows designers to accurately locate the error elements causing the error nodes to malfunction, quickly adjust the clock tree to be optimized, and further shorten the R&D cycle.

[0126] In an optional embodiment, before performing first clock tree synthesis on the target chip, the method further includes: for each clock tree in the target chip, obtaining a set of locations corresponding to all receivers corresponding to the current clock tree; determining a center location based on the set of locations; determining a placement area based on the center location and the sum of the areas of each standard unit in the current clock tree; and placing each of the standard units in the placement area.

[0127] In this embodiment, before synthesizing the first clock tree, the target chip needs to be laid out. The layout includes placing the standard cells required in the clock tree. When placing the standard cells, the origin coordinates of each receiver are traversed for each clock tree, i.e., the set of positions. The center position is determined according to the set of positions. For example, the sum of the x-coordinates and the sum of the y-coordinates of the origin coordinates of all receivers are calculated. The sum of the x-coordinates and the sum of the y-coordinates are divided by the number of receivers to obtain the x-coordinates and y-coordinates of the center position.

[0128] Further, the placement area is determined based on the center location and the sum of the areas of each standard unit. For example, all standard units contained in a single clock tree are obtained, and the sum of the areas of the standard units is calculated. Based on the sum of the areas of the standard units and the specified utilization rate, the area and location of the placement area are determined, and all standard units are placed in the placement area.

[0129] In related technologies, the placement of standard cells tends to be random. Please refer to [link / reference]. Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of the random placement of standard cells in one embodiment provided in this application. The standard cells (CI_1, CI_2, CI_3) need to be placed in the target chip. The standard cells are connected to the clock source and the receiver in the clock tree, as shown below. Figure 6 As shown, the clock signal emitted by the clock source sequentially travels through path 1, CI_1, path 2, CI_2, and path 3 to reach CI_3. From CI_3, it travels through path 4 to reach one receiver and through path 5 to reach another receiver. Figure 6 The distributed layout in the middle leads to an increase in clock paths, which in turn significantly increases physical latency.

[0130] Figure 7 This is a schematic diagram showing the placement of standard units in a placement area according to one embodiment provided in this application. Figure 6 The placement of the standard unit has been... Figure 7After the optimization shown, all standard units (CI_1, CI_2, CI_3) are placed at the center of the receiver. Figure 7 (The part within the dashed box) The clock signal emitted by the clock source sequentially travels through path 1, CI_1, and CI_2 to reach CI_3. From CI_3, it travels through path 4 to one receiver and through path 5 to another receiver. The standard units (CI_1, CI_2, CI_3) are stacked together, reducing the data transmission paths 2 between CI_1 and CI_2, and 3 between CI_2 and CI_3. The delay path is from... Figure 6 Reduce 1-5 to Figure 7 In numbers 1, 4, and 5, the physical delay from the clock source to standard unit 3 is compared to... Figure 6 The physical delay in the clock is smaller, which in turn reduces the physical delay from the clock source to each receiver.

[0131] The area utilization rate in the dashed box is specified as 50%, and 50% of the area in the dashed box is reserved for buffering in subsequent clock tree synthesis.

[0132] Through the above embodiments, the placement area of ​​standard cells in the clock tree is determined, avoiding the increase of clock length and delay path in the clock tree due to poor physical placement of standard cells, thereby reducing the delay time of the clock tree.

[0133] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0134] To implement the aforementioned clock tree error localization method, this application also proposes a clock tree error localization device 500, for details please refer to [link / reference needed]. Figure 8 , Figure 8 This is a schematic diagram of an embodiment of the clock tree error positioning device provided in this application.

[0135] The clock tree error positioning device 500 in this embodiment includes:

[0136] The acquisition module 51 is used to perform a first clock tree synthesis on the target chip and acquire the clock delay transitions corresponding to multiple clock trees during the first clock tree synthesis process.

[0137] The determination module 52 is used to determine the clock tree whose clock delay transition meets the first preset condition among multiple clock trees as the clock tree to be optimized;

[0138] The positioning module 53 is used to locate the error of the clock tree to be optimized based on the clock delay reports corresponding to multiple synthesis nodes of the clock tree to be optimized.

[0139] The determining module 52 is further configured to designate a clock tree whose clock delay jump is greater than a first preset value as a first clock tree to be optimized; and, based on the first clock tree to be optimized, to select a second clock tree associated with the first clock tree to be optimized from the remaining clock trees.

[0140] The determining module 52 is further configured to filter out candidate clock trees from the remaining clock trees, wherein the difference between the clock delay time of the candidate clock tree and the clock delay time of the first clock tree to be optimized is less than a second preset value; determine the common logic length of the first clock tree to be optimized and the candidate clock trees; and determine the candidate clock tree as the second clock tree to be optimized if the common logic length is greater than a preset threshold.

[0141] The determining module 52 is further configured to: determine the common receiving end of the first clock tree to be optimized and the candidate clock tree; obtain the first clock delay path from the first clock source of the first clock tree to be optimized to the common receiving end; obtain the second clock delay path from the second clock source of the candidate clock tree to the common receiving end; determine the common standard unit set of the first clock tree to be optimized and the candidate clock tree based on the first clock delay path and the second clock delay path; and determine the common logic length based on the common standard unit set and the common receiving end.

[0142] The positioning module 53 is further configured to perform a second clock tree synthesis on the clock tree to be optimized, wherein the second clock tree synthesis includes multiple synthesis nodes; during the second clock tree synthesis process, for each synthesis node, after the current synthesis node has finished running, a first clock delay report corresponding to the current synthesis node is obtained; based on the first clock delay report, a first clock delay transition of the clock tree to be optimized at the current synthesis node is determined; if the first clock delay transition meets a second preset condition, the next synthesis node of the current synthesis node is run; if the first clock delay transition does not meet the second preset condition, the current synthesis node is determined to be an error node.

[0143] The positioning module 53 is further configured to, after determining that the current integrated node is an error node, obtain the receiver delay set in the first clock delay report; determine the error receiver in the clock tree to be optimized based on the receiver delay set; obtain the element delay set in the error delay path corresponding to the error receiver; and determine the error element in the error delay path based on the element delay set.

[0144] The device further includes: a placement module, which is used to obtain a set of positions corresponding to all receivers of the current clock tree for each clock tree in the target chip; determine a center position based on the position set; determine a placement area based on the center position and the sum of the areas of each standard unit in the current clock tree; and place each of the standard units in the placement area.

[0145] To implement the aforementioned clock tree error localization method, this application also proposes another clock tree error localization device, for details please refer to [link / reference needed]. Figure 9 , Figure 9 This is a schematic diagram of another embodiment of the clock tree error positioning device provided in this application.

[0146] The clock tree error positioning device 400 in this embodiment includes a processor 41, a memory 42, an input / output device 43, and a bus 44.

[0147] The processor 41, memory 42, and input / output device 43 are respectively connected to the bus 44. The memory 42 stores program data, and the processor 41 is used to execute the program data to implement the clock tree error location method described in the above embodiment.

[0148] In this embodiment, processor 41 can also be referred to as a CPU (Central Processing Unit). Processor 41 may be an integrated circuit chip with signal processing capabilities. Processor 41 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor, or processor 41 can be any conventional processor.

[0149] This application also provides a computer storage medium / computer program product; please refer to the following: Figure 10 , Figure 10 This is a schematic diagram of an embodiment of the computer storage medium / computer program product provided in this application. The computer storage medium 600 is used to store a computer program 61. The computer program product 600 includes the computer program 61. When the computer program 61 is executed by a computer, it is used to implement the clock tree error positioning method of the above embodiment.

[0150] When the embodiments of this application are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0151] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A clock tree error localization method, characterized in that, The clock tree error localization method includes: Perform first clock tree synthesis on the target chip and obtain the clock delay transitions corresponding to multiple clock trees during the first clock tree synthesis process; The clock tree whose clock delay transition satisfies the first preset condition among multiple clock trees is identified as the clock tree to be optimized. Error location of the clock tree to be optimized is performed based on the clock delay reports corresponding to multiple synthesis nodes.

2. The clock tree error localization method according to claim 1, characterized in that, The step of determining the clock tree whose clock delay transitions satisfy a first preset condition from among multiple clock trees as the clock tree to be optimized includes: The clock tree whose clock delay jump is greater than a first preset value among the multiple clock trees is the first clock tree to be optimized; Based on the first clock tree to be optimized, a second clock tree to be optimized associated with the first clock tree is selected from the remaining clock trees.

3. The clock tree error localization method according to claim 2, characterized in that, Based on the first clock tree to be optimized, a second clock tree to be optimized associated with the first clock unit is selected from the remaining clock trees, including: Candidate clock trees are selected from the remaining clock trees, wherein the difference between the clock delay time of the candidate clock tree and the clock delay time of the first clock tree to be optimized is less than a second preset value. Determine the common logic length between the first clock tree to be optimized and the candidate clock trees; If the common logic length is greater than a preset threshold, the candidate clock tree is determined as the second clock tree to be optimized.

4. The clock tree error localization method according to claim 3, characterized in that, Determining the common logic length of the first clock tree to be optimized and the candidate clock trees includes: Determine the common receiving end of the first clock tree to be optimized and the candidate clock trees; Obtain the first clock delay path from the first clock source of the first clock tree to be optimized to the common receiver; Obtain the second clock delay path from the second clock source of the candidate clock tree to the common receiver; Based on the first clock delay path and the second clock delay path, determine the common standard unit set of the first clock tree to be optimized and the candidate clock trees; The common logic length is determined based on the common standard unit set and the common receiver.

5. The clock tree error localization method according to claim 1, characterized in that, The step of locating errors in the clock tree to be optimized based on clock delay reports at multiple synthesis nodes includes: The clock tree to be optimized is subjected to a second clock tree synthesis, wherein the second clock tree synthesis includes multiple synthesis nodes; During the second clock tree synthesis process, for each synthesis node, after the current synthesis node has finished running, the first clock delay report corresponding to the current synthesis node is obtained; Based on the first clock delay report, determine the first clock delay transition of the clock tree to be optimized at the current synthesis node; If the first clock delay transition satisfies the second preset condition, the next synthesis node of the current synthesis node is run; If the first clock delay transition does not meet the second preset condition, the current synthesis node is determined to be an error node.

6. The clock tree error localization method according to claim 5, characterized in that, After determining that the current synthesis node is an error node, the method further includes: Obtain the receiver delay set from the first clock delay report; The error receiver in the clock tree to be optimized is determined based on the receiver delay set. Obtain the set of element delays in the error delay path corresponding to the error receiver; The error elements in the error delay path are determined based on the set of element delays.

7. The clock tree error localization method according to claim 1, characterized in that, Before performing the first clock tree synthesis on the target chip, the method further includes: For each clock tree in the target chip, obtain the set of positions corresponding to all receivers for the current clock tree; The center position is determined based on the set of positions; The placement area is determined based on the sum of the areas of the center position and the standard units in the current clock tree; Each of the standard units is placed in the placement area.

8. A clock tree error positioning device, characterized in that, The clock tree error location device includes: The acquisition module is used to perform a first clock tree synthesis on the target chip and acquire the clock delay transitions corresponding to multiple clock trees during the first clock tree synthesis process. The determination module is used to determine the clock tree whose clock delay transition meets the first preset condition from multiple clock trees as the clock tree to be optimized. The positioning module is used to locate the error of the clock tree to be optimized based on the clock delay reports corresponding to multiple synthesis nodes.

9. A clock tree error positioning device, characterized in that, The clock tree error localization device includes a memory and a processor coupled to the memory; The memory is used to store program data, and the processor is used to execute the program data to implement the clock tree error localization method as described in any one of claims 1 to 7.

10. A computer storage medium / computer program product, characterized in that, The computer storage medium is used to store a computer program, the computer program product including the computer program, which, when executed by a computer, is used to implement the clock tree error localization method as described in any one of claims 1 to 7.

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