Method and system for automatically checking and correcting PCB (Printed Circuit Board) design rule

Abstract

The invention provides a method and a system for automatically checking and correcting a PCB (Printed Circuit Board) design rule, belonging to the technical field of PCB design. The method comprises the following steps of: analyzing data such as texts, images and tables in a PCB design document through a multi-modal large model, extracting a structured signal information table, automatically generating a dynamically adaptive checking rule, and automatically checking and correcting the PCB design rule. Comprising bit width check, connectivity verification and functional analysis. And the generated rule is optimized by combining a retrieval enhancement generation (RAG) technology with a verification rule base, so that the coverage is comprehensive and the accuracy is high. The system further evaluates the rule through a form verification tool, automatically corrects potential defects, and improves the quality and adaptability of the rule. According to the method, the efficiency and accuracy of PCB design inspection are remarkably improved, the manual intervention requirement is reduced, the method can be widely applied to complex electronic design scenes, and the rapid changing technology and market requirements are met.

Description

Technical Field

[0001] This invention relates to the field of PCB design technology, and more specifically to a method and system for automatic checking and correction of PCB design rules. Background Technology

[0002] In the field of modern electronic design automation (EDA), PCB design rule checking (DRC) is a critical step in ensuring the reliability and performance of printed circuit boards (PCBs). With the increasing complexity of electronic products, traditional manual checking methods can no longer meet the requirements of efficiency and accuracy. Automated DRC tools have emerged to identify potential problems early in the design process, such as insufficient trace spacing and via conflicts, reducing the cost and time of later corrections. However, existing DRC tools mainly rely on static rule bases, which are manually written by experienced engineers and cannot cover all complex design requirements. Furthermore, PCB design documents contain various types of data, such as text, images, and tables. Traditional DRC tools have limited capabilities in handling multimodal information and cannot fully utilize the rich information in PCB design documents. In recent years, advancements in Large Language Models (LLMs) and multimodal learning have provided new approaches to solving these problems, enabling more intelligent parsing and understanding of various information in PCB design documents, achieving more comprehensive and accurate DRC.

[0003] While existing DRC tools have improved the quality of PCB design, they still face numerous challenges. First, static rule bases can only cover common design issues, lacking sufficient support for specific or emerging needs, resulting in incomplete inspection results. Second, updating and maintaining rule bases requires significant time and manpower, making it difficult to keep pace with rapidly changing technological and market demands. Furthermore, existing tools have significant limitations in handling multimodal data, particularly design requirements described in natural language, often requiring manual intervention for translation and interpretation, increasing workload and increasing the risk of errors. To address these challenges, there is an urgent need for an intelligent, flexible, and efficient DRC solution capable of automatically parsing and understanding various information in PCB design documents, including text, images, and tables, and generating dynamic, adaptive inspection rules. Such a system would not only improve the accuracy and coverage of DRC but also significantly reduce maintenance costs, enhance design efficiency, and adapt to ever-changing technological and market demands.

[0004] Existing DRC tools rely on static rule bases, which require frequent manual updates and maintenance, resulting in high maintenance costs and difficulty in adapting to rapidly changing technological and market demands. For example, as PCB designs become more complex and diverse, the maintenance and updating of rule bases require significant manpower and time, increasing operational costs for enterprises. Furthermore, static rule bases can only cover common design problems and lack sufficient support for special or emerging design needs. Consequently, when faced with complex and ever-changing designs, the coverage and accuracy of DRC tools decrease, making it difficult to detect potential design flaws in a timely manner and increasing design risks.

[0005] Existing DRC tools have limited capabilities in processing multimodal data, resulting in inaccurate inspection results and a high error rate. Specifically, most existing DRC tools can only process single-type data, such as text or images, and cannot effectively integrate and utilize multimodal information. This means that when processing complex PCB design documents, the tools may miss important design details, thereby increasing the error rate and affecting the accuracy of the inspection results. Furthermore, because existing tools often require manual intervention for translation and interpretation when processing design requirements described in natural language, this not only increases workload but also prolongs inspection time and reduces overall work efficiency. Summary of the Invention

[0006] To address the problems of high maintenance costs and limited multimodal data processing capabilities of existing PCB Design Rule Check (DRC) tools, this invention proposes an automatic PCB design rule checking and correction method and system. This method can automatically parse and understand various information in PCB design documents, generate dynamic and adaptive check rules, and achieve efficient DRC.

[0007] The technical solution adopted by this invention to solve its technical problem is: In a first aspect, the present invention provides a method for automatic checking and correction of PCB design rules based on a multimodal large model, including: Input multimodal PCB data into the multimodal large model, where the multimodal PCB data types include: PCB design documents, signal definition files, and verified golden RTL designs; By analyzing PCB design documents using a multimodal large model, signal information is extracted and a structured signal information table is generated. Based on the structured signal information table and signal definition file, the natural language signal descriptions in the PCB design document are matched with the signal definitions in the actual hardware description language code to generate a signal mapping table. Based on PCB design rules, structured signal information tables, and signal mapping tables, check rules are automatically generated, including bit width check rules, connectivity check rules, and functional check rules. Use formal verification tools to verify the effectiveness of the inspection rules, and optimize the inspection rules based on the verification results; The optimized inspection rules are applied to verify the PCB design rules and automatically generate correction suggestions.

[0008] Furthermore, the step of parsing PCB design documents using a multimodal large model to extract signal information and generate a structured signal information table includes: S1.1, Multimodal data input and preprocessing, including: Image data analysis: Extract key features from the circuit diagram and generate a signal topology map using a convolutional neural network; Text data parsing: Extracting signal names and functional descriptions using named entity recognition and semantic analysis; Table data parsing: Extracting table information through optical character recognition and structured processing; S1.2, Multimodal large-scale model analysis of PCB design documents, understanding the content and transforming it into structured information, including: Signal name parsing: Extracting signal names appearing in PCB design documents using natural language processing algorithms; Signal function description: Analyze the function description of each signal and identify its role in the circuit; Signal connectivity: For image data, the connectivity between signals is extracted using image recognition technology, and the interconnections between signals are identified through the circuit topology. Signal attribute extraction: Extract the attributes of each signal to obtain detailed information about each signal; S1.3, concerning the image data parsing and signal layout analysis of PCB design documents, includes: Image feature extraction: Key features in the schematic diagram are extracted using a convolutional neural network; the correlation between different signals and circuit board components is identified by training a convolutional neural network model. Topology recognition: Based on image recognition results, a topology diagram of the relationship between signals is established, and the transmission path of each signal in the circuit is identified; Output signal connection topology diagram, a signal connection relationship diagram obtained through image processing technology, represents the transmission path of signals in the circuit board and their interdependencies; S1.4 After multimodal large model parsing, all extracted data will be integrated to generate the final structured output, including: The signal information obtained from text parsing, the signal connection relationships obtained from image parsing, and the signal attribute information extracted from tables are integrated into a unified structured data format; the generated structured information table includes a detailed description of all signals, bit width, and connection relationships.

[0009] Furthermore, based on the structured signal information table, the natural language signal descriptions in the PCB design document are matched with the signal definitions in the actual hardware description language code to generate a signal mapping table, including: S2.1, Input signal definition HDL file and structured signal information table; S2.2 uses a multimodal large language model to analyze signal declarations in signal definition files and matches them with a structured signal information table extracted from PCB design documents; S2.3, the matching process includes: Signal name matching: Extract and clean each signal name in the PCB design document, and match it one by one with the signal names defined in the HDL file; if the signal names match exactly, the signals are considered to be the same; if there are name differences, a fuzzy matching algorithm is used to determine whether they are the same signal. Functional description matching: For each signal, if the signal name matches, the functional description of the signal is further semantically analyzed using natural language processing technology to ensure that the functional description in the PCB design document is consistent with the implementation logic in the HDL code; Signal width matching: Check whether the signal width defined in the PCB design document is consistent with the width declared in the HDL file; if they are inconsistent, calibration and adjustment are required. S2.3, perform signal type and direction matching, and ensure that the signal type and direction are consistent in the PCB design document and HDL code through semantic analysis and rule matching; S2.4 If there are inconsistencies in signal name, function description, bit width, type, or direction, a detailed inconsistency report will be generated, listing each inconsistent signal and possible solutions. S2.4 Generate a signal mapping table based on the signal type and direction matching results, which lists the correspondence of each signal in the PCB design document and HDL code; if there are inconsistencies, mark them in the table.

[0010] Furthermore, the automatic generation of inspection rules based on PCB design rules, structured signal information tables, and signal mapping tables includes bit width inspection rules, connectivity inspection rules, and functional inspection rules, including: S3.1, Input the structured signal information table, signal mapping table, and PCB design rules; S3.2 uses a multimodal large language model to parse the structured signal information table and signal mapping table, and generates suitable verification rules based on the requirements of PCB design rules; S3.3 adopts a retrieval-enhanced generation approach that combines a verification knowledge base and a generative model to generate verification rules that better meet actual design requirements. It retrieves rules related to the current design from the verification knowledge base and combines the retrieved rules with the rules generated by the model to optimize the final generated verification assertions. S3.4, Output automatically generated inspection rules, including: Bit width check rule: Verify that the bit width of each signal meets the requirements in the PCB design document; Connectivity check rules: Verify that the connections between signals are correct; Functional verification rules: Verify that the function of the signals conforms to the description in the PCB design document; S3.5, all generated verification rules will be presented in the form of SystemVerilog assertions. The report will include the following: a detailed list of bit-width check rules, connectivity check rules, and functionality check rules; the generation process of each rule, the signals involved, and the compliance checks of the rule.

[0011] Furthermore, the process of using a multimodal large language model to parse the structured signal information table and signal mapping table, combined with the requirements of PCB design rules, generates suitable verification rules, including: S3.2.1 For each signal, check whether its bit width meets the bit width requirements defined in the document, and generate bit width check rules; generate corresponding bit width check rules by extracting signal bit width data from PCB design documents and HDL code; if the signal bit width is inconsistent, generate corresponding error messages; S3.2.2, Generate corresponding connectivity check rules through signal connection topology diagram and mapping table; Automatically generate check rules using signal connection relationship diagram to ensure that signals are correctly connected according to the designed topology; For each signal pair, check whether they are correctly connected according to design requirements; S3.2.3, Generate functional check rules. Functional checks ensure that these functions are correctly implemented in the design, including: combining the functional description of the signal with its actual function to achieve functional verification; if the signal does not work as expected, generate the corresponding error message.

[0012] Furthermore, the step of using formal verification tools to verify the effectiveness of the inspection rules and optimizing the inspection rules based on the verification results includes: S4.1, Input the generated bit width check rules, connectivity check rules, and functionality check rules, as well as the verified golden RTL design; S4.2, Set the verification metrics, including: syntax correctness and functional pass rate; S4.3, Syntax correctness verification: Ensure that the generated SystemVerilog assertions conform to the syntax specification and can be correctly executed in the formal verification tool; S4.4, Functional correctness verification; ensure that the generated SystemVerilog assertions can accurately identify potential problems in the design during the functional verification process and evaluate the effectiveness of the generated rules; Output the pass rate for each assertion, list the assertions that failed to be validated, and point out possible errors in the design; S4.5, evaluate the quality of the generated rules, and list the evaluation results for each assertion, including syntactic correctness and functional pass rate.

[0013] Furthermore, the optimized inspection rules are used to verify the PCB design rules and automatically generate correction suggestions, including: Based on the evaluation results, the generated rules are optimized, including: If some rules have a low pass rate or fail functional verification, adjust the rule generation strategy; For assertions that fail, the system automatically corrects the rules or requires manual intervention to modify them; Based on the verification results and optimization strategies, new and improved inspection rules are generated, and verification continues to ensure the effectiveness of the optimized rules.

[0014] Secondly, the present invention provides an automatic PCB design rule checking and correction system based on a multimodal large model, comprising: The data input module is used to input multimodal PCB data into the multimodal large model. The multimodal PCB data types include: PCB design documents, signal definition files, and verified golden RTL designs. The multimodal data parsing module is used to parse PCB design documents through a large multimodal model, extract signal information, and generate a structured signal information table. The signal mapping table generation module is used to match the natural language signal descriptions in the PCB design document with the signal definitions in the actual hardware description language code, based on the structured signal information table and signal definition file, to generate a signal mapping table. The inspection rule generation module is used to automatically generate inspection rules based on PCB design rules, structured signal information tables, and signal mapping tables, including bit width inspection rules, connectivity inspection rules, and functional inspection rules. The check rule verification module is used to verify the effectiveness of check rules using formal verification tools and optimize the check rules based on the verification results. The correction suggestion generation module is used to verify PCB design rules by applying optimized inspection rules and automatically generate correction suggestions.

[0015] Thirdly, the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method for automatic checking and correction of PCB design rules based on a multimodal large model.

[0016] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method for automatic checking and correction of PCB design rules based on a multimodal large model.

[0017] Fifthly, the present invention provides a computer program product, the computer program product comprising computer instructions, the computer instructions instructing a computer to execute the method for automatically checking and correcting PCB design rules based on a multimodal large model.

[0018] The beneficial effects of this invention are as follows: This invention utilizes a multimodal large model to automatically generate and update inspection rules. It parses text, images, tables, and other data in PCB design documents using this model, extracts structured signal information tables, and automatically generates dynamically adaptable inspection rules, including bit width checks, connectivity verification, and functional analysis. The generated rules are optimized using Retrieval Enhanced Generation (RAG) technology combined with a verification rule base to ensure comprehensive coverage and high accuracy. The system further evaluates the rules using formal verification tools, automatically correcting potential defects and improving rule quality and adaptability. This invention significantly improves the efficiency and accuracy of PCB design inspection, reduces the need for manual intervention, and can be widely applied to complex electronic design scenarios to meet rapidly changing technological and market demands. It can dynamically adapt to different design requirements, reduce manual intervention, significantly lower maintenance costs, and improve adaptability. Simultaneously, combined with the multimodal large model, this invention can intelligently parse and understand various information in PCB design documents, including text, images, and tables, achieving more comprehensive and accurate DRC, thereby improving inspection accuracy and coverage, reducing error rates, and enhancing overall work efficiency. It addresses the limitations of existing PCB Design Rule Check (DRC) tools, such as high maintenance costs of static rule bases and insufficient multimodal data processing capabilities. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This invention provides a flowchart of a method for automatic checking and correction of PCB design rules based on a multimodal large model; Figure 2 The present invention provides a schematic diagram for automatic PCB design rule checking and correction based on a multimodal large model. Figure 3 This invention provides an automatic PCB design rule checking and correction system based on a multimodal large model; Figure 4 This is a schematic diagram of an electronic device provided by the present invention. Detailed Implementation

[0021] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0022] Example 1 like Figure 1 As shown, this invention provides a method for automatically checking and correcting PCB design rules using a multimodal large model, including: S1. Input the multimodal PCB data into the multimodal large model. The multimodal PCB data types include: PCB design documents, signal definition files, and verified golden RTL designs. S2 analyzes PCB design documents using a multimodal large model, extracts signal information, and generates a structured signal information table. S3, based on the structured signal information table and signal definition file, matches the natural language signal descriptions in the PCB design document with the signal definitions in the actual hardware description language code to generate a signal mapping table. S4 automatically generates inspection rules based on PCB design rules, structured signal information tables, and signal mapping tables, including bit width inspection rules, connectivity inspection rules, and functional inspection rules. S5. Use formal verification tools to verify the effectiveness of the inspection rules and optimize the inspection rules based on the verification results. S6 applies optimized inspection rules to verify PCB design rules and automatically generates correction suggestions.

[0023] The advantages of the above solution are as follows: Traditional methods struggle to handle the "format barrier" between natural language documents and HDL code, requiring manual data conversion; multimodal large models can directly parse heterogeneous data, eliminating the "semantic gap" and significantly reducing data preprocessing costs. From signal information extraction and rule generation to inspection and correction suggestions, the entire process requires no manual intervention: traditional manual extraction of signal information and rule writing takes days to weeks, while this method can shorten it to hours; manual inspection is prone to missing complex rules (such as functional issues involving multiple signal linkages), while automated inspection can cover 100% of the generated rules, improving efficiency by more than 10 times. The semantic understanding capability of multimodal large models reduces the error in matching natural language and code (the error rate of traditional manual matching is about 5%-10%, while this method can reduce it to below 1%); formal verification tools ensure that the inspection rules have no logical loopholes, avoiding "missed detections" or "false detections" caused by rule errors, improving verification reliability by more than 30%. Traditional methods rely on fixed rule bases, making it difficult to adapt to customized design needs (such as special signal rules for new projects). This method, based on a multimodal large model, dynamically generates rules, enabling rapid adaptation to different projects and PCB designs of varying specifications, without the need for manual rule base reconstruction. PCB design rules are complex (involving electromagnetic compatibility, signal integrity, etc.), and traditional checks require the involvement of senior engineers. This method, through automated processes, solidifies experience into executable rules, reducing reliance on highly experienced personnel and accelerating the onboarding of newcomers. Therefore, this method, by combining a multimodal large model with formal verification, achieves "automation, precision, and flexibility" in PCB design rule checking, significantly shortening the design cycle and reducing error risks, representing a direction for intelligent upgrades in the field of PCB design verification.

[0024] The above plan is explained in detail below: (1) Data input: Input the multimodal PCB design documents into the system, including text descriptions, schematics, layout diagrams and specifications; (2) Data parsing: The document content is parsed using a multimodal large model to extract signal information and generate a structured signal information table; the data parsing in step (2) includes: Image data analysis: Extract key features from the circuit diagram and generate a signal topology map using a convolutional neural network; Text data parsing: Extracting signal names and functional descriptions using named entity recognition and semantic analysis; Table data parsing: Extracting table information through optical character recognition and structured processing.

[0025] (3) Rule generation: Based on the PCB design rules, structured signal information table and signal mapping table, check rules are automatically generated, including bit width check rules, connectivity check rules and functional check rules; the rule generation in step (3) adopts retrieval enhancement generation technology, combined with the system verification rule base to improve the rule quality.

[0026] (4) Rule Validation and Optimization: Validate the effectiveness of the inspection rules using formal validation tools, and optimize the inspection rules based on the validation results; the rule validation and optimization in step (4) includes: Syntax validation: Checks whether the generated rules conform to the SystemVerilog assertion syntax standard; Functional verification: Check whether the generated rules can correctly capture functional errors in the design.

[0027] (5) Inspection and Correction: The optimized inspection rules are applied to verify the PCB design rules, and correction suggestions are automatically generated. The inspection and correction in step (5) includes: Detect design defects using the generated inspection rules; Optimized rules provide suggestions for improvement to reduce design errors and increase efficiency.

[0028] In the multimodal data parsing and structured extraction steps, the multimodal data processing framework can simultaneously process PCB design documents in various formats, including text, images, and tables. It transforms unstructured data into unified structured information using NLP, OCR, and CV technologies. For signal information extraction based on M-LLM, it automatically extracts detailed information such as the name, bit width, functional description, and connection relationships of each signal from the PCB design document using a Large Language Model (M-LLM) with multimodal processing capabilities. The multimodal data processing framework efficiently parses PCB design documents in various formats, ensuring data consistency and accuracy. The M-LLM-based signal information extraction method reduces manual intervention and automatically extracts accurate signal information.

[0029] The automatic rule generation and optimization process includes rule type classification and generation logic: rule types are categorized into three types: bit width, connectivity, and functionality, ensuring broad and accurate rule coverage. Retrieval Enhancement Generation (RAG) technology combines SVA and formal validation knowledge bases to optimize the generated rule types, ensuring syntactic correctness and functional accuracy.

[0030] The rule type classification and generation logic steps comprehensively cover all checkpoints in PCB design, improving the efficiency and reliability of rule generation. The Retrieval Enhancement Generation (RAG) technology step enhances the quality and applicability of rules, ensuring their effectiveness.

[0031] The purpose of this invention is to achieve multimodal data parsing and automatic inspection rule generation. Through a multimodal data processing framework and M-LLM, PCB design documents are efficiently parsed and signal information extracted; through rule classification and RAG technology, high-quality inspection rules are automatically generated and optimized. These key technologies significantly improve the efficiency and accuracy of PCB design rule inspection, reducing manual intervention. Figure 2 The method of the present invention will be described in detail below: S1. Data Input Step: Input the multimodal PCB design document into the multimodal large model. Input data types include: PCB design documents include multimodal files such as text descriptions, schematics, layout diagrams, and specifications.

[0032] Signal definition file: Contains the definitions of all signals, such as input / output ports, internal signals, registers, etc.

[0033] Validated gold RTL design: used as a benchmark to evaluate the correctness of the generated inspection rules.

[0034] S2. The main technical steps after inputting the multimodal large model include: Step 1: Multimodal data parsing and structured extraction; Extract structured design information from PCB design documents for use in subsequent steps. Leveraging multimodal large-scale model analysis capabilities, accurately understand and extract various data formats such as text, images, and tables from the documents, transforming them into structured data tables to provide a foundation for subsequent signal definition mapping, rule generation, and other processes. Specifically, this includes: 1.1 Multimodal data input and preprocessing; Input data includes: PCB design documents include multimodal data formats such as text descriptions, schematics, layout diagrams, and specifications.

[0035] Formatting requirements: PCB design documents may include images (such as circuit diagrams and layout diagrams), tables (such as signal description tables), and text describing the design in natural language (such as design specifications and signal descriptions).

[0036] The input data needs to undergo preprocessing steps: Image preprocessing: For image data such as schematic diagrams and layout diagrams, computer vision technology (such as convolutional neural networks, CNN) is used to segment and recognize the design diagrams, and to extract connection information, component information, etc. in the circuit.

[0037] Text preprocessing: The text in the specification document is segmented, stop words are removed, named entity recognition (NER) is performed, and signal-related keywords (such as signal name, function description, etc.) are extracted.

[0038] Table data extraction: For tables containing signal definitions, OCR (Optical Character Recognition) technology is used to extract text from the image and perform table structuring.

[0039] 1.2 Multimodal Large Model (LLM 1 SPEC Analyzer) Analysis; Multimodal Large Model (LLM 1) is used to analyze data extracted from different sources (text, images, tables), understand its content, and transform it into structured information.

[0040] Signal name parsing: Extract signal names, such as "clk", "reset", "data_in", etc., from the document using natural language processing (NLP) algorithms.

[0041] Signal function description: Analyze the function description of each signal to identify its role in the circuit, such as input signal, output signal or clock signal.

[0042] Signal connectivity: For image data (such as schematics), image recognition technology is used to extract the connectivity between signals. The interconnections between signals are identified through the circuit's topology, especially the connections between clock signals, reset signals, and data transmission signals.

[0043] Signal attribute extraction: Extract the attributes of each signal, such as bit width, direction (input, output), and whether it is a clock signal.

[0044] The output mainly includes: a structured signal information table; detailed information for each signal, including signal name, bit width, function description, connection relationship, etc.

[0045] Table 1 Signal Information Table (Example):

[0046] 1.3 Image Data Parsing and Signal Layout Analysis; In PCB design, layout diagrams and schematics are important design inputs, containing information on the electrical connections and physical layout of signals. Further image processing and signal layout analysis are required for this image data.

[0047] Image feature extraction: Convolutional Neural Networks (CNNs) are used to extract key features from the schematic diagram, such as component connections, signal paths, and network structure. A CNN model is trained to identify the relationships between different signals and circuit board components.

[0048] Topology recognition: Based on image recognition results, a topology diagram of the relationships between signals is established, identifying the transmission path of each signal in the circuit. For example, the transmission path of the clock signal from the clock source to all registers, or the connection path between the data bus and each processing unit, can be identified.

[0049] The output mainly includes: a signal connection topology diagram: a diagram of signal connections obtained through image processing techniques, representing the transmission paths of signals on the circuit board and their interdependencies. Signal connection topology diagram (example): clk → [Register 1, Register 2, Sequential Circuit]; reset → [Register 1, Register 2]; data_in → [Data Receive Module]; data_out → [Data Send Module].

[0050] 1.4 Data Integration and Output: After multimodal large model analysis, all extracted data will be integrated to generate the final structured output. This output data provides the foundation for subsequent signal definition mapping and rule generation.

[0051] Data integration: Integrate the signal information obtained from text parsing, the signal connection relationships obtained from image parsing, and the signal attribute information extracted from tables into a unified structured data format (such as CSV, JSON).

[0052] Output structured information: The final generated structured information table will include detailed descriptions of all signals, bit widths, connection relationships, and other information, which will facilitate further processing in subsequent steps.

[0053] Output: Structured signal information table, signal connection topology diagram, etc., to ensure data accuracy and usability for subsequent steps.

[0054] Signal width calculation formula: Assuming the signal S has a width of Width(S), in the design, the signal width should meet the design specification Width(S) = n, where n is the width value specified in the PCB design document.

[0055] ; Signal connectivity verification formula: For signals S1 and S2, if they are connected, then: ; Step 2: Signal Definition Mapping Generation; This step matches the natural language signal descriptions in the PCB design document with the signal definitions in the actual Hardware Description Language (HDL) code to ensure signal consistency. This process is crucial for connecting the PCB design document with the hardware implementation, ensuring seamless integration of signal definitions from the PCB design document to the actual design. Specific operations include: 2.1 Input data preparation, including: Signal definition file (HDL file): contains signal declarations, comments and their functional definitions in the hardware design, and is usually written using a hardware description language (HDL) such as Verilog or VHDL.

[0056] Structured Signal Information Table: The output from step 1 contains signal information extracted from the PCB design document, such as signal name, bit width, function description, connection relationship, etc.

[0057] 2.2 Signal Definition Matching Model (LLM 2 Signal Mapper); This model uses a multimodal large language model (LLM 2 Signal Mapper) to analyze signal declarations in signal definition files (such as Verilog code) and match them with a structured signal information table extracted from PCB design documents. The model performs the matching task using the following steps: 2.3 Signal Name Matching: First, each signal name in the PCB design document is extracted and cleaned, and then matched one by one with the signal names defined in the HDL file. If the signal names match exactly, the signals are considered the same; if there are slight differences in the names (such as clk and clk_1), a fuzzy matching algorithm is used to determine whether they are the same signal. The signal name matching formula is as follows: ; Here, Signal_{doc} is the signal name in the PCB design document, and Signal_{hdl} is the signal name in the HDL file.

[0058] Functional description matching: For each signal, if the signal name matches, further semantic analysis of the signal's functional description is performed using natural language processing techniques (such as BERT, GPT, etc.) to ensure consistency between the functional description in the PCB design document and the implementation logic in the HDL code. For example, the PCB design document might describe the signal as a "clock signal," while the HDL code might use a comment to describe it as "clock." Semantic matching ensures the functional consistency of the signals. The functional description matching formula can be based on similarity calculations (such as cosine similarity) to determine the consistency of the functional descriptions. ; Among them, Desc_{doc} and Desc_{hdl} are signal description texts extracted from PCB design documents and HDL code, and their cosine similarity is calculated after vector representation.

[0059] Signal width matching: Check whether the signal widths defined in the PCB design document are consistent with the widths declared in the HDL file. If they are inconsistent, calibration and adjustment are required. For example, if the "data_in" signal width is 8 bits in the PCB design document, but is declared as 16 bits in the HDL file, this inconsistency needs to be noted in the report. The signal width matching formula is as follows: ; Here, Width_{doc} and Width_{hdl} are the signal bit widths in the PCB design document and HDL code, respectively.

[0060] 2.3 Signal Type and Direction Matching; The signal type (e.g., input signal, output signal, bidirectional signal) and direction (e.g., forward, reverse) are crucial for signal mapping. Semantic analysis and rule matching ensure that the signal type and direction are consistent in the PCB design document and HDL code.

[0061] Signal type matching: Check if the signal types are consistent, such as input signals, output signals, or clock signals. In PCB design documents, signal types may be defined using descriptive terms such as "input" and "output," while in HDL, signal types are declared using keywords such as input and output.

[0062] ; Here, Type_{doc} and Type_{hdl} are the signal types in the PCB design document and HDL code, respectively.

[0063] Signal direction matching: For bidirectional signals, match their directional description. For example, a signal might be described as an "input / output" signal in a PCB design document, while it might be declared as inout in the HDL. Matching signal directions ensures consistency between design and implementation.

[0064] ; Here, Direction_{doc} and Direction_{hdl} are the signal directions in the PCB design document and HDL code, respectively.

[0065] 2.4 Inconsistency Reporting and Handling; If inconsistencies exist in signal names, function descriptions, bit widths, types, or directions, a detailed inconsistency report will be generated, listing each inconsistent signal and its possible solutions. Depending on the rules, you can choose to automatically update the PCB design document or HDL code, or provide the report to the designer for manual correction.

[0066] Output: Generate a signal mapping table that lists the correspondence between each signal in the PCB design document and HDL code. Any inconsistencies are marked in the table, and suggested corrections are provided.

[0067] Table 2 Signal Mapping Table (Example):

[0068] Step 3: Automatic Check Rule Generation; Based on the extracted structured signal information table and signal mapping relationships, comprehensive and accurate check rules are automatically generated. These check rules will be used to verify whether the design meets specified requirements, including signal bit width, connectivity, and functionality. Specifically, the generated check rules include SystemVerilog Assertions (SVAs) for automated verification and remediation of potential problems in the design. Specific operations include: 3.1 Input data preparation; Input data includes: Structured signal information table: from step 1, it contains signal information extracted from the PCB design document, such as signal name, bit width, function description, connection relationship, etc.

[0069] Signal mapping table: from step 2, containing the correspondence between signals in the PCB design document and HDL code.

[0070] PCB design rules: Based on the specifications in the PCB design document, extract the basic PCB design rules and requirements (such as signal width, connection relationship, functional description, etc.).

[0071] 3.2 Rule Generation Model (LLM 3 SVA Generator); The LLM 3 SVA Generator is used to automatically generate verification rules. LLM 3 generates suitable verification rules by parsing the structured signal information table and signal mapping table, combined with the requirements of the PCB design rules.

[0072] 3.2.1 Bit Width Check Rule Generation; Bit width check rules are the basic rules to ensure that the signal bit width conforms to the design specifications. For each signal, check whether its bit width meets the bit width requirements defined in the document.

[0073] By extracting signal bit width data from PCB design documents and HDL code, corresponding bit width checking rules are generated. If the signal bit widths are inconsistent, corresponding error messages are generated.

[0074] Let the bit width of signal S be Width(S), and the bit width specified in the PCB design document be Width_{doc}(S), then the bit width checking rule can be expressed as: ; The generated SystemVerilog assertion (SVA) is as follows: assert property (Width(S) ==Width_{doc}(S)); This assertion rule ensures that the bit width of signal S is consistent with that specified in the PCB design document.

[0075] 3.2.2 Connectivity Check Rule Generation; Connectivity check rules are used to ensure that the connections between signals are correct and that the propagation of signal values ​​meets expectations. Corresponding connectivity check rules are generated using the signal connection topology diagram and mapping table. Specific operations include: By using a signal connection diagram, inspection rules are automatically generated to ensure that signals are correctly connected according to the designed topology.

[0076] For each signal pair, check that they are connected correctly as required by the design.

[0077] Suppose that signals S1 and S2 should be connected, and their connection relationship Connection(S1, S2) should be True. Then the connectivity check rule can be expressed as: ; The generated SystemVerilog assertions (SVAs) are as follows: assert property (Connection(S1, S2) == true); This assertion rule ensures that signals S1 and S2 are correctly connected as required by the design.

[0078] 3.2.3 Functional Check Rule Generation; Functional check rules ensure that the functionality of signals conforms to the description in the PCB design document. For example, a signal might be used to trigger the timing logic of a module or to control the transmission of signals. Functional checks ensure that these functions are correctly implemented in the design. This includes: Functional verification is achieved by combining the functional description of the signal with its actual function.

[0079] If the signal does not function as expected, an error message is generated accordingly.

[0080] Let the function of signal S be Func(S), and the function specified in the PCB design document be Func_{doc}(S), then the functionality check rule can be expressed as: ; The generated SystemVerilog assertions (SVAs) are as follows: The assertion rule `assert property (Func(S) == Func_{doc}(S));` ensures that the function of signal S conforms to the function specified in the PCB design document.

[0081] 3.3 Enhancement Techniques: Retrieval-Enhanced Generation (RAG); To improve the quality and accuracy of rules, SVAGenerator employs Retrieval-Enhanced Generation (RAG) technology. RAG combines existing verification knowledge bases (such as the system Verilog assertion library, formal verification knowledge base, etc.) with generative models, enabling the generation of verification rules that better meet actual design requirements.

[0082] Retrieve rules relevant to the current design from the existing validation knowledge base. Combine the retrieved rules with the rules generated by the model to optimize the final validation assertions.

[0083] For example, if the PCB design rules involve special timing checks, RAG can retrieve timing verification rules from the knowledge base and combine them with the functional description of the current signal to generate accurate functional check rules.

[0084] 3.4 Output the generated inspection rules; Finally, the SVA Generator outputs the following three types of inspection rules: Bit width check rule: Verify that the bit width of each signal meets the requirements in the PCB design document.

[0085] Connectivity check rule: Verify that the connections between signals are correct.

[0086] Functional check rules: Verify that the function of the signals conforms to the description in the PCB design document.

[0087] Each rule will be converted into a SystemVerilog assertion (SVA) and output in a standardized format.

[0088] 3.5 Results Display and Subsequent Steps; Generated SystemVerilog Assertions (SVA): All generated verification rules will be displayed in the form of SystemVerilog assertions for easy use in subsequent formal verification tools.

[0089] The generated report output includes the following: A detailed list of bit-width check rules, connectivity check rules, and functionality check rules; the generation process of each rule, the signals involved, and the compliance checks for each rule.

[0090] Step 4: Rule Evaluation and Optimization; Evaluate the quality of the automatically generated inspection rules and perform necessary optimizations. Using a formal verification tool (FPV), verify the syntactic and functional correctness of the generated SystemVerilog assertions (SVAs) to ensure that the generated rules can effectively check for potential problems in the design. Optimize the rules based on the verification results. Specific operations include: 4.1 Input data preparation; Input data includes: generated SystemVerilog assertions (SVA): from the output of step 3, containing all generated check rules (bit width, connectivity, functionality checks, etc.).

[0091] Verified Gold RTL Design: As a baseline design, it is used to functionally verify the generated assertions, ensuring that the generated rules can effectively identify problems in actual designs.

[0092] 4.2 Rule Assessment Preparation; Before conducting a rule assessment, the following needs to be prepared: Formal Verification Tool (FPV): Select a formal verification tool (such as Cadence JasperGold, Synopsys VC Formal, etc.) to verify the generated SystemVerilog assertions. Formal verification tools can prove the correctness of assertions using mathematical methods and check whether the design meets expectations.

[0093] Validation metrics: Set validation metrics, which mainly include: Syntax correctness: Check whether the syntax of the generated SystemVerilog assertions conforms to the standard and whether they can be successfully executed in a formal verification tool.

[0094] Functional pass rate: Check whether the assertions can correctly capture functional errors in the design and evaluate their effectiveness in actual design verification.

[0095] 4.3 Syntax Correctness Verification; Ensure that the generated SystemVerilog assertions conform to the syntax specification and can be correctly executed in the formal verification tool. Syntax errors will prevent the verification tool from running, affecting the entire verification process. Specific steps: Syntax checking: Input each generated SystemVerilog assertion into a formal validation tool (such as Cadence JasperGold). The tool will automatically check whether the assertion's syntax conforms to the SystemVerilog specification.

[0096] Validation failed: If there is a syntax error in the assertion, the formal validation tool will provide detailed error information to help developers correct it.

[0097] If an assertion is `assert property (Width(S) == Width_{doc}(S))`, then the syntax correctness verification is as follows: ; Syntax error report: If a syntax error exists, output an error report, listing the error assertions and suggested fixes.

[0098] 4.4 Functional Correctness Verification (Formal Verification); Ensure that the generated SystemVerilog assertions can accurately identify potential problems in the design during functional verification and evaluate the effectiveness of the generated rules. Specific operations include: Formal verification run: Input the generated SystemVerilog assertions along with the verified Golden RTL design into the formal verification tool for formal verification (FPV). The formal verification tool checks whether the design meets the expected functionality in the assertions using automated mathematical verification methods.

[0099] Verification Result Analysis: Analyze the pass / fail status of each assertion using the output of the formal verification tool. If an assertion passes verification, the design conforms to the rules; if an assertion fails verification, there are potential problems in the design, requiring further analysis and modification.

[0100] Let assertion A(S) represent the functional requirement of signal S, and the verification result be ValidationResult(A(S)). Then the formula for verifying functional correctness is as follows: ; The outputs include: Functional Validation Report: Outputs the pass rate for each assertion, lists the assertions that failed validation, and indicates potential errors in the design. Inconsistency Report: Reports the signals indicating that assertions failed during functional validation and related design errors.

[0101] 4.5 Evaluation Indicators; The quality of generated rules is mainly evaluated from the following dimensions: Syntax Correctness: Definition: All generated SystemVerilog assertions must be syntactically correct and able to execute successfully in the formal verification tool. Metric: Check whether all assertions pass the syntax check of the formal verification tool and generate a syntax error report.

[0102] Functional pass rate: Definition: The functional correctness of an assertion refers to its ability to effectively capture functional errors in the design. Metric: The pass rate of each generated assertion in formal verification is statistically analyzed to evaluate its functional detection capability. Syntax correctness ratio: ; Functionality pass rate: ; Output an evaluation report: List the evaluation results for each assertion, including metrics such as syntactic correctness and functional pass rate. For example, out of 100 generated assertions, 95 passed the syntactic check, resulting in a functional pass rate of 85%.

[0103] 4.6 Rule Optimization; Based on the evaluation results, the generated rules are optimized to improve their accuracy and coverage, ensuring that the rules can effectively detect potential problems in the design. Specific operations include: Adjusting the generation algorithm: If some rules have a low pass rate or fail functional verification, the rule generation strategy can be adjusted. For example, the coverage and accuracy of rules can be improved by enhancing the precision of rule descriptions, improving RAG technology, and updating the verification knowledge base.

[0104] Automated correction: For assertions that fail, the system can automatically correct the rules or allow manual intervention to modify the rules, ensuring that the rules can be effectively applied to design verification.

[0105] The optimization plan includes: Enhancing the rule generation model: By introducing more design knowledge and utilizing advanced formal verification techniques, the capabilities of the assertion generation model are improved. Feedback optimization: Based on feedback from the formal verification tool, potential problems in the generated rules are corrected to improve the rule verification capability.

[0106] Output: Optimized Rules: Based on the verification results and optimization strategy, new and improved inspection rules are generated and verified again to ensure the effectiveness of the optimized rules. The flowchart is shown below: Example 2 like Figure 3 As shown, the present invention also provides a system for automatically checking and correcting PCB design rules using a multimodal large model, comprising: The data input module 100 is used to input multimodal PCB data into the multimodal large model, wherein the multimodal PCB data types include: PCB design documents, signal definition files, and verified golden RTL designs; The multimodal data parsing module 200 is used to parse PCB design documents through a multimodal large model, extract signal information, and generate a structured signal information table; The signal mapping table generation module 300 is used to match the natural language signal descriptions in the PCB design document with the signal definitions in the actual hardware description language code based on the structured signal information table and signal definition file to generate a signal mapping table. The inspection rule generation module 400 is used to automatically generate inspection rules based on PCB design rules, structured signal information table and signal mapping table, including bit width inspection rules, connectivity inspection rules and functional inspection rules; The inspection rule verification module 500 is used to verify the validity of inspection rules using formal verification tools and optimize the inspection rules based on the verification results. The correction suggestion generation module 600 is used to verify the PCB design rules by applying optimized inspection rules and automatically generate correction suggestions.

[0107] This invention proposes an automatic PCB design rule checking and correction system based on a multimodal large model, addressing the limitations of existing Design Rule Check (DRC) tools such as high maintenance costs of static rule bases and insufficient multimodal data processing capabilities. The system parses text, images, tables, and other data in PCB design documents using a multimodal large model, extracting structured signal information and automatically generating dynamically adaptable check rules, including bit width checks, connectivity verification, and functional analysis. The generated rules are optimized using Retrieval Enhanced Generation (RAG) technology combined with a verification rule base to ensure comprehensive coverage and high accuracy. The system further evaluates the rules using formal verification tools, automatically correcting potential defects and improving rule quality and adaptability. This invention significantly improves the efficiency and accuracy of PCB design checks, reduces the need for manual intervention, and can be widely applied to complex electronic design scenarios to meet rapidly changing technological and market demands.

[0108] Example 3 like Figure 4 As shown, a third objective of this invention is to provide an electronic device, including a memory 701, a processor 702, and a computer program stored in the memory 701 and executable on the processor. When the processor executes the computer program, it implements the aforementioned method for automatic PCB design rule checking and correction based on a multimodal large model. The device also includes a communication interface 703 and a bus 704.

[0109] When the processor executes the computer program, it implements the automatic PCB design rule checking and correction method based on a multimodal large model as described in Embodiment 1, specifically including: Input multimodal PCB data into the multimodal large model, where the multimodal PCB data types include: PCB design documents, signal definition files, and verified golden RTL designs; By analyzing PCB design documents using a multimodal large model, signal information is extracted and a structured signal information table is generated. Based on the structured signal information table and signal definition file, the natural language signal descriptions in the PCB design document are matched with the signal definitions in the actual hardware description language code to generate a signal mapping table. Based on PCB design rules, structured signal information tables, and signal mapping tables, check rules are automatically generated, including bit width check rules, connectivity check rules, and functional check rules. Use formal verification tools to verify the effectiveness of the inspection rules, and optimize the inspection rules based on the verification results; The optimized inspection rules are applied to verify the PCB design rules and automatically generate correction suggestions.

[0110] Example 4 The fourth objective of this invention is to provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the automatic PCB design rule checking and correction method based on a multimodal large model as described in Embodiment 1.

[0111] In this embodiment, the computer-readable storage medium is a non-volatile storage medium, specifically a ROM, RAM, disk, or optical disk. In this embodiment, the computer-readable storage medium is a 512GB NVMe SSD, which uses 3D NAND flash memory technology and features high-speed read / write performance and long lifespan.

[0112] When the computer program is executed by the processor, it implements the automatic PCB design rule checking and correction method based on a multimodal large model as described in Embodiment 1, specifically including: Input multimodal PCB data into the multimodal large model, where the multimodal PCB data types include: PCB design documents, signal definition files, and verified golden RTL designs; By analyzing PCB design documents using a multimodal large model, signal information is extracted and a structured signal information table is generated. Based on the structured signal information table and signal definition file, the natural language signal descriptions in the PCB design document are matched with the signal definitions in the actual hardware description language code to generate a signal mapping table. Based on PCB design rules, structured signal information tables, and signal mapping tables, check rules are automatically generated, including bit width check rules, connectivity check rules, and functional check rules. Use formal verification tools to verify the effectiveness of the inspection rules, and optimize the inspection rules based on the verification results; The optimized inspection rules are applied to verify the PCB design rules and automatically generate correction suggestions.

[0113] Example 5 The fifth objective of this invention is to provide a computer program product, which includes computer instructions that instruct a computer to execute the automatic PCB design rule checking and correction method based on a multimodal large model as described in Embodiment 1.

[0114] In this embodiment, the computer program product is a software package, including an installer, main program, configuration files, help documentation, and sample data. The software package is distributed as an ISO image file and can be installed on the target computer via CD or USB flash drive.

[0115] The computer instructions in the computer program product are written in multiple programming languages, including C++ (core algorithms and hardware interfaces), Python (data analysis and visualization), and JavaScript (web interface). The program architecture adopts a modular design, including the following main modules: Core module: Responsible for implementing the core algorithm of the automatic PCB design rule checking and correction method based on multimodal large model; Hardware interface module: responsible for communicating with sensors and control devices; Data storage module: responsible for storing runtime data in the database; Data analysis module: responsible for analyzing historical data and extracting useful information; Visualization module: Responsible for displaying data in chart form; Web service module: Provides a web interface for users to remotely access and control the system.

[0116] The computer instructions direct the computer to execute the automatic PCB design rule checking and correction method based on a multimodal large model as described in Embodiment 1, specifically including: Input multimodal PCB data into the multimodal large model, where the multimodal PCB data types include: PCB design documents, signal definition files, and verified golden RTL designs; By analyzing PCB design documents using a multimodal large model, signal information is extracted and a structured signal information table is generated. Based on the structured signal information table and signal definition file, the natural language signal descriptions in the PCB design document are matched with the signal definitions in the actual hardware description language code to generate a signal mapping table. Based on PCB design rules, structured signal information tables, and signal mapping tables, check rules are automatically generated, including bit width check rules, connectivity check rules, and functional check rules. Use formal verification tools to verify the effectiveness of the inspection rules, and optimize the inspection rules based on the verification results; The optimized inspection rules are applied to verify the PCB design rules and automatically generate correction suggestions.

[0117] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0118] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0119] This invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, readable storage media, optical storage, etc.) containing computer-usable program code.

[0120] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0121] Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort should fall within the scope of protection of the present invention.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for automatic checking and correction of PCB design rules based on a multimodal large model, characterized in that, include: Input multimodal PCB data into the multimodal large model, where the multimodal PCB data types include: PCB design documents, signal definition files, and verified golden RTL designs; By analyzing PCB design documents using a multimodal large model, signal information is extracted and a structured signal information table is generated. Based on the structured signal information table and signal definition file, the natural language signal descriptions in the PCB design document are matched with the signal definitions in the actual hardware description language code to generate a signal mapping table. Based on PCB design rules, structured signal information tables, and signal mapping tables, check rules are automatically generated, including bit width check rules, connectivity check rules, and functional check rules. Use formal verification tools to verify the effectiveness of the inspection rules, and optimize the inspection rules based on the verification results; The optimized inspection rules are applied to verify the PCB design rules and automatically generate correction suggestions.

2. The method for automatic checking and correction of PCB design rules based on a multimodal large model according to claim 1, characterized in that, The process of parsing PCB design documents using a multimodal large model, extracting signal information, and generating a structured signal information table includes: S1.1, Multimodal data input and preprocessing, including: Image data analysis: Extract key features from the circuit diagram and generate a signal topology map using a convolutional neural network; Text data parsing: Extracting signal names and functional descriptions using named entity recognition and semantic analysis; Table data parsing: Extracting table information through optical character recognition and structured processing; S1.2, Multimodal large-scale model analysis of PCB design documents, understanding the content and transforming it into structured information, including: Signal name parsing: Extracting signal names appearing in PCB design documents using natural language processing algorithms; Signal function description: Analyze the function description of each signal and identify its role in the circuit; Signal connectivity: For image data, the connectivity between signals is extracted using image recognition technology, and the interconnections between signals are identified through the circuit topology. Signal attribute extraction: Extract the attributes of each signal to obtain detailed information about each signal; S1.3, concerning the image data parsing and signal layout analysis of PCB design documents, includes: Image feature extraction: Key features in the schematic diagram are extracted using a convolutional neural network; the correlation between different signals and circuit board components is identified by training a convolutional neural network model. Topology recognition: Based on image recognition results, a topology diagram of the relationship between signals is established, and the transmission path of each signal in the circuit is identified; Output signal connection topology diagram, a signal connection relationship diagram obtained through image processing technology, represents the transmission path of signals in the circuit board and their interdependencies; S1.4 After multimodal large model parsing, all extracted data will be integrated to generate the final structured output, including: The signal information obtained from text parsing, the signal connection relationships obtained from image parsing, and the signal attribute information extracted from tables are integrated into a unified structured data format; the generated structured information table includes a detailed description of all signals, bit width, and connection relationships.

3. The method for automatic checking and correction of PCB design rules based on a multimodal large model according to claim 1, characterized in that, Based on the structured signal information table, the natural language signal descriptions in the PCB design document are matched with the signal definitions in the actual hardware description language code to generate a signal mapping table, including: S2.1, Input signal definition HDL file and structured signal information table; S2.2 uses a multimodal large language model to analyze signal declarations in signal definition files and matches them with a structured signal information table extracted from PCB design documents; S2.3, the matching process includes: Signal name matching: Extract and clean each signal name in the PCB design document, and match it one by one with the signal names defined in the HDL file; if the signal names match exactly, the signals are considered to be the same; if there are name differences, a fuzzy matching algorithm is used to determine whether they are the same signal. Functional description matching: For each signal, if the signal name matches, the functional description of the signal is further semantically analyzed using natural language processing technology to ensure that the functional description in the PCB design document is consistent with the implementation logic in the HDL code; Signal width matching: Check whether the signal width defined in the PCB design document is consistent with the width declared in the HDL file; if they are inconsistent, calibration and adjustment are required. S2.3, perform signal type and direction matching, and ensure that the signal type and direction are consistent in the PCB design document and HDL code through semantic analysis and rule matching; S2.4 If there are inconsistencies in signal name, function description, bit width, type, or direction, a detailed inconsistency report will be generated, listing each inconsistent signal and possible solutions. S2.4 Generate a signal mapping table based on the signal type and direction matching results, which lists the correspondence of each signal in the PCB design document and HDL code; if there are inconsistencies, mark them in the table.

4. The method for automatic checking and correction of PCB design rules based on a multimodal large model according to claim 1, characterized in that, The system automatically generates inspection rules based on PCB design rules, structured signal information tables, and signal mapping tables. These rules include bit width inspection rules, connectivity inspection rules, and functional inspection rules. S3.1, Input the structured signal information table, signal mapping table, and PCB design rules; S3.2 uses a multimodal large language model to parse the structured signal information table and signal mapping table, and generates suitable verification rules based on the requirements of PCB design rules; S3.3 adopts a retrieval-enhanced generation approach that combines a verification knowledge base and a generative model to generate verification rules that better meet actual design requirements. It retrieves rules related to the current design from the verification knowledge base and combines the retrieved rules with the rules generated by the model to optimize the final generated verification assertions. S3.4, Output automatically generated inspection rules, including: Bit width check rule: Verify that the bit width of each signal meets the requirements in the PCB design document; Connectivity check rules: Verify that the connections between signals are correct; Functional verification rules: Verify that the function of the signals conforms to the description in the PCB design document; S3.5, all generated verification rules will be presented in the form of SystemVerilog assertions. The report will include the following: a detailed list of bit-width check rules, connectivity check rules, and functionality check rules; the generation process of each rule, the signals involved, and the compliance checks of the rule.

5. The method for automatic checking and correction of PCB design rules based on a multimodal large model according to claim 4, characterized in that, The process involves using a multimodal large language model to parse the structured signal information table and signal mapping table, and combining this with the requirements of PCB design rules to generate suitable verification rules, including: S3.2.1 For each signal, check whether its bit width meets the bit width requirements defined in the document, and generate bit width check rules; generate corresponding bit width check rules by extracting signal bit width data from PCB design documents and HDL code; if the signal bit width is inconsistent, generate corresponding error messages; S3.2.2, Generate corresponding connectivity check rules through signal connection topology diagram and mapping table; Automatically generate check rules using signal connection relationship diagram to ensure that signals are correctly connected according to the designed topology; For each signal pair, check whether they are correctly connected according to design requirements; S3.2.3, Generate functional check rules. Functional checks ensure that these functions are correctly implemented in the design, including: combining the functional description of the signal with its actual function to achieve functional verification; if the signal does not work as expected, generate the corresponding error message.

6. The method for automatic checking and correction of PCB design rules based on a multimodal large model according to claim 1, characterized in that, The process of using formal verification tools to verify the effectiveness of the inspection rules and optimizing the inspection rules based on the verification results includes: S4.1, Input the generated bit width check rules, connectivity check rules, and functionality check rules, as well as the verified golden RTL design; S4.2, Set the verification metrics, including: syntax correctness and functional pass rate; S4.3, Syntax correctness verification: Ensure that the generated SystemVerilog assertions conform to the syntax specification and can be correctly executed in the formal verification tool; S4.4, Functional correctness verification; ensure that the generated SystemVerilog assertions can accurately identify potential problems in the design during the functional verification process and evaluate the effectiveness of the generated rules; Output the pass rate for each assertion, list the assertions that failed to be validated, and point out possible errors in the design; S4.5, evaluate the quality of the generated rules, and list the evaluation results for each assertion, including syntactic correctness and functional pass rate.

7. The method for automatic PCB design rule checking and correction based on a multimodal large model according to claim 6, characterized in that, The optimized inspection rules are used to verify the PCB design rules and automatically generate correction suggestions, including: Based on the evaluation results, the generated rules are optimized, including: If some rules have a low pass rate or fail functional verification, adjust the rule generation strategy; For assertions that fail, the system automatically corrects the rules or requires manual intervention to modify them; Based on the verification results and optimization strategies, new and improved inspection rules are generated, and verification continues to ensure the effectiveness of the optimized rules.

8. A system for automatic checking and correction of PCB design rules based on a multimodal large model, characterized in that, include: The data input module is used to input multimodal PCB data into the multimodal large model. The multimodal PCB data types include: PCB design documents, signal definition files, and verified golden RTL designs. The multimodal data parsing module is used to parse PCB design documents through a large multimodal model, extract signal information, and generate a structured signal information table. The signal mapping table generation module is used to match the natural language signal descriptions in the PCB design document with the signal definitions in the actual hardware description language code, based on the structured signal information table and signal definition file, to generate a signal mapping table. The inspection rule generation module is used to automatically generate inspection rules based on PCB design rules, structured signal information tables, and signal mapping tables, including bit width inspection rules, connectivity inspection rules, and functional inspection rules. The check rule verification module is used to verify the effectiveness of check rules using formal verification tools and optimize the check rules based on the verification results. The correction suggestion generation module is used to verify PCB design rules by applying optimized inspection rules and automatically generate correction suggestions.

9. An electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the automatic PCB design rule checking and correction method based on a multimodal large model as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the automatic PCB design rule checking and correction method based on a multimodal large model as described in any one of claims 1-7.

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