Maintaining hierarchical structure information within design documents

Abstract

A verification apparatus for verifying a design document for digital lithography includes a memory and a controller. The memory includes the design document. The controller is configured to access the design document and apply one or more compliance rules to the design document to determine a compliance of the design document. The compliance rules include at least one of the following: detecting non-orthogonal edges within the design document; detecting non-compliant overlapping structures within the design document; and detecting non-compliant interactions between a reference layer of the design document and a target layer of the design document. The controller is further configured to verify the design document in response to a comparison of a number of the non-orthogonal edges, the non-compliant overlapping structures, and the non-compliant interactions to a threshold.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate generally to verifying design files for digital lithography systems. BACKGROUND

[0002] Lithographic methods are used to manufacture semiconductor devices. Conventional lithographic methods include transferring a design pattern onto a set of photomasks, which are transferred onto photoresist. In a digital lithography process, an imaging process is used to directly digitize a design pattern onto photoresist. However, the amount of data transferred to digitize photoresist is large, limiting the speed of the digital lithography process. Further, current verification methods remove structural information from the design file.

[0003] Therefore, what is needed in the art is a method that reduces the amount of data while still maintaining the hierarchical structural information of the design file. SUMMARY

[0004] In one example embodiment, a method includes accessing a design file for a digital lithography apparatus and applying one or more compliance rules to the design file to determine compliance. Applying the one or more compliance rules includes detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting non-compliant interactions between a reference layer of the design file and a target layer of the design file. The method further includes verifying the design file in response to comparing a number of the non-orthogonal edges, the non-compliant overlapping structures, and the non-compliant interactions to a threshold.

[0005] In one example embodiment, a verification apparatus for verifying a design file for digital lithography includes a memory and a controller. The memory includes the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules include at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting non-compliant interactions between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to comparing a number of the non-orthogonal edges, the non-compliant overlapping structures, and the non-compliant interactions to a threshold.

[0006] In one example implementation, a computer program product to validate a design document for digital lithography includes a computer readable storage medium having computer readable program code embodied therewith. The computer readable program code, executable by one or more computer processors, to: access a design document; apply one or more compliance rules to the design document to determine compliance of the design document; and validate the design document in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures, and non-compliant interactions to a threshold. Applying one or more compliance rules to the design document includes at least one of: detecting non-orthogonal edges within the design document; detecting non-compliant overlapping structures within the design document; and detecting non-compliant interactions between a reference layer of the design document and a target layer of the design document. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description of the implementation, briefly summarized above, can be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only example implementations and are therefore not to be considered limiting of its scope, as the application can admit to other equally effective implementations.

[0008] Figure 1 is a schematic illustration of a digital lithography system in accordance with one or more implementations.

[0009] Figure 2 is a schematic illustration of a validation apparatus in accordance with one or more implementations.

[0010] Figure 3 is a flowchart of a method for validating a design document in accordance with one or more implementations.

[0011] Figure 4 is a flowchart of a design document for determining a compliant design document in accordance with one or more implementations.

[0012] Figure 5 , 6 , 7, 8, and 9 are schematic illustrations of a unit structure in accordance with one or more implementations.

[0013] To facilitate the understanding of this disclosure, like reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one implementation can be beneficially incorporated into other implementations without further recitation. DETAILED DESCRIPTION

[0014] The implementations described herein provide a method for validating a design file optimized to undergo digital pattern transfer while maintaining at least a portion of the hierarchical structure information within the original design file to reduce data volume and avoid data congestion. The method includes the steps of evaluating the design file against a combination of compliance rules to detect non-compliant cells of the design file. A list of non-compliant cells and / or location markers can be presented to a user for corrective action. The design file can be validated when a threshold is determined based on a proportion of non-compliant cells and / or location markers. The validated design file can be passed to a controller of a digital lithography system for processing.

[0015] Figure 1 is a perspective view of a digital lithography system 100 according to one or more implementations. The digital lithography system 100 includes a digital lithography apparatus 101 and a validation apparatus 130. The digital lithography apparatus 101 includes a platform 114 and a processing device 104. The platform 114 is supported by a pair of tracks 116 disposed on a platen 102. A substrate 120 is supported by the platform 114. The platform 114 is supported by a pair of tracks 116 disposed on a platen 102. The platform 114 moves along the pair of tracks 116 in an X direction as indicated by a coordinate system shown in Figure 1 . In one implementation, the pair of tracks 116 is a pair of parallel magnetic channels. As shown, each track of the pair of tracks 116 extends on a straight path. An encoder 118 is coupled to the platform 114 to provide information of the position of the platform 114 to a controller 122.

[0016] The controller 122 is generally designed to facilitate control and automation of the processing techniques described herein. The controller 122 can be coupled or in communication with the processing device 104, the platform 114, and the encoder 118. The processing device 104 and the encoder 118 can provide information to the controller 122 regarding substrate processing and substrate alignment. For example, the processing device 104 can provide information to the controller 122 to alert the controller 122 that substrate processing has been completed. The controller 122 facilitates control and automation of the digital lithography processing based on a design file provided by the validation apparatus 130. The design file (or computer instructions), which can be referred to as an imaging design file and can be read by the controller 122, determines which tasks can be performed on the substrate. The design file (e.g., the design file 220 of Figure 2 includes mask pattern data and code to monitor and control processing time and substrate position. The mask pattern data corresponds to a pattern to be written into photoresist using electromagnetic radiation.

[0017] The substrate 120 includes any suitable material, such as glass, that is used as part of a flat panel display. In other embodiments, the substrate 120 is made of other materials that can be used as part of a flat panel display. The substrate 120 has a film layer formed thereon to be patterned, such as by pattern etching thereof, and a photoresist layer formed on the film layer to be patterned, the photoresist layer being sensitive to electromagnetic radiation, such as UV or deep UV "light." A positive photoresist includes a portion of the photoresist that, when exposed to radiation, is soluble in a photoresist developer applied to the photoresist after a pattern is written into the photoresist using electromagnetic radiation, respectively. A negative photoresist includes a portion of the photoresist that, when exposed to radiation, is insoluble in a photoresist developer applied to the photoresist after a pattern is written into the photoresist using electromagnetic radiation, respectively. The chemical composition of the photoresist determines whether the photoresist is a positive or negative photoresist. Examples of photoresists include, but are not limited to, at least one of the following: diazonaphthoquinone, novolac, polymethyl methacrylate, polyimide methyl, and SU-8. After the photoresist is exposed to electromagnetic radiation, the resist is developed to leave a patterned photoresist on the underlying film layer. Then, using the patterned photoresist, the underlying film is pattern etched through openings in the photoresist to form part of the electronic circuitry of the display panel.

[0018] The processing device 104 includes a support 108 and a processing unit 106. The processing device 104 is disposed on the platform 102 across the pair of tracks 116 and thus includes the opening 112 for the pair of tracks 116 and the platform 114 to pass underneath the processing unit 106. The processing unit 106 is supported by the support 108 above the platform 102. In one embodiment, the processing unit 106 is a pattern generator configured to expose a photoresist in a photolithography process. In some embodiments, the pattern generator is configured to perform a maskless lithography process. The processing unit 106 includes a plurality of image projection systems.

[0019] During operation, the platform 114 is moved in the X direction from the loading position (as shown in FIG. 1A) to the processing position (as shown in FIG. 1B) and vice versa. The platform 114 is moved in the X direction by the pair of tracks 116 and the platform 114. Figure 1The substrate 120 is moved to a processing position (as shown in FIG. 1) by the substrate handler 102. The processing position is one or more positions below the processing unit 106. In this illustration, the digital lithography apparatus 101 is shown schematically, with the dimensions of the digital lithography apparatus 101 adjusted to be able to expose the entire width of the photoresist layer on the substrate 120 in the Y direction, i.e. the substrate 120 is small compared to a real flat panel display substrate. However, in a real processing system, the processing device 104 will be significantly smaller in the Y direction compared to the width of the substrate 120, and the substrate 120 will be moved sequentially under the processing device 104 in the -X direction, moved or stepped in the +Y direction under the processing device 104, or scanned in reverse in the +X direction under the processing device 104. This X direction scanning and Y direction stepping operation will continue until the entire substrate area has passed under the writeable area of the processing device 104.

[0020] Figure 2 A verification apparatus 130 according to one or more embodiments is illustrated. The verification apparatus 130 includes a computing apparatus 210 and an input / output (I / O) apparatus 230. The verification apparatus 130 can be used to generate, optimize, verify, and / or update a design document (e.g., design document 220).

[0021] The computing apparatus 210 can include a controller 212, a network interface 214, and a memory 216. The controller 212 retrieves and executes programming data stored in the memory 216 and coordinates the operation of other system elements. Similarly, the controller 212 stores and retrieves application data located in the memory 216. The controller 212 can be one or more central processing units (CPUs).

[0022] The memory 216 can store instructions and logic to be executed by the controller 212. Further, the memory 216 can be one or more of random access memory (RAM) and non-volatile memory (NVM). The NVM can be a hard disk, a network attached storage (NAS), and a removable storage device, among others. Further, the memory 216 can include a design application 218 and a design document 220.

[0023] The design application 218 generates, optimizes, verifies, and / or updates design data of the design document 220. The design application 218 can be controlled by the controller 212 to generate, optimize, and / or update the design data of the design document 220.

[0024] The design document 220 can be stored in memory and accessible by the controller 212 and the design application 218. The design document 220 can include design data that can be interpreted by the controller 122 to pattern the substrate 120. For example, the design document 220 indicates hierarchical entity design (layout) data. The hierarchical entity design data can be composed of core pixel regions and peripheral logic regions. The core pixel regions can be highly repetitive, representing greater than 90% of the design data. Further, maintaining a hierarchical structure reduces the amount of data transmitted to the controller 122. For example, the amount of data can be reduced by about 100 to about 1000 times compared to applying global biasing with a hierarchical geometry engine. Data bloat can result in an inability to transfer data within a data path. Further, the design application 218 can optimize global sizing and hierarchical repair within cell level sizing. The design document 220 can also be referred to as a design pattern document. The design document 220 can be provided in different formats. For example, the format of the design document 220 can be one of a GDS format and an OASIS format, among others. The design data of the design document 220 includes cells that have pattern structures to be produced on a substrate, such as the substrate 120. A cell can be a group of logic elements of a transistor or another element of a semiconductor element. In addition, a cell can include geometric objects, such as polygons (borders, paths, and other cells). The objects in a cell are assigned to a "layer" of the corresponding design. Different layers can represent different processing steps in a lithography process. A cell can be referenced whenever the element is to be drawn. For example, a cell corresponding to a transistor can be referenced whenever the transistor is to be drawn. Further, a cell can span one or more layers within a design of the design document. A cell hierarchy can include one or more cells. For example, a top level cell can include all elements of a corresponding object, and each cell at a lower level of the hierarchy can include elements of different portions of the object. The design document 220 can be in the form of a pixel cell, a raster map, or a similar document. The design document 220 can include regions of interest corresponding to one or more structures. The structures can be constructed as geometric shapes. Further, the regions of interest can be represented as cells during a verification and / or optimization process.

[0025] The I / O devices 230 can include one or more of a keyboard, a display device, a mouse, an audio device, and a touch screen, among others. The I / O devices 230 can be used to input information into the verification device 130 and / or output data from the verification device 130. For example, a user can use a keyboard and a pointing device to create and / or adjust elements of the design document 220.

[0026] The network interface 214 can transmit data via a communication network. For example, the network interface 214 can transmit the design document to the digital lithography device 101 via a communication network.

[0027] Global size adjustment of the design document 220 allows exposure dose to be set at a higher value so that structures within the design document 220 can be printed with the sizes indicated by the design document 220. Further, since data indicating structures can be represented by either dark or bright portions of the design document 220, during the size adjustment process, edges of the structures can be moved inward or outward by a first amount. The first amount can be less than a minimum width of the structures.

[0028] The design application 218 can be executed by the controller 212 to perform biasing at a cell level of the design document 220. Each of the cells can correspond to an identified region of interest within the design document 220. The biasing can include feature size adjustment to pattern structure data contained in the cells of the design document 220. The cell level size adjustment of the design document can be completed so that for two overlapping cells, if the corresponding drawing data is adjusted in size inward, no gap is formed between the cells. Similarly, if the drawing data is adjusted in size upward, the spacing between the cells is maintained so that the spacing can be resolved during a digital lithography process.

[0029] Figure 3 A method 300 for preparing a design document (e.g., the design document 220) for digital lithography is illustrated in accordance with one or more embodiments. At operation 310, one or more compliance checks are performed on the design document. For example, the one or more compliance checks can include three compliance checks on the design document. The compliance checks can include identifying data where cell-to-cell interaction occurs. Further, the compliance checks can include identifying all non-orthogonal edges in the cell interaction regions. The non-orthogonal edges are flagged as errors. Further, the one or more compliance checks can include a down bias check during which overlapping regions in the design document 220 are checked. Any overlapping regions within one or more cells should be compared to a target down bias threshold. Non-compliant overlapping regions correspond to overlapping regions that have less overlap than the target down bias threshold. Further, for up bias, the one or more compliance checks can check for space violations in the cells after up bias is completed. For selective biasing and gray scale, the one or more compliance checks can include determining whether a reference layer and a target layer produce different results for cell level operations and de-layered level operations. The design application 218 is executed by the controller 212 to perform the one or more compliance checks on the design document 220. Performing the compliance checks can include identifying one or more regions of interest within the cells of the design document 220 and comparing the cells to one or more compliance rules. For Figure 4 The compliance checks are described in more detail.

[0030] At operation 320, biasing is performed at the cell level of the design document 220. Biasing can include upward or downward biasing at the cell level without considering the influence of neighboring polygons from other cell instances in the hierarchical structure. Biasing can be applied globally or to selected regions. Since the results from the biasing process can create insufficient overlap between the structural elements identified by operation 310, the results of biasing at the cell level can not match the results generated by the global sizing process from the top-level design cell. Operation 320 can be applied to design data that passes or meets the compliance check of operation 310. For example, some non-compliance errors can not be fixable in operation 330. Design documents that include such errors can be flagged as failing the compliance check, and biasing can not be performed on such design documents. Further, the amount of processing time utilized by operation 320 is reduced compared to traditional global sizing using hierarchical geometry engines, since operation 320 does not consider inter-cell interactions. Further, operation 320 maintains the hierarchical structure as the same as the input design document 220.

[0031] At operation 330, hierarchical level fixing of the design document generated by operation 320 is performed. The design application 218 can be executed on the controller 212 and performs hierarchical level fixing of the output design document from operation 320. Hierarchical level fixing of the design document can be completed based on the determination that the design document is non-compliant. The hierarchical level fixing process can be completed during the cell level downward biasing process completed during operation 320. For example, the hierarchical level fixing process can include filling gaps that are less than twice the amount of downward biasing. The gaps can be introduced by the downward biasing operation performed during operation 320 and can be a result of insufficient overlap identified by operation 310. Performing hierarchical level fixing of the output of operation 320 can add additional data at the common parent cell of interacting cell instances. However, unlike traditional global biasing, the fixing operation can be limited to a small range or region and is less likely to cause flattening of the hierarchical structure. For example, hierarchical level fixing can be applied to about 2% or less of the design document. Thus, the impact on the amount of data for hierarchical level fixing of operation 330 is limited. Further, traditional global sizing can result in flattening of the hierarchical structure, which can increase the amount of data transferred to the controller 122. The use of compliance rules of operation 310 can reduce the amount of data by at least about 90% compared to traditional methods of verifying and preparing design documents for digital lithography. Further, operation 330 is optional and can be omitted from the method 300.

[0032] Figure 4A method 400 for verifying a design document is illustrated in accordance with one or more embodiments. For design documents determined to be compliant with the compliance rules as described for operation 420 of method 400, the results produced using cell-level biasing and repair are substantially similar to the biasing performed using a conventional hierarchical geometry engine. However, when utilizing the compliance rules as described for method 400, the amount of data provided to digital lithography apparatus 101 for digital lithography is reduced. For example, when utilizing global size adjustment, a gap can exist between cells for each non-compliant location, and an additional polygon can be required to maintain the correctness of the corresponding bias, resulting in an increase in the amount of data. Further, a design document determined to include a non-orthogonal interaction edge can be rejected, as such errors can be unrepairable. The verification process as described for method 400 can be used to correlate with the amount of data provided to digital lithography apparatus 101.

[0033] At operation 410, a design document is accessed. For example, design document 220 can be accessed from memory 216. Design application 218 can access design document 220 from memory 216 and identify one or more regions of interest within design document 220.

[0034] At operation 420, a compliance check of the design document is performed. For example, design application 218 executes on controller 212 and applies one or more rules to design document 220 to determine whether the design document is compliant. As described above, determining a non-compliant location can include detecting a non-orthogonal structure, an insufficient overlap structure, and / or a selective operation difference between a cell level and a hierarchical level. Operations 422-426 describe the compliance check in more detail.

[0035] At operation 422, design application 218 determines whether a non-orthogonal edge exists within a region of interest of a cell. Determining a non-orthogonal edge can include determining whether edges of an overlap structure can be at an angle other than 0 degrees or 180 degrees. For example, design application 218 can identify one or more structures or polygons, and a region of interest between cells, identify one or more edges from the structures, and determine whether the identified edges are not orthogonal to each other. If a non-orthogonal edge is identified, the corresponding region of interest can be marked as non-compliant and added to an error list.

[0036] Design application 218 provides for analyzing a design document to detect interactions of structures of adjacent cells and marking the detected interactions as regions of interest to determine the regions of interest. Referring to Figure 6Application 218 can determine region of interest 616 by detecting inter-unit interactions between structure 614 and the structures of other units within a common hierarchical layer. The interacting structures are those that at least partially overlap. Further, the interacting structures are located within a common hierarchical layer. View 610 of unit 600 includes regions of interest 616 (e.g., regions of interest 616a and 616b) that correspond to the interactions between structure 614 and the structures of other adjacent units. For example, region of interest 616a corresponds to the location where structure 614 interacts with the structure of a first unit, while region of interest 616b corresponds to the location where structure 614 interacts with the structure of a second unit. One or more regions of interest may be omitted if it is found that structure 614 does not interact with the corresponding structure of another unit. Further, as illustrated in view 620, region of interest 616a corresponds to the interaction between structure 614 and structure 626 within a hierarchical level.

[0037] Application 218 further generates markers within the cells, where these markers correspond to the edges of the cell structure. These markers can be used to detect non-compliant regions of interest and their corresponding non-compliant cells. For example... Figure 6 As illustrated, unit 600 is marked with marker 612, and these markers correspond to the edges of structure 614. Application 218 uses the markers at the overlapping edges of the overlapping structures to determine whether the region of interest (ROI) is compliant. For example, detecting non-compliant ROI includes the following steps: selecting a marker corresponding to the interaction between the two structures, and determining whether the angle formed between the selected markers differs from 0 degrees to 180 degrees. (See reference...) Figure 6and view 620, markers 612a and 624 are selected based on being determined to correspond to overlapping edges of the interaction between structures 614 and 626. In other words, markers 612a and 624 are selected because they identify a layered interaction of structures 614 and 626. Thus, markers 612a and 626 can be used by design application 218 to determine whether region of interest 616a is compliant. For example, as indicated by region 636 of view 630, a non-orthogonal edge between structures 614 and 626 is detected and marked. Determining the non-orthogonal edge includes determining whether the angle between markers 612a and 624 is a value other than 0 degrees or 180 degrees. For example, design application 218 measures the angle formed between markers 612a and 624, and if the value is different from 0 degrees or 180 degrees, then region of interest 616a is determined to be non-compliant. When a determination is made that the angle formed between selected markers 612a and 624 has a value other than 0 degrees or 180 degrees, region of interest is determined by design application 218 to be non-compliant, and cell 600 is marked as non-compliant and added to the error list. Alternatively, if it is determined that the region of interest does not contain a non-orthogonal edge, then the region of interest and corresponding cell are determined to be compliant. Further, a design document determined to include one or more non-compliant cells can be rejected.

[0038] At operation 424, design application 218 determines whether the overlapping structure elements are compliant. For example, design application 218 is executed by controller 212 to identify overlapping edges within the region of interest, determine the number of overlapping edges, and determine whether the number of overlapping edges satisfies an edge threshold. The edge threshold can be set such that a compliant region of interest of a cell does not have more than three adjacent edges within the overlapping region. Further, a region of interest that satisfies the overlap threshold can be a region of interest that does not have more adjacent edges than defined by the edge threshold. Referring to Figure 7 Region of interest 700 can be evaluated by design application 218 to determine whether region of interest 700 satisfies the overlap threshold. For example, region of interest 700 includes structures 702 and 704. Design application 218 compares the number of edges of structure 704 that overlap structure 702 to an overlap threshold. The value of the overlap threshold can be three. Further, the overlap threshold can have a value less than three or greater than three. As shown in Figure 7 As shown in FIG. 6B, the number of edges of structure 704 that overlap structure 702 is five, and region of interest 700 can be marked as non-compliant and added to the error list.

[0039] Further, operation 424 can include the steps of identifying one or more edges of at least one of structure 702 and structure 704 and determining whether the distance of the overlap is less than a distance threshold. If the amount of overlap is less than the distance threshold, the corresponding region of interest can be indicated as non-compliant. Referring to Figure 8 FIG. 8 illustrates a region of interest 800 including structures 802 and 804. Structure 804 overlaps structure 802 by a first amount indicated by region 806. The amount of overlap is compared by design application 218 to an overlap threshold to determine whether the cell including region of interest 800 is compliant. The overlap threshold can be at least the same value as a target bias amount (e.g., an amount used to bias a cell during size re-tuning). If the amount of overlap indicated by region 806 fails to satisfy the overlap threshold, the cell including region of interest 800 can be determined to be non-compliant and added to the error list.

[0040] At operation 426, design application 218 determines whether there are selective biasing errors within the cell composition. For example, design application 218 can identify one or more structures within the cell and compare the structures to composite hierarchical data of the design document (e.g., design document 220) to determine whether there are discrepancies during the selected process. When a structure is missing from the cell, an error can be determined to exist. For example, as illustrated in Figure 9 region of interest 900 includes a reference layer 902 and a target layer 904. However, as indicated from hierarchical composite view 910, reference layer 902 is overlapped by another target layer 904 from a different cell instance. Accordingly, the cell including region of interest 900 can be identified as including an error and non-compliant. Thus, the cell including region of interest 900 can be added to the error list.

[0041] At operation 430, a user is prompted to resolve the errors. For example, a user can be prompted to resolve the errors identified within the error list. The error list can be generated by operation 420. Further, the error list can be evaluated and grouped based on their severity. For example, non-compliant errors generated by operations 422 and 426 can be grouped and identified for corrective action. Further, non-compliant errors from operation 424 can be compared to a percentage threshold to determine whether the design document passes a compliance check. For example, if 95% of the edges identified during operation 424 satisfy the overlap threshold, the design document passes the check. However, if greater than 5% of the edges identified during operation 424 do not satisfy the overlap threshold, the design document fails the check. Further, a reduction in the amount of data transmitted to controller 122 can be achieved when the percentage of edges that satisfy the overlap threshold is greater than about 95%. Additionally or alternatively, design application 218 can be executed by controller 212 and generate an error list based on a compliance check of operation 420.

[0042] The design application 218 executed by the controller 212 can output a list of errors to the user via the I / O device and request that the user update the design file 220 to correct the identified errors. For example, the list of errors can be presented to the user via a display device of the verification device 130. The user can update the design file 220 to correct the identified errors. After the design file has been corrected, the updated design file can be evaluated and verified using the method 400. Alternatively, the user can choose to ignore the request to correct the identified errors and pass the design file 220 to the digital lithography device 101. However, using a design file that has not been verified can result in errors during the digital lithography process.

[0043] The method 400 can additionally include an optional operation 440 to repair the design file. For example, by filling gaps (or spaces) between cell elements at one or more of the non-compliant regions. The operation 440 can be implemented in response to the detection or determination of non-compliant errors from the operation 424 for automatically repairing the design file. Alternatively, the method 400 can include the operation 440 as an alternative or supplement to requesting the user to resolve the identified errors to reduce the amount of data. Further, in addition to patching gaps between cells or cell elements, the combination of cell-level down-biasing can result in equivalent results compared to conventional global biasing results. Moreover, the described cell-level biasing operations do not change the hierarchical structure and thus do not increase the amount of data transferred to the controller 122. The amount of data can increase during design repair operations (e.g., operation 440) and thus, a design file with fewer non-compliant errors will result in a more compact design file.

[0044] At operation 450, the design file is verified. For example, when no errors are identified during the verification process (e.g., method 400), the design file 220 can be verified by the design application 218 as compliant and ready for use in a digital lithography process. After the design file has been verified, the design file 220 can be passed to the digital lithography device 101. For example, the design file 220 can be passed to the controller 122 of the digital lithography device 101 via the network interface 214 and a communication network. Alternatively or additionally, the design file 220 can be saved to a removable memory before being transferred to the digital lithography device 101.

[0045] Verifying the design file used in a digital lithography process helps to reduce errors that can occur during the digital lithography process. For example, the verification process can identify errors in the design file before the design file is provided to the digital lithography process. Further, by performing the verification at the cell level and making adjustments to the design file at the hierarchical level, the amount of data provided to the digital lithography process can be reduced.

[0046] The methods presented in Figure 3 and 4 may be stored in a computer program product and executed on a controller, such as the controller 122 and / or 212. A computer program product can include one or more computer-readable storage media having computer-readable program instructions thereon for causing a processor to carry out aspects of the present application.

[0047] The computer-readable storage media can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer-readable storage media can include the memory 216. The computer-readable storage media can be, for example but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage media includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, and / or the like.

[0048] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium or an external storage device into a respective computing / processing device, or be downloaded from a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or an external storage device. A network adapter card or a network interface in each computing / processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device.

[0049] Computer-readable program instructions for carrying out operations of the present application can be in any interpretation, whether they be assembly-language instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or any combination of one or more of the above in source code or object code, written in any combination of one or more programming languages, including an object-oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. In some embodiments, the computer-readable program instructions can be executed by electronic circuitry, including for example programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA), through utilization of state information of the computer-readable program instructions to personalize the electronic circuitry.

[0050] Aspects of the application are described herein with reference to flowchart and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart and / or block diagrams, and combinations of blocks in the flowchart and / or block diagrams, can be implemented by computer readable program instructions.

[0051] These computer readable program instructions can be provided to a controller 122 and / or controller 212. Further, the computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a storage device 216 that can also include a memory.

[0052] While the forgoing examples are related to the example of the present disclosure, other and further examples of the present disclosure can be devised without departing from the basic scope thereof, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A method comprising the steps of: accessing a design document for a digital lithographic apparatus from a memory; detecting a region of interest in the design document based on interactions between cell structures in one or more hierarchical layers of the design document; applying one or more compliance rules to the design document to determine compliance of the design document by: detecting a non-orthogonal edge within the region of interest based on detecting that an edge of a first structure is not orthogonal to an edge of a second structure, wherein the first structure and the second structure overlap each other; detecting a non-compliant overlapping structure within the region of interest; and detecting a non-compliant interaction between a reference layer of the design document and a target layer of the design document; and verifying the design document in response to comparing a number of the non-orthogonal edge, the non-compliant overlapping structure, and the non-compliant interaction to a threshold value, wherein the verified design document is output to the digital lithographic apparatus to pattern a substrate based on the verified design document.

2. The method of claim 1, wherein detecting the non-orthogonal edge further comprises the steps of: detecting an overlap region between the first structure and the second structure.

3. The method of claim 2, wherein detecting the overlap region comprises the steps of: generating a plurality of markers around the first structure and the second structure; and selecting a first marker and a second marker of the plurality of markers that identify an interaction region of the first structure and the second structure, and wherein determining whether the first structure forms an orthogonal edge with the second structure comprises determining whether the first marker is orthogonal to the second marker.

4. The method of claim 1, wherein detecting the non-compliant overlapping structure comprises at least one of the steps of: comparing an amount that a third structure extends into a fourth structure to a first threshold value; identifying one or more edges of at least one of the third structure and the fourth structure that are not orthogonal in an overlap region between the third structure and the fourth structure; and comparing a number of adjacent edges of the third structure within the overlap region to an edge threshold value.

5. The method of claim 4, wherein a location corresponding to the third structure and the fourth structure is determined to be non-compliant in response to one or more of the following conditions: the amount that the third structure extends into the fourth structure exceeds the first threshold value; at least one non-orthogonal edge is identified in the overlap region; and the number of adjacent edges exceeds the edge threshold value.

6. The method of claim 1, wherein detecting the non-compliant overlapping structure comprises the steps of: identifying a third structure that overlaps a fourth structure; determining an amount of overlap between the third structure and the fourth structure; comparing the amount of overlap to a distance threshold value.

7. The method of claim 6, wherein a location corresponding to the third structure and the fourth structure is determined to be non-compliant in response to the amount of overlap being less than the distance threshold value.

8. A verification apparatus for verifying a design file for digital lithography, the verification apparatus comprising: a memory comprising the design file; and a controller configured to: access the design file; detect a region of interest in the design file based on interactions between cell structures in one or more hierarchical layers of the design file; apply one or more compliance rules to the design file to determine compliance of the design file by: detecting a non-orthogonal edge within the region of interest based on detecting that an edge of a first structure is not orthogonal to an edge of a second structure, wherein the first structure and the second structure overlap each other; detecting a non-compliant overlapping structure within the region of interest; and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file; and verify the design file in response to comparing a number of the non-orthogonal edge, the non-compliant overlapping structure, and the non-compliant interaction to a threshold value, wherein the verified design file is output to a digital lithography apparatus to pattern a substrate based on the verified design file.

9. The verification apparatus of claim 8, wherein detecting the non-orthogonal edge further comprises: detecting an overlap region between the first structure and the second structure.

10. The verification apparatus of claim 9, wherein detecting the overlap region comprises: generating a plurality of markers around the first structure and the second structure; and selecting first and second markers of the plurality of markers that identify an interaction region of the first structure and the second structure, and wherein determining whether the first structure fails to form the orthogonal edge with the second structure comprises determining whether the first marker is orthogonal to the second marker.

11. The verification apparatus of claim 8, wherein detecting the non-compliant overlapping structure comprises at least one of: comparing an amount that a third structure extends into a fourth structure to a first threshold value; identifying one or more edges of at least one of the third structure and the fourth structure that are non-orthogonal in an overlap region between the third structure and the fourth structure; and comparing a number of adjacent edges of the third structure within the overlap region to an edge threshold value.

12. The verification apparatus of claim 11, wherein a location corresponding to the third structure and the fourth structure is determined to be non-compliant in response to one or more of: the amount that the third structure extends into the fourth structure exceeds the first threshold value; at least one non-orthogonal edge is identified in the overlap region; and the number of adjacent edges exceeds the edge threshold value.

13. The verification apparatus of claim 8, wherein detecting the non-compliant overlapping structure comprises: identifying a third structure that overlaps a fourth structure; determining an amount of overlap between the third structure and the fourth structure; and comparing the amount of overlap to a distance threshold value. ​ 14. The verification device of claim 13, wherein locations corresponding to the third structure and the fourth structure are determined to be non-compliant in response to the amount of overlap being less than the distance threshold.

15. A computer program product for verifying a design file for digital lithography, the computer program product comprising: a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code executable by one or more computer processors to: access the design file from memory; detect a region of interest in the design file based on interactions between cell structures in one or more hierarchical layers of the design file; apply one or more compliance rules to the design file to determine compliance of the design file by: detecting a non-orthogonal edge within the region of interest based on detecting that an edge of a first structure is not orthogonal to an edge of a second structure, wherein the first structure and the second structure overlap each other; detecting a non-compliant overlapping structure within the region of interest; and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file; and verify the design file in response to comparing a number of the non-orthogonal edge, the non-compliant overlapping structure, and the non-compliant interaction to a threshold value, wherein the verified design file is output to a digital lithography device to pattern a substrate based on the verified design file.

16. The computer program product of claim 15, wherein detecting the non-orthogonal edge further comprises: detecting an overlap region between the first structure and the second structure within the design file.

17. The computer program product of claim 15, wherein detecting the non-compliant overlapping structure comprises at least one of: comparing an amount of a third structure extending into a fourth structure to a first threshold value; identifying one or more edges of at least one of the third structure and the fourth structure that are not orthogonal in an overlap region between the third structure and the fourth structure; and comparing a number of adjacent edges of the third structure within the overlap region to an edge threshold value.

18. The computer program product of claim 15, wherein detecting the non-compliant overlapping structure comprises: identifying a third structure that overlaps a fourth structure; determining an amount of overlap between the third structure and the fourth structure; and comparing the amount of overlap to a distance threshold value.

19. The computer program product of claim 16, wherein detecting the overlap region comprises: generating a plurality of markers around the first structure and the second structure; and selecting first and second markers of the plurality of markers that identify an interaction region of the first structure and the second structure, and wherein determining whether the first structure forms the orthogonal edge with the second structure comprises determining whether the first marker is orthogonal to the second marker.

20. The computer program product of claim 17, wherein a location corresponding to the third structure and the fourth structure is determined to be non-compliant in response to one or more of the following conditions: the amount that the third structure extends into the fourth structure exceeds the first threshold; at least one non-orthogonal edge is identified in the overlap region; and the number of adjacent edges exceeds the edge threshold.

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