The invention relates to the technical field of
chip design, in particular to a timing constraint
automation generation method. According to the method, the actual demand of the
clock needing to be created is determined based on the design document, and then the
clock list is generated based on the actual demand; the content of the
clock list comprises a PLL source, a clock type, a clock name, a source path, a main clock name, a main clock source path, a frequency, a main clock duty ratio, a derivative clock duty ratio, a frequency division coefficient, whether the clock has a cross-clock requirement or not, and the mutual relation between the created clocks; executing the script in a clock
list which needs to be read by the configuration script and the specified script; and traversing all options in the clock list by the script, generating a
time sequence constraint, and automatically finishing GCA check. According to the method, timing constraint compiling and checking can be automatically achieved through the script only by completing output of the clock list, and the method for compiling the timing constraint is accurate and easy to maintain.