A semiconductor electrical property measurement structure, measurement apparatus and measurement method

Abstract

The application provides a semiconductor electrical property measurement structure, which comprises a test array, the test array comprises a plurality of test units, and the plurality of test units are arranged in a matrix, wherein the test unit comprises at least two transistors, and the plurality of transistors are electrically connected in sequence, adjacent transistors in the test unit share the same electrode; in the test array, the middle electrode of part of the test units is grounded, and the edge electrode serves as a first signal output end; the middle electrode of another part of the test units serves as a second signal output end, and the edge electrode is grounded; when the electrode of the transistor is in a high resistance state, the output current of the test unit is reduced, and the range of the reduction of the output current represents the type of the electrode in the high resistance state in the test unit. The application can monitor the distribution behavior of a small number of defective vias existing in a large number of dense vias, and locate the position of the defective via.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor electrical measurement structure, measurement device and measurement method. Background Technology

[0002] As semiconductor device dimensions shrink, more and more devices are integrated within a unit area. Vias are critical structures in semiconductor devices used to connect metal wires or device endpoints between different layers. Therefore, as device dimensions shrink, via sizes also decrease and their numbers increase. The processes associated with vias and the surrounding pattern become important factors affecting yield.

[0003] In semiconductor products, especially semiconductor memory products using array device patterns, the high pattern density of gates and vias means that defects in some vias within the product can negatively impact product performance and production yield. When a small number of vias have high resistance but are not open-circuited, it is difficult to locate the high-resistance vias during electronic scanning imaging. While measuring each via individually can provide accurate monitoring, it is impossible to detect the distribution behavior of a small number of defective vias within a large number of densely packed vias during mass production. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor electrical measurement structure, measurement device and measurement method that can monitor the distribution behavior of a small number of defective vias in a large number of dense vias and locate the position of the defective vias.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0006] The present invention provides a semiconductor electrical measurement structure, including a test array, the test array including multiple test units, and the multiple test units are arranged in a matrix, wherein each test unit includes at least two transistors, and the multiple transistors are electrically connected in sequence, and adjacent transistors in the test unit share the same electrode;

[0007] In the test array, the middle electrode of some of the test units is grounded and the edge electrode is used as a first signal output terminal, while the middle electrode of another part of the test units is used as a second signal output terminal and the edge electrode is grounded.

[0008] When the electrodes of the transistor are in a high-resistance state, the output current of the test unit decreases, and the range of the decrease in the output current characterizes the type of electrode in the test unit that is in a high-resistance state.

[0009] In one embodiment of the present invention, the test array includes:

[0010] a plurality of first vias, a first end of which is connected to an electrode of the transistor;

[0011] a first metal layer, which is electrically connected to a second end of part of the first vias, and the first metal layer is grounded; and

[0012] a second metal layer, which is electrically connected to a second end of another part of the first vias, and the second metal layer is a signal output end of the test array and is electrically connected to a host computer.

[0013] In an embodiment of the present application, the measurement structure comprises an interlayer dielectric layer, which is arranged between the transistor and the first metal layer, between adjacent metal layers, wherein the second metal layer is located on a side of the first metal layer away from the transistor, and the second metal layer extends in a direction perpendicular to the extension direction of the first metal layer.

[0014] In an embodiment of the present application, the test array comprises:

[0015] a plurality of first address lines for locating a row of the test unit, the first metal layer being distributed according to the first address lines, wherein the first address lines are allowed to be selected by the host computer; and

[0016] a plurality of second address lines for locating a column of the test unit, the second metal layer being distributed according to the second address lines, wherein the second address lines are allowed to be selected by the host computer.

[0017] In an embodiment of the present application, the test array comprises a plurality of first type test units and a plurality of second type test units, the first type test units and the second type test units being randomly distributed or distributed in a preset manner in the test array;

[0018] In the first type test unit, the middle electrode is a source electrode and the source electrode is grounded, and the edge electrode is a drain electrode and the drain electrode is the first signal output end.

[0019] In the second type test unit, the middle electrode is a drain electrode and the drain electrode is grounded, and the edge electrode is a source electrode and the source electrode is the second signal output end.

[0020] In an embodiment of the present application, when the first via connected with the drain electrode in the test unit is in a high resistance state, the current signal output by the test unit has a drop amplitude greater than a first drop amplitude and less than a second drop amplitude compared with the reference signal, and when the first via connected with the source electrode in the test unit is in a high resistance state, the current signal output by the test unit has a drop amplitude greater than the second drop amplitude compared with the reference signal, wherein the second drop amplitude is greater than the first drop amplitude.

[0021] The present application provides a semiconductor electrical property measurement device, comprising:

[0022] The semiconductor electrical property measurement structure according to any one of the above, wherein the semiconductor electrical property measurement structure comprises a test array.

[0023] An address encoder electrically connected to the test array and configured to select any test unit in the test array;

[0024] A control module electrically connected to the address encoder and configured to send an address signal to the address encoder; and

[0025] A data output module electrically connected to the first signal output end and the second signal output end of the test unit and configured to output the current signal of the selected test unit.

[0026] In an embodiment of the present application, the control module or the host computer is electrically connected to the data output module and configured to obtain the drop amplitude of the current signal compared with the reference signal.

[0027] When the drop amplitude of the current signal is greater than a first drop amplitude and less than a second drop amplitude, the via connected with the drain electrode in the test unit is in a high resistance state, and the control module or the host computer outputs a first logic signal.

[0028] When the drop amplitude of the current signal is greater than the second drop amplitude, the via connected with the source electrode in the test unit is in a high resistance state, and the control module or the host computer outputs a second logic signal, wherein the second drop amplitude is greater than the first drop amplitude.

[0029] In an embodiment of the present application, the semiconductor electrical property measurement structure, the address encoder, the control module and the data output module are arranged on the same wafer.

[0030] The semiconductor electrical property measurement method based on the semiconductor electrical property measurement structure as described above comprises the following steps:

[0031] Iteratively obtaining the current signal of the test unit in the semiconductor electrical property measurement structure;

[0032] comparing the current signal with a reference signal, and obtaining a drop of the current signal compared with the reference signal; and

[0033] locating the electrode type in a high resistance state in the test unit according to the drop range of the current signal.

[0034] As described above, the present application provides a semiconductor electrical property measurement structure, a measurement device and a measurement method, and the unexpected technical effects of the present application are as follows: the test method provided by the present application is suitable for mass testing, and can distinguish high resistance defects of source or drain via holes, and accurately locate the specific position of specific defects. In the electrical property measurement structure provided by the present application, the detection sensitivity and accuracy are high, specifically, the drain via hole resistance can be detected by linear current drop in the source grounding mode, and the source via hole resistance can be detected by exponential current drop in the drain grounding mode, covering from slight to serious resistance abnormalities. The matrix arrangement of the present application can simulate high-density circuits, ensure that the detection results are consistent with the actual chip behavior, and identify process fluctuations through large-scale data statistics to guide process debugging. The present application can significantly improve the detection rate and yield control accuracy of via hole defects, and is suitable for advanced process memory array and high reliability chip testing.

[0035] Of course, implementing any product of the present application does not necessarily need to achieve all the advantages described above at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0037] Figure 1 It is a structure schematic diagram of a test device in an embodiment of the present application.

[0038] Figure 2 It is a structure schematic diagram of a via hole in a semiconductor device in an embodiment of the present application.

[0039] Figure 3 It is a distribution structure schematic diagram of a test array in an embodiment of the present application.

[0040] Figure 4 It is a structure schematic diagram of a first type test unit in an embodiment of the present application.

[0041] Figure 5 It is a structure schematic diagram of a second type test unit in an embodiment of the present application.

[0042] Figure 6A structure diagram of a control module in an embodiment of the present application.

[0043] In the figure: 100, control module; 110, address gating unit; 120, data acquisition unit; 130, data analysis unit; 200, first encoder; 300, second encoder; 400, test array; 410, first type test unit; 420, second type test unit; 500, substrate; 501, active region; 502, isolation structure; 503, interlayer dielectric layer; 504, polysilicon layer; M, interconnection layer; CT, via; D, drain electrode; S, source electrode; CT1, first via; CT2, second via; M1, first metal layer; M2, second metal layer; GND, ground terminal; D_OUT, output terminal; 600, data output module. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0045] Please refer to Figure 1 and Figure 2 The semiconductor electrical property measurement structure and the measurement method provided by the present application are used for testing the resistance deviation of the via CT, and the present application can monitor and obtain the resistance distribution behavior of a large number of dense vias CT. The semiconductor electrical property measurement structure provided by the present application is arranged on a test wafer or a multi-project wafer (MPW), and is arranged in a core region of the wafer. The core region refers to a region of the wafer except the edge region and the redundant region. The semiconductor measurement structure provided by the present application is in the form of a test array 400. The test array 400 can be used as a measured object and is electrically connected in a test device. In the embodiment, the test device includes a control module 100, a first encoder 200, a second encoder 300 and a data output module 600. The measurement method provided by the present application can be stored in a storage medium in the form of firmware. When the control module 100 calls and runs the firmware in the storage medium, the semiconductor electrical property measurement method provided by the present application can be realized. Specifically, the control module 100 can call the first encoder 200, the second encoder 300, the test array 400 and the data output module 600, and realize the acquisition of test data. According to the obtained test data, the control module 100 can actively analyze the test data and simulate the resistance distribution of the via CT in the test array 400.

[0046] Please refer toFigure 1 and Figure 3 As shown, in one embodiment of the present invention, the semiconductor electrical measurement structure includes a test array 400. The test array 400 includes multiple test units arranged in a matrix. Each test unit includes at least two transistors, and the transistors are sequentially electrically connected. In this embodiment, sequential electrical connection refers to the sequential arrangement of the transistors and the sequential connection of their electrodes. Adjacent transistors in a test unit share the same electrode. In this embodiment, the transistor is a MOS transistor, and the transistor includes a source electrode S, a gate electrode, and a drain electrode D. When voltage is applied to the gate electrode, the channel between the source electrode S and the drain electrode D is turned on, and the MOS transistor is activated. In this embodiment, the number of transistors in one test unit is, for example, two. Figure 3 The first and second transistors are shown. The first and second transistors share a common source electrode S or drain electrode D, and their gate electrodes are electrically connected to the power supply terminal. According to the conduction sequence set by the control module 100, the test unit is selected and turned on, thereby realizing the output of a current signal. The semiconductor electrical measurement structure provided by this invention can simulate the real circuit environment of a product. In this embodiment, the test unit adopts a design where at least two transistors share the same electrode and are arranged in a matrix, with a dense arrangement consistent with the high-density via CT environment of actual memory arrays. This structure can more realistically simulate the process defects and resistance distribution behavior of via CTs in actual circuits. Furthermore, by statistically measuring the large-scale matrix-distributed test unit, the tail behavior of the resistance distribution of via CTs can be captured, avoiding a decrease in overall yield due to a few defects. Moreover, the large-scale matrix-distributed test unit set by this invention eliminates random noise interference through statistical regularity, ensuring the reliability of the test results. The large-scale test unit refers to a test array 400 with a size of, for example, 512kB to 2MB.

[0047] Please see Figure 1 , Figure 3 to Figure 5As shown, in one embodiment of the present invention, in the test array 400, the middle electrode of some test units is grounded, and the edge electrode serves as the first signal output terminal D_OUT; the middle electrode of another part of the test units serves as the second signal output terminal D_OUT, and the edge electrode is grounded. The middle electrode is the common electrode of adjacent transistors in the test unit, and the edge electrode is the non-common electrode located at the edge of the transistor connection chain in the test unit. In this invention, a dual-mode electrode configuration is adopted. By the difference in output current between the two modes, high-resistance defects of source via CTs or drain via CTs can be distinguished, and the location of high-resistance via CTs can be accurately located. Specifically, in this embodiment, in the first mode, the middle electrode in the test unit is grounded, and the edge electrode serves as the output terminal D_OUT. This allows for focused monitoring of the resistance of the via CT connected to the drain electrode D. When the via CT connected to the drain electrode D has high resistance, the output current will decrease slightly due to the voltage division effect. In the second mode, the edge electrode of the test unit is grounded, and the middle electrode serves as the output terminal D_OUT. This mode focuses on monitoring the resistance of the via CT connected to the source electrode S. When the via CT connected to the source electrode S has high resistance, it significantly increases the source voltage, causing a decrease in the gate-source voltage. Simultaneously, the threshold voltage of the transistor increases, resulting in a substantial decrease in the output current. In this embodiment, without switching between the ground terminal GND and the output terminal D_OUT of the first type of test unit 410, the location of the high-resistance via CT can be determined by comparing the current data with a reference current and based on the magnitude of the decrease in the current data compared to the reference current. Therefore, this invention employs a shared electrode design, where adjacent transistors share an electrode, forcing the current to be conducted through the via CT under test. This further amplifies the impact of the high-resistance via CT on the output current, improving detection sensitivity.

[0048] Please see Figure 1 , Figure 3 to Figure 5 As shown, it should be noted that the electrical measurement structure of the present invention uses a standard MOS transistor design, requiring no special process and can be directly integrated into the wafer. Furthermore, it can adapt to the testing requirements of different process nodes by adjusting the matrix size or transistor type. Adjusting the matrix size, for example, involves increasing the number of test cells in the test array 400. The transistor type refers to setting the transistors as NMOS transistors or PMOS transistors. It should be noted that multiple transistors in the test cells of the present invention are of the same type. In one embodiment of the present invention, the test cells in the test array 400 can use different transistor types. In another embodiment of the present invention, all test cells in the test array 400 can use the same transistor type, thereby adapting to the testing requirements of different process nodes.

[0049] Please see Figure 1 and Figure 3As shown, in one embodiment of the present invention, a test array 400 is disposed on a wafer. The transistor includes a substrate 500, an isolation structure 502, an interlayer dielectric layer 503, a via CT, and an interconnect layer M. The substrate 500 is a silicon substrate used to form the semiconductor structure. The isolation structure 502 is disposed in the substrate 500 and isolates multiple active regions 501 within the substrate 500. In this embodiment, the isolation structure 502 is formed using a shallow trench isolation (STI) process. Ion implantation is performed on the active regions 501 to form multiple doped regions, thereby forming the drain electrode D and source electrode S of the transistor. A polysilicon layer 504 is then formed on the active regions 501, and the polysilicon layer 504 is patterned to form the gate electrode of the transistor. In this embodiment, the critical dimensions of the transistor can be consistent with the critical dimensions of the product to simulate the product's process environment as closely as possible. The substrate 500, source electrode S, drain electrode D, and gate electrode form the device layer of the semiconductor electrical measurement structure. In this embodiment, an interlayer dielectric layer 503 is disposed on the device layer and is used to isolate the device layer and the metal interconnect structure. In this embodiment, one end of the via CT passes through the interlayer dielectric layer 503 and is electrically connected to the electrode of the transistor, or to an interconnect layer M. The other end of the via CT is electrically connected to the interconnect layer M. The interconnect layer M is a base layer in a semiconductor stack structure and is used to connect various semiconductor devices to form an integrated circuit.

[0050] Please see Figure 1 , Figure 3 to Figure 5 As shown, in one embodiment of the present invention, the electrical measurement structure includes multiple first vias CT1, multiple second vias CT2, a first metal layer M1, and a second metal layer M2. The first end of each first via CT1 is connected to the source electrode S or drain electrode D of the transistor, and the second end of each first via CT1 passes through the interlayer dielectric layer 503 and is connected to either the first metal layer M1 or the second metal layer M2. The first metal layer M1 is grounded, and the second metal layer M2 serves as the signal output terminal D_OUT of the electrical measurement structure. A current signal can be output through the signal output terminal D_OUT. In this embodiment, the second metal layer M2 is located above the first metal layer M1, and the second metal layer M2 and the first metal layer M1 can be adjacent layers or separated by multiple interconnect layers M. In this embodiment, the second metal layer M2 is located on the side of the first metal layer M1 away from the transistor, and the extension direction of the second metal layer M2 is perpendicular to the extension direction of the first metal layer M1. For example, the horizontal direction X is set as the first direction, and the vertical direction Y is set as the second direction. The first metal layer M1 extends along the first direction, and the second metal layer M2 extends along the second direction. In this embodiment, the first end of the second via CT2 is connected to the gate electrode, and there can be multiple second vias CT2 connected to the gate electrode.

[0051] As shown in Figure 1 , Figure 3 to Figure 5 In an embodiment of the present application, the electrical measurement structure includes a polysilicon layer 504 disposed on the substrate 500. The polysilicon layer 504 is patterned to form the gate layer of the transistors. In this embodiment, the polysilicon layer 504 has multiple strips and extends in a preset direction, for example, in a direction perpendicular to the connection direction of the middle transistors of the test cells. The polysilicon layer 504 covers the active regions 501 of multiple transistors and simultaneously serves as the gate electrodes of the multiple transistors. The second via CT2 is applied with a high voltage, and the gate electrodes of the multiple transistors are simultaneously turned on, thereby achieving the simultaneous turn-on of the multiple transistors. The coverage pattern of the polysilicon layer 504 provided in this embodiment is only an example. In other embodiments of the present application, the coverage pattern of the polysilicon layer 504 can be adjusted according to different test requirements or different test scales. For example, the polysilicon layer 504 can be arranged to connect multiple transistors, or the polysilicon layer 504 can be arranged to connect a single transistor.

[0052] As shown in Figure 1 , Figure 3 to Figure 5 In an embodiment of the present application, the test array 400 includes multiple first address lines and multiple second address lines. The first address lines are used to locate the rows of the test cells. In this embodiment, the first metal layer M1 is distributed according to the first address lines, and the first address lines can be selected by the host computer. The multiple second address lines are used to locate the columns of the test cells. In this embodiment, the second metal layer M2 is distributed according to the second address lines, and the second address lines can be selected by the host computer. In the test, when any test cell in the test array 400 is to be subjected to the turn-on test, the corresponding test cell can be accurately selected by selecting the first address line and the second address line corresponding to the test cell. In this embodiment, each address line has a corresponding unique number.

[0053] As shown in Figure 1 , Figure 3 to Figure 5 In an embodiment of the present application, the test array 400 includes multiple first type test cells 410 and multiple second type test cells 420. The first type test cells 410 and the second type test cells 420 are randomly distributed or distributed in a preset manner in the test array 400. Regarding the preset distribution manner, for example, Figure 1 and Figure 3As shown, the first type of test cells 410 share the gate electrode, and the first type of test cells 410 are distributed along the extension direction of the polysilicon layer 504. The second type of test cells 420 share the gate electrode, and the second type of test cells 420 are distributed along the extension direction of the polysilicon layer 504. The array rows of the first type of test cells 410 and the array rows of the second type of test cells 420 can be staggered. In the present application, the distribution of the first type of test cells 410 and the second type of test cells 420 in the test array 400 can be adjusted by adjusting the distribution of the polysilicon layer 504. In another embodiment of the present application, a first region for distributing the first type of test cells 410 and a second region for distributing the second type of test cells 420 can be provided. In this way, the test results of the first type of test cells 410 and the second type of test cells 420 can be better distinguished, and the conduction test process on the first region and the second region can be controlled.

[0054] As shown in FIG. 4, the test array 400 includes a plurality of first type of test cells 410 and a plurality of second type of test cells 420. The first type of test cells 410 and the second type of test cells 420 are arranged in an array row. The first type of test cells 410 and the second type of test cells 420 are arranged in an array column. Figure 1 、 Figure 3 to Figure 5 As shown in FIG. 4, the test array 400 includes a plurality of first type of test cells 410 and a plurality of second type of test cells 420. The first type of test cells 410 and the second type of test cells 420 are arranged in an array row. The first type of test cells 410 and the second type of test cells 420 are arranged in an array column.

[0055] As shown in FIG. 4, the test array 400 includes a plurality of first type of test cells 410 and a plurality of second type of test cells 420. The first type of test cells 410 and the second type of test cells 420 are arranged in an array row. The first type of test cells 410 and the second type of test cells 420 are arranged in an array column. Figure 1 、 Figure 3 to Figure 5As shown in the embodiment of the present application, the semiconductor electrical property measuring device comprises a semiconductor electrical property measuring structure and a peripheral circuit. In the embodiment, the peripheral circuit comprises a first encoder 200, a second encoder 300, a data output module 600 and a control module 100. The control module 100 can be a logic circuit capable of implementing the semiconductor electrical property measuring method provided by the present application, or a processor capable of calling firmware to implement the measuring method of the present application, such as an ARM processor. When the control module 100 is a logic circuit, the control module 100 can be formed on the same wafer as the semiconductor electrical property measuring structure of the present application, and the control module 100 can serve as the peripheral circuit. The control module 100 is electrically connected to a host computer, and can acquire current data of the semiconductor electrical property measuring structure according to timing signals and control instructions set by the host computer. The host computer is used to set control instructions and timing signals required for measurement, and converts these parameters into electrical signals recognizable by the control module 100 (logic circuit), so as to ensure that the measurement action is executed in order according to the preset logic. The control instructions include, for example, starting / stopping current collection and setting current collection precision range, etc. The timing signals include, for example, time interval and signal triggering sequence of the control module 100 driving the measuring structure to collect data, etc. Moreover, after the control module 100 acquires the current data from the semiconductor measuring structure, the data is uploaded to the host computer, and the host computer collects the current data. In the embodiment, the first encoder 200 and the second encoder 300 are both address encoders. The first encoder 200 is electrically connected to the first address line and the control module 100, can receive address signals of the control module 100, decode the address signals to obtain specific address information, and select the first address line corresponding to the address information. The second encoder 300 is electrically connected to the second address line and the control module 100, can receive address signals of the control module 100, decode the address signals to obtain specific address information, and select the second address line corresponding to the address information. Specifically, the first address line can be used to locate the row of the test unit, and the second address line can be used to locate the column of the test unit.

[0056] Please refer to Figure 1 , Figure 3 to Figure 5 As shown in the embodiment of the present application, the control module 100 can further comprise a clock unit, which is used to output a timing signal for selecting the test unit, so as to adjust the order of selecting each test unit. It should be noted that the timing signal output by the clock unit can be adjusted according to different processes or different scales of the object to be tested. For example, by adjusting the timing, the first type of test unit 410 is preferentially selected, or a certain column is preferentially selected, or a test unit that has a problem in previous testing is preferentially selected.

[0057] Please refer to Figure 1 , Figure 3 to Figure 5As shown, in one embodiment of the present invention, the data output control module 100 includes, for example, an operational amplifier circuit and an output port D_OUT. In this embodiment, the operational amplifier circuit is electrically connected to the first signal output port D_OUT and the second signal output port D_OUT, amplifies the current signal, and outputs it through the output port D_OUT. The output port D_OUT is electrically connected to the host computer, transmitting the output current signal to the host computer. In this embodiment, the test unit in the test array 400 may further include a selection transistor. After the first encoder 200 and the second encoder 300 parse the address signal, they can select the selection transistor of the corresponding test unit and output the current signal of the corresponding test unit. The selection transistor is a MOSFET.

[0058] Please refer to Figure 1 , Figure 3 to Figure 6 As shown, in one embodiment of the present invention, the control module 100 includes an address selection unit 110. The address selection unit 110 is electrically connected to the first encoder 200 and the second encoder 300, and is used to generate an address signal to select the corresponding test unit in the test array 400. In this embodiment, the data output module 600 is electrically connected to a host computer, and the host computer performs data analysis on the acquired current signal. In another embodiment of the present invention, the data acquisition unit 120 is electrically connected to the data output module 600, acquires the current signal, and converts the current signal into current data through analog-to-digital conversion. The data analysis unit 130 is electrically connected to the data acquisition unit 120 and acquires the current data of each test unit. It should be noted that the reference current used as a comparison reference in the test can be current data preset by the tester, or it can be the average current data of the test array 400. All test units in the test array 400 are transistors formed simultaneously using the same process. In this embodiment, if the current data of the test unit is less than the reference current, a high resistance condition occurs in the via current transformer (CT) of the test unit. In mass testing, abnormal test units can be directly identified through current data. In this embodiment, the data analysis unit 130 can be a comparator.

[0059] Please refer to Figure 1 , Figure 3 to Figure 6As shown, in an embodiment of the present application, the abnormal test unit is analyzed by taking the NMOS transistor as an example. If the test unit is the first type of test unit 410, the ground end GND is the central electrode and the source electrode S, and the output end D_OUT is the edge electrode and the drain electrode D. When reading the current of the test unit, the weakening effect of the high resistance of the two-end via CT on the reading current is smaller, and the weakening effect of the high resistance of the middle via CT on the reading current is larger. Therefore, in the case of the drain electrode D being the high resistance of the via CT, the current data decreases slightly. In the case of the source electrode S being the high resistance of the via CT, the current data decreases greatly. If the test unit is the second type of test unit 420, the ground end GND is the edge electrode and the source electrode S, and the output end D_OUT is the middle electrode and the drain electrode D. When reading the current of the test unit, the weakening effect of the high resistance of the two-end via CT on the reading current is larger, and the weakening effect of the high resistance of the middle via CT on the reading current is smaller. Therefore, in the case of the drain electrode D being the high resistance of the via CT, the current data decreases slightly. In the case of the source electrode S being the high resistance of the via CT, the current data decreases greatly.

[0060] It should be noted that, for the slight decrease and the great decrease mentioned in the present application, the amplitudes can be distinguished by setting a first threshold range and a second threshold range. For example, the current data decreases by 0-20%, which is a slight decrease. For example, the current data decreases by 20-50%, which is a great decrease.

[0061] Please refer to Figure 1 to Figure 6As shown, the semiconductor electrical property measurement structure provided by the present application comprises a test array 400. The test array 400 comprises a plurality of test units, and the plurality of test units are arranged in a matrix. Each test unit comprises at least two transistors, and the plurality of transistors are electrically connected in sequence. In the test unit, adjacent transistors share the same electrode. In the test array 400, the middle electrodes of some test units are grounded, and the edge electrodes are used as the first signal output end D_OUT. The middle electrodes of the other test units are used as the second signal output end D_OUT, and the edge electrodes are grounded. When the electrodes of the transistors are in a high resistance state, the output current of the test unit decreases, and the range of the decrease of the output current represents the type of the electrode in the high resistance state in the test unit. The present application provides a semiconductor electrical property measurement device, which comprises a semiconductor electrical property measurement structure, an address encoder, a control module 100 and a data output module 600. The address encoder is electrically connected to the test array 400 and is used to select any test unit in the test array 400. The control module 100 is electrically connected to the address encoder and sends an address signal to the address encoder. The data output module 600 is electrically connected to the first signal output end D_OUT and the second signal output end D_OUT of the test unit, and outputs the current signal of the selected test unit.

[0062] The unexpected technical effect of the present application is that the test method provided by the present application is suitable for large-scale testing, and can distinguish high resistance defects of source or drain via holes and accurately locate the specific position of specific defects. In the electrical property measurement structure provided by the present application, the detection sensitivity and accuracy are high. Specifically, in the source grounding mode, the drain via hole resistance can be detected by the linear decrease of the current, and in the drain grounding mode, the source via hole resistance can be detected by the exponential decrease of the current, covering from slight to serious resistance abnormalities. The matrix arrangement of the present application can simulate high-density circuits, ensure that the detection results are consistent with the actual chip behavior, and identify process fluctuations through large-scale data statistics to guide process debugging. The present application can significantly improve the detection rate and yield control accuracy of via hole defects, and is suitable for advanced process memory array and high reliability chip testing.

[0063] The above disclosed embodiments of the present application are only used to help explain the present application. The embodiments do not describe all the details, nor limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of the present application. The embodiments are selected and described in detail in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well understand and utilize the present application. The present application is limited by the claims and their full scope and equivalents.

Claims

1. A semiconductor electrical measurement structure, comprising: The test array comprises a plurality of test units, a plurality of first vias, a first metal layer and a second metal layer, and the plurality of test units are arranged in a matrix, wherein each test unit comprises two transistors, the two transistors in the test unit are of the same type, and the two transistors are electrically connected in sequence, in the test unit, adjacent transistors share the same electrode, the same electrode is a source electrode or a drain electrode, the source electrode and the drain electrode of the transistor are connected to the first end of the plurality of first vias, the first metal layer is electrically connected to the second end of part of the first vias, and the first metal layer is grounded, and the second metal layer is electrically connected to the second end of another part of the first vias, and the second metal layer is a signal output end of the test array and is electrically connected to an upper computer; In the test array, the middle electrode of part of the test units is connected to the first metal layer through the first via and is grounded, and the edge electrode is connected to the second metal layer through the first via and is a first signal output end, and the middle electrode of another part of the test units is connected to the second metal layer through the first via and is a second signal output end, and the edge electrode is connected to the first metal layer through the first via and is grounded, wherein the middle electrode is a shared electrode of adjacent transistors in the test unit, and the edge electrode is a non-shared electrode of the transistor located at the edge of the connection chain of the transistor in the test unit; When the electrode of the transistor is in a high resistance state, the output current of the test unit decreases, and the range of the decrease of the output current represents the type of the electrode in the high resistance state in the test unit, thereby determining the first via electrically connected to the electrode in the high resistance state.

2. The semiconductor electrical measurement structure of claim 1, wherein The metrology structure comprises an interlayer dielectric layer arranged between the transistor and the first metal layer and between adjacent metal layers, wherein the second metal layer is located on the side of the first metal layer away from the transistor, and the extension distribution direction of the second metal layer is perpendicular to the extension distribution direction of the first metal layer.

3. The semiconductor electrical measurement structure of claim 1, wherein, The test array comprises: a plurality of first address lines for positioning the row of the test unit, the first metal layer is distributed according to the first address line, wherein the first address line is allowed to be selected by the upper computer; and a plurality of second address lines for positioning the column of the test unit, the second metal layer is distributed according to the second address line, wherein the second address line is allowed to be selected by the upper computer.

4. The semiconductor electrical measurement structure of claim 1, wherein, The part of the test array comprises a plurality of first type test units and a plurality of second type test units, and the first type test units and the second type test units are randomly distributed or distributed in a preset manner in the test array; In the first type test unit, the middle electrode is a source electrode and the source electrode is grounded, and the edge electrode is a drain electrode and the drain electrode is the first signal output end. In the second type of test unit, the middle electrode is a drain electrode and the drain electrode is grounded, and the edge electrode is a source electrode and the source electrode is the second signal output terminal.

5. The semiconductor electrical measurement structure of claim 4, wherein, In the test unit, when the first via connected to the drain electrode is in a high resistance state, the current signal output by the test unit decreases by an amplitude greater than a first amplitude and less than a second amplitude compared to a reference signal, and when the first via connected to the source electrode is in a high resistance state, the current signal output by the test unit decreases by an amplitude greater than the second amplitude compared to the reference signal, wherein the second amplitude is greater than the first amplitude.

6. A semiconductor electrical property measurement device, comprising: Comprising: The semiconductor electrical property measurement structure of any one of claims 1-5, wherein the semiconductor electrical property measurement structure comprises a test array. An address encoder electrically connected to the test array and configured to select any test unit in the test array; A control module electrically connected to the address encoder and configured to send an address signal to the address encoder; and A data output module electrically connected to the first signal output terminal and the second signal output terminal of the test unit and configured to output a current signal of the selected test unit. The data output module and the host computer are each electrically connected to the control module and configured to obtain an amplitude of decrease of the current signal compared to a reference signal; 7. The semiconductor electrical property measurement apparatus of claim 6, wherein When the amplitude of decrease of the current signal is greater than a first amplitude and less than a second amplitude, a via connected to the drain electrode in the test unit is in a high resistance state, and the control module outputs a first logic signal; When the amplitude of decrease of the current signal is greater than the second amplitude, a via connected to the source electrode in the test unit is in a high resistance state, and the control module outputs a second logic signal, wherein the second amplitude is greater than the first amplitude. The semiconductor electrical property measurement structure, the address encoder, the control module, and the data output module are disposed on the same wafer.

8. The semiconductor electrical property measurement apparatus of claim 6, wherein the semiconductor electrical property measurement apparatus is configured to perform the measurement of the electrical property of the semiconductor device under test by applying a voltage to the semiconductor device under test and measuring a current through the semiconductor device under test. Comprising the following steps:

9. A method for measuring electrical properties of a semiconductor device based on a structure as claimed in claim 1, characterized in that Iteratively obtaining a current signal of a test unit in the semiconductor electrical property measurement structure; Comparing the current signal with a reference signal and obtaining an amplitude of decrease of the current signal compared to the reference signal; According to the range of the amplitude of decrease of the current signal, the type of electrode in a high resistance state in the test unit is located, and then the first via electrically connected to the electrode in a high resistance state is determined. ​ ​

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