Inductor structure and preparation method thereof, and chip packaging structure and preparation method thereof

Abstract

The invention provides an inductor structure and a preparation method thereof, and a chip packaging structure of an integrated inductor and a preparation method thereof, the inductor is formed in an empty slot in a plastic packaging layer, and a first inductor pattern structure, a vertical bonding wire and a second inductor pattern structure of a substrate are utilized to form a plane inductor or a three-dimensional inductor in the vertical direction. Compared with a traditional planar inductor in the horizontal direction, the inductor with the large inductance value can be formed under the relatively small area, the problem of welding failure of the surface-mounted inductor does not need to be considered compared with the surface-mounted inductor, the surface-mounted inductor is provided with the inductor shell, the overall size is large, however, the inductor does not need to be manufactured with the shell, and the manufacturing cost is reduced. And the area of the inductance region corresponding to the same inductance value is smaller than that of a surface-mounted inductor, so that the inductor is particularly suitable for application scenes with higher requirements on the performance of the inductor and limited sizes.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to an inductor structure and its fabrication method, and a chip packaging structure and fabrication method for integrated inductors. Background Technology

[0002] Please refer to Figure 1 Existing SiP (System-In-Package) technology achieves high functional integration and compact design by integrating multiple active devices, passive devices, and chips into a single package. Integrated inductors, as important components in SiP packages, play a crucial role in power management and signal transmission.

[0003] The integrated inductors in existing SiP solutions are mainly planar inductors or surface-mount inductors. Planar inductors are manufactured using planar processes, where the inductor structure is formed by patterning a metal layer on the package substrate; while surface-mount inductors use methods such as screen printing or inkjet printing, and a pick-and-place machine is used to accurately place the surface-mount inductor at a predetermined position on the substrate.

[0004] However, planar inductors used in SiP packaging have smaller inductance values ​​and limited quality factors (Q values), making them suitable for low-frequency or radio frequency applications. Surface-mount inductors have a wide range of applications, but they increase the difficulty of molding, package size, and reliability risks. Inductor performance (such as inductance value and current carrying capacity) is generally size-dependent, and miniaturization using existing solutions often leads to a decrease in inductor performance. For example, reducing the inductor size may reduce its inductance value and current carrying capacity, making it difficult to meet the requirements of some applications with high inductor performance requirements. Summary of the Invention

[0005] The problem this application aims to solve is to provide an inductor structure and fabrication method, and an integrated inductor chip packaging structure and fabrication method, thereby addressing the issue that miniaturization in existing solutions often leads to a decrease in inductor performance.

[0006] To address the above problems, this application provides an inductor structure, comprising: A substrate, wherein a first surface of the substrate has an inductive region, and the substrate has a first inductive pattern structure corresponding to the inductive region; A molding layer covering the first surface of the substrate, wherein the molding layer has a slot that exposes the first inductor pattern structure; An inductive magnetic adhesive layer that fills the empty slot; A vertical bonding line runs through the inductor magnetic adhesive layer, one end of which is located on the upper surface of the first inductor pattern structure, and the other end of which is exposed on the upper surface of the inductor magnetic adhesive layer. The second inductor pattern structure is located on the upper surface of the inductor magnetic adhesive layer and the upper surface of the exposed vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are electrically connected and constitute an inductor.

[0007] As an optional implementation, the first inductor pattern structure includes multiple first metal strip structures on the same straight line, and the second inductor pattern structure includes multiple second metal strip structures on the same straight line. The first metal strip structures and the second metal strip structures are arranged in parallel and staggered in the vertical direction. The ends of the first metal strip structures and the second metal strip structures are mapped on the first surface of the substrate with overlapping vertical bonding lines that connect the ends of the first metal strip structures and the ends of the second metal strip structures respectively. The first inductor pattern structure, the vertical bonding lines, and the second inductor pattern structure are connected to form a planar S-shaped inductor.

[0008] As an optional implementation, the first inductor pattern structure includes multiple first metal strip structures on multiple parallel straight lines, and the second inductor pattern structure includes multiple second metal strip structures on multiple parallel straight lines and adjacent metal interconnect structures. The first and second metal strip structures are parallel, and there are multiple first metal strip structures and multiple second metal strip structures on each parallel straight line. The first metal strip structure and the corresponding second metal strip structures on a straight line are vertically staggered. The ends of the corresponding first metal strip structures and second metal strip structures overlap on the first surface of the substrate. A portion of the vertical bonding lines connect the ends of the first metal strip structures and the ends of the second metal strip structures respectively. The ends of the adjacent metal interconnect structures and the outer ends of the first metal strip structures located at the outermost edge on the two corresponding straight lines overlap on the first surface of the substrate. A portion of the vertical bonding lines connect the ends of the adjacent metal interconnect structures and the outer ends of the first metal strip structures at the outermost edge respectively. The adjacent metal interconnect structures are used to connect the first metal strip structures on different straight lines through the vertical bonding lines. The first inductor pattern structure, the vertical bonding lines, and the second inductor pattern structure are connected to form a vertical planar S-shaped inductor. The adjacent metal interconnect structures are connected to the planar S-shaped inductors of adjacent parallel planes to form a three-dimensional S-shaped inductor.

[0009] As an optional implementation, the first inductor pattern structure includes multiple first metal strip structures on multiple parallel straight lines, and the second inductor pattern structure includes multiple second metal strip structures on multiple parallel straight lines, wherein the number of first metal strip structures on each parallel straight line is one, and the number of second metal strip structures on each parallel straight line is one. The mappings of the first metal strip structure and the second metal strip structure on the first surface of the substrate intersect, and the mappings of the ends of the first metal strip structure and the second metal strip structure on the first surface of the substrate overlap. The vertical bonding line connects the ends of the first metal strip structure and the ends of the second metal strip structure respectively. The first metal strip structure and the second metal strip structure are connected end to end by the vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are connected to form a spiral three-dimensional S-shaped inductor.

[0010] As an optional implementation, the first inductor pattern structure includes a spiral-shaped first metal strip structure, and the second inductor pattern structure includes a spiral-shaped second metal strip structure. The first metal strip structure and the second metal strip structure are connected end to end using the vertical bonding line, and the first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are connected to form a three-dimensional spiral inductor.

[0011] As an optional implementation, the first inductor pattern structure is located inside the substrate or on the upper surface of the substrate. When the first inductor pattern structure is located inside the substrate, the first surface of the substrate exposes the area of ​​the first inductor pattern structure used for bonding vertical bonding lines.

[0012] As an optional implementation, it also includes a protective layer located on the upper surface of the molding layer and the second inductor pattern structure.

[0013] As an optional implementation, the material of the inductive magnetic adhesive layer is silicone magnetic adhesive or epoxy magnetic adhesive.

[0014] This invention also provides a method for fabricating an inductor structure, comprising: A substrate is provided, wherein a first surface of the substrate has an inductive region, and the substrate has a first inductive pattern structure corresponding to the inductive region; A molding layer is formed on the first surface of the substrate, the molding layer having a slot in the inductor region, the slot exposing the first inductor pattern structure; A vertical bonding line is formed on the upper surface of the first inductor pattern structure, one end of the vertical bonding line is located on the upper surface of the first inductor pattern structure, and the height of the vertical bonding line is greater than the depth of the slot. The empty slot is filled with an inductive magnetic adhesive layer, and the upper surface of the inductive magnetic adhesive layer exposes the other end of the vertical bonding line. A second inductor pattern structure is formed on the upper surface of the inductor magnetic adhesive layer and the upper surface of the exposed vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are electrically connected and constitute an inductor.

[0015] As an optional implementation, the first inductor pattern structure is located inside the substrate or on the upper surface of the substrate. When the first inductor pattern structure is located inside the substrate, the first surface of the substrate exposes the area of ​​the first inductor pattern structure used for bonding vertical bonding lines.

[0016] As an optional implementation, it further includes forming a protective layer on the upper surface of the molding layer and the second inductor pattern structure.

[0017] As an optional implementation, the specific steps of filling the empty slot with an inductive magnetic adhesive layer, with the upper surface of the inductive magnetic adhesive layer exposing the other end of the vertical bonding line, are as follows: The cavity is filled with an inductive magnetic adhesive material, the thickness of which is greater than the depth of the cavity. The inductive magnetic adhesive material is ground to form an inductive magnetic adhesive layer, and the upper surface of the inductive magnetic adhesive layer exposes the other end of the vertical bonding line.

[0018] This invention also provides a chip package structure for an integrated inductor, comprising: A substrate, wherein a first surface of the substrate has an inductor region and a chip region, the substrate has a first inductor pattern structure corresponding to the inductor region, and a chip structure is disposed on the surface of the substrate corresponding to the chip region. A molding compound covering the first surface of the substrate and the chip structure, wherein the molding compound has a slot in the inductor region, the slot exposing the first surface of the substrate; An inductive magnetic adhesive layer that fills the empty slot; A vertical bonding line runs through the inductor magnetic adhesive layer, one end of which is located on the upper surface of the first inductor pattern structure, and the other end of which is exposed on the upper surface of the inductor magnetic adhesive layer. A second inductor pattern structure is located on the upper surface of the inductor magnetic adhesive layer and the upper surface of the exposed vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are electrically connected and constitute an inductor. The inductor is electrically connected to the chip structure through the substrate.

[0019] As an optional implementation, the first inductor pattern structure includes multiple first metal strip structures on the same straight line, and the second inductor pattern structure includes multiple second metal strip structures on the same straight line. The first metal strip structures and the second metal strip structures are arranged in parallel and staggered in the vertical direction. The ends of the first metal strip structures and the second metal strip structures are mapped on the first surface of the substrate with overlapping vertical bonding lines that connect the ends of the first metal strip structures and the ends of the second metal strip structures respectively. The first inductor pattern structure, the vertical bonding lines, and the second inductor pattern structure are connected to form a planar S-shaped inductor.

[0020] As an optional implementation, the first inductor pattern structure includes multiple first metal strip structures on multiple parallel straight lines, and the second inductor pattern structure includes multiple second metal strip structures on multiple parallel straight lines and adjacent metal interconnect structures. The first and second metal strip structures are parallel, and there are multiple first metal strip structures and multiple second metal strip structures on each parallel straight line. The first metal strip structure and the corresponding second metal strip structures on a straight line are vertically staggered. The ends of the corresponding first metal strip structures and second metal strip structures overlap on the first surface of the substrate. A portion of the vertical bonding lines connect the ends of the first metal strip structures and the ends of the second metal strip structures respectively. The ends of the adjacent metal interconnect structures and the outer ends of the first metal strip structures located at the outermost edge on the two corresponding straight lines overlap on the first surface of the substrate. A portion of the vertical bonding lines connect the ends of the adjacent metal interconnect structures and the outer ends of the first metal strip structures at the outermost edge respectively. The adjacent metal interconnect structures are used to connect the first metal strip structures on different straight lines through the vertical bonding lines. The first inductor pattern structure, the vertical bonding lines, and the second inductor pattern structure are connected to form a vertical planar S-shaped inductor. The adjacent metal interconnect structures are connected to the planar S-shaped inductors of adjacent parallel planes to form a three-dimensional S-shaped inductor.

[0021] As an optional implementation, the first inductor pattern structure includes multiple first metal strip structures on multiple parallel straight lines, and the second inductor pattern structure includes multiple second metal strip structures on multiple parallel straight lines, wherein the number of first metal strip structures on each parallel straight line is one, and the number of second metal strip structures on each parallel straight line is one. The mappings of the first metal strip structure and the second metal strip structure on the first surface of the substrate intersect, and the mappings of the ends of the first metal strip structure and the second metal strip structure on the first surface of the substrate overlap. The vertical bonding line connects the ends of the first metal strip structure and the ends of the second metal strip structure respectively. The first metal strip structure and the second metal strip structure are connected end to end by the vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are connected to form a spiral three-dimensional S-shaped inductor.

[0022] As an optional implementation, the first inductor pattern structure includes a spiral-shaped first metal strip structure, and the second inductor pattern structure includes a spiral-shaped second metal strip structure. The first metal strip structure and the second metal strip structure are connected end to end using the vertical bonding line, and the first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are connected to form a three-dimensional spiral inductor.

[0023] As an optional implementation, the first inductor pattern structure is located inside the substrate or on the upper surface of the substrate. When the first inductor pattern structure is located inside the substrate, the first surface of the substrate exposes the area of ​​the first inductor pattern structure used for bonding vertical bonding lines.

[0024] As an optional implementation, a protective layer is located on the upper surface of the molding layer and the second inductor pattern structure.

[0025] As an optional implementation, the material of the inductive magnetic adhesive layer is silicone magnetic adhesive or epoxy magnetic adhesive.

[0026] As an optional implementation, the height of the inductor is greater than the thickness of the chip structure.

[0027] As an optional implementation, the number of inductors may be one or more, and the number of chip structures may be one or more.

[0028] This invention provides a method for fabricating a chip package structure with integrated inductors, comprising: A substrate is provided, wherein a first surface of the substrate has an inductor region and a chip region, the substrate has a first inductor pattern structure corresponding to the inductor region, and a chip structure is disposed on the surface of the substrate corresponding to the chip region. A molding layer is formed on the first surface of the substrate and the surface of the chip structure. The molding layer has a slot in the inductor region, and the slot exposes the first inductor pattern structure. A vertical bonding line is formed on the surface of the first inductor pattern structure, one end of the vertical bonding line is located on the upper surface of the first inductor pattern structure, and the height of the vertical bonding line is greater than the depth of the slot. The empty slot is filled with an inductive magnetic adhesive layer, and the upper surface of the inductive magnetic adhesive layer exposes the other end of the vertical bonding line. A second inductor pattern structure is formed on the upper surface of the inductor magnetic adhesive layer and the upper surface of the exposed vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are electrically connected and constitute an inductor. The inductor is electrically connected to the chip structure through the substrate.

[0029] As an optional implementation, the first inductor pattern structure is located inside the substrate or on the upper surface of the substrate. When the first inductor pattern structure is located inside the substrate, the first surface of the substrate exposes the area of ​​the first inductor pattern structure used for bonding vertical bonding lines.

[0030] As an optional implementation, it further includes forming a protective layer on the upper surface of the molding layer and the second inductor pattern structure.

[0031] As an optional implementation, the specific steps of filling the empty slot with an inductive magnetic adhesive layer, with the upper surface of the inductive magnetic adhesive layer exposing the other end of the vertical bonding line, are as follows: The cavity is filled with an inductive magnetic adhesive material, the thickness of which is greater than the depth of the cavity. The inductive magnetic adhesive material is ground to form an inductive magnetic adhesive layer, and the upper surface of the inductive magnetic adhesive layer exposes the other end of the vertical bonding line.

[0032] As an optional implementation, the number of inductors may be one or more, and the number of chip structures may be one or more.

[0033] The advantages of the technical solution in this application are: The inductor structure provided in this application includes a substrate, a first surface of the substrate having an inductor region, and the substrate having a first inductor pattern structure corresponding to the inductor region; a molding compound covering the first surface of the substrate, and the molding compound having a slot in the inductor region, the slot exposing the first surface of the substrate; an inductor magnetic adhesive layer filling the slot; a vertical bonding line penetrating the inductor magnetic adhesive layer, one end of the vertical bonding line being located on the upper surface of the first inductor pattern structure, and the other end of the vertical bonding line being located on the upper surface of the inductor magnetic adhesive layer; and a second inductor pattern structure located on the upper surface of the inductor magnetic adhesive layer and the upper surface of the exposed vertical bonding line, wherein the first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are electrically connected and constitute an inductor.

[0034] In this application, the inductor structure is formed within a slot in the molding compound. A vertical planar inductor or a three-dimensional inductor is formed by utilizing the first inductor pattern structure, vertical bonding lines, and second inductor pattern structure of the substrate, and then filling it with an inductor magnetic adhesive layer. Compared with traditional horizontal planar inductors, it is possible to form an inductor with a larger inductance value in a relatively small area. Compared with surface mount inductors, it is not necessary to consider the soldering failure problem of surface mount inductors. Furthermore, surface mount inductors have a larger overall volume due to their inductor shell, but the inductor in this application does not require a shell. The area of ​​the inductor region corresponding to the same inductance value is smaller than that of a surface mount inductor, making it particularly suitable for applications with high inductance performance requirements but limited size.

[0035] In the chip packaging structure with integrated inductor of this application, the inductor and the chip are integrated on the same substrate surface, and the area and height occupied by the inductor are much smaller than those of the surface-mount inductor with the same inductance value. This makes it suitable for more chip packaging scenarios and is beneficial for manufacturing thinner SiP packaging structures.

[0036] Furthermore, the first inductor pattern structure is located inside the substrate or on the upper surface of the substrate. Since it is not necessary to fabricate an additional first inductor pattern structure, the height occupied by the inductor is much smaller than that of the surface mount inductor with the same inductance value, which is beneficial for fabricating a thinner SiP package structure. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0038] Figure 1 This is a schematic diagram of an existing SiP packaging structure; Figures 2-10 This is a schematic diagram illustrating the fabrication process of the chip packaging structure for the integrated inductor according to an embodiment of the present invention. Figures 11-13 These are schematic diagrams of the inductor structure in different embodiments of this application; Figure 14 This is a schematic flowchart illustrating the fabrication method of the chip packaging structure for an integrated inductor according to an embodiment of the present invention. Figures 15-22 This is a schematic diagram of the fabrication process of the inductor structure according to an embodiment of the present invention; Figure 23 This is a schematic flowchart of the method for preparing the inductor structure according to an embodiment of the present invention. Detailed Implementation

[0039] To make the technical problems, technical solutions and beneficial effects to be solved by this application clearer, the following describes this application in further detail with reference to the accompanying drawings and embodiments.

[0040] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects and is not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that such data can be used interchangeably where appropriate.

[0041] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with another component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or point coupling, or they can be in electrical contact or point coupling through an intermediate component.

[0043] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0044] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0045] This application first provides a chip packaging structure for an integrated inductor, please refer to... Figure 10 ,include: The substrate 10 has an inductor region 12 and a chip region 11 on its first surface. The substrate 10 has a first inductor pattern structure 21 corresponding to the inductor region 12, and a chip structure 15 is provided on the surface of the substrate 10 corresponding to the chip region 11. A molding layer 50 covers the first surface of the substrate 10 and the chip structure 15, and the molding layer 50 has a slot in the inductor region 12, the slot exposing the first surface of the substrate 10. An inductive magnetic adhesive layer 40 fills the empty slot; A vertical bonding line 22 runs through the inductive magnetic adhesive layer 40, with one end of the vertical bonding line 22 located on the upper surface of the first inductive pattern structure 21 and the other end of the vertical bonding line 22 exposed on the upper surface of the magnetic adhesive layer 40. The second inductor pattern structure 23 is located on the upper surface of the inductor magnetic adhesive layer 40 and the upper surface of the exposed vertical bonding line 22. The first inductor pattern structure 21, the vertical bonding line 22, and the second inductor pattern structure 23 are electrically connected and constitute an inductor. The inductor is electrically connected to the chip structure 15 through the substrate 10. Electrical connection structure 14 located on the second surface of the substrate 10.

[0046] In this embodiment, the integrated inductor chip packaging structure adopts system-in-package technology to integrate the chip structure and the inductor into one packaging structure. Since the inductor is formed in the empty slot of the molding layer, the empty slot is filled with the inductor magnetic adhesive layer 40. The first inductor pattern structure 21, the vertical bonding line 22, and the second inductor pattern structure 23 are electrically connected to form the inductor. Compared with the traditional horizontal planar inductor, it is possible to form an inductor with a larger inductance value in a relatively small area. Compared with surface mount inductors, there is no need to consider the problem of soldering failure of surface mount inductors. Surface mount inductors have a larger overall volume due to their inductor shell, but the inductor of this application does not need to be made into a shell. The area of ​​the inductor region corresponding to the same inductance value is smaller than that of the surface mount inductor, which is particularly suitable for some application scenarios with high inductor performance requirements but limited size.

[0047] Specifically, the substrate 10 can be one of a ceramic substrate, a silicon substrate, a glass substrate, a PCB substrate, a redistribution substrate, etc. The substrate 10 includes a first surface and an opposing second surface. The first surface of the substrate 10 is used for mounting active and passive devices such as chip structures and inductors. The second surface of the substrate 10 has an electrical connection structure 14 for connecting to other electrical structures. The electrical connection structure of the second surface is electrically connected to the chip structure and inductors on the first surface through internal wiring of the substrate 10. The electrical connection structure 14 can be a solder ball or a solder bump, etc.

[0048] In this embodiment, the first surface of the substrate 10 has an inductor region 12 and a chip region 11. The inductor region 12 is used to form an inductor, and the chip region 11 is used to mount a chip structure.

[0049] The inductor region 12 can be one or more, and the number of corresponding inductors can also be one or more. The chip region 11 can be one or more, and the corresponding chip structure can also be one or more.

[0050] In other embodiments, the first surface of the substrate may also have other active device regions or passive device regions, etc., with the corresponding active device regions encapsulating other active devices and the passive device regions encapsulating other passive devices.

[0051] In other embodiments, it may also include connecting elements, sensors, drivers, or integrated passive elements.

[0052] Specifically, the active devices can be chips (ICs): integrated circuits, transistors, diodes, field-effect transistors (FETs), etc.; passive devices can be resistors, capacitors, inductors, etc.; connecting elements can be pins and connectors, fuses; sensors can be temperature sensors, vibration sensors, etc.; drivers can be motor drivers, etc.; integrated passive components can be integrated capacitors and integrated resistors, etc.

[0053] The molding layer 50 covers the first surface of the substrate 10 and the chip structure 15, and the molding layer 50 has a slot in the inductor region 12, the slot exposing the first surface of the substrate 10, and the slot is filled with an inductor magnetic adhesive layer 40.

[0054] The molding layer 50 can be made of different materials depending on the process. The materials of the molding layer 50 can be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin, etc., and the forming process can be injection molding or transfer molding.

[0055] The inductor magnetic adhesive layer 40 in the empty slot can be an organosilicon magnetic adhesive or an epoxy magnetic adhesive. The magnetic adhesive contains a magnetic conductor (such as ferrite, carbonyl iron powder, etc.) to give the adhesive magnetic properties. This embodiment of the invention adjusts the inductance value of the corresponding inductor by selecting different magnetic adhesives, different empty slot sizes, different first inductor pattern structures, and different second inductor pattern structures. This allows the chip packaging structure to integrate more inductors with different inductance values, without considering the limitations of existing surface-mount inductor values, resulting in greater design flexibility.

[0056] The inductor structure includes a first inductor pattern structure 21, a vertical bonding line 22, and a second inductor pattern structure 23. By utilizing the vertical bonding line 22, the inductor structure can be configured as a vertical planar inductor or a three-dimensional inductor, and the inductance value can be relatively large under the same package area.

[0057] In one embodiment, please refer to Figure 11 The inductor structure includes a first inductor pattern structure 21, a vertical bonding line 22, and a second inductor pattern structure 23. The first inductor pattern structure 21 includes multiple first metal strip structures on the same straight line, and the second inductor pattern structure 23 includes multiple second metal strip structures on the same straight line. The mappings of the straight lines corresponding to the first inductor pattern structure 21 and the straight lines corresponding to the second inductor pattern structure 23 on the first surface of the substrate overlap, and the first and second metal strip structures are arranged in parallel and staggered in the vertical direction. The mappings of the ends of the first and second metal strip structures on the first surface of the substrate overlap. The vertical bonding line 22 connects the ends of the first and second metal strip structures respectively. The first inductor pattern structure 21, the vertical bonding line 22, and the second inductor pattern structure 23 are connected to form a vertically oriented planar S-shaped inductor.

[0058] In this embodiment, the planar S-shaped inductor occupies only the area of ​​a long metal strip on the substrate, but ultimately forms a planar S-shaped inductor with a relatively large inductance value.

[0059] In another embodiment, please refer to Figure 13 The inductor structure includes a first inductor pattern structure 21, vertical bonding lines 22, and a second inductor pattern structure 23. The first inductor pattern structure 21 includes multiple first metal strip structures on multiple parallel straight lines, and the second inductor pattern structure 23 includes multiple second metal strip structures on multiple parallel straight lines and adjacent metal interconnect structures. The first and second metal strip structures are parallel, and there are multiple first metal strip structures and multiple second metal strip structures on each parallel straight line. A first metal strip structure and corresponding second metal strip structures on a straight line are vertically staggered. The ends of the corresponding first and second metal strip structures overlap on the first surface of the substrate. Some of the vertical bonding lines 22 connect the ends of the first and second metal strip structures respectively. The ends of adjacent metal interconnect structures and the outer ends of the outermost first metal strip structures on the two corresponding straight lines overlap on the first surface of the substrate. Some of the vertical bonding lines 22 connect the ends of adjacent metal interconnect structures and the outer ends of the outermost first metal strip structures respectively. The adjacent metal interconnect structures are used to connect the first metal strip structures on different straight lines through the vertical bonding lines 22. The first inductor pattern structure 21, the vertical bonding lines 22, and the second inductor pattern structure 23 are connected to form a vertical planar S-shaped inductor, and are connected to the planar S-shaped inductors of adjacent parallel planes through the adjacent metal interconnect structures to form a three-dimensional S-shaped inductor.

[0060] In other embodiments, the adjacent metal interconnect structure can be formed in the first inductor pattern structure 21, and the adjacent metal interconnect structure can be used to connect the planar S-shaped inductors of adjacent parallel planes to form a three-dimensional S-shaped inductor.

[0061] In another embodiment, please refer to Figure 12 The inductor structure includes a first inductor pattern structure 21, vertical bonding lines 22, and a second inductor pattern structure 23. The first inductor pattern structure 21 includes multiple first metal strip structures on multiple parallel straight lines, and the second inductor pattern structure 23 includes multiple second metal strip structures on multiple parallel straight lines. The number of first metal strip structures and the number of second metal strip structures on each parallel straight line are both one and one, respectively. The mappings of the first metal strip structure and the second metal strip structure on the first surface of the substrate intersect, and the mappings of the ends of the first metal strip structure and the second metal strip structure on the first surface of the substrate overlap. The vertical bonding line 22 connects the ends of the first metal strip structure and the ends of the second metal strip structure respectively. The first metal strip structure and the second metal strip structure are connected end to end by the vertical bonding line. The first inductor pattern structure 21, the vertical bonding line 22, and the second inductor pattern structure 23 are connected to form a spiral three-dimensional S-shaped inductor.

[0062] In this embodiment, a spiral three-dimensional S-shaped inductor is formed by connecting the first inductor pattern structure 21, the vertical bonding line 22, and the second inductor pattern structure 23. Compared with the traditional planar inductor in the horizontal direction, an inductor with a larger inductance value can be formed in a relatively small area.

[0063] In another embodiment, the inductor structure includes a first inductor pattern structure, a vertical bonding line, and a second inductor pattern structure. The first inductor pattern structure includes a spiral first metal strip structure, and the second inductor pattern structure includes a spiral second metal strip structure. The first metal strip structure and the second metal strip structure are connected end to end by the vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are connected to form a three-dimensional spiral inductor.

[0064] The first inductor pattern structure 21 and the second inductor pattern structure 23 are metal interconnect patterns, such as copper interconnect patterns, aluminum interconnect patterns, etc. In other embodiments, they can also be other interconnect patterns that can achieve conductivity.

[0065] The vertical bonding line 22 is a vertical bonding line formed using a vertical bonding line process. The vertical bonding line is made of gold wire, silver wire, copper wire, silver alloy wire, etc., and the vertical bonding line is almost perpendicular to the substrate.

[0066] One end of the vertical bonding line 22 is located on the upper surface of the first inductor pattern structure 21, and the other end of the vertical bonding line 22 is exposed on the upper surface of the magnetic adhesive layer 40 and connected to the second inductor pattern structure 23.

[0067] Since the inductor of this application is integrated in the empty slot of the molding layer, compared with the traditional horizontal planar inductor, the packaging structure of this application can form an inductor with a large inductance value in a relatively small area. Compared with surface mount inductors, the packaging structure of this application does not need to consider the problem of soldering failure of surface mount inductors. Surface mount inductors have a larger overall volume due to the inductor shell, but the inductor of this application does not need to make a shell and is directly filled with magnetic adhesive. The area of ​​the inductor region corresponding to the same inductance value is smaller than that of surface mount inductors, which is particularly suitable for some application scenarios with high inductance performance requirements but limited size.

[0068] In the chip packaging structure with integrated inductor of this application, the inductor and the chip are integrated on the same substrate surface, and the area and height occupied by the inductor are much smaller than those of the surface-mount inductor with the same inductance value. This makes it suitable for more chip packaging scenarios and is beneficial for manufacturing thinner SiP packaging structures.

[0069] When the first inductor pattern structure is located inside the substrate or on the upper surface of the substrate, since there is no need to make an additional first inductor pattern structure, the height occupied by the inductor will be much smaller than that of the surface mount inductor with the same inductance value, which is beneficial for making a thinner SiP package structure.

[0070] In this embodiment of the invention, the chip structure 15 is a single chip, a stacked chip structure, or a chip package structure, and the chip structure 15 is electrically connected to an inductor through a substrate.

[0071] The chips may include power chips, logic chips, memory chips, AI chips, etc. In some embodiments, the logic chip may include gate arrays, cell substrate arrays, embedded arrays, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), central processing units (CPUs), microprocessor units (MPUs), microcontroller units (MCUs), integrated circuits (ICs), application processors (APs), display driver ICs (DDIs), radio frequency (RF) chips, power supply chips, or complementary metal-oxide-semiconductor (CMOS) image sensors. In some embodiments, the memory chip may include volatile memory chips (such as dynamic random access memory (DRAM) or static RAM (SRAM)) or non-volatile memory chips (such as flash memory (Flash), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (ReRAM)). In one specific embodiment, the memory chip may include high-bandwidth memory (HBM) containing DRAM chips. In one specific embodiment, the AI ​​chip may include GPU chips, application-specific integrated circuits (ASICs) specifically for AI processing, etc.

[0072] In this embodiment, the height of the inductor is greater than the thickness of the chip structure, meaning the molding compound completely covers the surface of the chip structure. In other embodiments, the thickness of the chip structure may be flush with the molding compound.

[0073] Please refer to Figure 10 In order to protect the second inductor pattern structure 23 on the surface of the molding compound 50, the surface of the molding compound 50 is also provided with a protective layer 60. The material of the protective layer 60 is molding compound or dielectric layer, etc., so as to avoid the exposure of the second inductor pattern structure 23.

[0074] In other embodiments, other encapsulation structures may also be formed on the upper surface of the molding layer, such as a second chip encapsulation structure and a second molding layer.

[0075] In other embodiments, the upper surface of the molding layer may not have any other structures formed therein.

[0076] This invention also provides a method for fabricating a chip packaging structure with integrated inductors; please refer to [link / reference]. Figure 14 ,include: Step S10: Provide a substrate, the first surface of the substrate having an inductor region and a chip region, the substrate having a first inductor pattern structure corresponding to the inductor region, and the surface of the substrate corresponding to the chip region having a chip structure. Step S20: A molding layer is formed on the first surface of the substrate and the surface of the chip structure. The molding layer has a slot in the inductor region, and the slot exposes the first inductor pattern structure. Step S30: A vertical bonding line is formed on the surface of the first inductor pattern structure. One end of the vertical bonding line is located on the upper surface of the first inductor pattern structure, and the height of the vertical bonding line is greater than the depth of the slot. Step S40: The empty slot is filled with an inductive magnetic adhesive layer, and the upper surface of the inductive magnetic adhesive layer exposes the other end of the vertical bonding line. In step S50, a second inductor pattern structure is formed on the upper surface of the inductor magnetic adhesive layer and the upper surface of the exposed vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are electrically connected and constitute an inductor. The inductor is electrically connected to the chip structure through the substrate.

[0077] For details, please refer to Figure 2 and Figure 3 A substrate 10 is provided, wherein a first surface of the substrate 10 has an inductor region 12 and a chip region 11, the substrate 10 has a first inductor pattern structure 21 corresponding to the inductor region 12, and a chip structure 15 is provided on the surface of the substrate 10 corresponding to the chip region 11.

[0078] In some embodiments, the substrate 10 has a first inductance pattern structure 21 corresponding to the inductance region 12, and the first inductance pattern structure 21 is located inside the substrate 10 or on the upper surface of the substrate.

[0079] When the first inductor pattern structure 21 is located inside the substrate 10, the first surface of the substrate 10 exposes the area of ​​the first inductor pattern structure 21 for bonding vertical bonding lines.

[0080] Please refer to Figure 4 A molding compound 50 is formed on the first surface of the substrate 10 and the surface of the chip structure 15. The molding compound 50 has a slot 45 in the inductor region 12, and the slot 45 exposes the first surface of the substrate 10.

[0081] Please refer to Figure 5 A vertical bonding line 22 is formed on the surface of the first inductor pattern structure 21. One end of the vertical bonding line 22 is located on the upper surface of the first inductor pattern structure 21, and the height of the vertical bonding line 22 is greater than the depth of the slot 45.

[0082] The vertical bonding line 22 is a vertical bonding line formed using a vertical bonding line process. The vertical bonding line is made of gold wire, silver wire, copper wire, bonding silver alloy wire, etc., and the vertical bonding line is almost perpendicular to the substrate.

[0083] Please refer to Figure 6 , Figure 7 The empty slot 45 is filled with an inductive magnetic adhesive layer 40, and the upper surface of the inductive magnetic adhesive layer 40 exposes the other end of the vertical bonding line 22.

[0084] Specifically, the steps for filling the empty slot with an inductive magnetic adhesive layer, with the upper surface of the inductive magnetic adhesive layer exposing the other end of the vertical bonding line, are as follows: The cavity 45 is filled with an inductive magnetic adhesive material, the thickness of which is greater than the depth of the cavity 45. The inductive magnetic adhesive material is ground to form an inductive magnetic adhesive layer 40, the upper surface of which exposes the other end of the vertical bonding line 22.

[0085] Please refer to Figure 8 A second inductor pattern structure 23 is formed on the upper surface of the inductor magnetic adhesive layer 40 and the upper surface of the exposed vertical bonding line 22. The first inductor pattern structure 21, the vertical bonding line 22, and the second inductor pattern structure 23 are electrically connected and constitute an inductor. The inductor is electrically connected to the chip structure through the substrate.

[0086] The method for forming the second inductor pattern structure is a sputtering process.

[0087] Please refer to Figure 9 A protective layer 60 is formed on the upper surface of the molding layer 50 and the surface of the second inductor pattern structure 23.

[0088] The protective layer 60 is made of molding compound or dielectric layer, etc., so as to avoid the exposure of the second inductor pattern structure 23.

[0089] In other embodiments, other encapsulation structures may also be formed on the upper surface of the molding layer, such as a second chip encapsulation structure and a second molding layer.

[0090] In other embodiments, the upper surface of the molding layer may not have any other structures formed therein.

[0091] Please refer to Figure 10 An electrical connection structure 14 is formed on the second surface of the substrate 10.

[0092] This application first provides an inductor structure, please refer to... Figure 22 ,include: Substrate 110, the first surface of the substrate has an inductor region, and the substrate 110 has a first inductor pattern structure 121 corresponding to the inductor region; A molding layer 150 covers the first surface of the substrate 110, and the molding layer 150 has a slot that exposes the first inductor pattern structure 121. An inductive magnetic adhesive layer 140 fills the empty slot; A vertical bonding line 122 runs through the inductive magnetic adhesive layer 140, with one end of the vertical bonding line 122 located on the upper surface of the first inductive pattern structure 121, and the other end of the vertical bonding line 122 exposed on the upper surface of the magnetic adhesive layer 140. The second inductor pattern structure 123 is located on the upper surface of the inductor magnetic adhesive layer 140 and the upper surface of the exposed vertical bonding line 122. The first inductor pattern structure 121, the vertical bonding line 122, and the second inductor pattern structure 123 are electrically connected and constitute an inductor. Electrical connection structure 114 located on the second surface of the substrate 110.

[0093] In this embodiment, the inductor is formed in a slot in the molding layer, and the slot is filled with an inductor magnetic adhesive layer 140. The first inductor pattern structure 121, the vertical bonding line 122, and the second inductor pattern structure 123 are electrically connected to form the inductor. Compared with traditional planar inductors in the horizontal direction, it is possible to form an inductor with a larger inductance value in a relatively small area. Compared with surface-mount inductors, it is not necessary to consider the problem of soldering failure of surface-mount inductors. Surface-mount inductors have a larger overall volume due to their inductor shell, but the inductor in this application does not require a shell. The area of ​​the inductor region corresponding to the same inductance value is smaller than that of surface-mount inductors, and the inductance value can be arbitrarily adjusted. It is particularly suitable for some application scenarios with high requirements for inductor performance but limited size, or application scenarios that require some special inductance values.

[0094] Specifically, the substrate 110 can be one of a ceramic substrate, silicon substrate, glass substrate, PCB substrate, redistribution substrate, etc. The substrate 110 includes a first surface and an opposing second surface. The first surface of the substrate 110 is used to encapsulate an inductor, and the second surface of the substrate 110 has an electrical connection structure 114 for connection with other electrical structures. The electrical connection structure of the second surface is electrically connected to the inductor on the first surface. The electrical connection structure 114 can be a solder ball or a solder bump, etc.

[0095] In other embodiments, the first surface of the substrate may also have other active device regions or passive device regions, etc., with the corresponding active device regions encapsulating other active devices and the passive device regions encapsulating other passive devices.

[0096] The molding layer 150 covers the first surface of the substrate 110, and the molding layer 150 has a slot that exposes the first inductor pattern structure 121. The slot is filled with an inductor magnetic adhesive layer 140.

[0097] The molding layer 150 can be made of different molding layer materials depending on the process. The material of the molding layer 150 can be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin, etc., and the forming process can be injection molding or transfer molding.

[0098] The inductor magnetic adhesive layer 140 filling the empty slot can be an organosilicon magnetic adhesive or an epoxy magnetic adhesive. The magnetic adhesive contains a magnetic conductor (such as ferrite, carbonyl iron powder, etc.) to give the adhesive magnetic properties. In this embodiment of the invention, by selecting different magnetic adhesives, different empty slot sizes, different first inductor pattern structures, and different second inductor pattern structures, the inductance value of the corresponding inductor can be adjusted. This allows the inductor structure to fabricate inductors with more different inductance values, without considering the limitations of existing surface-mount inductor values, thus providing greater design flexibility.

[0099] The inductor structure includes a first inductor pattern structure 121, a vertical bonding line 122, and a second inductor pattern structure 123. By utilizing the vertical bonding line 122, the inductor structure can be configured as a vertical planar inductor or a three-dimensional inductor, and the inductance value of the inductor can be relatively large under the same package area.

[0100] In one embodiment, the inductor structure includes a first inductor pattern structure, a vertical bonding line, and a second inductor pattern structure. The first inductor pattern structure includes multiple first metal strip structures on the same straight line, and the second inductor pattern structure includes multiple second metal strip structures on the same straight line. The mappings of the straight lines corresponding to the first inductor pattern structure and the straight lines corresponding to the second inductor pattern structure on the first surface of the substrate overlap, and the first and second metal strip structures are arranged in parallel and staggered in the vertical direction. The mappings of the ends of the first and second metal strip structures on the first surface of the substrate overlap. The vertical bonding line connects the ends of the first and second metal strip structures respectively. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are connected to form a vertically oriented planar S-shaped inductor.

[0101] In this embodiment, the planar S-shaped inductor occupies only the area of ​​a long metal strip on the substrate, but ultimately forms a planar S-shaped inductor with a relatively large inductance value.

[0102] In another embodiment, the inductor structure includes a first inductor pattern structure, vertical bonding lines, and a second inductor pattern structure. The first inductor pattern structure includes multiple first metal strip structures on multiple parallel straight lines, and the second inductor pattern structure includes multiple second metal strip structures on multiple parallel straight lines and adjacent metal interconnect structures. The first and second metal strip structures are parallel, and there are multiple first metal strip structures and multiple second metal strip structures on each parallel straight line. A first metal strip structure and corresponding second metal strip structures on a straight line are vertically staggered. The ends of the corresponding first and second metal strip structures overlap on the first surface of the substrate. Some of the vertical bonding lines connect the ends of the first and second metal strip structures respectively. The ends of adjacent metal interconnect structures and the outer ends of the outermost first metal strip structures on the two corresponding straight lines overlap on the first surface of the substrate. Some of the vertical bonding lines connect the ends of adjacent metal interconnect structures and the outer ends of the outermost first metal strip structures respectively. The adjacent metal interconnect structures are used to connect the first metal strip structures on different straight lines through the vertical bonding lines. The first inductor pattern structure, the vertical bonding lines, and the second inductor pattern structure are connected to form a vertical planar S-shaped inductor. The planar S-shaped inductors are connected to adjacent parallel planes through the adjacent metal interconnect structures to form a three-dimensional S-shaped inductor.

[0103] In other embodiments, the adjacent metal interconnect structure can be formed in the first inductor pattern structure, and the adjacent metal interconnect structure can be used to connect the planar S-shaped inductors of adjacent parallel planes to form a three-dimensional S-shaped inductor.

[0104] In another embodiment, the inductor structure includes a first inductor pattern structure, vertical bonding lines, and a second inductor pattern structure. The first inductor pattern structure includes multiple first metal strip structures on multiple parallel straight lines, and the second inductor pattern structure includes multiple second metal strip structures on multiple parallel straight lines. The number of first metal strip structures and the number of second metal strip structures on each parallel straight line are both one and one, respectively. The mappings of the first metal strip structure and the second metal strip structure on the first surface of the substrate intersect, and the mappings of the ends of the first metal strip structure and the second metal strip structure on the first surface of the substrate overlap. The vertical bonding lines connect the ends of the first metal strip structure and the ends of the second metal strip structure respectively. The first metal strip structure and the second metal strip structure are connected end to end by the vertical bonding lines. The first inductor pattern structure, the vertical bonding lines, and the second inductor pattern structure are connected to form a spiral three-dimensional S-shaped inductor.

[0105] This embodiment utilizes a first inductor pattern structure, a vertical bonding line, and a second inductor pattern structure to form a spiral three-dimensional S-shaped inductor. Compared with traditional horizontal planar inductors, it can form an inductor with a larger inductance value in a relatively small area.

[0106] In another embodiment, the inductor structure includes a first inductor pattern structure, a vertical bonding line, and a second inductor pattern structure. The first inductor pattern structure includes a spiral first metal strip structure, and the second inductor pattern structure includes a spiral second metal strip structure. The first metal strip structure and the second metal strip structure are connected end to end by the vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are connected to form a three-dimensional spiral inductor.

[0107] The first inductor pattern structure 121 and the second inductor pattern structure 123 are metal interconnect patterns, such as copper interconnect patterns, aluminum interconnect patterns, etc. In other embodiments, they can also be other interconnect patterns that can achieve conductivity.

[0108] The vertical bonding line 122 is a vertical bonding line formed using a vertical bonding line process. The vertical bonding line is made of gold wire, silver wire, copper wire, silver alloy wire, etc., and the vertical bonding line is almost perpendicular to the substrate.

[0109] One end of the vertical bonding line 122 is located on the upper surface of the first inductor pattern structure 121, and the other end of the vertical bonding line 122 is exposed on the upper surface of the magnetic adhesive layer 140 and connected to the second inductor pattern structure 123.

[0110] Because the inductor in this application is integrated into the slot of the molding compound, compared with the traditional horizontal planar inductor, the packaging structure of this application can form an inductor with a larger inductance value in a relatively small area. Compared with surface-mount inductors, the packaging structure of this application does not need to consider the soldering failure problem of surface-mount inductors. Surface-mount inductors have a larger overall volume due to their inductor shell, but the inductor in this application does not need to make a shell and is directly filled with magnetic adhesive. The area of ​​the inductor region corresponding to the same inductance value is smaller than that of surface-mount inductors. This is particularly suitable for some application scenarios with high inductance performance requirements but limited size. In addition, the inductor structure can produce more inductors with different inductance values ​​without considering the limitations of existing surface-mount inductor inductance values, resulting in greater design flexibility.

[0111] When the first inductor pattern structure is located inside the substrate or on the upper surface of the substrate, since there is no need to make an additional first inductor pattern structure, the height occupied by the inductor will be much smaller than that of the surface-mount inductor with the same inductance value, which is beneficial for making a thinner inductor structure.

[0112] Please refer to Figure 22In order to protect the second inductor pattern structure 123 on the upper surface of the molding compound 150, the upper surface of the molding compound 150 also has a protective layer 160. The material of the protective layer 160 is molding compound or dielectric layer, etc., so as to avoid the exposure of the second inductor pattern structure 123.

[0113] In other embodiments, the upper surface of the molding layer may also have other encapsulation structures formed thereon.

[0114] In other embodiments, the upper surface of the molding layer may not have any other structures formed therein.

[0115] This invention also provides a method for fabricating an inductor structure; please refer to [the relevant documentation]. Figure 23 ,include: Step S110: Provide a substrate, wherein a first surface of the substrate has an inductor region, and the substrate has a first inductor pattern structure corresponding to the inductor region; Step S120: A molding layer is formed on the first surface of the substrate. The molding layer has a slot in the inductor region, and the slot exposes the first inductor pattern structure. Step S130: A vertical bonding line is formed on the upper surface of the first inductor pattern structure. One end of the vertical bonding line is located on the upper surface of the first inductor pattern structure, and the height of the vertical bonding line is greater than the depth of the slot. Step S140: The empty slot is filled with an inductive magnetic adhesive layer, and the upper surface of the inductive magnetic adhesive layer exposes the other end of the vertical bonding line. In step S150, a second inductor pattern structure is formed on the upper surface of the inductor magnetic adhesive layer and the upper surface of the exposed vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are electrically connected and constitute an inductor.

[0116] For details, please refer to Figure 15 A substrate 110 is provided, the first surface of the substrate has an inductive region, and the substrate 110 has a first inductive pattern structure 121 corresponding to the inductive region.

[0117] In some embodiments, the first inductor pattern structure 121 is located inside the substrate 110 or on the upper surface of the substrate 110.

[0118] When the first inductor pattern structure 121 is located inside the substrate 110, the first surface of the substrate 110 exposes the area of ​​the first inductor pattern structure 121 for bonding vertical bonding lines.

[0119] Please refer to Figure 16A molding layer 150 is formed on the first surface of the substrate 110. The molding layer 150 has a slot 145 that exposes a first inductance pattern structure 121 on the first surface of the substrate 110.

[0120] Please refer to Figure 17 A vertical bonding line 122 is formed on the upper surface of the first inductor pattern structure 121. One end of the vertical bonding line 122 is located on the upper surface of the first inductor pattern structure 121, and the height of the vertical bonding line 122 is greater than the depth of the slot 145.

[0121] The vertical bonding line 122 is a vertical bonding line formed using a vertical bonding line process. The vertical bonding line is made of gold wire, silver wire, copper wire, silver alloy wire, etc., and the vertical bonding line is almost perpendicular to the substrate.

[0122] Please refer to Figure 18 , Figure 19 The empty slot 145 is filled with an inductive magnetic adhesive layer 140, and the upper surface of the inductive magnetic adhesive layer 140 exposes the other end of the vertical bonding line 122.

[0123] Specifically, the steps for filling the empty slot with an inductive magnetic adhesive layer, with the upper surface of the inductive magnetic adhesive layer exposing the other end of the vertical bonding line, are as follows: The cavity 145 is filled with an inductive magnetic adhesive material, the thickness of which is greater than the depth of the cavity 145. The inductive magnetic adhesive material is ground to form an inductive magnetic adhesive layer 140, the upper surface of which exposes the other end of the vertical bonding line 122.

[0124] Please refer to Figure 20 A second inductor pattern structure 123 is formed on the upper surface of the inductor magnetic adhesive layer 140 and the upper surface of the exposed vertical bonding line 122. The first inductor pattern structure 121, the vertical bonding line 122, and the second inductor pattern structure 123 are electrically connected and constitute an inductor.

[0125] The method for forming the second inductor pattern structure is a sputtering process.

[0126] Please refer to Figure 21 A protective layer 160 is formed on the upper surface of the molding layer 150 and the surface of the second inductor pattern structure 123.

[0127] The protective layer 160 is made of molding compound or dielectric layer, etc., so as to avoid the exposure of the second inductor pattern structure 123.

[0128] In other embodiments, the upper surface of the molding layer may also have other encapsulation structures formed thereon.

[0129] In other embodiments, the upper surface of the molding layer may not have any other structures formed therein.

[0130] Please refer to Figure 22 An electrical connection structure 114 is formed on the second surface of the substrate 110.

[0131] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0132] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. An inductor structure, characterized in that, include: A substrate, wherein a first surface of the substrate has an inductive region, and the substrate has a first inductive pattern structure corresponding to the inductive region; A molding layer covering the first surface of the substrate, wherein the molding layer has a slot that exposes the first inductor pattern structure; An inductive magnetic adhesive layer that fills the empty slot; A vertical bonding line runs through the inductor magnetic adhesive layer, one end of which is located on the upper surface of the first inductor pattern structure, and the other end of which is exposed on the upper surface of the inductor magnetic adhesive layer. A second inductor pattern structure is located on the upper surface of the inductor magnetic adhesive layer and the upper surface of the exposed vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are electrically connected and constitute an inductor.

2. The inductor structure as described in claim 1, characterized in that, The first inductor pattern structure includes multiple first metal strip structures on the same straight line, and the second inductor pattern structure includes multiple second metal strip structures on the same straight line. The first metal strip structures and the second metal strip structures are arranged in parallel and staggered in the vertical direction. The ends of the first metal strip structures and the second metal strip structures overlap on the first surface of the substrate. The vertical bonding lines connect the ends of the first metal strip structures and the ends of the second metal strip structures respectively. The first inductor pattern structure, the vertical bonding lines, and the second inductor pattern structure are connected to form a planar S-shaped inductor.

3. An inductor structure as described in claim 1, characterized in that, The first inductor pattern structure includes multiple first metal strip structures on multiple parallel straight lines, and the second inductor pattern structure includes multiple second metal strip structures on multiple parallel straight lines and adjacent metal interconnect structures. The first and second metal strip structures are parallel, and there are multiple first metal strip structures and multiple second metal strip structures on each parallel straight line. The first metal strip structure and the corresponding second metal strip structures on a straight line are vertically staggered. The ends of the corresponding first metal strip structures and second metal strip structures overlap on the first surface of the substrate. A portion of the vertical bonding lines connect the ends of the first metal strip structures and the ends of the second metal strip structures respectively. The ends of the adjacent metal interconnect structures and the outer ends of the first metal strip structures located at the outermost edge on the two corresponding straight lines overlap on the first surface of the substrate. A portion of the vertical bonding lines connect the ends of the adjacent metal interconnect structures and the outer ends of the first metal strip structures at the outermost edge respectively. The adjacent metal interconnect structures are used to connect the first metal strip structures on different straight lines through the vertical bonding lines. The first inductor pattern structure, the vertical bonding lines, and the second inductor pattern structure are connected to form a vertical planar S-shaped inductor. The adjacent metal interconnect structures are connected to the planar S-shaped inductors of adjacent parallel planes to form a three-dimensional S-shaped inductor.

4. An inductor structure as described in claim 1, characterized in that, The first inductor pattern structure includes multiple first metal strip structures on multiple parallel straight lines, and the second inductor pattern structure includes multiple second metal strip structures on multiple parallel straight lines, wherein there is one first metal strip structure and one second metal strip structure on each parallel straight line. The mappings of the first metal strip structure and the second metal strip structure on the first surface of the substrate intersect, and the mappings of the ends of the first metal strip structure and the second metal strip structure on the first surface of the substrate overlap. The vertical bonding line connects the ends of the first metal strip structure and the ends of the second metal strip structure respectively. The first metal strip structure and the second metal strip structure are connected end to end by the vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are connected to form a spiral three-dimensional S-shaped inductor.

5. An inductor structure as described in claim 1, characterized in that, The first inductor pattern structure includes a spiral-shaped first metal strip structure, and the second inductor pattern structure includes a spiral-shaped second metal strip structure. The first metal strip structure and the second metal strip structure are connected end to end using the vertical bonding line, and the first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are connected to form a three-dimensional spiral inductor.

6. An inductor structure as described in claim 1, characterized in that, The first inductor pattern structure is located inside the substrate or on the upper surface of the substrate. When the first inductor pattern structure is located inside the substrate, the first surface of the substrate exposes the area of ​​the first inductor pattern structure used for bonding vertical bonding lines.

7. An inductor structure as described in claim 1, characterized in that, Also includes: A protective layer located on the upper surface of the molding layer and the second inductor pattern structure.

8. An inductor structure as described in claim 1, characterized in that, The material of the inductive magnetic adhesive layer is silicone magnetic adhesive or epoxy magnetic adhesive.

9. A method for fabricating an inductor structure, characterized in that, include: A substrate is provided, wherein a first surface of the substrate has an inductive region, and the substrate has a first inductive pattern structure corresponding to the inductive region; A molding layer is formed on the first surface of the substrate, the molding layer having a slot in the inductor region, the slot exposing the first inductor pattern structure; A vertical bonding line is formed on the upper surface of the first inductor pattern structure, one end of the vertical bonding line is located on the upper surface of the first inductor pattern structure, and the height of the vertical bonding line is greater than the depth of the slot. The empty slot is filled with an inductive magnetic adhesive layer, and the upper surface of the inductive magnetic adhesive layer exposes the other end of the vertical bonding line. A second inductor pattern structure is formed on the upper surface of the inductor magnetic adhesive layer and the upper surface of the exposed vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are electrically connected and constitute an inductor.

10. The method for preparing an inductor structure as described in claim 9, characterized in that, The first inductor pattern structure is located inside the substrate or on the upper surface of the substrate. When the first inductor pattern structure is located inside the substrate, the first surface of the substrate exposes the area of ​​the first inductor pattern structure used for bonding vertical bonding lines.

11. The method for preparing an inductor structure as described in claim 9, characterized in that, Also includes: A protective layer is formed on the surface of the molding layer and the second inductor pattern structure.

12. The method for preparing an inductor structure as described in claim 9, characterized in that, The specific steps for filling the empty slot with an inductive magnetic adhesive layer, with the upper surface of the inductive magnetic adhesive layer exposing the other end of the vertical bonding line, are as follows: The cavity is filled with an inductive magnetic adhesive material, the thickness of which is greater than the depth of the cavity. The inductive magnetic adhesive material is ground to form an inductive magnetic adhesive layer, and the upper surface of the inductive magnetic adhesive layer exposes the other end of the vertical bonding line.

13. A chip package structure for an integrated inductor, characterized in that, include: A substrate, wherein a first surface of the substrate has an inductor region and a chip region, the substrate has a first inductor pattern structure corresponding to the inductor region, and a chip structure is disposed on the surface of the substrate corresponding to the chip region. A molding compound covering the first surface of the substrate and the chip structure, wherein the molding compound has a slot in the inductor region, the slot exposing the first surface of the substrate; An inductive magnetic adhesive layer that fills the empty slot; A vertical bonding line runs through the inductor magnetic adhesive layer, one end of which is located on the upper surface of the first inductor pattern structure, and the other end of which is exposed on the upper surface of the inductor magnetic adhesive layer. A second inductor pattern structure is located on the upper surface of the inductor magnetic adhesive layer and the upper surface of the exposed vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are electrically connected and constitute an inductor. The inductor is electrically connected to the chip structure through the substrate.

14. The chip packaging structure for an integrated inductor as described in claim 13, characterized in that, The first inductor pattern structure includes multiple first metal strip structures on the same straight line, and the second inductor pattern structure includes multiple second metal strip structures on the same straight line. The first metal strip structures and the second metal strip structures are arranged in parallel and staggered in the vertical direction. The ends of the first metal strip structures and the second metal strip structures are mapped on the first surface of the substrate with overlapping vertical bonding lines that connect the ends of the first metal strip structures and the ends of the second metal strip structures respectively. The first inductor pattern structure, the vertical bonding lines, and the second inductor pattern structure are connected to form a planar S-shaped inductor.

15. The chip packaging structure for an integrated inductor as described in claim 13, characterized in that, The first inductor pattern structure includes multiple first metal strip structures on multiple parallel straight lines, and the second inductor pattern structure includes multiple second metal strip structures on multiple parallel straight lines and adjacent metal interconnect structures. The first and second metal strip structures are parallel, and there are multiple first metal strip structures and multiple second metal strip structures on each parallel straight line. The first metal strip structure and the corresponding second metal strip structures on a straight line are vertically staggered. The ends of the corresponding first metal strip structures and second metal strip structures overlap on the first surface of the substrate. A portion of the vertical bonding lines connect the ends of the first metal strip structures and the ends of the second metal strip structures respectively. The ends of the adjacent metal interconnect structures and the outer ends of the first metal strip structures located at the outermost edge on the two corresponding straight lines overlap on the first surface of the substrate. A portion of the vertical bonding lines connect the ends of the adjacent metal interconnect structures and the outer ends of the first metal strip structures at the outermost edge respectively. The adjacent metal interconnect structures are used to connect the first metal strip structures on different straight lines through the vertical bonding lines. The first inductor pattern structure, the vertical bonding lines, and the second inductor pattern structure are connected to form a vertical planar S-shaped inductor. The adjacent metal interconnect structures are connected to the planar S-shaped inductors of adjacent parallel planes to form a three-dimensional S-shaped inductor.

16. The chip packaging structure for an integrated inductor as described in claim 13, characterized in that, The first inductor pattern structure includes multiple first metal strip structures on multiple parallel straight lines, and the second inductor pattern structure includes multiple second metal strip structures on multiple parallel straight lines, wherein there is one first metal strip structure and one second metal strip structure on each parallel straight line. The mappings of the first metal strip structure and the second metal strip structure on the first surface of the substrate intersect, and the mappings of the ends of the first metal strip structure and the second metal strip structure on the first surface of the substrate overlap. The vertical bonding line connects the ends of the first metal strip structure and the ends of the second metal strip structure respectively. The first metal strip structure and the second metal strip structure are connected end to end by the vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are connected to form a spiral three-dimensional S-shaped inductor.

17. The chip packaging structure for an integrated inductor as described in claim 13, characterized in that, The first inductor pattern structure includes a spiral-shaped first metal strip structure, and the second inductor pattern structure includes a spiral-shaped second metal strip structure. The first metal strip structure and the second metal strip structure are connected end to end using the vertical bonding line, and the first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are connected to form a three-dimensional spiral inductor.

18. The chip packaging structure for an integrated inductor as described in claim 13, characterized in that, The first inductor pattern structure is located inside the substrate or on the upper surface of the substrate. When the first inductor pattern structure is located inside the substrate, the first surface of the substrate exposes the area of ​​the first inductor pattern structure used for bonding vertical bonding lines.

19. The chip packaging structure for an integrated inductor as described in claim 13, characterized in that, A protective layer located on the upper surface of the molding layer and the second inductor pattern structure.

20. The chip packaging structure for an integrated inductor as described in claim 13, characterized in that, The material of the inductive magnetic adhesive layer is silicone magnetic adhesive or epoxy magnetic adhesive.

21. The chip packaging structure for an integrated inductor as described in claim 13, characterized in that, The height of the inductor is greater than the thickness of the chip structure.

22. The chip packaging structure for an integrated inductor as described in claim 13, characterized in that, The number of inductors is one or more, and the number of chip structures is one or more.

23. A method for fabricating a chip package structure with integrated inductors, characterized in that, include: A substrate is provided, wherein a first surface of the substrate has an inductor region and a chip region, the substrate has a first inductor pattern structure corresponding to the inductor region, and a chip structure is disposed on the surface of the substrate corresponding to the chip region. A molding layer is formed on the first surface of the substrate and the surface of the chip structure. The molding layer has a slot in the inductor region, and the slot exposes the first inductor pattern structure. A vertical bonding line is formed on the surface of the first inductor pattern structure, one end of the vertical bonding line is located on the upper surface of the first inductor pattern structure, and the height of the vertical bonding line is greater than the depth of the slot. The empty slot is filled with an inductive magnetic adhesive layer, and the upper surface of the inductive magnetic adhesive layer exposes the other end of the vertical bonding line. A second inductor pattern structure is formed on the upper surface of the inductor magnetic adhesive layer and the upper surface of the exposed vertical bonding line. The first inductor pattern structure, the vertical bonding line, and the second inductor pattern structure are electrically connected and constitute an inductor. The inductor is electrically connected to the chip structure through the substrate.

24. The method for fabricating a chip package structure with an integrated inductor as described in claim 23, characterized in that, The first inductor pattern structure is located inside the substrate or on the upper surface of the substrate. When the first inductor pattern structure is located inside the substrate, the first surface of the substrate exposes the area of ​​the first inductor pattern structure used for bonding vertical bonding lines.

25. The method for fabricating a chip package structure with an integrated inductor as described in claim 23, characterized in that, Also includes: A protective layer is formed on the surface of the molding layer and the second inductor pattern structure.

26. The method for fabricating a chip package structure with an integrated inductor as described in claim 23, characterized in that, The specific steps for filling the empty slot with an inductive magnetic adhesive layer, with the upper surface of the inductive magnetic adhesive layer exposing the other end of the vertical bonding line, are as follows: The cavity is filled with an inductive magnetic adhesive material, the thickness of which is greater than the depth of the cavity. The inductive magnetic adhesive material is ground to form an inductive magnetic adhesive layer, and the upper surface of the inductive magnetic adhesive layer exposes the other end of the vertical bonding line.

27. The method for fabricating a chip package structure with an integrated inductor as described in claim 23, characterized in that, The number of inductors is one or more, and the number of chip structures is one or more.

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