Gallium arsenide-based heterojunction bipolar transistor and preparation method thereof

Abstract

The invention belongs to the field of semiconductor devices, and particularly discloses a gallium arsenide-based heterojunction bipolar transistor and a preparation method thereof. The GaAs-based HBT device disclosed by the invention adopts an inverted structure, and the semiconductor substrate in the processing technology is used as a conductive N-type semiconductor layer to participate in the conduction of the device; according to the technical scheme of the invention, the parasitic capacitance between the P-type GaAs base and the N-type InGaP layer of the GaAs-based HBT device is small, the contact resistance between the topmost layer in the collector region and the electrode of the collector region can be effectively reduced, the physical isolation between the adjacent GaAs-based HBT devices can be realized by etching the mesa so as to improve the isolation effect, the heat dissipation effect of the emitter region is good, and the service life of the emitter region is prolonged. And a traditional substrate through hole process is not needed, so that the process cost is saved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, specifically to a gallium arsenide-based heterojunction bipolar transistor and its fabrication method. Background Technology

[0002] The epitaxial structure of most commercially available GaAs-based heterojunction bipolar transistors (HBTs) involves the following process steps: epitaxial layers are grown incrementally on the front side of a GaAs semi-insulating wafer substrate, followed by etching, electrode fabrication, ion implantation to isolate the epitaxial layer, and the creation of vias on the substrate. These vias then connect to external electrodes located on the back side of the substrate for electrical connection. The epitaxial layers are in a positive orientation, consisting of an emitter, base, and collector layer from top to bottom. In this design, the top emitter layer has poor heat dissipation, requiring a thicker metal layer for cooling, resulting in high manufacturing costs. Furthermore, the parasitic capacitance between the base and collector is significant, affecting the overall device performance. The GaAs semi-insulating substrate does not participate in the conduction process; it only serves as a substrate to support the heterojunction bipolar transistor. The typical fabrication process for the isolation epitaxial layer involves first growing the front-side device on the substrate, then rotating it to the back side of the substrate, thinning the back side, and then creating vias on the substrate to connect to the external electrodes. The process of creating through-holes in a substrate is complicated, requires high precision, and is difficult, which increases production costs.

[0003] Some researchers have reversed the fabrication order of the epitaxial layers on the substrate, placing them from top to bottom as collector, base, and emitter layers. This allows for a smaller parasitic capacitance between the base and collector for the same emitter area. Furthermore, the inverted epitaxial layer eliminates the need for a back-side via to connect to the front-side emitter, further reducing process costs. However, this method still suffers from poor heat dissipation. Summary of the Invention

[0004] To address the problems in the fabrication of HBTs in the prior art, this invention provides a gallium arsenide-based heterojunction bipolar transistor and its fabrication method.

[0005] To achieve the above objectives, the following technical solutions are specifically included:

[0006] In a first aspect, the present invention provides a gallium arsenide-based heterojunction bipolar transistor, comprising a base electrode, an emitter region disposed on the base electrode, a base region disposed on the emitter region, a collector region disposed on the base region, and a passivation layer;

[0007] The emission region includes a first N-type GaAs emitter and an N-type semiconductor layer stacked sequentially, wherein the first N-type GaAs emitter is located on the side closer to the base electrode;

[0008] The base region includes a P-type GaAs base electrode and an electrode disposed at the end of the P-type GaAs base electrode; the number of electrodes in the base region is an integer greater than 1.

[0009] The current collector region is located in the middle of the P-type GaAs base, and the current collector region and the electrode of the base region are separated by a portion of the passivation layer; the current collector region includes an N-type InGaP layer, an N-type GaAs current collector, and an electrode of the current collector region stacked sequentially, and the N-type InGaP layer is located near the base region and is in contact with the P-type GaAs base.

[0010] The passivation layer covers a portion of the surface of the base region and a portion of the surface of the collector region, and exposes a portion of the top surface of the electrode in the base region and a portion of the top surface of the electrode in the collector region.

[0011] In the gallium arsenide-based heterojunction bipolar transistor (GaAs-based HBT) of the present invention, the collector region, base region, and emitter region are respectively arranged from top to bottom. An inverted structure is adopted. With the same emitter area, compared with the conventional upright structure, the collector region is located in the middle of the P-type GaAs base. Therefore, the contact area between the P-type GaAs base and the N-type InGaP layer is smaller than the area of ​​the P-type GaAs base. The relatively small contact area between the P-type GaAs base and the N-type InGaP layer allows for a smaller parasitic capacitance between them, thereby improving the RF gain and cutoff frequency of the GaAs-based HBT and enhancing the performance of the device structure.

[0012] Meanwhile, since the collector region is located at the top layer, the doping concentration of the top layer within the collector region can be increased without considering lattice mismatch. This significantly and effectively reduces the contact resistance between the top layer and the electrodes of the collector region, reducing it by approximately 10 from the original 10. -6 Ω*cm 2 Reduced to 2×10 -7 Ω*cm 2 This is beneficial for improving the electrical performance of the device. Furthermore, the inverted structure of this invention allows for thinning of each layer in the base and collector regions, reducing the overall thickness of the base and collector regions. The smaller overall thickness of the base and collector regions on a single GaAs-based HBT device allows for physical isolation to be achieved through etching mesa surfaces, improving the isolation effect between adjacent GaAs-based HBT devices (resistivity reaches approximately 1×10⁻⁶). 8(Ω and above), eliminating the need for traditional ion implantation isolation processes, thus reducing isolation process costs. In GaAs-based HBTs, the base electrode is typically grounded. In this invention, the emitter region is positioned on the base electrode, and the emitter region contacts the metal base electrode. This not only increases the area of ​​the emitter region but also improves its heat dissipation. Furthermore, the N-type semiconductor layer in the emitter region is obtained by thinning the original semiconductor substrate. It serves as one of the functional layers in the GaAs-based HBT device, participating in conductivity. Because of its participation in conductivity, the emitter region and base region can be electrically connected. Therefore, the N-type semiconductor layer does not need to serve merely as a supporting substrate as in traditional methods, requiring vias on its back side to connect to the base electrode. This reduces conventional substrate via processes, lowering production difficulty and costs.

[0013] In summary, the GaAs-based HBT device of the present invention adopts an inverted structure, and uses the semiconductor substrate in the processing as a conductive N-type semiconductor layer to participate in the conductivity of the device. This allows the GaAs-based HBT device to have the following characteristics: small parasitic capacitance between the P-type GaAs base and the N-type InGaP layer; effective reduction of contact resistance between the top layer and the electrode in the collector region; physical isolation between adjacent GaAs-based HBT devices can be achieved by etching mesa to improve the isolation effect; good heat dissipation effect in the emitter region; and no need to use traditional substrate via technology to save process costs.

[0014] Preferably, the emitter region further includes an N-type InGaAs cap layer, which is disposed between the first N-type GaAs emitter and the base electrode. Adding the N-type InGaAs cap layer can improve the fit between the first N-type GaAs emitter and the base electrode, reduce the contact resistance between them, and thus improve the overall performance of the device.

[0015] Preferably, the collector region further includes an N-type InGaAs cap layer, which is disposed between the N-type GaAs collector and the electrode of the collector region. Adding the N-type InGaAs cap layer can improve the fit between the N-type GaAs collector and the electrode of the collector region, reduce the contact resistance between them, and thus improve the overall performance of the device.

[0016] Preferably, the material of the N-type InGaAs cap layer has a doping concentration greater than or equal to 1×10⁻⁶. 19 atom / cm 3 For N-type InGaAs, a further preferred doping concentration is (1-2)×10⁻⁶. 19 atom / cm 3The thickness of the N-type InGaAs cap layer is 50-500 nm. Preferably, in the emitter region, the material of the first N-type GaAs emitter has a doping concentration greater than or equal to 1 × 10⁻⁶. 8 atom / cm 3 For N-type GaAs, a further preferred doping concentration is (1-5)×10⁻⁶. 8 atom / cm 3 The thickness of the first N-type GaAs emitter is 20-200 nm.

[0017] Preferably, the N-type semiconductor layer comprises an N-type GaAs layer. When the N-type semiconductor layer is an N-type GaAs layer, it forms a heterojunction structure with the P-type GaAs base.

[0018] Preferably, in the emission region, the N-type semiconductor layer is made of a material with a doping concentration greater than or equal to 1×10⁻⁶. 17 atom / cm 3 N-type GaAs, with a further preferred doping concentration of 1×10⁻⁶. 17 -5×10 19 atom / cm 3 The thickness of the N-type semiconductor layer is 10-50 μm.

[0019] Preferably, the emitter region further includes a second N-type GaAs emitter, which is disposed between the N-type semiconductor layer and the P-type GaAs base; the material of the second N-type GaAs emitter includes materials with a doping concentration greater than or equal to 1×10⁻⁶. 8 atom / cm 3 For N-type GaAs, a further preferred doping concentration is (1-5)×10⁻⁶. 8 atom / cm 3 The thickness of the second N-type GaAs emitter is 0.1-1 μm. When a second N-type GaAs emitter is added, the second N-type GaAs emitter and the P-type GaAs base form a heterojunction structure. The N-type semiconductor layer can be replaced with a semiconductor material other than N-type GaAs, which can increase the types of substrates of the present invention. Furthermore, because InGaAs is present on its surface, the contact resistance can be further reduced, and the electrical performance of the device can be improved.

[0020] Preferably, in the base region, the material of the p-type GaAs base includes materials with a doping concentration greater than or equal to 1×10⁻⁶. 18 atom / cm 3 P-type GaAs, with a further preferred doping concentration of 1×10⁻⁶. 18 -1×10 19 atom / cm 3The thickness of the P-type GaAs base is 0.02-1 μm.

[0021] Preferably, in the current collector region, the N-type InGaP layer is made of a material with a doping concentration greater than or equal to 1×10⁻⁶. 16 atom / cm 3 N-type InGaP, with a further preferred doping concentration of 1×10⁻⁶. 16 -1×10 18 atom / cm 3 The thickness of the N-type InGaP layer is 20-60 nm.

[0022] Preferably, in the current collector region, the N-type GaAs current collector is made of a material with a doping concentration greater than or equal to 1×10⁻⁶. 15 atom / cm 3 N-type GaAs with a doping concentration of 1×10 15 -1×10 18 atom / cm 3 The thickness of the N-type GaAs collector is 1-3 μm.

[0023] Preferably, the base electrode, the electrode of the base region, and the electrode of the current collector region are all metal-based conductive layers, and the metal in the metal-based conductive layer includes at least one of Au, Pt, Ti, and Pt.

[0024] Preferably, the thicknesses of the base electrode, the electrode of the base region, and the current collector region are each independently selected from 100nm-1000nm.

[0025] Preferably, the passivation layer comprises Si3N4. The passivation layer further achieves electrical isolation between the electrodes in the base region and the electrodes in the collector region.

[0026] Secondly, the present invention provides a method for fabricating the gallium arsenide-based heterojunction bipolar transistor, comprising the following steps:

[0027] S1. On the front side of an unthinned N-type semiconductor substrate, a second N-type GaAs emitter, a P-type GaAs base, an N-type InGaP layer, an N-type GaAs collector, and an optional N-type InGaAs cap layer are epitaxially prepared sequentially.

[0028] S2. Prepare multiple first electrodes for current collection regions on the N-type GaAs current collector or optionally on the N-type InGaAs cap layer;

[0029] S3. Let a single first electrode of the current collector region, the N-type InGaP layer corresponding to the first electrode of the current collector region, the N-type GaAs collector electrode, and an optional N-type InGaAs cap layer be a single current collector region; with each first electrode of the current collector region as the center, etch a portion of the N-type InGaP layer, the N-type GaAs collector electrode, and the optional N-type InGaAs cap layer, and expose the P-type GaAs base, thereby obtaining multiple spaced current collector regions on the P-type GaAs base;

[0030] S4. A base region first electrode matching each collector region is fabricated on the P-type GaAs base, and the base region first electrode is not in contact with the collector region; on the P-type GaAs base, a single collector region and its matching base region first electrode constitute a unit component.

[0031] S5. Along the thickness direction, a spacer groove is provided on the P-type GaAs base and the optional second N-type GaAs emitter to space two adjacent unit components;

[0032] S6. A passivation layer is deposited on the surface of the P-type GaAs base, the optional second N-type GaAs emitter, the first electrode of the base region, the current collector region and the spacer trench.

[0033] S7. Then, the passivation layer is etched on the top of the first electrode in the base region and the top of the first electrode in the collector region to expose a portion of the top surface of the first electrode in the base region and a portion of the top surface of the first electrode in the collector region. A second electrode in the base region and a second electrode in the collector region are deposited on the exposed portion of the top surface of the first electrode in the base region and the second electrode in the collector region, respectively. The first electrode in the base region and the second electrode in the base region constitute the electrode of the base region, and the first electrode in the collector region and the second electrode in the collector region constitute the electrode of the collector region.

[0034] S7. Thin the back side of the unthinned N-type semiconductor substrate to obtain an N-type semiconductor layer;

[0035] S9. On the back side of the N-type semiconductor layer, a first N-type GaAs emitter, an optional N-type InGaAs cap layer and a base electrode are sequentially epitaxially formed. After cutting, the gallium arsenide-based heterojunction bipolar transistor is obtained.

[0036] In the method of this invention, the N-type semiconductor substrate, originally used as a support, is thinned, and then an emitter and a base electrode are fabricated on its back side. This results in the GaAs-based HBT device of this invention having an inverted structure, with the emitter region located on the base electrode. The emitter region has a large area and good heat dissipation, eliminating the need for traditional substrate via processes, thus saving on process costs. Compared to the prior art, this invention has the following advantages: The GaAs-based HBT device of this invention adopts an inverted structure, and the semiconductor substrate in the processing technology participates in the device's conductivity as a conductive N-type semiconductor layer. This allows the GaAs-based HBT device to have low parasitic capacitance between the P-type GaAs base and the N-type InGaP layer, effectively reducing the contact resistance between the top layer of the collector region and the electrodes of the collector region, enabling physical isolation between adjacent GaAs-based HBT devices to be achieved through mesa etching to improve isolation, good heat dissipation in the emitter region, and saving on process costs by eliminating the need for traditional substrate via processes. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the GaAs-based HBT structure in Example 1;

[0038] Figure 2 This is a schematic diagram of the GaAs-based HBT structure in Example 2;

[0039] Figure 3 This is a schematic diagram of the GaAs-based HBT structure in Example 3;

[0040] Figure 4 This is a flowchart of steps S1-S3 in Example 3;

[0041] Figure 5 This is a flowchart of steps S4-S7 in Example 3;

[0042] Figure 6 This is a flowchart of steps S8-S9 in Example 3;

[0043] Explanation of reference numerals in the attached figures: 100 - base electrode, 201 - first N-type GaAs emitter in the emitter region, 202 - N-type semiconductor layer in the emitter region, 203 - second N-type GaAs emitter in the emitter region, 204 - N-type InGaAs cap layer in the emitter region, 301 - P-type GaAs base in the base region, 302 - electrode in the base region, electrode 302 in the base region is composed of the first electrode (302a) and the second electrode (302b) in the base region; 401 - N-type InGaP layer in the collector region, 402 - N-type GaAs collector in the collector region, 403 - electrode in the collector region, electrode 403 in the collector region is composed of the first electrode (403a) and the second electrode (403b) in the collector region, 404 - N-type InGaAs cap layer in the collector region, 500 - passivation layer. Detailed Implementation

[0044] To better illustrate the purpose, technical solution, and advantages of this invention, specific embodiments will be used to further explain the invention below. Unless otherwise specified, the test methods used in the embodiments and / or comparative examples are conventional methods; the materials and reagents used, unless otherwise specified, are commercially available.

[0045] It should be understood that in the description of this invention, the terms "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. That is, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Furthermore, unless otherwise stated, "a plurality of" means two or more.

[0046] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0047] In this article, "+" and "-" in "N+", "N-", "P+", and "P-" represent relatively high and low ion doping concentrations, respectively, that is, relatively high and low concentration ion doping.

[0048] In the following embodiments, the P-type GaAs base 301, N-type InGaP layer 401, N-type GaAs collector 402, first N-type GaAs emitter 201 and base electrode 100 are all prepared by vapor phase epitaxial growth of the corresponding films.

[0049] In the fabrication of HBT, the base electrode 100, the first N-type GaAs emitter 201, the second N-type GaAs emitter 203, the N-type InGaAs cap layer 204 in the emitter region, the P-type GaAs base 301, the electrode 302 in the base region, the N-type InGaP layer 401, the N-type GaAs collector 402, the N-type InGaAs cap layer 404 in the collector region, the electrode 403 in the collector region, and the passivation layer 500, as epitaxial layers of the N-GaA substrate, are all fabricated using vapor phase epitaxial growth.

[0050] The present invention relates to the step of "etching", which can be carried out by wet etching or dry etching; in the wet etching method, a mixed solution of phosphoric acid and hydrogen peroxide is used as the etching solution to remove the corresponding epitaxial layer; in the dry etching method, a mixed gas of Cl2 and BCl3 is used as the etching gas, and etching is carried out by ICP.

[0051] Example 1

[0052] A gallium arsenide-based heterojunction bipolar transistor, such as Figure 1 As shown, it includes a base electrode 100, an emitter region disposed on the base electrode 100, a base region disposed on the emitter region, a collector region disposed on the base region, and a passivation layer 500;

[0053] The emitter region includes a first N-type GaAs emitter 201 and an N-type semiconductor layer 202 stacked sequentially, with the first N-type GaAs emitter 201 located on the side close to the base electrode 100;

[0054] The base region includes a P-type GaAs base 301 and electrodes 302 disposed at the end of the P-type GaAs base 301; the number of electrodes 302 in the base region is 2.

[0055] The collector region is located in the middle of the P-type GaAs base 301, and the collector region and the base electrode 302 are separated by a partial passivation layer 500. The collector region includes an N-type InGaP layer 401, an N-type GaAs collector electrode 402, and an electrode 403 of the collector region stacked sequentially. The N-type InGaP layer 401 is located near the base region and is in contact with the P-type GaAs base 301. The passivation layer 500 covers a portion of the surface of the base region and a portion of the surface of the collector region, and exposes a portion of the top surface of the base electrode 302 and a portion of the top surface of the collector electrode 403.

[0056] Its preparation method specifically includes the following steps:

[0057] S1. Prepare a cleaned N-GaA substrate with a thickness of 675 μm and a doping concentration of 1 × 10⁻⁶. 17 atom / cm3 Then, on the front side of the substrate, a P-type GaAs base 301, an N-type InGaP layer 401, and an N-type GaAs collector 402 are sequentially deposited using vapor phase epitaxy. The thickness of the P-type GaAs base 301 is... The material has a doping concentration of 1×10⁻⁶. 19 atom / cm 3 The thickness of the P+GaAs; N-type InGaP layer 401 is The material has a doping concentration of 3×10⁻⁶. 17 atom / cm 3 The thickness of the N+InGaP; N-type GaAs collector 402 is The material has a doping concentration of 1×10⁻⁶. 17 atom / cm 3 N+GaAs;

[0058] S2. According to the designed pattern, multiple first electrodes 403a of the current collector region are prepared on the N-type GaAs current collector 402 by photolithography and vapor deposition. The material is Au.

[0059] S3. Let a single collector region first electrode 403a, the N-type InGaP layer 401 corresponding to the first collector region 403a, and the N-type GaAs collector electrode 402 be a single collector region. With each collector region first electrode 403a as the center, along the thickness direction, a mixed solution of hydrochloric acid and phosphoric acid is used as the etching solution to wet-etch a portion of the N-type InGaP layer and the N-type GaAs collector electrode 402, and expose the P-type GaAs base 301, thereby obtaining multiple spaced collector regions on the P-type GaAs base 301.

[0060] S4. Two base region first electrodes 302a matching each collector region are prepared on the surface of the P-type GaAs base 301. Observing along the length direction, with the collector region as the center, the base region first electrodes 302a are disposed on both sides of the collector region, and the base region first electrodes 302a do not contact the collector region. On the P-type GaAs base 301, a single collector region and its matching base region first electrode 302a constitute a unit component.

[0061] S5. Along the thickness direction, spacer grooves are set on the P-type GaAs base 301 to form unit components with adjacent etched mesa. The etching method is: etching is performed by ICP using a mixed gas of Cl2 and BCl3.

[0062] S6. A passivation layer 500 is deposited on the surface of the P-type GaAs base 301 (side), the first electrode 302a of the base region, the current collector region and the spacer groove by vapor phase epitaxial growth.

[0063] S7. Next, a passivation layer 500 is etched on the top of the first base electrode 302a and the first collector electrode 403a using a dry etching method to expose a portion of the top surface of the first base electrode 302a and the first collector electrode 403a. A second base electrode 302b and a second collector electrode 403b are then deposited on the exposed portions of the top surfaces of the first base electrode 302a and the first collector electrode 403a, respectively. The first base electrode 302a and the second base electrode 302b constitute the electrode 302 of the base region, and the first collector electrode 403a and the second collector electrode 403b constitute the electrode 403 of the collector region. The second collector electrode 403b and the second base electrode 302b serve as metal interconnects to connect individual HBT dies and to the pads of external interconnects. This achieves the connection between the inside and outside of the chip.

[0064] S8. Rotate the entire assembly to the back side of the N-GaA substrate and thin the back side of the N-GaA substrate to a thickness of 20μm to obtain the N-type semiconductor layer 202.

[0065] S9. On the back side of the N-type semiconductor layer 202, a first N-type GaAs emitter 201 and a base electrode 100 are sequentially deposited using vapor phase epitaxy. The entire layer is then cut according to the positions corresponding to the spacer trenches to obtain multiple gallium arsenide-based heterojunction bipolar transistors. The thickness of the first N-type GaAs emitter 201 is... The material is N+GaAs with a doping concentration of 4×10⁻⁶. 8 atom / cm 3 The thickness of the base electrode 100 is 200 nm, and the material is TiPtAu.

[0066] In the GaAs-based HBT of this invention, the collector region, base region, and emitter region are respectively arranged from top to bottom, adopting an inverted structure. With the same emitter area, compared to the conventional upright structure, the collector region is located in the middle of the P-type GaAs base 301. Therefore, the contact area between the P-type GaAs base 301 and the N-type InGaP layer 401 is smaller than the area of ​​the P-type GaAs base 301. This relatively smaller contact area allows for a smaller parasitic capacitance between them, improving the RF gain and cutoff frequency of the GaAs-based HBT and enhancing the device structure performance. Simultaneously, because the collector region is located on the top layer, the doping concentration of the top layer in the collector region can be increased without considering lattice mismatch. This significantly and effectively reduces the contact resistance between the top layer and the electrode 403 in the collector region, approximately reducing it from the original 10... -6 Ω*cm 2 Reduced to 2×10 -7 Ω*cm2 This is beneficial for improving the electrical performance of the device. Furthermore, the inverted structure of this invention allows for thinning of each layer in the base and collector regions, reducing the overall thickness of the base and collector regions. The smaller overall thickness of the base and collector regions on a single GaAs-based HBT device allows for physical isolation to be achieved through etching mesa surfaces, improving the isolation effect between adjacent GaAs-based HBT devices (resistivity reaches approximately 1×10⁻⁶). 8 (Ω and above), eliminating the need for traditional ion implantation isolation processes, thus reducing isolation process costs. The base electrode 100 in a GaAs-based HBT is typically a grounded electrode. In this invention, the emitter region is positioned on the base electrode 100, and the emitter region contacts the metal base electrode 100. This not only increases the area of ​​the emitter region but also improves its heat dissipation. Furthermore, the N-type semiconductor layer 202 in the emitter region is obtained by thinning the original semiconductor substrate. It serves as one of the functional layers in the GaAs-based HBT device, participating in conductivity. Because of its participation in conductivity, the emitter region and base region can be electrically connected. Therefore, the N-type semiconductor layer 202 does not need to serve merely as a supporting substrate as in traditional methods, requiring vias on its back side to connect to the base electrode 100. This reduces conventional substrate via processes, lowering production difficulty and costs.

[0067] Example 2

[0068] A gallium arsenide-based heterojunction bipolar transistor, such as Figure 2 As shown, it includes a base electrode 100, an emitter region disposed on the base electrode 100, a base region disposed on the emitter region, a collector region disposed on the base region, and a passivation layer 500;

[0069] The emission region includes a first N-type GaAs emitter 201, an N-type semiconductor layer 202 and a second N-type GaAs emitter stacked in sequence. The first N-type GaAs emitter 201 is located on the side close to the base electrode 100, and the second N-type GaAs emitter is disposed between the N-type semiconductor layer 202 and the P-type GaAs base 301.

[0070] The base region includes a P-type GaAs base 301 and an electrode 302 disposed at the end of the P-type GaAs base 301; the number of electrodes 302 in the base region is 2.

[0071] The collector region is located in the middle of the P-type GaAs base 301, and the collector region and the base electrode 302 are separated by a partial passivation layer 500. The collector region includes an N-type InGaP layer 401, an N-type GaAs collector electrode 402, and an electrode 403 of the collector region stacked sequentially. The N-type InGaP layer 401 is located near the base region and is in contact with the P-type GaAs base 301. The passivation layer 500 covers a portion of the surface of the base region and a portion of the surface of the collector region, and exposes a portion of the top surface of the base electrode 302 and a portion of the top surface of the collector electrode 403.

[0072] Its preparation method specifically includes the following steps:

[0073] S1. Prepare a cleaned N-GaA substrate with a thickness of 675 μm and a doping concentration of 1 × 10⁻⁶. 17 atom / cm 3 Then, on the front side of the substrate, a second N-type GaAs emitter, a P-type GaAs base 301, an N-type InGaP layer 401, and an N-type GaAs collector 402 are sequentially deposited using vapor phase epitaxy. The thickness of the second N-type GaAs emitter is... The material is N+GaAs with a doping concentration of 4×10⁻⁶. 8 atom / cm 3 The thickness of the P-type GaAs base 301 is... The material has a doping concentration of 1×10⁻⁶. 19 atom / cm 3 The thickness of the P+GaAs; N-type InGaP layer 401 is The material has a doping concentration of 3×10⁻⁶. 17 atom / cm 3 The thickness of the N+InGaP; N-type GaAs collector 402 is The material has a doping concentration of 1×10⁻⁶. 17 atom / cm 3 N+GaAs;

[0074] S2. According to the designed pattern, multiple first electrodes 403a of the current collector region are prepared on the N-type GaAs current collector 402 by photolithography and vapor deposition. The material is Au.

[0075] S3. Let a single collector region first electrode 403a, the N-type InGaP layer 401 and the N-type GaAs collector electrode 402 corresponding to the single collector region first electrode 403a be a single collector region; take each collector region first electrode 403a as the center, etch a portion of the N-type InGaP layer 401 and the N-type GaAs collector electrode 402 along the thickness, and expose the P-type GaAs base 301, and obtain multiple spaced collector regions on the P-type GaAs base 301;

[0076] S4. Two base region first electrodes 302a matching each collector region are fabricated on the surface of the P-type GaAs base 301. Observing along the length direction, with the collector region as the center, the base region first electrodes 302a are disposed on both sides of the collector region, and the base region first electrodes 302a do not contact the collector region. On the P-type GaAs base 301, a single collector region and its matching base region first electrode 302a constitute a unit component. The etching method is: etching is performed by ICP using a mixed gas of Cl2 and BCl3.

[0077] S5. Along the thickness direction, spacer grooves are provided on the P-type GaAs base 301 and the second N-type GaAs emitter to form unit components with adjacent etched mesa.

[0078] S6. Using vapor phase epitaxial growth, a passivation layer 500 is deposited on the surface of the second N-type GaAs emitter (side), P-type GaAs base 301 (side), base region first electrode 302a, current collector region and spacer trench.

[0079] S7. Next, the passivation layer 500 is etched on the top of the first electrode 302a in the base region and the top of the first electrode 403a in the collector region using a dry etching method to expose a portion of the top surface of the first electrode 302a in the base region and a portion of the top surface of the first electrode 403a in the collector region. The second electrode 302b in the base region and the second electrode 403b in the collector region are deposited on the exposed portion of the top surface of the first electrode 302a in the base region and the second electrode 403b in the collector region, respectively. The first electrode 302a and the second electrode 302b in the base region constitute the electrode 302 in the base region, and the first electrode 403a and the second electrode 403b in the collector region constitute the electrode 403 in the collector region.

[0080] S8. Rotate the entire assembly to the back side of the N-GaA substrate and thin the back side of the N-GaA substrate to a thickness of 20μm to obtain the N-type semiconductor layer 202.

[0081] S9. On the back side of the N-type semiconductor layer 202, a first N-type GaAs emitter 201 and a base electrode 100 are sequentially deposited using vapor phase epitaxy. The entire layer is then cut according to the positions corresponding to the spacer trenches to obtain multiple gallium arsenide-based heterojunction bipolar transistors. The thickness of the first N-type GaAs emitter 201 is... The material is N+GaAs with a doping concentration of 4×10⁻⁶. 8 atom / cm 3 The thickness of the base electrode 100 is 200 nm, and the material is TiPtAu.

[0082] Compared with Example 1, this example adds a second N-type GaAs emitter. The second N-type GaAs emitter and the P-type GaAs base 301 form a heterojunction structure. The N-type semiconductor layer 202 can be replaced with a semiconductor material other than N-type GaAs, which can increase the types of substrates of the present invention.

[0083] Example 3

[0084] A gallium arsenide-based heterojunction bipolar transistor, such as Figure 3 As shown, it includes a base electrode 100, an emitter region disposed on the base electrode 100, a base region disposed on the emitter region, a collector region disposed on the base region, and a passivation layer 500;

[0085] The emitter region includes an N-type InGaAs cap layer 204, a first N-type GaAs emitter 201, an N-type semiconductor layer 202 and a second N-type GaAs emitter, which are stacked from bottom to top. The N-type InGaAs cap layer 204 in the emitter region is disposed between the base electrode 100 and the first N-type GaAs emitter 201.

[0086] The base region includes a P-type GaAs base 301 and an electrode 302 disposed at the end of the P-type GaAs base 301; the number of electrodes 302 in the base region is 2.

[0087] The collector region is located in the middle of the P-type GaAs base 301, and the collector region and the electrode 302 of the base region are separated by a partial passivation layer 500. The collector region includes an N-type InGaP layer 401, an N-type GaAs collector electrode 402, an N-type InGaAs cap layer 404 in the collector region, and an electrode 403 of the collector region, which are stacked in sequence. The N-type InGaP layer 401 is located on the side close to the base region and is in contact with the P-type GaAs base 301.

[0088] The passivation layer 500 covers a portion of the surface of the base region and a portion of the surface of the collector region, and exposes a portion of the top surface of the electrode 302 in the base region and a portion of the top surface of the electrode 403 in the collector region.

[0089] Its preparation method specifically includes the following steps:

[0090] S1. Prepare a cleaned N-GaA substrate with a thickness of 675 μm and a doping concentration of 1 × 10⁻⁶ μm. 17 atom / cm 3 Then, on the front side of the substrate, a second N-type GaAs emitter, a P-type GaAs base 301, an N-type InGaP layer 401, an N-type GaAs collector 402, and an N-type InGaAs cap layer 404 in the collector region are sequentially deposited using vapor phase epitaxy. Figure 4 As shown; where the thickness of the second N-type GaAs emitter is The material is N+GaAs with a doping concentration of 4×10⁻⁶. 8 atom / cm 3 The thickness of the P-type GaAs base 301 is... The material has a doping concentration of 1×10⁻⁶. 19 atom / cm 3 The thickness of the P+GaAs; N-type InGaP layer 401 is The material has a doping concentration of 3×10⁻⁶. 17 atom / cm 3 The thickness of the N+InGaP; N-type GaAs collector 402 is The material has a doping concentration of 1×10⁻⁶. 17 atom / cm 3 The thickness of the N+GaAs cap layer 404 in the collector region is... The material has a doping concentration of 1×10⁻⁶. 19 atom / cm 3 N+InGaAs;

[0091] S2. According to the designed pattern, multiple first electrodes 403a of the current collector region, made of Au, are sequentially fabricated on the N-type GaAs current collector 402 by photolithography and vapor deposition. Figure 4 As shown;

[0092] S3. Let a single collector region first electrode 403a, the corresponding N-type InGaP layer 401, and the N-type GaAs collector 402 be considered as a single collector region. Centered on each collector region first electrode 403a, along the thickness direction, using a mixed solution of hydrochloric acid and phosphoric acid as the etching solution, wet-etch the N-type InGaP layer 401, the N-type GaAs collector 402, and a portion of the N-type InGaAs cap layer in the collector region, exposing the P-type GaAs base 301, thus obtaining multiple spaced collector regions on the P-type GaAs base 301; For example... Figure 4 As shown;

[0093] S4. Two base region first electrodes 302a, matching each collector region, are fabricated on the surface of the P-type GaAs base 301. Viewed along the length direction, with the collector region as the center, the base region first electrodes 302a are positioned on both sides of the collector region, and the base region first electrodes 302a do not contact the collector region. On the P-type GaAs base 301, a single collector region and its matching base region first electrode 302a constitute a unit component; for example... Figure 5 As shown;

[0094] S5. Along the thickness direction, spacer grooves are formed on the P-type GaAs base 301 and the second N-type GaAs emitter to form unit components with adjacent etched mesa surfaces; such as Figure 5 As shown; the etching method is: etching is performed by ICP using a mixture of Cl2 and BCl3 gas;

[0095] S6. A passivation layer 500 is deposited on the surface of the P-type GaAs base 301 (side), the second N-type GaAs emitter (side), the first electrode 302a of the base region, the current collector region and the spacer groove by vapor phase epitaxial growth.

[0096] S7. Next, the passivation layer 500 is etched using a dry etching method on the top of the first electrode 302a in the base region and the top of the first electrode 403a in the collector region to expose a portion of the top surface of the first electrode 302a in the base region and a portion of the top surface of the first electrode 403a in the collector region. A second electrode 302b in the base region and a second electrode 403b in the collector region are then deposited on the exposed portions of the top surfaces of the first electrode 302a in the base region and the second electrode 403a in the collector region, respectively. The first electrode 302a and the second electrode 302b in the base region constitute the electrode 302 in the base region, and the first electrode 403a and the second electrode 403b in the collector region constitute the electrode 403 in the collector region. Figure 5 As shown;

[0097] S8. Rotate the entire assembly to the back side of the N-GaA substrate, and thin the back side of the N-GaA substrate to a thickness of 20 μm to obtain the N-type semiconductor layer 202; Figure 6 As shown;

[0098] S9. A first N-type GaAs emitter 201, an N-type InGaAs cap layer for the emitter region, and a base electrode 100 are sequentially deposited on the back side of the N-type semiconductor layer using vapor phase epitaxy. The entire structure is then cut according to the positions corresponding to the spacer slots to obtain multiple gallium arsenide-based heterojunction bipolar transistors. The thickness of the first N-type GaAs emitter 201 is... The material is N+GaAs with a doping concentration of 4×10⁻⁶. 8 atom / cm 3 The base electrode 100 has a thickness of 200 nm and is made of TiPtAu material; the N-type InGaAs cap layer 204 in the emitter region has a thickness of [missing information]. The material has a doping concentration of 1×10⁻⁶. 19 atom / cm 3 N+InGaAs; such as Figure 6 As shown.

[0099] Compared with Embodiment 2, this embodiment adds an N-type InGaAs cap layer to the emitter region and the collector region, which can improve the fit between the first N-type GaAs emitter 201 and the base electrode 100, as well as between the N-type GaAs collector 402 and the electrode 403 of the collector region, reduce the contact resistance between them, and help improve the overall performance of the device.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A gallium arsenide-based heterojunction bipolar transistor, characterized in that, It includes a base electrode, an emitter region disposed on the base electrode, a base region disposed on the emitter region, a collector region disposed on the base region, and a passivation layer; The emitter region includes a first N-type GaAs emitter and an N-type semiconductor layer stacked sequentially, wherein the first N-type GaAs emitter is located on the side closer to the base electrode; The base region includes a P-type GaAs base electrode and an electrode disposed at the end of the P-type GaAs base electrode; the number of electrodes in the base region is an integer greater than 1. The current collector region is located in the middle of the P-type GaAs base, and the current collector region and the electrode of the base region are separated by a portion of the passivation layer; the current collector region includes an N-type InGaP layer, an N-type GaAs current collector, and an electrode of the current collector region stacked sequentially, and the N-type InGaP layer is located near the base region and is in contact with the P-type GaAs base. The passivation layer covers a portion of the surface of the base region and a portion of the surface of the collector region, and exposes a portion of the top surface of the electrode in the base region and a portion of the top surface of the electrode in the collector region.

2. The gallium arsenide-based heterojunction bipolar transistor as described in claim 1, characterized in that, Includes at least one of the following: The emitter region further includes an N-type InGaAs cap layer, which is disposed between the first N-type GaAs emitter and the base electrode; The current collector region further includes an N-type InGaAs cap layer, which is disposed between the N-type GaAs current collector and the electrode of the current collector region; The N-type InGaAs cap layer is made of a material with a doping concentration greater than or equal to 1×10⁻⁶. 19 atom / cm 3 The N-type InGaAs cap layer has a thickness of 50-500 nm. The N-type semiconductor layer includes an N-type GaAs layer.

3. The gallium arsenide-based heterojunction bipolar transistor as described in claim 1, characterized in that, In the emitter region, the material of the first N-type GaAs emitter has a doping concentration greater than or equal to 1×10⁻⁶. 8 atom / cm 3 The thickness of the first N-type GaAs emitter is 20-200 nm.

4. The gallium arsenide-based heterojunction bipolar transistor as described in claim 1, characterized in that, The emitter region further includes a second N-type GaAs emitter, which is disposed between the N-type semiconductor layer and the P-type GaAs base; the material of the second N-type GaAs emitter includes materials with a doping concentration greater than or equal to 1×10⁻⁶. 8 atom / cm 3 The second N-type GaAs emitter has a thickness of 0.1-1 μm.

5. The gallium arsenide-based heterojunction bipolar transistor as described in claim 1, characterized in that, In the emission region, the N-type semiconductor layer is made of GaAs and has a thickness of 10-50 μm.

6. The gallium arsenide-based heterojunction bipolar transistor as described in claim 1, characterized in that, In the base region, the material of the P-type GaAs base includes materials with a doping concentration greater than or equal to 1×10⁻⁶. 18 atom / cm 3 The P-type GaAs has a base thickness of 0.02-1 μm.

7. The gallium arsenide-based heterojunction bipolar transistor as described in claim 1, characterized in that, In the current collector region, the N-type InGaP layer is made of a material with a doping concentration greater than or equal to 1×10⁻⁶. 16 atom / cm 3 The N-type InGaP layer has a thickness of 20-60 nm.

8. The gallium arsenide-based heterojunction bipolar transistor as described in claim 1, characterized in that, In the current collector region, the N-type GaAs current collector is made of a material with a doping concentration greater than or equal to 1×10⁻⁶. 15 atom / cm 3 The N-type GaAs has a collector electrode thickness of 1-3 μm.

9. The gallium arsenide-based heterojunction bipolar transistor as described in claim 1, characterized in that, The base electrode, the electrode of the base region, and the electrode of the current collector region are all metal-based conductive layers, and the metal in the metal-based conductive layer includes at least one of Au, Pt, Ti, and Pt; the passivation layer includes Si3N4.

10. A method for fabricating a gallium arsenide-based heterojunction bipolar transistor according to any one of claims 1 to 9, characterized in that, Includes the following steps: S1. On the front side of an unthinned N-type semiconductor substrate, a second N-type GaAs emitter, a P-type GaAs base, an N-type InGaP layer, an N-type GaAs collector, and an optional N-type InGaAs cap layer are epitaxially prepared sequentially. S2. Prepare multiple first electrodes for current collection regions on the N-type GaAs current collector or optionally on the N-type InGaAs cap layer; S3. Let a single first electrode of the current collector region, the N-type InGaP layer corresponding to the first electrode of the current collector region, the N-type GaAs collector electrode, and an optional N-type InGaAs cap layer be a single current collector region; with each first electrode of the current collector region as the center, etch a portion of the N-type InGaP layer, the N-type GaAs collector electrode, and the optional N-type InGaAs cap layer, and expose the P-type GaAs base, thereby obtaining multiple spaced current collector regions on the P-type GaAs base; S4. A base region first electrode matching each collector region is fabricated on the P-type GaAs base, and the base region first electrode is not in contact with the collector region; on the P-type GaAs base, a single collector region and its matching base region first electrode constitute a unit component. S5. Along the thickness direction, a spacer groove is provided on the P-type GaAs base and the optional second N-type GaAs emitter to space two adjacent unit components; S6. A passivation layer is deposited on the surface of the P-type GaAs base, the optional second N-type GaAs emitter, the first electrode of the base region, the current collector region and the spacer trench. S7. Then, the passivation layer is etched on the top of the base region first electrode and the top of the collector region first electrode to expose a portion of the top surface of the base region first electrode and a portion of the top surface of the collector region first electrode. A base region second electrode and a collector region second electrode are deposited on the exposed portion of the top surface of the base region first electrode and the portion of the top surface of the collector region first electrode, respectively. The first electrode of the base region and the second electrode of the base region constitute the electrode of the base region, and the first electrode of the collector region and the second electrode of the collector region constitute the electrode of the collector region; S8. Thin the back side of the unthinned N-type semiconductor substrate to obtain an N-type semiconductor layer; S9. On the back side of the N-type semiconductor layer, a first N-type GaAs emitter, an optional N-type InGaAs cap layer and a base electrode are sequentially epitaxially formed. After cutting, the gallium arsenide-based heterojunction bipolar transistor is obtained.

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