Structure for enhancing safe working area capability of shield gate trench MOSFET device and preparation method thereof

Abstract

The invention discloses a structure for enhancing the capability of a safe working region of a shield gate trench MOSFET device and a preparation method, and the structure is characterized in that a thick gate oxide layer region and a thin gate oxide layer region are formed in an active region trench of the MOSFET device, so that a high-threshold-voltage cell and a low-threshold-voltage cell are formed; when the gate-source voltage is small in the using process of the device, the low-threshold-voltage cells are opened, the high-threshold-voltage cells are not opened, and a part of cells are not opened, so that the power density of the whole device is reduced, the heat dissipation capability is enhanced, the zero-temperature coefficient point of the device is reduced, the safe working area of the device is improved, and the service life of the device is prolonged. A device structure with a wide safe working area characteristic is integrated in an active area, so that the performance of the safe working area is enhanced, the conduction loss of the device is still not influenced after the device is completely started, and the device has a wider application prospect; in addition, the manufacturing process method is simple and can be compatible with a traditional MOSFET manufacturing process.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to the structure and fabrication method for enhancing the safe operating area capability of shielded gate trench MOSFET devices. Background Technology

[0002] Shielded gate trench MOSFETs, as an advanced power MOSFET technology, reduce the gate-drain overlap area and gate-drain capacitance by introducing a shielded gate electrode, thereby improving switching speed, reducing dynamic losses, and increasing cell density to reduce on-resistance. They are widely used in power systems, electronic fuses, automobiles, and other applications requiring high linear-mode performance. These applications demand both lower on-loss and the ability to operate under high voltage and current for extended periods, meaning a large safe operating area.

[0003] When existing MOSFET devices operate in linear mode, they simultaneously experience high drain voltage and high drain current, resulting in high power consumption. When the electrothermal stress exceeds a certain critical value, hot spots will appear in localized areas of the active region, leading to thermal runaway and device failure.

[0004] Therefore, improving the safe operating area performance of MOSFET devices has become an urgent problem to be solved. Summary of the Invention

[0005] This application aims to at least solve the technical problems existing in the prior art. To this end, the first aspect of this application proposes a method for fabricating a structure that enhances the safe operating area capability of a shielded gate trench MOSFET device, the method comprising: Multiple active region trenches are formed on the epitaxial layer located on the semiconductor substrate, and an inner pad oxide layer is formed on the surface of the epitaxial layer and each active region trench. Shielding polysilicon is deposited in the trench of each active region, and the shielding polysilicon and the inner pad oxide layer are etched in the trench so that the top of the shielding polysilicon is located outside the inner pad oxide layer. The first oxide layer is formed on the sidewalls of each active region trench and on the top of the shielded polysilicon through the first thermal oxidation process, and photoresist is formed using a gate oxide photomask to remove the first oxide layer in the areas not covered by the photoresist. A first gate oxide layer and a second gate oxide layer are formed on the sidewalls of the active region trench through a second thermal oxidation process, and then processed to form gate polysilicon; wherein, the first target thickness of the first gate oxide layer is smaller than the second target thickness of the second gate oxide layer. The active region is formed by sequentially implanting ions into the body region and the source region using a photomask.

[0006] In one possible implementation, a first gate oxide layer and a second gate oxide layer are formed on the sidewalls of the active region trench via a second thermal oxidation process, including: Through a second thermal oxidation process, at least one first gate oxide layer and at least one second gate oxide layer are formed on the sidewall of each active region trench; wherein the first gate oxide layer corresponds to a first length and the second gate oxide layer corresponds to a second length.

[0007] In one possible implementation, the first gate oxide layer and the second gate oxide layer are arranged at intervals.

[0008] In one possible implementation, a first gate oxide layer and a second gate oxide layer are formed on the sidewalls of the active region trench by a second thermal oxidation process, and the process further includes: Through a second thermal oxidation process, a first gate oxide layer and a second gate oxide layer are formed on the sidewalls of different active region trenches; wherein, the active region trench in which the first gate oxide layer is formed is called the first trench, and the active region trench in which the second gate oxide layer is formed is called the second trench.

[0009] In one possible implementation, the first trench and the second trench are arranged alternately.

[0010] In one possible implementation, bulk ion implantation and source ion implantation are performed sequentially using a photomask, including: A single bulk ion implantation is performed using a photomask, wherein the bulk ion implantation concentration distribution of the first gate oxide layer and the second gate oxide layer is the same. Source ion implantation is performed using a photomask above the ion region of the bulk region.

[0011] In one possible implementation, the method further includes: Obtain the preset thickness of the first oxide layer on the sidewall of the active region trench; Calculate the first thickness difference between the first target thickness and the preset thickness, and calculate the second thickness difference between the second target thickness and the preset thickness; Based on the first thickness difference and the second thickness difference, a second thermal oxidation process is performed.

[0012] In one possible implementation, the method further includes: A low-temperature oxide layer and a borosilicate glass layer are sequentially deposited on the surface of the epitaxial layer, and contact holes are formed by etching with a contact hole photomask.

[0013] In one possible implementation, the method further includes: A metal layer is deposited on the entire surface of the device, and the metal layer structure is formed by metal layer photolithography.

[0014] The second aspect of this application proposes a structure for enhancing the safe operating area capability of a shielded gate trench MOSFET device, which is prepared according to the preparation method of the structure for enhancing the safe operating area capability of a shielded gate trench MOSFET device described in the first aspect above.

[0015] The embodiments of this application have the following beneficial effects: This application provides a structure and fabrication method for enhancing the safe operating area capability of a shielded gate trench MOSFET device. The method includes: forming multiple active region trenches on an epitaxial layer located on a semiconductor substrate; forming an inner pad oxide layer on the surface of the epitaxial layer and each active region trench; depositing shielded polysilicon in the trench of each active region trench; etching the shielded polysilicon and the inner pad oxide layer in the trench so that the top of the shielded polysilicon is located outside the inner pad oxide layer; forming a first oxide layer on the sidewall of each active region trench and the top of the shielded polysilicon through a first thermal oxidation process; forming photoresist using a gate oxide photomask; removing the first oxide layer in the area not covered by the photoresist; forming a first gate oxide layer and a second gate oxide layer on the sidewall of the active region trench through a second thermal oxidation process; and forming gate polysilicon, wherein the first target thickness of the first gate oxide layer is less than the second target thickness of the second gate oxide layer; and performing body ion implantation and source ion implantation sequentially using a photomask to form the active region. This solution creates high-threshold voltage cells and low-threshold voltage cells by forming thick and thin gate oxide regions in the active region trench of the MOSFET device. During operation, when the gate-source voltage is low, the low-threshold voltage cells turn on while the high-threshold voltage cells remain off. The partial shutdown of cells reduces the overall power density and enhances heat dissipation, thereby lowering the zero-temperature coefficient point and improving the safe operating area. Essentially, it integrates a device structure with a wide safe operating area in the active region, enhancing its performance. Furthermore, it does not affect the conduction loss even when the device is fully turned on, broadening its application prospects. Moreover, by using the same ion implantation concentration distribution in the thick and thin gate oxide regions, the high-threshold voltage cells and low-threshold voltage cells are achieved due to the different oxide layer thicknesses at the same ion implantation concentration, further enhancing the wide safe operating area characteristic. Additionally, this manufacturing process is simple and compatible with traditional MOSFET manufacturing processes. Attached Figure Description

[0016] Figure 1 A flowchart illustrating the steps of a method for fabricating a structure that enhances the safe operating area capability of a shielded gate trench MOSFET device, as provided in this application embodiment; Figure 2 A schematic diagram of a substrate and an epitaxial layer provided in an embodiment of this application; Figure 3 A schematic diagram of an active region trench provided for an embodiment of this application; Figure 4 This is a schematic diagram of an inner liner oxide layer provided in an embodiment of this application; Figure 5 A schematic diagram of an etched shielding polysilicon and an inner oxide layer provided in an embodiment of this application; Figure 6 This is a schematic diagram showing the result of the first thermal oxidation process provided in an embodiment of this application; Figure 7 This is a schematic diagram illustrating the removal of a portion of the first oxide layer, provided as an embodiment of this application. Figure 8 A schematic diagram of a first gate oxide layer and a second gate oxide layer provided in an embodiment of this application; Figure 9 This is a schematic diagram of a cross-sectional view of a device provided in an embodiment of this application; Figure 10 A schematic diagram of another first gate oxide layer and a second gate oxide layer provided in an embodiment of this application; Figure 11 A schematic diagram of another device cross-section provided in an embodiment of this application; Figure 12 A schematic diagram of a cross-sectional view of another device provided in an embodiment of this application; Figure 13 This is a schematic diagram of a second thermal oxidation process provided in an embodiment of this application; Figure 14 A schematic diagram illustrating the formation of a gate polysilicon according to an embodiment of this application; Figure 15 This is a schematic diagram of a body region ion implantation provided in an embodiment of this application; Figure 16 This is a schematic diagram of source ion implantation provided in an embodiment of this application; Figure 17 A schematic diagram of a low-temperature oxide layer and a borosilicate glass layer provided in an embodiment of this application; Figure 18 This is a schematic diagram of an etching process for forming a contact hole, provided as an embodiment of this application. Figure 19 This is a schematic diagram of a metal layer structure provided in an embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, the use of "based on" or "according to" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" or "according to" one or more of the stated conditions or values ​​may in practice be based on additional conditions or beyond the stated values.

[0019] like Figure 1 As shown, Figure 1 A flowchart illustrating the steps of a method for fabricating a structure to enhance the safe operating area capability of a shielded gate trench MOSFET device, as provided in this application embodiment, includes: Step 102: Multiple active region trenches are formed on the epitaxial layer located on the semiconductor substrate, and an inner pad oxide layer is formed on the surface of the epitaxial layer and each active region trench.

[0020] The shielded gate trench MOSFET device described in this application includes N-type MOSFETs and P-type MOSFETs. If it is an N-type MOSFET, its substrate and epitaxial layer are both N-type doped, for example, doped with arsenic or phosphorus. The source region is heavily N-type doped, and the body region is P-type doped. Furthermore, the gate polysilicon is heavily N-type doped polysilicon. Interchanging these doping types—that is, converting N-type to P-type and vice versa—results in a P-type MOSFET.

[0021] This application uses an N-type MOSFET as an example for illustration. Figure 2 As shown, Figure 2 This is a schematic diagram of a substrate and an epitaxial layer provided in an embodiment of this application, wherein, Figure 2 In the middle, an N-type lightly doped epitaxial layer 2 is grown on an N-type heavily doped semiconductor substrate 1.

[0022] Next, multiple active region trenches 3 can be formed on the epitaxial layer 2 located on the semiconductor substrate 1 through photolithography and etching processes, such as... Figure 3 As shown, Figure 3 This is a schematic diagram of an active region trench provided in an embodiment of this application. Figure 3 The active area trench in the middle has a U-shaped structure.

[0023] like Figure 4 As shown, Figure 4 This is a schematic diagram of an inner oxide layer provided in an embodiment of this application. An inner oxide layer 4 can be grown on the surface of the epitaxial layer 2 and each active region trench 3 through a thermal oxidation process or a combination of thermal oxidation and chemical vapor deposition. Optionally, the thickness of the inner oxide layer 4 can be different depending on the withstand voltage of different devices.

[0024] Step 104: Deposit and form shielding polysilicon in the trench of each active region, and etch the shielding polysilicon and the inner pad oxide layer in the trench so that the top of the shielding polysilicon is located outside the inner pad oxide layer.

[0025] Among them, such as Figure 5 As shown, Figure 5 This is a schematic diagram of an etched shielding polysilicon and inner oxide layer provided in an embodiment of this application. In this embodiment, shielding polysilicon 5 is formed by polysilicon deposition in each active region trench 3. At this time, the deposited shielding polysilicon 5 will fill the entire trench.

[0026] Next, using a shielded polysilicon photomask, the shielded polysilicon 5 within the active region trench 3 is etched to a certain depth, which can be determined by the channel and gate lengths, and the photoresist is removed. Then, the inner oxide layer 4 is etched onto the silicon surface, exposing the top of the shielded polysilicon 5 to the outside of the inner oxide layer 4.

[0027] Step 106: A first oxide layer is formed on the sidewall of each active region trench and on top of the shielded polysilicon through a first thermal oxidation process, and a photoresist is formed using a gate oxide photomask to remove the first oxide layer in the areas not covered by the photoresist.

[0028] Among them, such as Figure 6 As shown, Figure 6 This is a schematic diagram of a first thermal oxidation process provided in an embodiment of this application. The first thermal oxidation process forms a first oxide layer on the sidewalls of each active region trench 3 and on the top of the shielding polysilicon. .

[0029] Next, as Figure 7 As shown, Figure 7 This is a schematic diagram illustrating the removal of a portion of the first oxide layer according to an embodiment of this application. The first oxide layer in the area not covered by the photoresist can be removed by forming a photoresist 6 using a gate oxide photomask. And remove the photoresist.

[0030] Step 108: A first gate oxide layer and a second gate oxide layer are formed on the sidewall of the active region trench through a second thermal oxidation process, and then processed to form gate polysilicon.

[0031] In this process, the first target thickness a of the first gate oxide layer is less than the second target thickness b of the second gate oxide layer. Through the second thermal oxidation process, the first gate oxide layer a and the second gate oxide layer b can be formed on the sidewall of the active region trench 3, respectively. The first gate oxide layer a is also called the thin gate oxide layer, and the second gate oxide layer b is also called the thick gate oxide layer.

[0032] In some alternative embodiments, when the first gate oxide layer a and the second gate oxide layer b are formed on the sidewalls of the active region trench 3 by the second thermal oxidation process, the first gate oxide layer a and the second gate oxide layer b can be formed on the sidewalls of different active region trenches 3 by the second thermal oxidation process.

[0033] The active region trench forming the first gate oxide layer is called the first trench, and the active region trench forming the second gate oxide layer is called the second trench. The first trench and the second trench are arranged alternately. Optionally, the first trench and the second trench can be arranged with one or more trenches in between. For example, multiple first trenches forming the first gate oxide layer can be spaced out before the second trenches forming the second gate oxide layer are configured. The proportion of the first trench and the second trench can also be combined in different ways according to actual needs.

[0034] For example, such as Figure 8 As shown, Figure 8 This is a schematic diagram of a first gate oxide layer and a second gate oxide layer provided in an embodiment of this application. Region a is a thin gate oxide layer, region b is a thick gate oxide layer, region c is gate polysilicon, and other film layers are not shown. The first trench and the second trench are arranged with an interval of one. The cross-sectional view of the device obtained along the dashed line formed by A and B is shown below. Figure 9 As shown, that is Figure 9 This is a schematic diagram of a cross-sectional view of a device provided in an embodiment of this application. The process illustrations of the fabrication method given in the embodiments of this application are all based on this... Figure 9 The corresponding cross-sectional diagrams of the devices are provided as examples.

[0035] In some alternative embodiments, when the first gate oxide layer and the second gate oxide layer are formed on the sidewalls of the active region trench by the second thermal oxidation process, at least one first gate oxide layer and at least one second gate oxide layer can also be formed on the sidewalls of each active region trench by the second thermal oxidation process, and the first gate oxide layer and the second gate oxide layer can be arranged alternately.

[0036] Wherein, the first gate oxide layer corresponds to a first length, and the second gate oxide layer corresponds to a second length, and the first length and the second length can be configured in different proportions. For example, as shown... Figure 10 As shown, Figure 10 This is a schematic diagram of another first gate oxide layer and a second gate oxide layer provided in an embodiment of this application, wherein the first length and the second length are configured in a 1:1 ratio, that is, the first length and the second length are the same. Along Figure 10 The cross-sectional view of the device obtained by the dashed lines formed by A and B in the diagram is shown below. Figure 11 As shown, the gate oxide layer thickness on the sidewalls of all active region trenches is 'a', i.e. Figure 11 A schematic diagram of another device cross-section provided in an embodiment of this application; along Figure 10 The cross-sectional view of the device obtained by the dashed lines formed by C and D is shown in the figure. Figure 12 As shown, the gate oxide layer thickness on the sidewalls of all active region trenches is b, i.e. Figure 12 This is a schematic diagram of another device cross-section provided in an embodiment of this application.

[0037] In this embodiment, when the first gate oxide layer and the second gate oxide layer are formed on the sidewalls of the active region trench, they can be formed in different trenches or in the same trench, and different configurations such as length and quantity can be made, which improves the flexibility of forming the first gate oxide layer and the second gate oxide layer and simplifies the process.

[0038] In some alternative embodiments, when performing the second thermal oxidation process, the preset thickness of the first oxide layer on the sidewall of the active area trench can be obtained first, then the first thickness difference between the first target thickness and the preset thickness can be calculated, and the second thickness difference between the second target thickness and the preset thickness can be calculated. Finally, the second thermal oxidation process can be performed based on the first thickness difference and the second thickness difference.

[0039] In particular, the first oxide layer in the area not covered by photoresist has been removed during the above preparation process. That is, the preset thickness in the area not covered by photoresist is 0, so the first thickness difference between the first target thickness and the preset thickness is the first target thickness a. The preset thickness in the area covered by photoresist remains the same. Then the second target thickness b and the preset thickness can be calculated. The second thickness difference between them. Typically, after configuring the oxide layer thickness of the second thermal oxidation process as 'a', the second target thickness 'b' is the difference between 'a' and 'b'. The sum, such as Figure 13 As shown, Figure 13 This is a schematic diagram of a second thermal oxidation process provided in an embodiment of this application.

[0040] Next, gate polysilicon can be deposited, and then etched below the surface of epitaxial layer 2 through chemical mechanical polishing and etching, typically to about 0.1 micrometers below the silicon surface, forming the final gate polysilicon c, such as... Figure 14 As shown, Figure 14 This is a schematic diagram of forming a gate polysilicon according to an embodiment of this application.

[0041] Step 110: Use a photomask to sequentially perform body ion implantation and source ion implantation to form an active region.

[0042] In the process of sequentially performing body ion implantation 8 and source ion implantation 9 using a photomask, a single body ion implantation can be performed using the photomask, wherein the body ion implantation concentration distribution of the first gate oxide layer and the second gate oxide layer is the same. Source ion implantation is then performed using the photomask above the body ion region. For example... Figure 15 As shown, Figure 15 This is a schematic diagram illustrating body ion implantation as provided in an embodiment of this application. Figure 16 As shown, Figure 16 This is a schematic diagram of source ion implantation provided in an embodiment of this application.

[0043] Next, a low-temperature oxide layer 10 and a borosilicate glass layer 11 can be sequentially deposited on the surface of the epitaxial layer, such as... Figure 17 As shown, Figure 17 This is a schematic diagram of a low-temperature oxide layer and a borosilicate glass layer deposited according to an embodiment of this application.

[0044] Then, using a contact hole mask, contact hole 12 is etched to form, as shown. Figure 18 As shown, Figure 18 This is a schematic diagram of an etching process for forming a contact hole, provided as an embodiment of this application.

[0045] Finally, a metal layer can be deposited on the entire surface of the device, and a metal layer structure 13 can be formed by metal layer photolithography, such as... Figure 19 As shown, Figure 19 This is a schematic diagram of a metal layer structure provided in an embodiment of this application.

[0046] This application provides a structure and fabrication method for enhancing the safe operating area capability of a shielded gate trench MOSFET device. The method includes: forming multiple active region trenches on an epitaxial layer located on a semiconductor substrate, forming an inner pad oxide layer on the surface of the epitaxial layer and each active region trench, depositing shielded polysilicon in the trench of each active region trench, etching the shielded polysilicon and the inner pad oxide layer in the trench so that the top of the shielded polysilicon is located outside the inner pad oxide layer, forming a first oxide layer on the sidewall of each active region trench and the top of the shielded polysilicon through a first thermal oxidation process, forming photoresist using a gate oxide photomask, removing the first oxide layer in the area not covered by the photoresist, forming a first gate oxide layer and a second gate oxide layer on the sidewall of the active region trench through a second thermal oxidation process, and forming gate polysilicon, wherein the first target thickness of the first gate oxide layer is less than the second target thickness of the second gate oxide layer, and performing body ion implantation and source ion implantation sequentially using a photomask to form the active region. This solution creates high-threshold voltage cells and low-threshold voltage cells by forming thick and thin gate oxide regions in the active region trench of the MOSFET device. During operation, when the gate-source voltage is low, the low-threshold voltage cells turn on while the high-threshold voltage cells remain off. The partial shutdown of cells reduces the overall power density and enhances heat dissipation, thereby lowering the zero-temperature coefficient point and improving the safe operating area. Essentially, it integrates a device structure with a wide safe operating area in the active region, enhancing its performance. Furthermore, it does not affect the conduction loss even when the device is fully turned on, broadening its application prospects. Moreover, by using the same ion implantation concentration distribution in the thick and thin gate oxide regions, the high-threshold voltage cells and low-threshold voltage cells are achieved due to the different oxide layer thicknesses at the same ion implantation concentration, further enhancing the wide safe operating area characteristic. Additionally, this manufacturing process is simple and compatible with traditional MOSFET manufacturing processes.

[0047] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0048] This application also provides a structure for enhancing the safe operating area capability of a shielded gate trench MOSFET device. This structure is prepared according to the above-described method for enhancing the safe operating area capability of a shielded gate trench MOSFET device. Specific implementation processes and beneficial effects can be found in the above-described method embodiments, and will not be repeated here.

[0049] It is readily understood that, based on the several embodiments provided in this application, those skilled in the art can combine, split, or reorganize the embodiments of this application to obtain other embodiments, none of which exceed the protection scope of this application.

[0050] The above detailed embodiments further illustrate the purpose, technical solution, and beneficial effects of the embodiments of this application. It should be understood that the above are merely specific embodiments of the embodiments of this application and are not intended to limit the protection scope of the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solutions of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A method for fabricating a structure that enhances the safe operating area capability of a shielded gate trench MOSFET device, characterized in that, The method includes: Multiple active region trenches are formed on an epitaxial layer located on a semiconductor substrate, and an inner pad oxide layer is formed on the surface of the epitaxial layer and each of the active region trenches; A shielding polysilicon is deposited in the trench of each active region trench, and the shielding polysilicon and the inner pad oxide layer in the trench are etched so that the top of the shielding polysilicon is located outside the inner pad oxide layer. A first oxide layer is formed on the sidewall of each active region trench and on the top of the shielded polysilicon through a first thermal oxidation process, and a photoresist is formed using a gate oxide photomask to remove the first oxide layer in the area not covered by the photoresist. A first gate oxide layer and a second gate oxide layer are formed on the sidewalls of the active region trench through a second thermal oxidation process, and then gate polysilicon is formed; wherein, the first target thickness of the first gate oxide layer is smaller than the second target thickness of the second gate oxide layer. The active region is formed by sequentially implanting ions into the body region and the source region using a photomask.

2. The method according to claim 1, characterized in that, The process of forming a first gate oxide layer and a second gate oxide layer on the sidewalls of the active region trench through a second thermal oxidation process includes: Through a second thermal oxidation process, at least one first gate oxide layer and at least one second gate oxide layer are formed on the sidewall of each active region trench; wherein the first gate oxide layer corresponds to a first length and the second gate oxide layer corresponds to a second length.

3. The method according to claim 2, characterized in that, The first gate oxide layer and the second gate oxide layer are arranged at intervals.

4. The method according to any one of claims 1-3, characterized in that, The process of forming a first gate oxide layer and a second gate oxide layer on the sidewalls of the active region trench through a second thermal oxidation process further includes: Through a second thermal oxidation process, a first gate oxide layer and a second gate oxide layer are formed on the sidewalls of different active region trenches; wherein, the active region trench forming the first gate oxide layer is called the first trench, and the active region trench forming the second gate oxide layer is called the second trench.

5. The method according to claim 4, characterized in that, The first groove and the second groove are arranged alternately.

6. The method according to any one of claims 1-3, characterized in that, The process of sequentially performing bulk ion implantation and source ion implantation using a photomask includes: A single bulk ion implantation is performed using a photomask, wherein the bulk ion implantation concentration distributions of the first gate oxide layer and the second gate oxide layer are the same. Source ion implantation is performed using a photomask above the ion region of the bulk region.

7. The method according to any one of claims 1-3, characterized in that, The method further includes: Obtain the preset thickness of the first oxide layer on the sidewall of the active region trench; Calculate a first thickness difference between the first target thickness and the preset thickness, and calculate a second thickness difference between the second target thickness and the preset thickness; Based on the first thickness difference and the second thickness difference, a second thermal oxidation process is performed.

8. The method according to any one of claims 1-3, characterized in that, The method further includes: A low-temperature oxide layer and a borosilicate glass layer are sequentially deposited on the surface of the epitaxial layer, and contact holes are formed by etching using a contact hole photomask.

9. The method according to any one of claims 1-3, characterized in that, The method further includes: A metal layer is deposited on the entire surface of the device, and the metal layer structure is formed by metal layer photolithography.

10. A structure for shielding the safe operating area capability of a gate trench MOSFET device, characterized in that, The structure is prepared by the method for preparing a structure that enhances the safe operating area capability of a shielded gate trench MOSFET device according to any one of claims 1-9.

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