Semiconductor structure and preparation method thereof, and semiconductor device

Abstract

The invention discloses a semiconductor structure, a preparation method thereof and a semiconductor device, and belongs to the technical field of semiconductors. The semiconductor structure comprises a substrate which comprises a first surface and a second surface which are oppositely arranged; the groove is recessed from the first surface to the interior of the substrate, and the interface of the groove and the substrate is in a step shape; the buried oxide structure comprises a first buried oxide region and a plurality of second buried oxide regions, the first buried oxide region extends into the substrate from the bottom of the groove, and the second buried oxide regions extend into the substrate from part of the side wall of the groove; the epitaxial layer is arranged in the groove in the buried oxide structure; and the cavity is arranged in the substrate among the epitaxial layer, the first buried oxide region and the second buried oxide region, the depth of the cavity is equal to that of the second buried oxide region, and the atmosphere in the cavity is the same as the atmosphere when the epitaxial layer is formed. According to the semiconductor structure, the preparation method thereof and the semiconductor device provided by the invention, the preparation cost of the semiconductor device can be reduced, and the performance of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor structure, its fabrication method, and a semiconductor device. Background Technology

[0002] Compared to bulk silicon, silicon-on-insulator (SOI) structures, by introducing a buried oxide layer between the substrate and the top silicon layer, can reduce the parasitic capacitance between the source / drain and the substrate in metal-oxide-semiconductor (MOS) devices, thereby reducing short-channel effects and leakage current, and thus optimizing the performance, power consumption, and reliability of semiconductor devices. However, current MOS processes are based on bulk silicon substrates, and there are significant differences between MOS and SOI processes in terms of substrate structure and device physical characteristics, resulting in incompatibility between SOI and MOS processes, which affects the fabrication of SOI MOS devices. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor structure and its fabrication method, as well as a semiconductor device, which can improve the compatibility of SOI and MOS processes, reduce the fabrication cost of SOI MOS devices, physically isolate conductive paths in the substrate, increase the resistivity of the substrate, and greatly reduce substrate losses, thereby improving the performance of the semiconductor structure in terms of high frequency, radio frequency, low power consumption, and signal integrity.

[0004] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution.

[0005] This invention provides a semiconductor structure comprising at least: The substrate includes a first surface and a second surface disposed opposite to each other; The groove is recessed from the first surface into the substrate, and the interface between the groove and the substrate is stepped. The buried oxide structure includes a first buried oxide region and a plurality of second buried oxide regions, wherein the first buried oxide region extends from the bottom of the groove into the substrate, and the second buried oxide regions extend from a portion of the sidewall of the groove into the substrate; An epitaxial layer is disposed within the groove on the buried oxide structure; and A cavity is disposed within the substrate between the epitaxial layer, the first buried oxide region, and the second buried oxide region, and the depth of the cavity is equal to the depth of the second buried oxide region, and the atmosphere in the cavity is the same as the atmosphere during the formation of the epitaxial layer.

[0006] In one embodiment of the present invention, the stepped shape includes at least a first step, a second step, and a connecting portion. The first step is the bottom of the groove, the second step is disposed on both sides of the first step, and the surface of the first step is lower than the surface of the second step, the surface of the second step is lower than the first surface, and the connecting portion connects the first step and the second step.

[0007] In one embodiment of the present invention, the second buried oxide region extends from the connecting portion into the substrate, the first buried oxide region extends from the first layer step into the substrate, and the edge of the first buried oxide region is located in the substrate below the second buried oxide region.

[0008] This invention also proposes a method for fabricating a semiconductor structure, comprising at least the following steps: A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other; A groove is formed in the substrate, the groove is recessed from the first surface into the substrate, and the interface between the groove and the substrate is stepped. The size of the groove decreases in the direction from the first surface to the second surface. An embedded oxide structure is formed within the substrate. The embedded oxide structure includes a first embedded oxide region and a plurality of second embedded oxide regions. The first embedded oxide region extends from the bottom of the groove into the substrate, and the second embedded oxide regions extend from a portion of the sidewall of the groove near the first embedded oxide region into the substrate. An epitaxial layer is formed within the groove on the buried oxide structure; and A cavity is formed in the substrate between the epitaxial layer, the first buried oxide region, and the second buried oxide region.

[0009] In one embodiment of the present invention, the formation of the groove includes at least the following steps: A pad oxide layer is formed on the first surface; A first nitride layer is formed on the pad oxide layer; A portion of the first nitride layer, a portion of the pad oxide layer, and a portion of the substrate are etched to form a recess, the recess being recessed from the first nitride layer into the substrate; A second nitriding layer is formed on the bottom and sidewalls of the recess, and on the first nitriding layer; and The second nitride layer and the substrate within the recess, as well as the first nitride layer and a portion of the second nitride layer on the first surface, or the first nitride layer, the second nitride layer and a portion of the pad oxide layer, are vertically etched, while retaining the second nitride layer on the sidewall of the recess, to form the groove.

[0010] In one embodiment of the present invention, the depth of the vertical etching is greater than the thickness of the second nitride layer, but less than the sum of the thicknesses of the second nitride layer, the first nitride layer, and the pad oxide layer.

[0011] In one embodiment of the present invention, the substrate exposed in the groove is subjected to an oxidation treatment to form the buried oxide structure.

[0012] The present invention also provides a semiconductor device comprising at least: The aforementioned semiconductor structure; A deep well region extends from the first surface into the epitaxial layer and the substrate, and at least extends to contact the second buried oxide region; At least two shallow trench isolation structures are symmetrically arranged in the deep trap region on both sides of the cavity; A trap region is located within the deep trap region between two adjacent shallow trench isolation structures; A gate is disposed on the well region in the cavity; A source doped region is disposed within the well region on one side of the gate; and A drain-doped region is disposed within the well region on the other side of the gate.

[0013] In one embodiment of the present invention, the orthogonal projection of the buried oxide structure and the cavity onto the direction of the first surface falls within the well region between the source doped region and the drain doped region.

[0014] In one embodiment of the present invention, the orthogonal projection of the buried oxide structure and the cavity onto the direction of the first surface extends from the well region between the source doped region and the drain doped region to the source doped region and the drain doped region on both sides.

[0015] In summary, this invention provides a semiconductor structure, its fabrication method, and a semiconductor device. Through improvements to the semiconductor structure and its fabrication method, the unexpected technical effects of this application include the ability to fabricate various types of SOI structures using conventional bulk silicon substrates, increasing the resistivity of the substrate in the SOI structure, and significantly reducing substrate losses. It also improves the compatibility between SOI and MOS processes, thereby reducing the fabrication cost of SOI MOS devices. Furthermore, it reduces the dielectric constant of the substrate, thereby reducing the coupling capacitance between the SOI MOS device and the substrate, and improving the device's isolation, noise figure, and linearity. Finally, it enables the design of both bulk silicon MOS devices and SOI MOS devices on the same bulk silicon substrate, increasing the diversity of product functions.

[0016] Of course, implementing any of the methods of this invention does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the formation of the pad oxide layer, the first nitride layer, and the first photoresist layer.

[0019] Figure 2 This is a schematic diagram of the formation of the concave portion.

[0020] Figure 3 This is a schematic diagram of the formation of the second nitride layer.

[0021] Figure 4 This is a schematic diagram of the groove formation.

[0022] Figure 5 A schematic diagram of the formation of an oxygen-buried structure.

[0023] Figure 6 A schematic diagram illustrating the formation of the epitaxial layer and cavity.

[0024] Figure 7 This is a schematic diagram of a semiconductor structure in one embodiment.

[0025] Figure 8 This is a schematic diagram of a semiconductor structure in another embodiment.

[0026] Figure 9 A schematic diagram illustrating the formation of the protective layer.

[0027] Figure 10 This is a schematic diagram of the formation of a deep trap region.

[0028] Figure 11 This is a schematic diagram of the formation of the third nitride layer.

[0029] Figure 12 This is a schematic diagram of the formation of the second photoresist layer.

[0030] Figure 13 A schematic diagram illustrating the formation of shallow trenches.

[0031] Figure 14 This is a schematic diagram of the formation of the repair layer.

[0032] Figure 15 A schematic diagram for forming an insulating medium.

[0033] Figure 16 A schematic diagram of the planarization of the third nitrided layer and the insulating medium.

[0034] Figure 17 This is a schematic diagram of the formation of the trap region.

[0035] Figure 18 This is a schematic diagram showing the formation of the gate oxide layer and the gate.

[0036] Figure 19 This is a schematic diagram showing the formation of the source lightly doped region and the drain lightly doped region.

[0037] Figure 20 A schematic diagram of the formation of the sidewall.

[0038] Figure 21 This is a schematic diagram of a semiconductor device in one embodiment.

[0039] Figure 22 This is a schematic diagram of a semiconductor device in another embodiment.

[0040] Label Explanation: 10. Substrate; 101. First surface; 102. Second surface; 11. Pad oxide layer; 121. First nitride layer; 122. Second nitride layer; 123. First photoresist layer; 1231. First portion; 1232. Second portion; 124. Recess; 13. Groove; 131. First step layer; 132. Second step layer; 133. Connector; 14. Buried oxide structure; 141. First buried oxide region; 142. Second buried oxide region; 15. Cavity; 16. Epitaxial layer; 17. Protective layer; 18. Deep well region; 19. Third nitride layer; 20. Second photoresist layer; 201. Opening; 21. Shallow trench; 22. Repair layer; 23. Shallow trench isolation structure; 231. Insulating dielectric; 24. Well region; 25. Gate oxide layer; 26. Gate; 27. Source doped region; 271. Lightly doped source region; 272. Heavily doped source region; 28. Drain doped region; 281. Lightly doped drain region; 282. Heavily doped drain region; 29. ​​Sidewall; 291. First sidewall; 292. Second sidewall; 293. Third sidewall; 294. Fourth sidewall. Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0042] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0043] The technical solution of the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] Please see Figure 4 , Figure 7 and Figure 8 As shown, the present invention provides a semiconductor structure, which includes a substrate 10, a groove 13, a buried oxide structure 14, a cavity 15, and an epitaxial layer 16, etc. The substrate 10 includes a first surface 101 and a second surface 102 disposed opposite to each other. A groove 13 is recessed into the substrate 10 from the first surface 101, and the interface between the groove 13 and the substrate 10 is stepped. The size of the groove 13 decreases in the direction from the first surface 101 to the second surface 102. The buried oxide structure 14 includes a first buried oxide region 141 and a plurality of second buried oxide regions 142. The first buried oxide region 141 extends into the substrate 10 from the bottom of the groove 13. The second buried oxide regions 142 extend into the substrate 10 from a portion of the sidewall of the groove 13 near the first buried oxide region 141. An epitaxial layer 16 is disposed in the groove 13 on the buried oxide structure 14. A cavity 15 is disposed in the substrate 10 between the epitaxial layer 16, the first buried oxide region 141 and the second buried oxide regions 142. The depth of the cavity 15 is equal to the depth of the second buried oxide region 142. The atmosphere in the cavity 15 is the same as the atmosphere when the epitaxial layer 16 was formed. In the semiconductor structure provided by the present invention, by introducing a cavity 15 in the substrate 10, the conductive path in the substrate 10 can be physically isolated, the resistivity of the substrate 10 can be increased, and the loss of the substrate 10 can be greatly reduced, thereby improving the performance of the semiconductor structure in high frequency, radio frequency, low power consumption and signal integrity, and increasing the competitiveness of the semiconductor structure in applications such as communication, radar or aerospace electronics.

[0045] Please see Figure 1As shown, this invention also provides a method for fabricating a semiconductor structure, used to prepare various types of SOI structures such as partially depleted silicon-on-insulator (PD SOI) structures and fully depleted silicon-on-insulator (FD SOI) structures. In this embodiment, the method for fabricating the semiconductor structure is described using a PD SOI structure as an example. First, a substrate 10 is provided. The substrate 10 includes a first surface 101 and a second surface 102 disposed opposite to each other. The substrate 10 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafers, or other semiconductor materials formed from III / V compounds. The substrate 10 can be an intrinsic semiconductor, or ions can be implanted into the substrate 10 to form an N-type semiconductor or a P-type semiconductor. Furthermore, this invention does not limit the thickness of the substrate 10. In this embodiment, a method for fabricating a semiconductor structure is described, for example, using a P-type silicon substrate 10. The doping ions in the P-type silicon substrate 10 are, for example, boron (B) or boron fluoride (BF2). + P-type ions such as indium (In) or indium (In).

[0046] Please see Figure 1 As shown, in one embodiment of the present invention, a pad oxide layer 11 is formed on the first surface 101. The pad oxide layer 11 is, for example, made of a material such as silicon oxide, and the thickness of the pad oxide layer 11 is, for example, 10nm-50nm, specifically, 25nm, 35nm, 40nm, 45nm, or 50nm. The pad oxide layer 11 is formed, for example, by thermal oxidation, in-situ water vapor growth, or chemical vapor deposition. Specifically, for example, after placing the substrate 10 in a furnace tube at a temperature of, for example, 900°C-1150°C, oxygen is introduced, and the substrate 10 reacts with oxygen at a high temperature to generate a dense pad oxide layer 11.

[0047] Please see Figure 1As shown, in one embodiment of the present invention, after forming the pad oxide layer 11, a first nitride layer 121 is formed on the pad oxide layer 11. The first nitride layer 121 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide. The thickness of the first nitride layer 121 is, for example, 50nm-120nm, specifically, for example, 60nm, 75nm, 80nm, 100nm, 110nm or 120nm. The first nitride layer 121 is formed, for example, by a method such as low pressure chemical vapor deposition (LPCVD). Specifically, for example, the substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia, and the reaction is carried out at a pressure of, for example, 2 Torr-10 Torr and a temperature of, for example, 700°C-800°C, to deposit the first nitride layer 121. Among them, the pad oxide layer 11 and the first nitride layer 121 can serve as masks during the subsequent formation of the groove 13, protecting other parts of the substrate 10 from damage when etching the substrate 10.

[0048] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the first nitride layer 121, photoresist is formed on the first nitride layer 121 by, for example, spin coating or spray coating. After exposure and development processes, the photoresist is patterned to form the first photoresist layer 123. The first photoresist layer 123 includes a first portion 1231 and a second portion 1232. The first portion 1231 and the second portion 1232 are disposed at intervals on the first nitride layer 121 and expose a portion of the first nitride layer 121.

[0049] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, using a first photoresist layer 123 as a mask, the exposed first nitride layer 121, pad oxide layer 11, and part of the substrate 10 are etched to form a recess 124. The first photoresist layer 123 is then removed, for example, by an ashing process, followed by, for example, by wet cleaning, to remove any residual polymer within the recess 124 from the etching process. The recess 124 is recessed into the substrate 10 from the first nitride layer 121, and the present invention does not limit the distance between the bottom of the recess 124 and the second surface 102, which can be selected according to the type and requirements of the SOI structure. In this embodiment, the distance between the bottom of the recess 124 and the second surface 102 is, for example, smaller than the distance between the bottom of the recess 124 and the first surface 101.

[0050] Please see Figures 2 to 3As shown, in one embodiment of the present invention, after the recess 124 is formed, a second nitride layer 122 is formed on the bottom and sidewalls of the recess 124 and on the first nitride layer 121. The second nitride layer 122 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide. The second nitride layer 122 is formed, for example, by chemical vapor deposition or atomic layer deposition. The present application does not limit the thickness of the second nitride layer 122, and it can be selected according to actual needs.

[0051] Please see Figures 3 to 4 As shown, in one embodiment of the present invention, after forming the second nitride layer 122, the second nitride layer 122 and the substrate 10, as well as the nitride layer or nitride layer and part of the pad oxide layer 11 on the first surface 101, are vertically etched in the direction from the first surface 101 to the second surface 102, while retaining the second nitride layer 122 on the sidewall of the recess 124. The depth of the vertical etching is, for example, greater than the thickness of the second nitride layer 122, but less than the sum of the thicknesses of the second nitride layer 122, the first nitride layer 121, and the pad oxide layer 11. In this embodiment, the depth of the vertical etching is, for example, greater than the thickness of the second nitride layer 122, but less than the sum of the thicknesses of the second nitride layer 122 and the first nitride layer 121.

[0052] Please see Figure 4 As shown, in one embodiment of the present invention, after vertical etching of the nitride layer and the substrate 10, a groove 13 is formed in the substrate 10. The interface between the groove 13 and the substrate 10 is, for example, stepped, and the size of the groove 13 decreases in the direction from the first surface 101 to the second surface 102. The number of stepped layers is, for example, at least two. In this embodiment, the stepped structure is, for example, two layers, including, for example, a first step 131, a second step 132, and a connecting portion 133. The first step 131 is the interface between the bottom of the groove 13 and the substrate 10. The second step 132 is, for example, symmetrically arranged on both sides of the first step 131, and the surface of the first step 131 is lower than the surface of the second step 132. The surface of the second step 132 is lower than the first surface 101. The connecting portion 133 connects the first step 131 and the second step 132.

[0053] Please see Figures 4 to 5As shown, in one embodiment of the present invention, after the groove 13 is formed, the substrate 10 exposed within the groove 13 is oxidized, for example, by Rapid Thermal Processing (RTP) and In-Situ Steam Generation (ISSG) processes to obtain a buried oxide structure 14. Specifically, the substrate 10 with the groove 13, the second nitride layer 122, the first nitride layer 121, and the pad oxide layer 11 is placed in an RTP device, and after hydrogen and oxygen are introduced, it is rapidly heated to, for example, 1000°C-1500°C, and the silicon in the substrate 10 exposed within the groove 13 is oxidized in situ to form the buried oxide structure 14. The thickness of the buried oxide structure 14 is, for example, 100nm-200nm. The buried oxide structure 14 includes a first buried oxide region 141 and a second buried oxide region 142. The first buried oxide region 141 extends from the bottom of the groove 13, i.e., the first step 131, into the substrate 10 to a second depth. There are, for example, multiple second buried oxide regions 142, which extend from a portion of the sidewall of the groove 13 into the substrate 10 to a first depth. Specifically, in this embodiment, a second buried oxide region 142 is provided on each side of the first buried oxide region 141, and the second buried oxide region 142 extends from the connecting portion 133 into the substrate 10 to a first depth. Further, the edge of the first buried oxide region 141 is located in the substrate 10 below the second buried oxide region 142, that is, the length of the first buried oxide region 141 is greater than the length of the bottom of the groove 13. The first buried oxide region 141 and the second buried oxide region 142 are continuously arranged, and the first depth and the second depth are equal.

[0054] Please see Figures 5 to 6 As shown, in one embodiment of the present invention, after the buried oxide structure 14 is formed, the first nitride layer 121 and the second nitride layer 122 are removed. The nitride layer is removed, for example, by a wet etching method, and the wet etching solution is, for example, a hot phosphoric acid aqueous solution, the temperature of the hot phosphoric acid is, for example, 160°C-180°C, and the concentration of the hot phosphoric acid is, for example, 85wt%-90wt%.

[0055] Please see Figures 4 to 6As shown, in one embodiment of the present invention, after removing the nitride layer, lateral epitaxial growth is performed in the groove 13 to form an epitaxial layer 16, which fills the groove 13 on the second buried oxide region 142. Specifically, the epitaxial layer 16 extends from the second step 132 into the groove 13 on the second buried oxide region 142 until it is flush with the first surface 101 and connects the substrate 10 on both sides of the groove 13. The thickness of the epitaxial layer 16 is, for example, 50nm-200nm. In this embodiment, the epitaxial layer 16 is formed, for example, by molecular beam epitaxy (MBE). Specifically, for example, the substrate 10 with the buried oxide structure 14 and the pad oxide layer 11 is placed in the MBE growth chamber, and then the MBE growth chamber is evacuated to make the atmosphere inside the MBE growth chamber a vacuum. Then, a silicon atom beam is sprayed into the groove 13, and lateral epitaxial growth is performed in the groove 13. In another embodiment of the present invention, the epitaxial layer 16 is formed, for example, by a vapor phase epitaxy method. Specifically, for example, a substrate 10 with a buried oxide structure 14 and a pad oxide layer 11 is placed in an epitaxial growth reactor, and then a silicon source gas and a reducing gas are introduced into the epitaxial growth reactor and heated. The silicon source gas is reduced to silicon atoms, and the silicon atoms undergo lateral epitaxial growth within the groove 13. The silicon source gas includes, for example, at least one of silane and dichlorosilane, and the reducing gas includes, for example, hydrogen. The heating temperature is, for example, 800°C-1200°C.

[0056] Please see Figure 6As shown, in one embodiment of the present invention, after the epitaxial layer 16 is formed, a cavity 15 is naturally formed between the epitaxial layer 16, the first buried oxide region 141, and the second buried oxide region 142. The atmosphere in the cavity 15 is the same as the atmosphere during the formation of the epitaxial layer 16. Specifically, when the epitaxial layer 16 is formed using the MBE method, the atmosphere in the cavity 15 is, for example, a vacuum; when the epitaxial layer 16 is formed using a vapor phase epitaxy method, the atmosphere in the cavity 15 is, for example, a silicon source gas and a reducing gas. Since silicon dioxide has a dielectric constant of 3.9-4.2, by setting a cavity 15 within the substrate 10, and ensuring that the cavity 15 contains only gas and is not filled with silicon dioxide or other materials, a cavity 15 with a dielectric constant of approximately 1.006 can be obtained, which is much smaller than the dielectric constant of silicon dioxide. This reduces the overall dielectric constant of the semiconductor structure and physically isolates the conductive paths in the substrate 10, increasing the resistivity of the substrate 10 and reducing its losses. Consequently, this improves the performance of the semiconductor structure in high-frequency, radio frequency, low-power, and signal integrity aspects, increasing its competitiveness in applications such as communications, radar, and aerospace electronics. Furthermore, since the depth of the cavity 15 is equal to the depth of the second buried oxide region 142, the volume within the cavity 15 can be adjusted according to the depth of the second buried oxide region 142, thereby regulating the amount of atmosphere filling the cavity 15. This alters the degree to which the cavity 15 reduces the dielectric constant of the semiconductor structure, further optimizing the performance of the semiconductor structure in high-frequency, radio frequency, low-power, and signal integrity aspects.

[0057] Please see Figures 6 to 7 As shown, in one embodiment of the present invention, after forming the cavity 15, the pad oxide layer 11 is removed to obtain a PD SOI structure. The pad oxide layer 11 is removed, for example, by wet etching. The wet etching solution includes, for example, hydrofluoric acid and water, and the volume ratio of hydrofluoric acid to water is, for example, 1:(50-100).

[0058] Please see Figure 8 As shown, based on the above-described fabrication method, this invention also provides another semiconductor structure, such as an FD SOI structure. The thickness of the epitaxial layer 16 is, for example, 5 nm-10 nm, and the thickness of the buried oxide structure 14 is, for example, 10 nm-25 nm. Using the fabrication method provided by this invention, various types of SOI structures, such as PD SOI and FD SOI, can be fabricated using a bulk silicon substrate 10, reducing the cost of SOI structures.

[0059] Please see Figure 4 , Figure 7 , Figure 8 , Figure 21 and Figure 22As shown, based on the above-described semiconductor structure, the present invention also provides a semiconductor device, including a semiconductor structure, a deep well region 18, a shallow trench isolation structure 23, a well region 24, a gate 26, a source doped region 27, and a drain doped region 28. The deep well region 18 extends from the first surface 101 into the epitaxial layer 16 and the substrate 10, and extends at least to contact the second buried oxide region 142. The shallow trench isolation structures 23 are symmetrically disposed within the deep well regions 18 on both sides of the cavity 15. The well region 24 is disposed within the deep well region 18 between two adjacent shallow trench isolation structures 23. The gate 26 is disposed on the well region 24 on the cavity 15. The source doped region 27 is disposed within the well region 24 on one side of the gate 26, and the drain doped region 28 is disposed within the well region 24 on the other side of the gate 26. In the semiconductor device provided by this invention, by combining SOI and MOS processes to process the bulk silicon substrate 10, an SOI MOS device can be obtained, thereby improving the compatibility of SOI and MOS processes, reducing the fabrication cost of the SOI MOS device, and, since the semiconductor structure contains a cavity 15, the coupling capacitance between the SOI MOS device and the substrate 10 can be reduced, improving the device's isolation, noise figure, and linearity. The SOI MOS device can be an N-type metal-oxide-semiconductor (NMOS) device or a P-type metal-oxide-semiconductor (PMOS) device, and can also be used to fabricate complementary metal-oxide-semiconductor (CMOS) devices. In this embodiment, an SOI NMOS device is used as an example to illustrate the structure and fabrication process of the semiconductor device.

[0060] Please see Figure 7 and Figure 8 As shown, in one embodiment of the present invention, the semiconductor structure is, for example, a PD SOI structure or an FD SOI structure. In this embodiment, the semiconductor device is described using a PD SOI structure as an example.

[0061] Please see Figure 7 and Figure 9As shown, in one embodiment of the present invention, a protective layer 17 is formed on the first surface 101 of the semiconductor structure, covering the epitaxial layer 16 and the substrate 10. The protective layer 17 is, for example, a dense silicon oxide material, and its thickness is, for example, 30 Å-60 Å, specifically 50 Å, 55 Å, or 60 Å. It can be formed, for example, by thermal oxidation, in-situ water vapor growth, or chemical vapor deposition. In this embodiment, the semiconductor structure is placed in a furnace tube at a temperature of, for example, 900°C-1150°C, and oxygen is introduced. The substrate 10 and the epitaxial layer 16 react with the oxygen at a high temperature to generate the protective layer 17. By providing the protective layer 17, the surface of the semiconductor structure can be protected from damage during subsequent ion implantation.

[0062] Please see Figures 9 to 10 As shown, in one embodiment of the present invention, after forming the protective layer 17, first ions are implanted into the semiconductor structure from the first surface 101 to form a deep well region 18. The deep well region 18 extends from the first surface 101 into the epitaxial layer 16 and the substrate 10, and extends at least to contact the second buried oxide region 142. In this embodiment, the interface of the deep well region 18 in the semiconductor structure contacts the top of the second buried oxide region 142. The first ion is, for example, an N-type ion such as phosphorus (P) or arsenic (As). The implantation energy of the first ion is, for example, 2MeV-4MeV, and the implantation dose of the first ion is, for example, 1×10⁻⁶. 15 ions / cm 2 -2×10 12 ions / cm 2 .

[0063] Please see Figures 10 to 11 As shown, in one embodiment of the present invention, after forming the deep well region 18, a third nitride layer 19 is formed on the protective layer 17. The third nitride layer 19 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide. The third nitride layer 19 is formed, for example, by LPCVD. The thickness of the third nitride layer 19 can be selected according to actual needs.

[0064] Please see Figures 11 to 12 As shown, in one embodiment of the present invention, after forming the third nitride layer 19, photoresist is formed on the third nitride layer 19, for example, by spin coating or spray coating. After exposure and development processes, the photoresist is patterned to form a second photoresist layer 20. The second photoresist layer 20 covers a portion of the third nitride layer 19, and openings 201 are formed within the second photoresist layer 20. For example, there are at least two openings 201, located on both sides of the buried oxide structure 14. In this embodiment, for example, there are two openings 201, which are symmetrically arranged and expose portions of the third nitride layer 19 on both sides of the buried oxide structure 14.

[0065] Please see Figures 12 to 13As shown, in one embodiment of the present invention, using the second photoresist layer 20 as a mask, the exposed third nitride layer 19, protective layer 17, and part of the deep well region 18 are etched to form shallow trenches 21, and then the second photoresist layer 20 is removed. The shallow trenches 21 may be at least two. In this embodiment, for example, there are two shallow trenches 21, symmetrically arranged on both sides of the buried oxide structure 14, extending from the third nitride layer 19 into the deep well region 18, with the bottom of the shallow trenches 21 located within the deep well region 18.

[0066] Please see Figures 13 to 14 As shown, in one embodiment of the present invention, after the shallow trench 21 is formed, the inner wall of the shallow trench 21 is oxidized, for example, by an RTP process, to form a repair layer 22, so as to repair the damage to the deep well region 18 caused by etching during the formation of the shallow trench 21. The repair layer 22 may include materials such as silicon oxide, and the thickness of the repair layer 22 can be set according to actual needs.

[0067] Please see Figures 14 to 15 As shown, in one embodiment of the present invention, after forming the repair layer 22, an insulating medium 231 is deposited on the repair layer 22 until it completely fills the shallow trench 21 and covers the surface of the third nitride layer 19. Then, an annealing treatment is performed to improve the density of the insulating medium 231. The insulating medium 231 is deposited, for example, by high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect-ratio process chemical vapor deposition (HARP-CVD). The material of the insulating medium 231 can be silicon oxide, which has high adaptability to abrasion, or it can be an insulating material such as fluorosilicone glass.

[0068] Please see Figures 15 to 16 As shown, in one embodiment of the present invention, after depositing the insulating medium 231, the insulating medium 231 is planarized, for example by using a chemical mechanical polishing (CMP) process to perform non-selective grinding to planarize the insulating medium 231 and the third nitride layer 19, so that the insulating medium 231 and the protective layer 17 have the same height.

[0069] Please see Figure 13 , Figures 16 to 17As shown, in one embodiment of the present invention, after planarizing the insulating medium 231, a second ion is injected from the first surface 101 into the deep well region 18 between the two shallow trenches 21 to form a well region 24. The well region 24 extends from the first surface 101 into the deep well region 18. The distance between the bottom of the well region 24 and the bottom of the deep well region 18 is, for example, greater than the distance between the bottom of the shallow trenches 21 and the bottom of the deep well region 18. The type of the second ion is, for example, opposite to the type of the first ion, and the second ion is, for example, B or BF2. + Or P-type ions such as In, the second ion is implanted multiple times. In this embodiment, for example, the trap region 24 is formed by implanting the second ion four times. Specifically, during the first implantation, the implantation energy of the second ion is, for example, 100 keV-150 keV, and the implantation dose of the second ion is, for example, 3 × 10⁻⁶. 13 ions / cm 2 -4×10 13 ions / cm 2 During the second implantation, the implantation energy of the second ion is, for example, 50 keV-100 keV, and the implantation dose of the second ion is, for example, 6 × 10⁻⁶. 12 ions / cm 2 -9×10 12 ions / cm 2 During the third implantation, the implantation energy of the second ion is, for example, 20 keV-50 keV, and the implantation dose of the second ion is, for example, 3 × 10⁻⁶. 12 ions / cm 2 -5×10 12 ions / cm 2 During the fourth implantation, the implantation energy of the second ion is, for example, 20 keV-30 keV, and the implantation dose of the second ion is, for example, 6 × 10⁻⁶. 12 ions / cm 2 -7×10 12 ions / cm 2 .

[0070] Please see Figures 17 to 18 As shown, in one embodiment of the present invention, after forming the well region 24, the insulating medium 231 and the protective layer 17 on the first surface 101 are removed, and the remaining insulating medium 231 is defined as the shallow trench isolation structure 23. The removal of the insulating medium 231 and the protective layer 17 is performed, for example, using CMP processes or etching methods.

[0071] Please see Figure 18As shown, in one embodiment of the present invention, after forming the shallow trench isolation structure 23, an oxide material is deposited on the first surface 101. After the oxide material covers the first surface 101, a gate material is deposited on the oxide material. After the gate material covers the oxide material, photoresist is formed on the gate material, for example by spin coating or spray coating. After exposure and development processes, the photoresist is patterned to form a patterned photoresist layer (not shown in the figure). The patterned photoresist layer covers part of the gate material on the cavity 15. Using the patterned photoresist layer as a mask, the exposed oxide material and gate material are etched. The remaining oxide material is defined as the gate oxide layer 25, and the remaining gate material is defined as the gate 26. Then the patterned photoresist layer is removed. The gate oxide layer 25 and the gate 26 are disposed on a portion of the well region 24 on the cavity 15. The material of the gate oxide layer 25 includes, for example, silicon oxide, and the material of the gate 26 includes, for example, polysilicon. The thickness of the gate oxide layer 25 is, for example, 2nm-10nm, and the thickness of the gate 26 is, for example, 200nm-250nm.

[0072] Please see Figures 18 to 19 As shown, in one embodiment of the present invention, after the gate 26 is formed, third ions are implanted from the first surface 101 into the well regions 24 on both sides of the gate 26 to form a lightly doped source region 271 and a lightly doped drain region 281. The lightly doped source region 271 is located in the well region 24 between one sidewall of the gate 26 and the adjacent shallow trench isolation structure 23, and the lightly doped drain region 281 is located in the well region 24 between the other sidewall of the gate 26 and the adjacent shallow trench isolation structure 23. The type of the third ion is opposite to that of the second ion; the third ion is, for example, an N-type ion such as P or As.

[0073] Please see Figures 19 to 20As shown, in one embodiment of the present invention, after forming the source light doped region 271 and the drain light doped region 281, sidewalls 29 are formed on the first surface 101 on both sides of the gate 26 and the gate oxide layer 25. The sidewalls 29 extend from the sidewalls of the gate 26 and the gate oxide layer 25 to a portion of the source light doped region 271 and a portion of the drain light doped region 281. Specifically, a first layer of material is first deposited on the substrate 10 and the gate 26. Then, a second layer of material is deposited on the first layer of material, a third layer of material is deposited on the second layer of material, and a fourth layer of material is deposited on the third layer of material. After that, the fourth layer of material, the third layer of material, the second layer of material, and the first layer of material on the gate 26 and part of the substrate 10 are removed by processes such as dry etching or wet etching. The four layers of material on both sides of the gate 26 and the gate oxide layer 25 are retained. The retained first layer of material is defined as the first sidewall 291, the second layer of material is defined as the second sidewall 292, the third layer of material is defined as the third sidewall 293, and the fourth layer of material is defined as the fourth sidewall 294. The first sidewall 291, the second sidewall 292, the third sidewall 293, and the fourth sidewall 294 are defined as sidewall 29. The materials of the first sidewall 291 and the third sidewall 293 include, for example, silicon oxide, and the materials of the second sidewall 292 and the fourth sidewall 294 include, for example, silicon nitride. The thicknesses of the first sidewall 291, the second sidewall 292, the third sidewall 293 and the fourth sidewall 294 can be equal or unequal, depending on the actual situation.

[0074] Please see Figures 20 to 21 As shown, in one embodiment of the present invention, after forming the sidewall 29, a fourth ion is implanted from the first surface 101 into the source lightly doped region 271 and the drain lightly doped region 281 on both sides of the sidewall 29 to form the source heavily doped region 272 and the drain heavily doped region 282. The source lightly doped region 271 and the source heavily doped region 272 are defined as source doped region 27, and the drain lightly doped region 281 and the drain heavily doped region 282 are defined as drain doped region 28. The source heavily doped region 272 extends from the first surface 101 into the source lightly doped region 271, and the drain heavily doped region 282 extends from the first surface 101 into the drain lightly doped region 281. The fourth ion is of the same type as the third ion, for example, an N-type ion such as P or As, and the implantation energy and implantation dose of the fourth ion are greater than those of the third ion.

[0075] Please see Figures 21 to 22 As shown, the relative positions of the buried oxide structure 14, cavity 15, source doped region 27, and drain doped region 28 are not limited in this invention and can be selected according to actual conditions. Please refer to... Figure 21 As shown, in this embodiment, the orthogonal projection of the buried oxide structure 14 and the cavity 15 in the direction of the first surface 101 extends from the well region 24 between the source doped region 27 and the drain doped region 28 to the source doped region 27 and the drain doped region 28 on both sides. Please refer to... Figure 22 As shown, in another embodiment of the present invention, the orthogonal projection of the buried oxide structure 14 and the cavity 15 in the direction of the first surface 101 falls within the well region 24 between the source doped region 27 and the drain doped region 28.

[0076] Please see Figures 1 to 22 As shown, in the semiconductor device provided by this invention, it is not necessary to purchase a wafer with an SOI structure as a substrate 10. SOI and MOS processes can be performed sequentially on the bulk silicon substrate 10 to obtain an SOI MOS device, improving the compatibility of SOI and MOS processes and reducing the production cost of the semiconductor device. Furthermore, since the SOI structure provided by this invention contains a cavity 15, the dielectric constant of the substrate 10 can be reduced, thereby reducing the coupling capacitance between the SOI MOS device and the substrate 10 and improving the device's isolation, noise figure, and linearity. In addition, through regionalized structural design, the SOI MOS device and the bulk silicon MOS device provided by this invention can be integrated on the same chip, increasing the versatility of device product functions.

[0077] In summary, this invention provides a semiconductor structure, its fabrication method, and a semiconductor device. By introducing cavities into the semiconductor structure, this application achieves unexpected technical effects, including increased substrate resistivity, reduced substrate losses, and improved performance of the semiconductor device such as isolation, noise figure, and linearity. Furthermore, the semiconductor structure, its fabrication method, and the semiconductor device provided by this invention improve the compatibility of SOI and MOS processes and reduce the fabrication cost of SOI MOS devices.

[0078] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor structure, characterized in that, At least including: The substrate includes a first surface and a second surface disposed opposite to each other; The groove is recessed from the first surface into the substrate, and the interface between the groove and the substrate is stepped. The buried oxide structure includes a first buried oxide region and a plurality of second buried oxide regions, wherein the first buried oxide region extends from the bottom of the groove into the substrate, and the second buried oxide regions extend from a portion of the sidewall of the groove into the substrate; An epitaxial layer is disposed within the groove on the buried oxide structure; and A cavity is disposed within the substrate between the epitaxial layer, the first buried oxide region, and the second buried oxide region, and the depth of the cavity is equal to the depth of the second buried oxide region, and the atmosphere in the cavity is the same as the atmosphere during the formation of the epitaxial layer.

2. The semiconductor structure according to claim 1, characterized in that, The stepped shape includes at least a first step, a second step, and a connecting part. The first step is the bottom of the groove, the second step is disposed on both sides of the first step, and the surface of the first step is lower than the surface of the second step, the surface of the second step is lower than the first surface, and the connecting part connects the first step and the second step.

3. The semiconductor structure according to claim 2, characterized in that, The second buried oxide region extends from the connecting portion into the substrate, the first buried oxide region extends from the first layer step into the substrate, and the edge of the first buried oxide region is located in the substrate below the second buried oxide region.

4. A method for fabricating a semiconductor structure, characterized in that, At least the following steps are included: A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other; A groove is formed in the substrate, the groove is recessed from the first surface into the substrate, and the interface between the groove and the substrate is stepped. The size of the groove decreases in the direction from the first surface to the second surface. An embedded oxide structure is formed within the substrate. The embedded oxide structure includes a first embedded oxide region and a plurality of second embedded oxide regions. The first embedded oxide region extends from the bottom of the groove into the substrate, and the second embedded oxide regions extend from a portion of the sidewall of the groove near the first embedded oxide region into the substrate. An epitaxial layer is formed within the groove on the buried oxide structure; and A cavity is formed in the substrate between the epitaxial layer, the first buried oxide region, and the second buried oxide region.

5. The preparation method according to claim 4, characterized in that, The formation of the groove includes at least the following steps: A pad oxide layer is formed on the first surface; A first nitride layer is formed on the pad oxide layer; A portion of the first nitride layer, a portion of the pad oxide layer, and a portion of the substrate are etched to form a recess, the recess being recessed from the first nitride layer into the substrate; A second nitriding layer is formed on the bottom and sidewalls of the recess, and on the first nitriding layer; and The second nitride layer and the substrate within the recess, as well as the first nitride layer and a portion of the second nitride layer on the first surface, or the first nitride layer, the second nitride layer and a portion of the pad oxide layer, are vertically etched, while retaining the second nitride layer on the sidewall of the recess, to form the groove.

6. The preparation method according to claim 5, characterized in that, The depth of the vertical etching is greater than the thickness of the second nitride layer, but less than the sum of the thicknesses of the second nitride layer, the first nitride layer, and the pad oxide layer.

7. The preparation method according to claim 4, characterized in that, The substrate exposed within the groove is subjected to an oxidation treatment to form the buried oxide structure.

8. A semiconductor device, characterized in that, At least including: The semiconductor structure according to any one of claims 1-3; The deep well region extends from the first surface into the epitaxial layer and the substrate, and extends at least to contact the second buried oxide region; At least two shallow trench isolation structures are symmetrically arranged in the deep trap region on both sides of the cavity; A trap region is located within the deep trap region between two adjacent shallow trench isolation structures; A gate is disposed on the well region in the cavity; A source doped region is disposed within the well region on one side of the gate; as well as A drain-doped region is disposed within the well region on the other side of the gate.

9. The semiconductor device according to claim 8, characterized in that, The orthogonal projection of the buried oxide structure and the cavity onto the direction of the first surface falls within the well region between the source doped region and the drain doped region.

10. The semiconductor device according to claim 8, characterized in that, The orthogonal projection of the buried oxide structure and the cavity onto the direction of the first surface extends from the well region between the source doped region and the drain doped region to the source doped region and the drain doped region on both sides.

Images