Semiconductor chamber assembly with advanced coating technology

Abstract

The present technology generally relates to semiconductor processing systems and methods. Systems and methods include a chamber having a plurality of chamber components, such as a susceptor, a lid stack, a panel, an electrode, and a showerhead. The panel is supported by the cover stack and defines a plurality of first apertures, and the showerhead is located between the panel and the base and defines a plurality of second apertures. In systems and methods, the panel, showerhead, cover stack, susceptor, or a combination thereof includes a coating of yttrium fluoride, yttrium oxyfluoride, or yttrium fluoride and yttrium oxyfluoride having a thickness greater than 10 [mu] m over at least a portion of the individual chamber components, or a combination thereof.

Description

Technical Field

[0001] This application claims the benefit and priority of U.S. Patent Application No. 18 / 181,077, filed March 9, 2023, entitled “SEMICONDUCTOR CHAMBER COMPONENTS WITH ADVANCED COATING TECHNIQUES”, the entire contents of which are incorporated herein by reference.

[0002] This technology relates to semiconductor systems, processes, and equipment. More specifically, this technology relates to systems that include or form a coating on a chamber component. Background Technology

[0003] Integrated circuits are made possible by processes that create complex patterned material layers on the surface of a substrate. Creating patterned material on the substrate requires controlled methods for removing exposed material. Chemical etching is used for various purposes, including transferring patterns from photoresist to underlying layers, thinning layers, or thinning the lateral dimensions of features already present on the surface. It is generally desirable to have etching processes that etch one material faster than another, thereby facilitating processes such as pattern transfer. Such etching processes are claimed to be selective for the first material. Due to the diversity of materials, circuits, and processes, etching processes have evolved to be selective for a wide range of materials.

[0004] Depending on the materials used in the process, etching processes can be called wet or dry etching. Wet HF etching preferentially removes silicon oxide compared to other dielectrics and materials. However, wet processes may struggle to penetrate certain confined trenches and can sometimes distort the remaining material. Wet processes can also damage chamber components. For example, HF etchants can chemically erode chamber components made of metals such as aluminum alloys. Dry etching, generated in the regional plasma formed within the substrate processing area, can penetrate more confined trenches and refines the remaining structure with less distortion. However, regional plasma can damage the substrate by generating an electric arc during discharge. Regional plasma and plasma effluent can also damage chamber components.

[0005] Therefore, there is a need for improved systems and methods for producing high-quality devices and structures. This technology addresses these and other needs. Summary of the Invention

[0006] This technology is generally implemented for semiconductor processing systems. The system includes a chamber having multiple chamber components, such as a base, a capping layer, a panel, and a spray nozzle. In the system, the base is configured to support a semiconductor substrate. In the system, the panel is supported by the capping layer and defines a plurality of first holes. In one embodiment, the spray nozzle is located between the panel and the base and defines a plurality of second holes. In the system, the panel, spray nozzle, capping layer, base, or a combination thereof includes a yttrium fluoride, yttrium oxyfluoride, or a yttrium fluoride and yttrium oxyfluoride coating, which has a thickness greater than 10 μm or less than about 100 nm on at least a portion of each chamber component or combination thereof.

[0007] In one embodiment, a panel, a spray head, or both a panel and a spray head define a surface facing the chamber, the surface having an exposed surface with an exposed surface area, wherein greater than or about 80% of the exposed surface area comprises a yttrium fluoride, yttrium oxyfluoride, or a coating of yttrium fluoride and yttrium oxyfluoride. In further embodiments, greater than or about 90% of the exposed surface area of ​​the panel, the spray head, or both a panel and a spray head comprises a yttrium fluoride, yttrium oxyfluoride, or a coating of yttrium fluoride and yttrium oxyfluoride. Furthermore, in another embodiment, the yttrium fluoride, yttrium oxyfluoride, or yttrium fluoride and yttrium oxyfluoride coating has a thickness greater than or about 50 μm on at least a portion of each chamber component or combination thereof. Additionally or alternatively, in embodiments, a plurality of first holes, a plurality of second holes, or a combination of both define a hole surface having a hole surface area, wherein greater than or about 70% of the hole surface area comprises yttrium fluoride, yttrium oxyfluoride, or a coating of yttrium fluoride and yttrium oxyfluoride. In further embodiments, the yttrium fluoride, yttrium oxyfluoride, or yttrium fluoride and yttrium oxyfluoride coating on the hole surface further comprises yttrium oxide, YOFx, or a combination of both.

[0008] Embodiments of this technology also include a method of coating a semiconductor processing chamber component. The method includes positioning a component having an exposed surface within the chamber. The method includes depositing a coating comprising yttrium oxide on at least a portion of the exposed surface. The method includes exposing the coating to a high-power plasma process with a power greater than or approximately 2 watts and a pressure of 500 millitor. The method includes: the high-power plasma process comprising infusing a fluorinated precursor into the chamber, forming plasma from the fluorinated precursor to generate plasma effluent, and contacting the coating surface with the plasma effluent. The method includes converting at least a portion of the yttrium oxide in the coating to yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride.

[0009] In embodiments, the plasma further comprises hydrogen, ammonia, helium, argon, or combinations thereof. In more embodiments, the fluorine-containing precursor comprises nitrogen trifluoride. In more embodiments, the method includes depositing yttrium oxide via atomic layer deposition, plasma spraying, electron beam deposition, chemical vapor deposition, physical vapor deposition, plasma-enhanced chemical vapor deposition, or a combination thereof. In more embodiments, yttrium oxide is deposited via a combination of atomic layer deposition and plasma spraying or electron beam deposition. Additionally or alternatively, in embodiments, the component defines a plurality of holes, each hole having an exposed hole surface, wherein a coating is deposited on at least a portion of the exposed hole surface. In more embodiments, the high-power plasma process includes a power of about 10 watts to about 3000 watts, a pressure of about 1 Torr to about 15 Torr, and a voltage of about 10 volts to about 1000 volts. In embodiments, the high-power plasma process is performed for a period of time sufficient to convert at least about 50% by weight of yttrium oxide into yttrium fluoride, yttrium oxyfluoride, or yttrium fluoride and yttrium oxyfluoride. In many embodiments, the high-power plasma process is performed for at least about 1 hour. In many other embodiments, the high-power plasma process is performed for a period of time sufficient to provide a coating with a thickness greater than or about 1 μm.

[0010] This technology also relates generally to a method for coating one or more components of a semiconductor processing chamber. The method includes positioning a plurality of chamber components having exposed surfaces within the semiconductor processing chamber. The method includes: the components being a panel defining a plurality of first orifices and a spray head defining a plurality of second orifices. The method includes depositing a coating comprising yttrium oxide on at least a portion of the exposed surfaces of the plurality of chamber components. The method includes converting at least a portion of the yttrium oxide into yttrium fluoride, yttrium oxyfluoride, or a combination of yttrium fluoride and yttrium oxyfluoride within the semiconductor processing chamber.

[0011] In one embodiment, the plurality of chamber components further include a cover layer supporting the panel and a base configured to support the semiconductor substrate. In other embodiments, the method is performed under pressure. In further embodiments, the semiconductor processing chamber further includes a first electrode and a second electrode, wherein the first electrode and the second electrode are configured to provide at least about 2 watts of power during conversion.

[0012] Compared to conventional systems and techniques, this type of technology offers numerous advantages. For example, embodiments of this technology can protect even hard-to-reach parts of the chamber, such as increasingly smaller panels or spray nozzles, from the effects of any number of etching processes. Furthermore, due to the increased coating density, the coating formed on the substrate support and / or other components can be maintained for hundreds or thousands of wafers, increasing throughput, and the coating can be maintained even in highly corrosive atmospheres. These and other embodiments, along with their numerous advantages and features, are described in more detail below with reference to the accompanying drawings. Attached Figure Description

[0013] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of the specification and figures.

[0014] Figure 1 The illustration shows a top plan view of an exemplary processing system according to some embodiments of the present technology.

[0015] Figure 2A The illustration shows a schematic cross-sectional view of an exemplary processing chamber according to an embodiment of the present technology.

[0016] Figure 2B The illustration shows an embodiment according to this technology. Figure 2A A detailed view of a portion of the treatment chamber shown.

[0017] Figure 3 The illustration shows a bottom plan view of an exemplary spray head according to an embodiment of the present technology.

[0018] Figure 4 The illustrations depict exemplary operations in methods according to some embodiments of the present technology.

[0019] Figures 5A to 5C The illustration shows a cross-sectional schematic diagram of an exemplary chamber component according to some embodiments of the present technology.

[0020] Several of the accompanying drawings are illustrative. It should be understood that the drawings are for illustrative purposes and should not be considered to be drawn to scale unless specifically stated otherwise. Furthermore, as illustrative drawings, they are provided to aid understanding and may not include all aspects or information compared to a realistic representation, and may include exaggerated material for illustrative purposes.

[0021] In the accompanying drawings, similar parts and / or features may have the same reference numerals. Furthermore, various parts of the same type may be distinguished by adding a letter after the reference numerals to differentiate them. If only the first reference numeral is used in the description, the description applies to any similar part having the same first reference numeral, regardless of which letter it contains. Detailed Implementation

[0022] Semiconductor processing can include numerous operations that create complex patterned materials on a substrate. These operations can include multiple formation and removal processes that utilize corrosive or erosive materials, including plasma-enhanced materials formed remotely or at the substrate level. While etchants may preferentially etch the substrate material, chemical etchants can also contact other components within the chamber. Etching agents may chemically erode components, and depending on the process performed, one or more components may be bombarded by plasma effluent, which may also erode the material. The chemical and physical damage to chamber components caused by etchants can lead to wear over time, potentially increasing chamber replacement costs and downtime, and can contaminate the chamber due to reactive species particles formed from corrosion of the chamber walls. As a non-limiting example, in some localized or wafer-level plasma operations, spray heads or manifolds may operate as ground electrodes to generate plasma in the substrate processing area, where substrate supports or other components may operate as plasma-generating electrodes. The spray head, operating as a ground electrode, may be bombarded by plasma species, releasing metal species that form the spray head into the plasma. If such metal contaminants come into contact with the substrate, they may cause a short circuit during operation. Similarly, plasma-enhanced deposition processes can be used to form or deposit materials on a substrate, and these materials can also be deposited on chamber components.

[0023] Conventional techniques struggle to limit corrosion and erosion of chamber components, and due to damage caused by one or both of these mechanisms, conventional techniques tend to require periodic component replacement. Therefore, some conventional designs allow for routine replacement of spray heads or coating of spray heads with bombardment-resistant ceramic materials, such as yttrium oxide-based coatings. Attempts have been made to improve ceramic-based coatings using high-quality deposition techniques, such as electron beam or plasma spraying. However, while such coatings offer sufficient resistance to some bombardment or erosion, they are insufficient to withstand chemical reactions with plasma effluent species or contact with high-energy plasma species. In other words, such exposure can still lead to erosion and corrosion of the coating, particularly in areas where coating formation is poor or where high-energy plasma (e.g., capacitively coupled plasma) is present.

[0024] Furthermore, such coatings can reduce the amount of process gases or plasma present, especially during the first few substrates after the start of the process. For example, ceramic coatings (such as yttrium oxide-based coatings) absorb plasma species and release hydrogen, causing the coating to peel off and change its composition after initial exposure to the process plasma. Therefore, because the coating interacts with the process plasma, the film properties deposited on the first few substrates are significantly different from ideal conditions; this is often referred to as the "first wafer effect."

[0025] Furthermore, many chamber components include hard-to-access connectors, orifices, capping layers, and increasingly smaller features, such as spray heads and / or panels that include multiple orifices for transporting species through the chamber. If the coating does not completely cover each orifice sidewall and all exposed surfaces, plasma species formed remotely may cause the same problems as those formed in the region. Additionally, if the orifices are not small enough, regional plasma may leak through them, damaging other upstream components. However, when the orifices are formed small enough, many line-of-sight coating devices cannot provide a complete coating within the orifices. Therefore, ceramic-based coatings struggle to adequately cover these small features because deposition methods that produce high-quality coatings (such as electron beam or plasma spraying) are insufficient to cover the orifices and features, especially as the size of the orifices and features continues to decrease. Furthermore, the deposition thickness of such coating methods is limited to coatings less than 10 μm, which is insufficiently thick or dense for many high-energy processes. Attempts have been made to utilize atomic layer deposition (ALD) to improve the coverage of small features. However, the deposition thickness of ALD is further limited, with yttrium oxide coatings having a thickness of 500 nm or less. Therefore, existing chamber components cannot operate stably in plasma environments for extended periods, especially in high-energy environments.

[0026] This technology overcomes the aforementioned and other problems by coating chamber components with a high-quality pre-halogenated coating prior to substrate processing. For example, chamber components can be completely coated on exposed surfaces within the semiconductor processing chamber. Furthermore, the coating can be characterized by increased thickness and / or density, which improves resistance to chemical and high-power plasma systems and allows the components to be used to process multiple wafers before recoating. Moreover, since the coating is at least partially halogenated, the "first wafer effect," even if not eliminated, is significantly reduced, eliminating the need for "seasoning" the chamber and substrate. Furthermore, due to the unique method proposed herein, the coating according to this technology can be applied in situ within an assembled semiconductor processing chamber (e.g., a chamber used to process a substrate). Therefore, the chamber and its components can be easily recoated without removing the unit from the processing flow. Additionally, this process allows for greater coverage of exposed surfaces of the chamber and its components, reducing the risk of surface corrosion and erosion during processing.

[0027] While the remainder will conventionally identify specific etching and deposition processes utilizing the disclosed techniques, it will be readily understood that these systems and methods are equally applicable to deposition and cleaning processes and chambers that may occur in the chambers or other chambers. Therefore, this technique should not be construed as being limited to any particular etching process or chamber. Furthermore, although exemplary chambers have been described to provide a basis for this technique, it should be understood that this technique can actually be applied to any semiconductor processing chamber that allows the operations described herein.

[0028] Figure 1 The figure illustrates a top plan view of one embodiment of a deposition, etching, baking, and curing chamber processing system 100 according to an embodiment. In the figure, a pair of front-opening unified pods (FOUPs) 102 supply substrates of various sizes, which are received by a robotic arm 104 and first placed in a low-pressure holding region 106, and then placed into one of the substrate processing chambers 108a to f located in series sections 109a to c. A second robotic arm 110 is used to transfer substrate wafers from the holding region 106 to the substrate processing chambers 108a to f. Each substrate processing chamber 108a to f can be assembled to perform multiple substrate processing operations, including cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), etching, pre-cleaning, degassing, orientation, and other substrate processes. The substrate processing chambers 108a to f may include one or more system components for deposition, annealing, curing, and / or etching. Any one or more of the processes described herein can be performed in a chamber separate from the manufacturing system shown in the different embodiments. It will be understood that other configurations of chambers 108a to f are contemplated for system 100.

[0029] Figure 2AA cross-sectional view of an exemplary processing chamber system 200 is illustrated, which has partitioned plasma generation regions within the processing chamber. During coating according to the present technology, a processing gas may flow into a first plasma region 215 through a gas inlet assembly 205. A remote plasma system (RPS) 201 may be included in the system and may process the first gas, which then travels through the gas inlet assembly 205. The inlet assembly 205 may include two or more distinct gas supply channels, wherein a second channel (not shown) may bypass the RPS 201 (if included).

[0030] The accompanying drawings illustrate chamber components such as a cooling plate 203, a panel 217, an ion suppressor 223, a spray nozzle 225, and a base 265. A substrate 255 is mounted on the chamber components, and each chamber component may be included according to embodiments. In some embodiments, the cooling plate and panel may operate as aspects of a cover assembly, also referred to as a cover stack. The base 265 may have heat exchange channels through which a heat exchange fluid flows to control the temperature of the substrate. This heat exchange fluid may be operable to heat and / or cool the substrate or wafer during processing operations. The substrate support disk of the base 265 may comprise aluminum, ceramic, or a combination thereof, and may also be resistively heated to achieve relatively high temperatures, such as from up to or about 100°C to above or about 1100°C, using embedded resistance heating elements.

[0031] Panel 217 may be conical, conical, or other similar structures having a narrow top portion extending to a wide bottom portion. Alternatively, panel 217 may be flat as shown and include multiple through channels for distributing the process gas. Depending on the use of RPS 201, plasma-generating gases and / or plasma-excited species may pass through multiple holes in panel 217, such as... Figure 2B As shown, this is to ensure more uniform delivery to the first plasma region 215.

[0032] Exemplary configurations may include directing the gas inlet assembly 205 to a gas supply region 258 separated from the first plasma region 215 by the panel 217, such that gas / species flows into the first plasma region 215 through an opening in the panel 217. Selectable structural and operational features may be chosen to prevent significant backflow of plasma from the first plasma region 215 into the supply region 258, the gas inlet assembly 205, and the fluid supply system 210. The conductive top of the panel 217 or chamber and the spray head 225 are shown with an insulating ring 220 located between the features, which allows an alternating current potential to be applied to the panel 217 relative to the spray head 225 and / or the ion suppressor 223. The insulating ring 220 may be located between the panel 217 and the spray head 225 and / or the ion suppressor 223, allowing capacitively coupled plasma (CCP) to form in the first plasma region. A baffle (not shown) may be additionally located in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow rate of fluid entering the region through the gas inlet assembly 205.

[0033] Ion suppressor 223 may comprise a plate or other geometry defining a plurality of holes throughout the structure, the holes being configured to suppress the migration of charged ion species out of the first plasma region 215 while allowing uncharged neutral or radical species to pass through ion suppressor 223 into the activation gas delivery region between the suppressor and the spray head. In embodiments, ion suppressor 223 may comprise a porous plate having various aperture configurations. These uncharged species may include highly reactive species that are transported through the holes along with a low-reactive carrier gas. As described above, migration of ion species through the holes can be reduced and, in some cases, completely suppressed. Controlling the amount of ion species passing through ion suppressor 223 can advantageously provide enhanced control over the gas mixture in contact with the underlying wafer substrate, which in turn can enhance control over the deposition and / or etching characteristics of the gas mixture. For example, adjusting the ion concentration of the gas mixture can significantly alter etching selectivity, such as the SiNx:SiOx etching ratio, Si:SiOx etching ratio, etc. In alternative embodiments of performing deposition, the balance between conformal and flowable deposition of the dielectric material can also be altered.

[0034] Multiple orifices in ion suppressor 223 can be configured to control the passage of activating gas (i.e., ions, free radicals, and / or neutral species) through ion suppressor 223. For example, the aspect ratio (or aperture to length ratio) and / or geometry of the orifices can be controlled to reduce the flow rate of charged ions in the activating gas passing through ion suppressor 223. The orifices in ion suppressor 223 may include a tapered portion facing plasma excitation region 215 and a cylindrical portion facing spray head 225. The shape and dimensions of the cylindrical portion can control the flow rate of ion species to spray head 225. An adjustable electrical bias can also be applied to ion suppressor 223 as an additional means of controlling the flow rate of ion species through the suppressor.

[0035] Ion suppressor 223 can be used to reduce or eliminate the amount of ionic charged species traveling from the plasma generation region to the substrate. Uncharged neutral and free radical species can still pass through openings in the ion suppressor and react with the substrate. It should be noted that, in some embodiments, complete elimination of ionic charged species in the reaction region surrounding the substrate may not be possible. In some cases, ionic species are intended to reach the substrate to perform etching and / or deposition processes. In such cases, the ion suppressor can help control the concentration of ionic species in the reaction region to a level conducive to the process.

[0036] The combination of the spray head 225 and the ion suppressor 223 allows the plasma present in the first plasma region 215 to avoid directly exciting the gas in the substrate processing region 233, while still allowing excited species to travel from the chamber plasma region 215 to the substrate processing region 233. In this way, the chamber can be configured to prevent plasma from contacting the substrate 255 being etched. This advantageously protects various complex structures and films patterned on the substrate, which could be damaged, misaligned, or warped if directly exposed to the generated plasma. Furthermore, the etching rate of oxide species may increase when plasma is allowed to contact or approach the substrate level. Therefore, if the exposed areas of the material are oxides, the material can be further protected by keeping the plasma away from the substrate.

[0037] The processing system may further include a power supply 240 electrically coupled to the processing chamber to provide electrical power to the panel 217, ion suppressor 223, spray head 225, and / or base 265, thereby generating plasma in the first plasma region 215 or processing region 233. Depending on the process being performed, the power supply may be configured to deliver an adjustable amount of power to the chamber. This configuration allows the use of adjustable plasma in the process being performed. Unlike remote plasma units that typically have an on / off function, adjustable plasma can be configured to deliver a specific amount of power to the plasma region 215 and / or substrate processing region 233. This, in turn, allows the formation of specific plasma characteristics, enabling precursors to dissociate in a specific manner to enhance the etch profile produced by such precursors.

[0038] Plasma can be ignited in the chamber plasma region 215 above the spray head 225 or in the substrate processing region 233 below the spray head 225, or simultaneously in both the chamber plasma region 215 and the substrate processing region 233. Plasma can be present in the chamber plasma region 215 to generate radical precursors from, for example, an inflowing fluorine-containing precursor or other precursor. An AC voltage, typically in the radio frequency (RF) range, can be applied between the conductive top of the processing chamber (such as panel 217) and the spray head 225 and / or the ion suppressor 223 to ignite the plasma in the chamber plasma region 215 during deposition. The RF power supply can generate a high RF frequency of 13.56 MHz, but other frequencies can also be generated alone or in combination with the 13.56 MHz frequency.

[0039] Figure 2B Detailed diagram 253 illustrates the characteristics affecting the distribution of the processed gas through panel 217. (See diagram 253 for example.) Figure 2A and 2B As shown, panel 217, cooling plate 203, and gas inlet assembly 205 intersect to define gas supply region 258, into which process gas can be delivered from gas inlet 205. Gas can fill gas supply region 258 and flow through aperture 259 in panel 217 to first plasma region 215. Aperture 259 can be configured to guide airflow in a substantially unidirectional manner, allowing process gas to flow into processing region 233, but partially or completely preventing its backflow into gas supply region 258 after crossing panel 217.

[0040] As shown in the figure, a plurality of holes 259 are defined on panel 217. While any shape of hole 259 is contemplated, it should be understood that, regardless of shape, each hole 259 defines an exposed hole surface 260 extending from a first side 261 to a second side 262 of panel 217 around the interior of each hole 259. This exposed hole surface 260 is exposed to or fluidly connected to the first plasma region 215 and gas inlet assembly 205. Furthermore, in embodiments, the exposed hole surfaces 260 of all holes 259 may define the hole surface area of ​​panel 217.

[0041] The gas distribution components used in the processing chamber section 200 (such as shower head 225) may be referred to as dual channel shower heads (DCSH), and in Figure 3 The embodiments described are detailed in the text. Dual-channel spray heads can provide etching processes that allow for the separation of etchant from the outside of the processing area 233, providing limited interaction between the etchant and the chamber components and each other before the etchant is delivered to the processing area.

[0042] The spray head 225 may include an upper plate 214 and a lower plate 216. These plates may be coupled to define a volume 218 between them. The coupling of the plates provides a first orifice 219 through the upper and lower plates and a second orifice 221 through the lower plate 216. The formed channel may be configured to provide a fluid passage from the volume 218 through the lower plate 216 only through the second orifice 221, and the first orifice 219 may be fluidly isolated from the volume 218 between the plate and the second fluid passage 221. Fluid may enter and exit the volume 218 through one side of the gas distribution assembly including the spray head 225. However, it should be understood that in embodiments, only a single type of orifice 219 may be defined through the spray head 225, and / or orifices 219 and 221 may be collectively referred to as "spray head orifices." Furthermore, in embodiments, both the first orifice 219 and the second orifice 221 may extend completely or partially through the spray head 225, thereby providing a fluid passage between the first plasma region 215 and the processing region 233. Furthermore, in some embodiments, the spray head 225 may be formed from a single plate.

[0043] Nevertheless, as shown in the figure, the spray head 225 defines a plurality of orifices 219 / 221. While any shape of orifices 219 / 221 is contemplated, it should be understood that, regardless of shape, each orifice 219 / 221 defines an exposed orifice surface 263 extending from a first side 264 to a second side 266 of the spray head 225 around each orifice 219 / 221, which is exposed to or fluidly connected to the first plasma region 215 and the processing region 233. Furthermore, in embodiments, the exposed orifice surfaces 263 of all orifices 219 / 221 may define the orifice surface area of ​​the spray head 225.

[0044] Figure 3 This is a bottom view of a spray head 325 used in a treatment chamber according to an embodiment. The spray head 325 may correspond to... Figure 2A The spray head 225 is shown. The through-hole 365, shown as a first orifice 219 view, can have multiple shapes and configurations to control and influence the flow rate of the precursor through the spray head 225. The small holes 375, shown as a second orifice 221 view, can be substantially uniformly distributed on the surface of the spray head, even between the through-holes 365, and can help provide a more uniform mixing of the precursor as it leaves the spray head compared to other configurations.

[0045] Figure 4 Exemplary operations in method 400 according to some embodiments of the present technology are illustrated. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 400 may include a number of optional operations, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many operations are described herein to provide a broader scope of structure formation but are not essential to the technology, or may be performed through alternative methods that are easier to understand.

[0046] Method 400 may include additional operations prior to initiating the listed operations. For example, additional processing operations may include forming or providing chamber components. The previous processing operations may be performed in the chamber in which method 400 is performed, or processing may be performed in one or more other processing chambers prior to delivering or mounting the chamber components into the semiconductor processing chamber in which method 400 is performed. In any case, method 400 may, as appropriate, include delivering one or more chamber components to a processing region of the semiconductor processing system 100, such as the processing chambers 108a to f described above, or other chambers that may include the aforementioned components. The chamber components may be deposited within one or more processing chambers 108a to f, such as the processing region 120 of the chambers described above. Method 400 describes... Figures 5A to 5C The operations illustrated herein will be described in conjunction with the operations of method 400. It should be understood that... Figures 5A to 5COnly partial schematic diagrams are shown, and one or more chamber components may include other components as shown in the figures, as well as alternative components of any size or configuration that may still benefit from various aspects of the present technology.

[0047] Figures 5A to 5C The illustration shows a chamber component 500 that can be coated according to embodiments of the present technology. As described above, the chamber component 500 can be any one or more chamber components having surfaces exposed inside a semiconductor processing chamber, such as the processing system 100 or processing chamber system 200 described above. Therefore, in embodiments, the chamber component 500 can be one or more of a cooling plate 203, a panel 217, an ion suppressor 223, a spray head 225, a base 265 (alone or including a substrate support) and / or a baffle, a supply device, an inlet, an outlet, and their supports. That is, in embodiments, the chamber component 500 can be any one or more components used in a plasma processing chamber. In embodiments, during operation 405, the chamber component 500 can be assembled in the processing chambers 108a to f or the processing chamber of the processing system 200 (e.g., for in-situ processes, as will be discussed in more detail below), or can be placed in the processing chambers 108a to f, such as on supports within the processing chamber (e.g., for external processes).

[0048] like Figure 5A As shown, the chamber component 500 may include a surface 501. Depending on the specific chamber component 500, the exposed surface 501 may include various features such as grooves, holes, and other features. In some embodiments, such as when the chamber component 500 is a panel and / or a shower head, the chamber component 500 may include a plurality of holes 520 ( Figure 5B As mentioned above.

[0049] Figures 5A to 5C The illustration shows a cross-sectional schematic of an exemplary corrosion-resistant and erosion-resistant coating deposited on a chamber component 500 according to some embodiments of the present technology. The figures provide exemplary views of various coating configurations intended to illustrate possible coating applications included in embodiments of the present technology, and may include coatings on multiple components in the chamber system 200, or on other components that may benefit from the corrosion-resistant coating. It should be understood that additional and alternative coating applications may be used during operation 410, which will be discussed in more detail later. Coating applications (such as the number and type of layers formed) may depend on the type of component to which the coating is applied and the configuration of the component. For example, if the component includes one or more orifices, the coating may include two or more layers of ceramic material or a coating of two or more layers of ceramic material (without contouring between layers) (such as yttrium oxide ceramic material) to provide complete coverage of the exposed surfaces of the chamber component, including the exposed surfaces of the individual orifices. Figures 5A to 5CThe exemplary chamber component 500 provided herein may be an illustration of any chamber component previously described.

[0050] In some embodiments, chamber component 500 may be made of aluminum, chromium, magnesium, nickel, alloys thereof, or combinations thereof. Alloys typically contain impurities of various alloying metals, even when chamber component 500 contains high-purity metal alloys. For example, aluminum alloys typically contain trace amounts of nickel, copper, iron, manganese, and chromium. In some embodiments, impurities may be present in the aluminum alloy in the following atomic weight percentages: nickel ranging from about 0.001% to about 0.5%; iron ranging from about 0.001% to about 0.25% by weight; copper ranging from about 0.15% to about 0.35%; manganese ranging from about 0.001% to about 0.2%; zinc ranging from about 0.001% to about 0.15%; chromium ranging from about 0.04% to about 0.28%; titanium ranging from about 0.001% to about 0.06%; and magnesium ranging from about 0.8% to about 1.2%. Depending on the circumstances, the total amount of other impurities present in the aluminum alloy may be approximately 0.15% by weight or less.

[0051] Figures 5A to 5C The illustrations also include a coating applied to the exposed surface 501 of the chamber component 500 according to the present technology. Although the illustrations show only a coating applied to one surface of the chamber component, it should be understood that the coating may be applied to all exposed surfaces of the chamber component (as described above, the surface facing the chamber or the surface exposed to the chamber), and is shown for illustrative purposes as covering only the surface illustrated in the figures. The corrosion- and erosion-resistant coating is resistant to corrosion and erosion and is configured to protect component 500 from reactive etchants, including halogen-containing effluents, gases, etchants, or deposition processes. For example, the corrosion- and erosion-resistant coating may be configured to protect component 500 from etchants or gases, even in high-power processes such as the CCP process.

[0052] Therefore, in an embodiment, a yttrium oxide-containing coating 510 can be deposited on the exposed surface 501 of the component 500 in operation 410. The yttrium oxide-containing coating 510 can extend on the exposed surface 501 of the component 500. Since the yttrium oxide-containing coating 510 is not the final coating of this technology, there is no required thickness or expensive coating technology. In other words, the further operation, which will be discussed in more detail below, is for converting the coating into a halogen-containing coating, which increases the thickness and / or density of the coating during the conversion. Therefore, in an embodiment, the yttrium oxide-containing coating 510 can be formed by thermal spraying, ALD, CVD, PVD, PECVD, combinations thereof, etc., known in the art.

[0053] The yttrium oxide-containing coating 510 can extend around the chamber component 500 to achieve a coating thickness greater than or about 5 nm, such as greater than or about 10 nm, such as greater than or about 50 nm, such as greater than or about 100 nm, such as greater than or about 250 nm, such as greater than or about 500 nm, such as greater than or about 750 nm, such as greater than or about 1 μm, such as greater than or about 2 μm, such as greater than or about 3 μm, such as greater than or about 4 μm, such as greater than or about 5 μm, such as greater than or about 6 μm, such as greater than or about 7 μm, such as greater than or about 8 μm, such as greater than or about 9 μm, such as up to 10 μm, or any range or value between the foregoing. In other words, as described above, as is known in the art, existing yttrium oxide deposition methods are limited to less than 500 nm when used in ALD coating methods and less than 10 μm when used in electron beam methods, which is insufficient to resist erosion and corrosion in highly corrosive environments and / or high-energy plasma systems for extended periods.

[0054] However, as mentioned above, the thickness of the yttrium oxide coating 510 may not be critical, as thickness and / or density can be increased according to this technology. Nevertheless, in embodiments, when the chamber component 500 has small-sized features or holes 520, two or more coating methods can be used to provide the yttrium oxide coating 510 on substantially all exposed surfaces of one or more chamber components. In other words, this technology transforms the underlying yttrium oxide coating 510 into a more robust halogen-containing coating, as discussed below. Therefore, the yttrium oxide coating 510 should be formed on all exposed surfaces where the halogenated coating of this technology is desired. Thus, in embodiments, a thick and high-quality yttrium oxide coating 510 can be formed on flat surfaces (and / or visually exposed surfaces) of the component using electron beams, thermal spraying, etc., and can be deposited on small features or holes 520 (and / or non-visually exposed surfaces) using ALD processes, etc.

[0055] Regardless of the method used, in an embodiment, the exposed surfaces of one or more chamber components 500 may define an exposed surface area (e.g., the surface area of ​​all exposed surfaces to be coated), wherein at least about 50%, such as greater than or about 60%, such as greater than or about 70%, such as greater than or about 80%, such as greater than or about 85%, such as greater than or about 90%, such as greater than or about 95%, such as greater than or about 97.5%, such as greater than or about 99%, or any range or value between the above percentages, is deposited with a yttrium oxide-containing coating 510.

[0056] Furthermore, as mentioned above, it should be understood that when one or more chamber components include one or more orifices, the exposed orifice surface area is included in the exposed surface area of ​​the chamber component. In any case, in embodiments, the exposed orifice surface area (which may include the surface area of ​​orifices in panels, spray heads, combinations thereof, etc.) is at least about 50%, such as greater than or about 60%, such as greater than or about 70%, such as greater than or about 80%, such as greater than or about 85%, such as greater than or about 90%, such as greater than or about 95%, such as greater than or about 97.5%, such as greater than or about 99%, or any range or value between the above percentages may be deposited with a yttrium oxide-containing coating 510, such as... Figure 5B As shown.

[0057] In this embodiment, yttrium oxide may form all or part of the yttrium oxide-containing coating 510, such as substantially all of the yttrium oxide-containing coating 510. In this embodiment, based on the weight of the coating 510, yttrium oxide may constitute at least about 70% by weight, such as greater than or about 75% by weight, such as greater than or about 80% by weight, such as greater than or about 85% by weight, such as greater than or about 90% by weight, such as greater than or about 92.5% by weight, such as greater than or about 95% by weight, such as greater than or about 97.5% by weight, such as greater than or about 99% by weight, or any range or value between the above percentages. However, in embodiments, the yttrium oxide-containing coating 510 may include additional components such as small amounts of fluorine (which may be present as fluorinated yttrium oxide YOFx), carbon or chamber contaminants (such as aluminum, zirconium or other similar materials), or other oxides in the yttrium oxide-containing coating 510 in amounts less than 50% by weight, such as less than or about 40% by weight, such as less than or about 30% by weight, such as less than or about 20% by weight, such as less than or about 10% by weight, such as less than or about 5% by weight, such as less than or about 2.5% by weight, such as less than or about 1% by weight, including non-yttrium oxide components.

[0058] After forming the yttrium oxide coating 510, plasma can be formed in operation 420 to generate plasma effluent. In some embodiments, the plasma can be formed in a remote plasma region within the chamber or coupled with the chamber fluid, and see above. Figures 1 to 3 The discussion states that plasma effluent generated by remote plasma can flow into the processing area. In some embodiments, plasma can be regionally formed within the processing area, and plasma effluent can be generated from the plasma within the processing area. In operation 430, once plasma effluent is generated, the surface containing the yttrium oxide coating 510 can come into contact with the plasma effluent.

[0059] In some embodiments, the plasma generated in operation 420 may be a hydrogen-containing plasma, a helium-containing plasma, an ammonia-containing plasma, an argon-containing plasma, or a combination thereof. Therefore, in some embodiments, the secondary ions or radicals in the plasma are plasmas containing hydrogen, ammonia, helium, or argon. Other types of secondary ions or radicals may also be used in method 400.

[0060] Nevertheless, regardless of the secondary ions and free radicals present in the plasma, this technique includes one or more halide ions or free radicals in the plasma. Therefore, in an embodiment, the method includes introducing a halogen-containing precursor in operation 420. In an embodiment, the halogen-containing precursor is any precursor that generates fluorine radicals. In an embodiment, the halogen-containing precursor is a fluorine-containing precursor. Furthermore, in an embodiment, the fluorine-containing precursor is nitrogen trifluoride (NF3).

[0061] In other words, this technology surprisingly discovers that, in operation 430, the fluorine-containing plasma interacts with the oxygen-rich yttrium oxide-containing coating under carefully controlled pressure and power, such as... Figure 5B As shown. Not wanting to be bound by theory, it is believed that the oxygen-rich yttrium oxide coating 510 acts as a free radical scavenger, interacting with fluorine free radicals present in the plasma. In operation 440, through continuous exposure to the plasma under high pressure and high power, the yttrium oxide coating 510 is transformed into a yttrium fluoride coating YF3, as... Figure 5C As shown. This conversion offers several benefits. For example, the conversion from yttrium oxide to yttrium fluoride increases the coating thickness and / or density (if needed), providing a more robust coating capable of withstanding harsher chamber environments or exhibiting a longer lifespan for the component. Furthermore, the conversion to yttrium fluoride imparts fluorine to the coating itself. This minimizes or eliminates the first wafer effect, as the yttrium oxide coating is less likely or less susceptible to interaction with the plasma processing gas.

[0062] Because the coating of this technology can be formed in situ within the semiconductor processing chamber, it offers a significant improvement over conventional chemical yttrium fluoride processes and deposition methods, allowing any exposed surface to be coated as soon as it appears in the processing chamber. Furthermore, for both in-situ and non-in-situ processes, this technology allows for the formation of thicker and / or denser coatings, and even robust coatings for small features or pores, compared to conventional methods.

[0063] Therefore, in the embodiments, operations 420, 430, and / or 440 can be considered as high-power plasma processes, and thus can be performed with power greater than or about 2 watts, such as greater than or about 5 watts, such as greater than or about 10 watts, such as greater than or about 25 watts, such as greater than or about 50 watts, such as greater than or about 75 watts, such as greater than or about 250 watts, such as greater than or about 500 watts, such as greater than or about 750 watts, such as greater than or about 1000 watts, such as greater than or about 1500 watts, such as greater than or about 2000 watts, such as greater than or about 2500 watts, such as up to about 3000 watts, or any range or value between the above wattages. Power can be provided as is known in the art or as described above. Furthermore, high-power plasma processes are performed at pressures greater than or about 500 mTorr, such as greater than or about 750 mTorr, such as greater than or about 1 Torr, such as greater than or about 1.5 Torr, such as greater than or about 2 Torr, such as greater than or about 2.5 Torr, such as greater than or about 3 Torr, such as greater than or about 3.5 Torr, such as greater than or about 4 Torr, such as greater than or about 4.5 Torr, such as greater than or about 5 Torr, such as greater than or about 6 Torr, such as greater than or about 7 Torr, such as greater than or about 8 Torr, such as greater than or about 9 Torr, such as greater than or about 10 Torr, such as greater than or about 11 Torr, such as greater than or about 12 Torr, such as greater than or about 13 Torr, such as greater than or about 14 Torr, such as up to about 15 Torr, or any range or value between the aforementioned Torr values. Pressures can be provided as known in the art or as described above.

[0064] Nevertheless, in implementations, high-power plasma processes may also include voltages greater than or about 10 volts, such as greater than or about 25 volts, such as greater than or about 50 volts, such as greater than or about 75 volts, such as greater than or about 100 volts, such as greater than or about 125 volts, such as greater than or about 150 volts, such as greater than or about 200 volts, such as greater than or about 250 volts, such as greater than or about 300 volts, such as greater than or about 350 volts, such as greater than or about 400 volts, such as greater than or about 450 volts, such as greater than or about 500 volts, such as greater than or about 600 volts, such as greater than or about 700 volts, such as greater than or about 800 volts, such as greater than or about 900 volts, such as up to about 1000 volts, or any range or value between the foregoing values.

[0065] Furthermore, in the embodiments, the high-power plasma process can be performed at high temperatures, such as at temperatures above or about 30°C, above or about 50°C, above or about 75°C, above or about 100°C, above or about 125°C, above or about 150°C, above or about 175°C, above or about 200°C, above or about 250°C, above or about 300°C, above or about 350°C, above or about 400°C, above or about 450°C, above or about 500°C, above or about 550°C, above or about 600°C, above or about 650°C, above or about 700°C, above or about 750°C, above or about 800°C, above or about 850°C, above or about 900°C, above or about 950°C, above or about 1000°C, or higher, or any range or value between the above temperatures.

[0066] In implementation, the high-power plasma process can be performed for a period of time sufficient to produce a thickness greater than or about 10 nm, such as greater than or about 25 nm, such as greater than or about 50 nm, such as greater than or about 75 nm, such as greater than or about 100 nm, such as greater than or about 250 nm, such as greater than or about 500 nm, such as greater than or about 750 nm, such as greater than or about 1 μm, such as greater than or about 5 μm, such as greater than or about 10 μm, such as greater than or about 15 μm, such as greater than or about 20 μm, such as greater than or about 25 μm, such as greater than or about 50 μm, such as greater than or about 100 μm, such as greater than or about 150 μm, such as greater than or about 200 μm, such as greater than or about 250 μm, such as greater than or about 300 μm, such as greater than or about 350 μm, such as greater than or about 400 μm, such as greater than or about 450 μm, such as greater than or about 500 μm, or such as less than or about 1000 μm. A fluorinated yttrium coating with a thickness of nm, such as less than or about 900 nm, such as less than or about 800 nm, such as less than or about 700 nm, such as less than or about 600 nm, such as less than or about 500 nm, such as less than or about 400 nm, such as less than or about 300 nm, such as less than or about 200 nm, such as less than or about 100 nm, or any range or value between the foregoing values. As described above, in embodiments, the thickness of the fluorinated yttrium coating may increase from the thickness of the yttrium oxide coating generally, or at one or more locations, or on one or more components. Nevertheless, in embodiments, the thickness of the fluorinated yttrium coating may generally be equal to the thickness of the yttrium oxide coating generally, or at one or more locations, or on one or more components, when necessary.

[0067] For example, in one embodiment, the coating thickness may be relatively thin, but the density is increased. Therefore, in one embodiment, the coating density may be greater than or about 2 g / cm³. 3Such as greater than or about 2.25 g / cm³ 3 Such as greater than or about 2.5 g / cm³ 3 Such as greater than or about 2.75 g / cm³ 3 Such as greater than or about 3 g / cm 3 Such as greater than or about 3.5 g / cm³ 3 Such as greater than or about 4g / cm 3 Such as greater than or about 4.5 g / cm 3 Such as greater than or about 5 g / cm 3 Such as greater than or about 5.5 g / cm 3 Such as greater than or about 6 g / cm 3 Such as greater than or about 6.5 g / cm³ 3 , or any range or value between the above values.

[0068] Additionally or alternatively, in embodiments, the high-power plasma process may be performed for more than or about 30 minutes, such as more than or about 45 minutes, such as more than or about 1 hour, such as more than or about 1.5 hours, such as more than or about 2 hours, such as more than or about 2.5 hours, such as more than or about 3 hours, such as more than or about 3.5 hours, such as more than or about 4 hours, such as more than or about 4.5 hours, such as more than or about 5 hours, or any range or value between the foregoing. However, as described above and below, in embodiments, the duration of the high-power plasma process is based on one or more factors that may depend on the required processing chamber, chamber components, etc., such as coating thickness or the percentage of coating converted to yttrium fluoride.

[0069] For example, in an implementation, it is assumed that the possible reaction methods of the process according to this technology may be:

[0070] 4Y₂O₃ + 8F → 8YOF + 2O₂

[0071] 2YOF + 4F → 2YF3 + O2

[0072] Therefore, in embodiments, depending on the processing conditions and / or the time allowed for the conversion operation 440 to be performed, a portion of the chamber component 500 may contain a layer 512 including yttrium oxide fluoride (such as YOFx), such as Figure 5CAs shown. Although layer 512 is shown below the fluorinated yttrium coating 514, it should be understood that in embodiments, layer 512 may be contained in discrete points or locations throughout the thickness of the fluorinated yttrium coating 514, or may exist only in a feature, such as a hole 520. Furthermore, in embodiments, layer 512 may also comprise individual unreacted yttrium oxide, or a combination of unreacted yttrium oxide and fluorinated yttrium oxide. Therefore, in embodiments, one or more holes 520 may have only partially converted coatings, or contain uncoated or coated yttrium oxide portions.

[0073] However, in the implementation, it should be understood that the high-power plasma process is performed for a period of time sufficient to convert yttrium oxide in coating 510 into yttrium fluoride at a rate of greater than or about 50% by weight, such as greater than or about 60% by weight, such as greater than or about 70% by weight, such as greater than or about 75% by weight, such as greater than or about 80% by weight, such as greater than or about 85% by weight, such as greater than or about 90% by weight, such as greater than or about 95% by weight, such as greater than or about 97.5% by weight, such as greater than or about 99% by weight, or any range or value between the foregoing.

[0074] Furthermore, in this embodiment, yttrium fluoride may form all or part of the yttrium fluoride coating 514, such as substantially all of the yttrium fluoride coating 514. In this embodiment, based on the weight of the coating 514, yttrium fluoride may constitute at least about 50% by weight, such as greater than or about 60% by weight, such as greater than or about 70% by weight, such as greater than or about 75% by weight, such as greater than or about 80% by weight, such as greater than or about 85% by weight, such as greater than or about 90% by weight, such as greater than or about 92.5% by weight, such as greater than or about 95% by weight, such as greater than or about 97.5% by weight, such as greater than or about 99% by weight, or any range or value between the foregoing. However, in embodiments, the yttrium fluoride coating 514 may include other components, such as small amounts of YOFx, yttrium oxide, carbon, or other non-yttrium fluoride impurities (such as aluminum, zirconium, or other similar materials), in amounts less than 50% by weight, such as less than or about 40% by weight, such as less than or about 30% by weight, such as less than or about 20% by weight, such as less than or about 10% by weight, such as less than or about 5% by weight, such as less than or about 2.5% by weight, such as less than or about 1% by weight, or any range or value between the foregoing.

[0075] As described above, the exposed surfaces of one or more chamber components 500 may define an exposed surface area (e.g., the surface area of ​​all exposed surfaces to be coated), wherein at least about 50%, such as greater than or about 60%, such as greater than or about 70%, such as greater than or about 80%, such as greater than or about 85%, such as greater than or about 90%, such as greater than or about 95%, such as greater than or about 97.5%, such as greater than or about 99%, or any range or value between the foregoing are deposited with a yttrium fluoride coating 514, such as Figure 5C As shown. In other words, it should be understood that, as used herein, “formed thereon” or “deposited thereon” may include a yttrium fluoride coating formed directly on the chamber component 500, or may include one or more intermediate layers, such as residual yttrium oxide or yttrium fluoride, between the yttrium fluoride coating and the chamber component.

[0076] Furthermore, as mentioned above, it should be clarified that when one or more chamber components include one or more orifices, the exposed orifice surface area is included in the exposed surface area of ​​the chamber component. In any case, in embodiments, at least about 50%, such as greater than or about 60%, such as greater than or about 70%, such as greater than or about 80%, such as greater than or about 85%, such as greater than or about 90%, such as greater than or about 95%, such as greater than or about 97.5%, such as greater than or about 99%, or any range or value between the foregoing may be deposited with a yttrium fluoride coating 514, such as... Figure 5C As shown.

[0077] Despite the selected process conditions and as described above, it should be understood that, in this embodiment, the technique can be an "in-situ process." This process includes a processing chamber that may be assembled with necessary or desired chamber components for processing a substrate, and the chamber components are coated within the chamber according to this technique, and these chamber components themselves will ultimately be used to process the substrate. In addition to the advantages discussed above, this assembly also has additional advantages, such as ensuring that exposed surfaces are coated without unnecessarily coating surfaces that are already covered or protected. However, it should be understood that this technique can also be used as a "non-in-situ process," still providing the aforementioned benefits. In this process, one or more components are loaded into a processing chamber, coated according to this technique, removed from the processing chamber, and subsequently assembled in a final processing chamber, in which these chamber components will be used to process the substrate. In this embodiment, the chamber used for coating the chamber components according to this technique can be any processing chamber in the aforementioned processing system 100 or chamber system 200. However, in this embodiment, the processing chamber can be a CCP processing chamber, a bias plasma chamber, or a combination thereof.

[0078] The corrosion- and erosion-resistant coatings formed according to this technology can protect chamber components from chemical and plasma erosion during processes such as etching, deposition, and cleaning. The corrosion- and erosion-resistant coatings provided herein can reduce or eliminate first-wafer effects and contamination of the substrate by the chamber component material. Therefore, this technology can improve device manufacturing while additionally increasing the lifespan of the chamber components.

[0079] In the foregoing description, numerous details have been set forth for illustrative purposes to help understand the various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details, or with additional details.

[0080] Multiple embodiments have been disclosed, and those skilled in the art will recognize that various modifications, other structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the technology, many well-known processes and components have not been described. Therefore, the above description should not be considered as limiting the scope of the technology.

[0081] Where a numerical range is provided, it should be understood that, unless the context explicitly specifies otherwise, this document also specifically discloses each intermediate value between the upper and lower limits of that range, down to the smallest fraction of the lower limit unit. Any smaller range between any given value or ungiven intermediate value within a given range and any other given value or intermediate value within that given range is included. The upper and lower limits of such smaller ranges may be independently included or excluded from the range, and each range is also covered by the technique in cases where any limit, neither limit, or both limits are included in the smaller range, based on any specifically excluded limit value within the given range. When a given range includes one or two limits, the range that does not include any or both of those limits is also included.

[0082] The singular forms “a”, “an”, and “the” used herein and in the appended claims include plural indications unless the context clearly specifies otherwise. Thus, for example, the indication of “a layer” includes a plurality of such layers, the indication of “the precursor” includes one or more precursors and their equivalents known to one of ordinary skill in the art to which this invention pertains, and so on.

[0083] Furthermore, the terms “comprise,” “comprising,” “contain,” “containing,” “include,” and “including” used in this specification and the following claims are intended to specify the presence of the stated feature, integer, component, or operation, but do not preclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor processing system, the semiconductor processing system comprising: A chamber, the chamber comprising a plurality of chamber components, the chamber components including A base configured to support a semiconductor substrate; Overlapping; A panel, the panel being supported by the cover layer, wherein the panel defines a plurality of first holes; and A spray head is located between the panel and the base, wherein the spray head defines a plurality of second holes; The panel, the spray head, the cover layer, the base, or a combination thereof comprises a coating containing yttrium fluoride, yttrium oxyfluoride, or yttrium fluoride and yttrium oxyfluoride, the coating having a thickness greater than 10 μm or less than about 100 nm on at least a portion of the respective chamber components or the combination thereof.

2. The semiconductor processing system of claim 1, wherein the panel, the spray head, or both the panel and the spray head define an exposed surface having an exposed surface area, wherein more than or about 80% of the exposed surface area comprises the coating containing yttrium fluoride, yttrium oxyfluoride, or yttrium fluoride and yttrium oxyfluoride.

3. The semiconductor processing system of claim 2, wherein the panel, the spray head, or the exposed surface area of ​​both the panel and the spray head comprises more than or about 90% of the coating containing yttrium fluoride, yttrium oxyfluoride, or yttrium fluoride and yttrium oxyfluoride.

4. The semiconductor processing system of claim 1, wherein the coating containing yttrium fluoride, yttrium oxyfluoride, or yttrium fluoride and yttrium oxyfluoride has a thickness greater than or about 50 μm on at least a portion of the respective chamber components or combinations thereof.

5. The semiconductor processing system of claim 1, wherein the plurality of first holes, the plurality of second holes, or the combination thereof define a hole surface having a hole surface area, wherein greater than or about 70% of the hole surface area comprises the coating containing yttrium fluoride, yttrium oxyfluoride, or yttrium fluoride and yttrium oxyfluoride.

6. The semiconductor processing system of claim 5, wherein the coating containing yttrium fluoride, yttrium oxyfluoride, or yttrium fluoride and yttrium oxyfluoride on the surface of the hole further comprises yttrium oxide, YOFx, or a combination thereof.

7. A method for coating a component of a semiconductor processing chamber, the method comprising: Position components with exposed surfaces within the cavity; A coating comprising yttrium oxide is deposited on at least a portion of the exposed surface; The coating is exposed to a high-power plasma process with a power greater than or approximately 2 watts and a pressure of 500 millitor, the high-power plasma process including... The fluorine-containing precursor is flowed into the chamber. The fluorine-containing precursor forms plasma to generate plasma effluent. The coating surface is brought into contact with the plasma effluent; and At least a portion of the yttrium oxide is converted into yttrium fluoride, yttrium oxyfluoride, or yttrium fluoride and yttrium oxyfluoride.

8. The method of claim 7, wherein the plasma further comprises hydrogen, ammonia, helium, argon, or a combination thereof.

9. The method of claim 8, wherein the fluorine-containing precursor comprises nitrogen trifluoride.

10. The method of claim 7, wherein the yttrium oxide is deposited by atomic layer deposition, plasma spraying, electron beam deposition, chemical vapor deposition, physical vapor deposition, plasma-enhanced chemical vapor deposition, or a combination thereof.

11. The method of claim 10, wherein the yttrium oxide is deposited by a combination of atomic layer deposition and plasma spraying or electron beam deposition.

12. The method of claim 7, wherein the component defines a plurality of holes, each hole having an exposed hole surface, and wherein the coating is deposited on at least a portion of the exposed hole surface.

13. The method of claim 7, wherein the high-power plasma process comprises a power of about 10 watts to about 3,000 watts, a pressure of about 1 Torr to about 15 Torr, and a voltage of about 10 volts to about 1,000 volts.

14. The method of claim 7, wherein the high-power plasma process is performed for a time period sufficient to convert at least about 50% by weight of the yttrium oxide into yttrium fluoride.

15. The method of claim 14, wherein the high-power plasma process is performed for at least about 1 hour.

16. The method of claim 7, wherein the high-power plasma process is performed for a time period sufficient to produce the coating with a thickness greater than or approximately 1 μm.

17. A method for coating one or more components of a semiconductor processing chamber, the method comprising: Multiple chamber components having exposed surfaces are positioned within the semiconductor processing chamber, the multiple chamber components including Panel, the panel defining a plurality of first holes and Spray head, the spray head defining a plurality of second holes; A coating comprising yttrium oxide is deposited on at least a portion of the exposed surfaces of the plurality of chamber components; In the semiconductor processing chamber, at least a portion of the yttrium oxide is converted into yttrium fluoride, yttrium oxyfluoride, or yttrium fluoride and yttrium oxyfluoride.

18. The method of claim 17, wherein the plurality of chamber components further includes a cover layer supporting the panel and a base configured to support a semiconductor substrate.

19. The method of claim 17, wherein the method is performed under pressure.

20. The method of claim 17, wherein the semiconductor processing chamber further includes a first electrode and a second electrode, wherein the first electrode and the second electrode are configured to provide at least about 2 watts of power during the conversion.

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