Optoelectronic device and method of manufacturing optoelectronic device

Abstract

The invention relates to an optoelectronic device (1) having a semiconductor layer stack (10) comprising a planar first current transport layer (11c) of a first doping type, a two-dimensional active layer (12) and a second current transport layer (13b) of a second doping type. A first electrically conductive contact layer (24) is arranged on the first current transport layer opposite at least a first portion of the active layer, and a second electrically conductive contact layer (30) as a structured layer is arranged on the second current transport layer opposite a second portion of the active layer. In order to increase the local current density in an active region (40) of the active layer that is partially common to or adjacent to the first and second portions of the active layer, the first and second portions are spatially offset from each other. Methods of manufacturing optoelectronic devices are also disclosed.

Description

[0001] This application claims priority to German patent application DE 10 2023 105 932.7, dated March 9, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0002] This invention relates to optoelectronic devices and methods for processing optoelectronic devices. Background Technology

[0003] Optoelectronic devices (also known as μ-LEDs) are becoming increasingly smaller, with lateral dimensions ranging from a few micrometers, for example, 2 μm to 20 μm. This small size enables μ-LEDs to be used for optical data communication between hardware components in computer systems and networks, optical networks, and more. Using μ-LEDs for optical data communication offers several key benefits. In addition to size, improved scalability and lower current consumption allow the use of optoelectronic devices such as VCSELs.

[0004] Conventional μ-LEDs offer similar benefits, and furthermore, include lower power consumption in short- and mid-range interconnects used for data communication. The latter is relevant because the reduced power consumption also alleviates the heat dissipation or temperature constraints typically found in high-density packaged hardware. However, in addition to high quantum efficiency, these μ-LEDs and optoelectronic devices generally require very fast switchability or high modulation capability of the light-emitting components to allow for high data rates. Such data rate ranges with modulation rates up to 10 GHz correspond to pulses of approximately 0.1 ns. These pulses need rise and fall times of approximately 20 ps to be detectable without a high error rate.

[0005] The main limitation in this regard is the radiative recombination lifetime of charge carriers, which restricts the rise and fall times of light emission in μ-LEDs when modulating the current through the optoelectronic component. In PWM applications with current switching on and off, the rise and fall times, primarily determined by the radiative recombination lifetime of charge carriers, distort the signal, thus requiring a longer on-pulse. This reduces the achievable data rate.

[0006] Current solutions and μ-LEDs have been shown to have too long a radiative recombination lifetime for the rise and fall times required to achieve data rates in the range of hundreds of megahertz and up to 1 GHz, and are therefore not optimal for such high data rates.

[0007] Therefore, the purpose of this application is to improve the modulation frequency and switchability of μ-LEDs and optoelectronic components to allow high data rates in the range of hundreds of MHz to several GHz. Summary of the Invention

[0008] This and other objectives are addressed by the subject matter of the independent claim. The features and other aspects of the proposed principle are outlined in the dependent claims.

[0009] This application proposes design changes to the semiconductor structure of optoelectronic components (such as μ-LEDs and lasers, such as VCSELs) to increase the local charge carrier density in the active region of the optoelectronic device. The increased local charge carrier density reduces the radiative lifetime when the current passing through the device is modulated. In this respect, the modulation can be only partial—i.e., between two different operating currents (corresponding to a modulation depth of less than 100%)—but can also be digital, as in PWM modulation.

[0010] Design changes to optoelectronic devices can reduce quantum efficiency and light intensity during device operation. However, by using various techniques to improve light extraction efficiency, the switchability of optoelectronic devices can be significantly increased without excessively compromising extraction efficiency.

[0011] Known methods for reducing radiative lifetime include background doping in the barrier or directly in the quantum well to increase charge carrier density. However, while beneficial, this approach is limited to small current states and may only work for certain specific currents. As an alternative, material quality can be reduced by realizing non-radiative defect centers to decrease charge carrier lifetime. However, this typically negatively impacts the device's internal quantum efficiency and long-term stability.

[0012] In the proposed principle, the electrical contacts of the n-doped and p-doped semiconductor materials are spatially offset laterally from each other. This offset results in an enhancement of the local current density, or charge carrier density, during operation of the device within a portion of the active layer, known as the active region. This increase in localized charge carrier density significantly improves switching and modulation speeds. Additional measures, such as removing portions of the top contact layer, reduce absorption and increase light extraction. Other measures, such as roughening or etching the emitting surface, also contribute to and improve light extraction.

[0013] In some other respects, the semiconductor layer stack of an optoelectronic device can be selectively etched to provide a high surface area to volume ratio. This allows for rapid carrier relaxation, thereby improving the overall modulation speed.

[0014] In one aspect of the proposed principle, an optoelectronic device includes a semiconductor layer stack having a planar first semiconductor layer of a first doping type, a second semiconductor layer of a second doping type, and an active layer disposed therebetween. The second semiconductor layer may further include a main emitting surface layer portion. In other words, light generated in the active layer during operation of the optoelectronic device is emitted through the main emitting surface layer portion. The optoelectronic device also includes a contact layer disposed on the first semiconductor layer opposite to at least a first portion of the active layer. Furthermore, a structured contact layer is provided disposed on the second semiconductor layer opposite to a second portion of the active layer.

[0015] According to the proposed principle, the first and second portions are spatially offset laterally from each other. This configuration increases the local charge carrier density in the active region of the active layer defined by the offset, which can be shared or adjacent to the first and second portions of the active layer, respectively.

[0016] By providing and positioning a structured contact layer, a spatial lateral offset is created, thereby reducing the effective active layer by decreasing the current diffused through the semiconductor layer. For the purposes of this application, the reduced effective active layer is referred to as the active region.

[0017] Therefore, in some aspects of the proposed principle, the active region is defined by the projection of the overlapping portion of the first and second portions of the active layer (i.e., the portion of the active layer covered by the overlapping portion). The charge carrier density during device operation is greatest in such an overlapping portion. Alternatively, the active region can be represented by the projection of the mutually facing edges of the contact layer and the structured contact layer onto the active layer, i.e., by the region of the active region within the projection of the edges toward the active layer. In such an embodiment, the contact layer and the structured contact layer do not overlap each other, but are spatially separated in the lateral direction. However, the region between the mutually facing edges of the respective contact layer and the structured contact layer includes an increased charge carrier density during device operation, thus constituting the active region.

[0018] By appropriately constructing the corresponding contact layer, an active region of a specific shape can be formed. For example, the active region can be implemented as a closed circumferential structure, specifically a ring-shaped or polygonal structure that respectively surrounds one of the first and second portions and is surrounded by the corresponding other of the first and second portions. Therefore, when viewed from the top or bottom, the active region forms a polygon or ring during device operation.

[0019] In some respects, it is useful to provide an active layer with a region larger than that of the contact layer, to form an active region that includes well-defined current or charge carrier confinement. In other respects, when viewed from above, the structured contact layer can form a closed circumferential structure, particularly a ring or polygon. In some respects, the circumferential structure surrounds a portion of the main emitting surface layer.

[0020] Several aspects involve further design changes compared to conventional optoelectronic devices. In some aspects, the second semiconductor layer is at least partially recessed in a region of the main emitting surface layer. In other words, some material of the second semiconductor layer is removed in a region of the main emitting surface layer. In some aspects, the second semiconductor layer comprises multiple layers, one of which is a highly n-doped current-spreading layer.

[0021] This sublayer can be arranged partially opposite to the second portion of the active layer. Therefore, in some aspects, the highly doped current-spreading sublayer opposite the first portion of the active layer is at least partially recessed, reducing its thickness. This prevents unwanted current diffusion of charge carriers injected through the structured contact layer. In some aspects, the recess can extend not only through a portion of the second semiconductor layer but also through the active layer itself. In such aspects, the active layer can form a closed circumferential structure, particularly by removing the annular or polygonal shape of the central portion.

[0022] In some respects, the recesses can be filled with an insulating material different from that of the active layer. In some respects, the exposed sidewalls of the second semiconductor layer and the active layer can be covered with a thin layer of dielectric material (e.g., SiO2 or Al2O3).

[0023] In some other aspects, dielectric material covers the contact layer, the first semiconductor layer, and the sidewalls of the active region, respectively. This dielectric material can be deposited on the outer sidewalls of such layers. This is, for example, the case when an optoelectronic device is a mesa-structured component. In some other aspects, the dielectric material can also be covered by a reflective layer, such as a reflective metal. The material can be part of a metal contact that contacts the portion of the contact layer deposited on the dielectric material. The reflective metal on the sidewalls acts as a mirror to reflect the generated light back to the main emitting surface.

[0024] Some other aspects involve increasing the switching speed by providing an auxiliary electrode to inject additional charge carriers into or deplete additional charge carriers from the active region during modulation or switching of the optoelectronic device. Therefore, according to the proposed principle, the optoelectronic device also includes a first auxiliary electrode electrically connected at a location outside a corresponding one of the first and second semiconductor layers. Thus, one of the first and second semiconductor layers now includes both carrier injection and carrier depletion possibilities; respectively, one is a main contact layer or a structured contact layer, and the other is the proposed additional first auxiliary electrode.

[0025] In some aspects, the optoelectronic device is further improved by a second auxiliary electrode, which is connected to the other of the first and second semiconductor layers at a location outside a corresponding one of the first and second portions. Therefore, by additionally applying current to the first and second auxiliary electrodes, respectively, carrier injection or depletion can be enhanced. Thus, such a structure allows the optoelectronic device to be modulated by the corresponding current of the additional auxiliary electrode while maintaining bias operation of the main current through the contact layer and the structured contact layer, respectively.

[0026] In some respects, the first auxiliary electrode and / or the second auxiliary electrode may form a ring-shaped structure surrounding a corresponding one of the first and second portions.

[0027] In the aforementioned respect, additional current is injected into the active region via the first and second auxiliary electrodes. However, a similar method can be implemented through the design and integration of the gate potential, allowing the operation of the optoelectronic components to be performed without additional integrated circuits for switching components.

[0028] In some aspects, μ-LEDs and optoelectronic devices include a dielectric gate material deposited on a sidewall portion of an active layer, extending partially onto an adjacent sidewall portion of at least one of a first semiconductor layer and a second semiconductor layer. A metal contact forming a conductive contact gate is applied to the dielectric material.

[0029] Therefore, the transistor gate is formed adjacent to the active layer (or active region), thereby providing the possibility of manipulating the optoelectronic device via a third potential. The gate can cover the active layer alone or together with one of the first and second semiconductor layers. In some other aspects, the gate can also be applied to one of the doped layers near the active region. This makes it possible to confine the transport and diffusion of charge carriers through such a segment. Furthermore, even combinations of all the aforementioned regions and layers are possible. This can be achieved by the gate being a classic 2D sheet gate as well as more complex structures such as a circumferential gate around the sidewalls of the active region.

[0030] Therefore, in some aspects, the dielectric material is arranged substantially parallel to the direction of charge carrier diffusion during device operation. Alternatively or additionally, the dielectric material may also be arranged substantially perpendicular to the active region. In the case where the optoelectronic device includes a centrally located recess extending through the active layer, the gate material may be disposed on the inner sidewall of such a recess directly adjacent to the active region. Furthermore, a second gate material may be deposited on the outer peripheral sidewall of the active layer.

[0031] On the other hand, a method for processing an optoelectronic device is involved. This method requires providing a first semiconductor layer having a first doping type, a second semiconductor layer having a second doping type, and an active layer located therebetween. A contact layer is deposited on the first semiconductor layer opposite at least a first portion of the active layer. The layer stack can then be re-bonded, and a temporary growth substrate can be removed to expose the surface of the second semiconductor layer.

[0032] A structured contact layer is then disposed on a second semiconductor layer opposite the second portion of the active layer, such that at least a portion of the surface of the second semiconductor layer opposite the contact layer is exposed. The respective steps of depositing the contact layer and the structured contact layer are performed such that the respective layers include a spatial offset towards each other in the lateral direction. This increases the local charge carrier density in the active region of the active layer between the respective first and second portions of the active layer.

[0033] As described above, the active region in the active layer is defined by the projection of the overlapping portions or the projection of the edges of the contact layers facing each other. Depending on the implementation, the active region can form a closed circumferential structure, such as a ring or a polygon.

[0034] In some other aspects, the method according to the proposed principle includes recessing the surface of the second semiconductor layer opposite the contact layer to form a recess. Therefore, a portion of the second semiconductor layer material is removed. The removed portion may constitute part of a highly doped current distribution layer that is part of the second semiconductor layer. Furthermore, a portion of the active layer may also be removed. In some aspects of the proposed principle, the portion of the first semiconductor layer opposite the contact layer may be removed to expose the surface of the contact layer or some remaining material of the first semiconductor layer.

[0035] In some other aspects, the step of providing the mesa-etched layer includes depositing dielectric material on the sidewalls of the first semiconductor layer and the active layer, respectively. Optionally, such dielectric material may also be deposited on the second semiconductor layer. The deposition of the dielectric material depends on the depth of the mesa etching process. Optionally, in some aspects, a metallic material may be deposited on the dielectric material, which acts as a reflector for light generated in the active region of the optoelectronic device.

[0036] In some other aspects, the first auxiliary electrode and the second auxiliary electrode can be deposited at a location outside a corresponding one of the first portion and the second portion, electrically connected to one of the first semiconductor layer and the second semiconductor layer. Both auxiliary electrodes can be implemented as annular structures surrounding a corresponding one of the first portion and the second portion.

[0037] Similarly, in one aspect, the method according to the proposed principle also includes depositing a dielectric gate material on a sidewall portion of the active layer, the dielectric gate material extending partially onto an adjacent sidewall portion of at least one of the first and second semiconductor layers. Alternatively, the dielectric gate material may also cover only one or two doped layers near the active region, thereby confining the transport and diffusion of charge carriers through such a segment.

[0038] Then, metal contacts are deposited to form conductive contact gates on the dielectric gate material. In this respect, the dielectric gate material can be arranged circumferentially on the inner sidewall of the active region. This is the case when the recess described above is formed in the optoelectronic device and penetrates the second semiconductor layer material. Similarly, the dielectric gate material can also be arranged on the circumferential outer sidewall of the active layer.

[0039] The first and second semiconductor layers have different doping types, and those skilled in the art will recognize that such doping types are not limited to specific p-doping or n-doping for the respective first and second semiconductor layers. The doping of the semiconductor layers can be interchanged. Furthermore, the respective first and second semiconductor layers may comprise multiple layers with different doping concentrations, distributions, and spatial variations. Additionally, both semiconductor layers may include an undoped cladding layer directly adjacent to the active layer to prevent dopant diffusion into the active layer.

[0040] The active layer itself may include one or more quantum well structures, multiple quantum well structures, or simple pn junctions. Regarding possible semiconductor materials, all types of group III-V semiconductor material systems should be mentioned, including nitride, arsenide, and phosphide systems. Therefore, examples include GaN, GaP, GaAs, AlGaN, AlGaP, AlGaAs, InGaN, InGaP, InGaAs, InAlGaN, InGaAlP, and InGaAlAs, as well as combinations thereof including different or varying concentrations of In or Al content. Attached Figure Description

[0041] Other aspects and implementations based on the proposed principles will become apparent in relation to the various embodiments and examples described in detail with reference to the accompanying drawings.

[0042] Figure 1A first embodiment of an optoelectronic device based on some aspects of the proposed principles is shown;

[0043] Figure 2 It shows that according to Figure 1 A top view of the optoelectronic device;

[0044] Figure 3 A second embodiment of an optoelectronic device based on some aspects of the proposed principles is shown;

[0045] Figure 4 A third embodiment of an optoelectronic device based on some aspects of the proposed principles is shown;

[0046] Figure 5 A fourth embodiment of an optoelectronic device based on some aspects of the proposed principles is shown;

[0047] Figure 6 A fifth embodiment of an optoelectronic device based on some aspects of the proposed principles is shown;

[0048] Figure 7 A sixth embodiment of an optoelectronic device based on some other aspects of the proposed principles is shown;

[0049] Figure 8 It shows that according to Figure 7 A top view of the optoelectronic device;

[0050] Figure 9 A seventh embodiment of an optoelectronic device based on some other aspects of the proposed principles is shown;

[0051] Figure 10 An eighth embodiment of an optoelectronic device based on some other aspects of the proposed principles is shown;

[0052] Figures 11A to 11E Several processing steps for processing optoelectronic devices based on some aspects of the proposed principles are shown. Detailed Implementation

[0053] The following embodiments and examples disclose various aspects and combinations thereof based on the proposed principles. The embodiments and examples are not always drawn to scale. Similarly, different elements may be enlarged or reduced in size to emphasize aspects. It goes without saying that the aspects of the embodiments and examples shown in the figures can be combined with each other without difficulty, which does not contradict the principles of the invention. Some aspects show regular structures or shapes. It should be noted that in practice, minor differences and deviations from the ideal form may occur; however, this will not contradict the inventive concept.

[0054] Furthermore, the various figures and aspects are not necessarily shown at the correct dimensions, and the proportions between the elements do not necessarily have to be substantially correct. Some aspects are highlighted by being shown enlarged. However, terms such as "above," "over," "below," "under," "larger," and "smaller" are correctly used to represent the elements in the figures. Therefore, such relationships between elements can be inferred from the figures.

[0055] In conventional implementations of optoelectronic devices and μ-LEDs as vertical devices, the corresponding metal contact layer on the n-doped side or for the p-doped side typically extends across the entire emitter surface or across the entire active layer to ensure a uniform current distribution into the active layer. Therefore, the corresponding semiconductor layer may also include a highly doped current distribution sublayer to ensure substantially uniform carrier injection into the active layer.

[0056] This invention now proposes confining charge carrier injection to only a small portion of the entire active layer (referred to as the active region). In other words, the injection of charge carriers, at least from one side into the semiconductor material and subsequently into the active layer, is no longer uniformly distributed across the entire region, but rather confined to a small portion of the available semiconductor material. Therefore, when the current through the device is modulated or when the optoelectronic device is switched from an "on" to an "off" operating state, the charge carrier density and current density within this segment increase significantly, allowing for very rapid and fast carrier depletion or injection, and vice versa.

[0057] Therefore, compared to conventional techniques, modulating optical emission via current amplitude modulation can occur significantly faster, where available charge carriers are distributed across a larger region, thus requiring a longer recombination time within the active region. The reduction in charge carrier lifetime, which limits radiative decay, is achieved by confining charge carriers to a smaller portion of the active layer. Although increasing the current density only in a small region of the active layer may lead to increased heat generation in that region, heat transfer mechanisms are well-established to ensure no damage to the optoelectronic device. Another potential drawback is the reduced optical emission due to the smaller region in which charge carriers can recombine. However, this drawback can be overcome by improving the switching and modulation speeds of the device, particularly relevant to optical data communication.

[0058] Therefore, the following embodiments are optimized for reduced radiative recombination lifetime, thereby improving the rise and fall times of the light pulse when modulating the current through the optoelectronic device. In this respect, the embodiments shown herein are to scale and can therefore be implemented in various sizes and with various technologies. Although only μ-LEDs are shown herein, the proposed principles can be transferred to VCSELs or other types of optoelectronic devices. In particular, the proposed principles are applicable to μ-LEDs with sizes or dimensions less than 100 μm, as small as tens of micrometers or even smaller.

[0059] Figure 1 A first implementation based on the proposed principles is shown.

[0060] The optoelectronic device or μ-LED 1 includes a semiconductor layer stack 10. The semiconductor layer stack 10 includes a first semiconductor layer 11 of a first conductivity or doping type, an active region 12, and a second semiconductor layer 13 of a second doping type disposed on top of each other. The active layer 12 may include a single quantum well, a pn junction, or multiple quantum wells, respectively.

[0061] The corresponding semiconductor layers 11 and 13 also include one or more sublayers for current distribution and other functions, which will be described in more detail below. In this regard, semiconductor layers 11 and 13 and active layer 12 may comprise III-V group semiconductor materials, and more specifically, ternary or quaternary materials based on nitride, arsenide or phosphide material systems.

[0062] Specifically, semiconductor layer 11 includes a current distribution sublayer 11b, a current transport layer 11c, and an undoped cladding layer 11a directly adjacent to the active layer 12. Similarly, the second semiconductor layer 13 includes an undoped cladding layer 13a, a current transport layer 13b, and a current distribution layer 13c adjacent to the active layer. The cladding layers 13a and 11a are undoped to prevent undesirable diffusion of dopants from the current transport layers 13b and 11c into the active region, respectively. The current transport layers 11c and 13b include a doping concentration that is constant but can vary with distance from the active region. The current distribution layers 11b and 13c are highly doped to provide equal current distribution across semiconductor layers 13 and 11, respectively.

[0063] The optoelectronic device 1 also includes a first contact layer 24, which is disposed directly on the current distribution layer 11b of the layer stack 10. The contact layer 24 may include a semiconductor material or a metal and is connected to a metal contact 20 within a recess 21 of the insulating material 22. The metal contact 20 injects charge carriers into the current distribution layer 11b via the contact layer 24.

[0064] like Figure 1 As shown, the material of the metal contact 20 is disposed in the recess of the dielectric material of layer 22 and contacts the contact layer 24. The dielectric material further extends toward the top surface of the semiconductor layer 11, surrounds the contact layer 24, and covers the sidewalls of the semiconductor layer 11. The dielectric material 25 further extends to the sidewalls of the active layer and partially extends onto the semiconductor layer 13.

[0065] This structure is similar to conventional optoelectronic devices, in which the mesa-etched sidewalls of the stacked semiconductor layers are covered with a corresponding dielectric material to prevent the formation of dangling bonds that would lead to nonradiative recombination centers. Furthermore, the dielectric material surrounding layers 22, 23, and 25 of the contact layer 24, semiconductor layer 11, and active layer 12 prevents oxygen diffusion or its damage.

[0066] In this embodiment, the main emitting surface 14 of the optoelectronic device 1 corresponds to the top surface of the semiconductor layer 13. The main emitting surface does not contain any contact material, but a structured contact layer 30 is deposited on the top surface of the layer 13.

[0067] More specifically, the structured contact layer 30 includes a ring structure but does not extend across a portion of the semiconductor layer 13, which is projected to reside above the contact layer 24 or the active layer 12. In other words, material of the contact layer 30 is removed to expose the main emitting surface 14, and it resides only on the portion of the semiconductor layer 13 that is not disposed directly above the active layer 12 or the contact layer 24. As a result, the contact layer 24 and the structured contact layer 30 are spatially offset from each other in the lateral direction, with a portion 40 adjacent to both of them.

[0068] The portion 40 is formed by the projection of the mutually facing outer edges of the respective contact layers 24 and 30 toward the active layer 12. It defines a common portion of the active layer 12, which is closest to the respective contact layers 24 and 30. During operation of the optoelectronic device, charge carriers provided by the structured contact layer 30 are likely to be injected into the active layer within portion 40 and subsequently recombine with charge carriers of opposite conductivity provided by the contact layer 24. In other words, the charge carriers injected into the active layer 12 are confined within portion 40 of the optoelectronic device and are therefore unevenly distributed across the entire active layer 12. The section of the active layer 12 within portion 40 is called the active region because most light emission occurs in this region during operation.

[0069] While confining charge carriers to a portion 40 of the active layer 12 can lead to reduced light emission, removing the contact layer 30 on the main emitting surface 14 can reduce the potential absorption of the contact layer 30 and thus improve the total light emission through the surface 14. Light extraction can be further improved by roughening or etching the surface 14.

[0070] Figure 2 Presented in Figure 1A top view of the corresponding embodiment. As indicated, the structured contact layer 30 forms an annular structure surrounding the portion 40, which is realized by the projections of the structured contact layer 30 and contact layer 24 toward the active layer 12, respectively. During device operation, due to charge carrier confinement, the main emission is likely to originate from the active region in the portion 40. By constructing the corresponding contact layer 30, layer stack 12, or contact layer 24, the shape and size of the portion 40 can be altered, thereby controlling light emission during current modulation entering the optoelectronic device.

[0071] Figure 3 Another embodiment based on the proposed principles is shown. Identical elements are represented by the same reference numerals. In this embodiment, the dielectric material of insulating layers 22, 23, and 24 extends across the side surfaces of the optoelectronic device, and thus covers not only the sidewalls of semiconductor layer 11 and active region 12, but also the sidewalls of semiconductor layer 13. As shown, dielectric layer material 26 extends from the bottom surface of contact layer 24, which realizes recess 21, across the sidewalls to the level of main emitting surface 14. Furthermore, the material of metal contact 20 is deposited on dielectric material 26, acting as a mirror for emitting light laterally.

[0072] In some aspects, the second semiconductor layer 13 includes a highly doped current distribution layer 13c adjacent to the contact layer 30. The highly doped current distribution layer 13c distributes charge carriers injected from the contact layer 30 substantially equally across the semiconductor region to uniformly inject charge carriers into the active layer. The inventors now propose removing segments or portions of the highly doped current distribution layer 13c to confine carrier injection to a smaller portion.

[0073] Figure 4 A corresponding implementation is illustrated. In this solution, the central portion of the current distribution layer 13c is removed, exposing the main emitter surface 14 of the top surface of the sublayer 13b, which serves as the second semiconductor layer 13. The area of ​​the current distribution layer 13c that is removed is slightly smaller than the corresponding area of ​​the contact layer 24. Therefore, the contact layer 24 overlaps with the corresponding edge portion of the structured contact layer 30 at its edge portion. Thus, an overlap portion 41 is achieved, in which carrier injection occurs through the contact layer 24 and the structured contact layer 30. Charge carriers are transferred into the overlap portion 41 or the active region closely adjacent to it. Therefore, the partial removal of the current distribution layer can further significantly constrain the current injection in the active layer, thereby increasing the current density in the active region of the overlap portion 41.

[0074] The exposed surface of the transport sublayer 13b can be protected by depositing an insulating layer material in the recess. This insulating layer material ( Figure 4(Not shown) The exposed remaining portion of the sidewall surface covering the main emitting surface 14 and the current distribution layer 13c. In some other cases, the recesses in the semiconductor layer 13 may extend further toward the active layer and even through the active layer 12 in order to further confine charge carriers to the overlapping portion 41.

[0075] Figure 5 The other aspect shown relates to improvements in charge carrier removal during modulation of the current passing through the optoelectronic device.

[0076] To this end, additional auxiliary electrodes are placed on the p-doped or n-doped side, respectively, to further facilitate the flow or depletion of charge carriers through the active region during modulation. Consequently, the rise and fall times become faster (or steeper), and the switching of the optoelectronic device is significantly faster than conventional devices. This is achieved by providing or depleting the active region for generating emitted light with charge carriers.

[0077] Figure 5 Two auxiliary electrodes 50 and 51 are shown. Electrode 50 is disposed on the exposed portion of the first semiconductor layer 11 near the active region 12. For this purpose, a portion of the dielectric material 23 is removed and replaced by the contact material of the auxiliary electrode 50. Similarly, a second auxiliary contact electrode 51 is disposed on the exposed sidewall portions of the current distribution layer 13c and the current transport layer 13b, respectively. Electrode 51 is separated from the structured contact layer 30 so that the auxiliary electrode 51 can be controlled independently.

[0078] In this example, auxiliary electrodes 50 and 51 are located on specific sides of the optoelectronic device. However, the auxiliary electrodes can extend and be implemented as annular electrodes surrounding the sidewall portions of the first semiconductor layer 11 and the second semiconductor layer 13, respectively. In such an implementation, additional charge carrier injection is uniformly performed around the active layer 12 to increase charge carrier injection and depletion. Figure 5 In one embodiment, the overlapping portion 41 is formed by the corresponding edge portions of the contact layers 24 and 30 projected onto the active region (typically in the section of the active layer 12 between the overlapping portions).

[0079] Figure 6 It shows that Figure 4 Features of the implementation method and Figure 5 The implementation method and the device consisting of additional auxiliary contact electrodes 50 and 51, respectively. Figure 6 In this embodiment, the central portion of the current distribution layer 13c is removed, forming a central recess and exposing the top surface of the current transport layer 13b. The auxiliary electrode 50 contacts the first semiconductor layer 11 independently of the main contact layer 24. Conversely, the auxiliary electrode 51 contacts the second semiconductor layer 13, but also contacts the structured contact layer 30 via a shortcut. Therefore, in Figure 6In this embodiment, the total surface area of ​​the structured contact layer 30 is increased by the second auxiliary electrode 51. The first auxiliary electrode 50 can be activated or deactivated independently according to the desired switching and modulation speed.

[0080] Figure 7 Another embodiment is shown in which the auxiliary electrode 50 is arranged to surround a portion of the first semiconductor layer 11, but is isolated from the contact layer 24 and the metal contact 20 by materials 22 and 23, respectively. Furthermore, in this embodiment, the recess extends further down into the contact layer 24, thereby also removing material from the central portion of the active layer 12 and the first semiconductor layer 11. Thus, the annular structure of the current-constrained portion 40 and the active region is retained for the optoelectronic device. The structured contact layer 30 is spatially offset relative to the contact layer 24 in the lateral direction by the non-overlapping portion 40. Any current injection from the contact layer 24 or the structured contact layer 30 will likely recombine within the current-constrained portion 40. Furthermore, the auxiliary electrode 50 is in electrical contact with the portion 40, particularly with the first semiconductor layer 11 defining the current-constrained portion 40. The close proximity of the auxiliary contact electrode 50 can improve the overall switching speed and rise and fall times.

[0081] The structured contact layer 30 and the resulting recesses can have various forms and shapes, such as Figure 8 A and Figure 8 As shown in the top view of B. Figure 8 Figure A shows a top view of the optoelectronic device, wherein the structured contact layer 30 comprises a substantially rectangular shape, and the corresponding current-constraining portion 40 and its active region are also rectangular in shape. During operation of the optoelectronic device, any light emission from the optoelectronic device is now emitted from the surface of portion 40, either from its top surface or its side surface.

[0082] Figure 8 B illustrates a similar implementation, in which the structured contact layer 30 is shaped into a circle. Similarly, the portion 40 and its active region of semiconductor material, as well as the recesses exposing the contact layer 24, are also shaped surfaces.

[0083] In some embodiments, the recess is filled with a dielectric transparent material to provide improved emission from the optoelectronic device and protect the surface of portion 40 from oxidation or any mechanical damage. In this regard, the top and side surfaces of portion 40 or portion 41 can be further configured to provide improved outgoing coupling. Additionally, the centrally located recess can be filled with a conversion material, such as quantum dots. However, to achieve light conversion in the optoelectronic device, the lifetime of photons absorbed and converted by the conversion material should be significantly shorter than the switching or modulation period of a current-constrained optoelectronic device according to the proposed principles, to avoid reduced switching speed or other disadvantages.

[0084] Figure 5 , Figure 6 and Figure 7 Previous embodiments have shown auxiliary electrodes for injecting additional charge carriers into the semiconductor material to increase or deplete the charge carrier density in the active region (i.e., the sections of the active layer in portions 40 or 41, respectively).

[0085] However, this embodiment can be modified to provide a transistor-like optoelectronic device in which one or more gates 60, 61 are arranged on the exposed sidewalls of the active layer 12. These gates function similarly to MOSFET gates, and the potential applied to the respective dielectric gates changes the channel and active layer band structure, and thus increases or decreases the internal resistance or current. Such a method applied to optoelectronic devices according to the proposed principle improves switching speed.

[0086] Figure 9 and Figure 10 A corresponding exemplary embodiment of such a gated optoelectronic device is shown.

[0087] exist Figure 9 In China, optoelectronic devices include those similar to Figure 6 or Figure 7 In this embodiment, a recess is created, and a portion of semiconductor layer 13 and layer 11 is removed, exposing the sidewalls of the second semiconductor layer 13, the active layer 12, and a portion of the sidewalls of layer 11. The exposed top surface of the first semiconductor layer 11 is covered by a small layer 61 of dielectric material. A gate 60 (which is also a dielectric material) is deposited on the sidewalls of the active region and extends slightly below and above the active region, thereby also covering portions of the sidewalls of layers 13 and 11. In other words, the gate 60, for example, covers the multi-quantum-well structure of the active region and the adjacent cladding layers of the first and second semiconductor layers.

[0088] A metal contact 62 is applied above the gate 60. When viewed from above, the gate 60 and the metal contact 62 are implemented as an annular circumferential structure within a recess of the device. By providing a voltage to the metal contact 62, the strip structure adjacent to the gate 60 changes and deforms according to the thickness of the overlapping portion 41 and the size of the current-constrained portion. Therefore, the gate 60 can act as a switch or modulator, changing the total current entering the active region.

[0089] Figure 10 Another embodiment is shown, wherein corresponding gates are implemented on the two sidewalls of the active layer 12 at the respective current-constrained portions 41. In particular, the first gate structure is implemented on the inner sidewall of the active layer 12, i.e., facing the central region of the optoelectronic device, while the second gate 64 is formed as a ring that completely surrounds the active layer 12 on the outside.

[0090] Metal contacts 65 are disposed on the second gate 64. The metal contacts may be distributed across the gate 64, or as follows: Figure 10 The diagram shows a slight shift. In both cases (for gates 60 and 64), by applying a voltage, charge carriers can be repelled or attracted, resulting in injection or depletion within the active region.

[0091] The two gates are controlled independently to apply corresponding voltages to the active layer 12 and the current-constrained portion 41, respectively. The overall emission is modulated according to the switching speed of the gate potentials and the modulation frequency by varying the voltages applied to the respective gates. Therefore, the device can operate in a continuous manner, and modulation (especially amplitude modulation) is performed by applying potentials to the gate voltages.

[0092] exist Figure 9 and Figure 10 In one implementation, the gate material is applied across the active region. However, this may not be necessary. Instead, the gate material can be applied only to one or two doped layers near the active region, leaving the active region untouched by gate material. Keeping the surface of the active region free of any gate material and therefore without potential can be beneficial for IQU within the active region. However, any transport channels in the doped layers can be narrowed by the potential provided by the gate structure and the metal on the other side of the gate.

[0093] In similar operations, Figure 6 and Figure 7 The auxiliary electrode 50 can be used to inject or deplete charge carriers into the active regions of portions 40 and 41, respectively. These embodiments enable the emission of the optoelectronic device to be modulated by an additional current or voltage signal, even though the optoelectronic device itself is already operating above its threshold.

[0094] Figures 11A to 11E Various steps for processing optoelectronic devices based on the proposed principles are shown.

[0095] The method includes steps such as processing a semiconductor layer stack 10 based on a III-V semiconductor material on a temporary growth substrate 5. The layer stack 10 is deposited on the growth substrate 5 as multiple individual layers and their sublayers, which is adapted to be fabricated for subsequent growth processes. For example, the growth substrate 5 includes one or more buffer layers to reduce surface defects and obtain a flat and defect-free growth surface.

[0096] The second semiconductor layer 13 is deposited on the buffer layer of the substrate 5. As previously described, the second semiconductor layer 13 may include multiple sublayers, including but not limited to a first highly doped sublayer 13c adjacent to the buffer layer of the growth substrate 5. Figure 11A(Not shown in the image). The highly doped sublayer represents the current injection layer in a conventional device. Additional sublayers may include a doped charge carrier transport layer and a cladding layer. The cladding layer is undoped and separates the multi-quantum-well structure 12 from the doped transport sublayer of the second semiconductor layer 13.

[0097] The active layer 12 is implemented using a multi-quantum-well structure comprising multiple alternating barrier layers and quantum-well layers. The band gap in the barrier layer is slightly increased compared to adjacent quantum-well layers. Further measures, such as silicon doping in the barrier layer and other aspects, can be implemented during the deposition of the active layer 12.

[0098] The top surface of the active layer 12 is covered by another undoped cladding layer, which is part of the first semiconductor layer 11 deposited thereon. Above the undoped cladding layer, a charge carrier transport sublayer and a current distribution sublayer of the semiconductor layer 12 are deposited. Therefore, the first semiconductor layer 11 and the second semiconductor layer 13 comprise multiple differently doped sublayers that implement certain functions. The doping distribution and doping concentration can already reflect some of the subsequent steps and measures taken to improve the switchability of the optoelectronic device according to the proposed principles.

[0099] On the top surface of layer 11, a hard mask layer is deposited and then configured as the central portion of the capping layer stack 10.

[0100] exist Figure 11B The subsequent mesa etching process shown etches portions of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. The mesa etching process utilizes a hard mask 70 to provide the mesa-etched structure of the optoelectronic device. The mesa etching extends along the first semiconductor layer 11, the multiple quantum well structure 12, and partially extends onto the second semiconductor layer 13. The exposed sidewalls are then cleaned and covered with a thin layer of a dielectric material, such as Al2O3.

[0101] In a subsequent step, additional transparent dielectric material is deposited on the top surface and on the sidewalls forming the dielectric material, on portion 22 of the top surface, on portion 23 of the sidewalls of semiconductor layers 11 and 12, and on portion 25 of the sidewalls of semiconductor layer 13. The hard mask 70 can then be removed. This step can also be performed before the dielectric material is applied.

[0102] In this configuration, the dielectric material deposited thereon is then structured to form recesses filled with a highly doped contact layer material forming the contact 24. In this embodiment, the diameter of the contact layer 24 is smaller than the diameter of the active layer 12, with some of the dielectric material located above layer 11. Given that the shape of the contact layer 24 already provides some current injection constraints, variations of this portion of the structure can be readily derived.

[0103] The highly doped material of the contact layer 24 can be a semiconductor material, but it can also be a metal or alloy or a combination thereof.

[0104] In subsequent steps, the layer stack is re-bonded, with the surface of contact layer 24 and dielectric material 22 attached to temporary support carrier 5a. The growth substrate 5 is removed to expose the surface of the second semiconductor layer 13, particularly its highly doped current-injected sublayer 13c. The resulting component is... Figure 11C As shown in the image.

[0105] exist Figure 11D In the subsequent steps shown, the material of the contact layer 30 is deposited on the top surface and structured, for example, to form a central recess of the second semiconductor layer 13 and expose the top surface 14. The top surface may also later form part of the main emitting surface of the optoelectronic device. The material of the contact layer 30 includes highly doped semiconductor materials, but may also include metals. The contact layer 30 is configured to have very low resistance at the interface between the contact layer 30 and the highly doped current-injected sublayer 13c.

[0106] like Figure 11D As shown, the recesses within the material of the contact layer 30 are adjusted such that, when viewed from a top view, the inner edges of the contact layers 30 facing each other are located outside the projection of the contact layer 24 on the other side. Similarly, when viewed from a top view, the outer edge of the contact layer 24 does not intersect with the material of the contact layer 30.

[0107] Therefore, a circumferential portion of the active layer 12 is formed, which lies outside the projection of the contact layer 24 onto the active layer 12 and outside the projection of the structured contact layer 30 onto the active layer 12. Figure 11D and Figure 11E The region marked as 12a is called the active region.

[0108] The constraint on current injection is further enhanced by removing a portion of the second semiconductor layer 13, particularly the sublayer 13c in the central recess. This is achieved, for example, by using the contact layer 30 as a mask layer and selectively etching a portion of the sublayer 13c within the central recess of the structured mask layer 30. This recess improves the current constraint so that the current injected via the contact layer 30 and the contact 24 will diffuse primarily into the segment 12a of the active layer 12 that forms the active region of the optoelectronic device.

[0109] Reference tag list

[0110] 1 Optoelectronic devices

[0111] 10 Semiconductor layer stacking

[0112] 11 Semiconductor layer

[0113] 11a, 12a cladding layers

[0114] 11b, 13c current distribution layer

[0115] 11c Current transport layer

[0116] 12 Active Layer

[0117] 13 Semiconductor layer

[0118] 13b sublayer

[0119] 14 Main Launch Surface

[0120] 20 Metal contacts

[0121] 21 recess

[0122] 22 Insulation materials

[0123] 23, 25 Insulation Materials

[0124] 24 Contact Layer

[0125] 30 Structured contact layer

[0126] 40, 41 active regions

[0127] 50, 51 Auxiliary contact electrodes

[0128] 60, 64 gate

[0129] 61 Insulation Materials

[0130] 62, 65 metal contacts

Claims

1. An optoelectronic device, comprising: - A semiconductor layer stack, the semiconductor layer stack comprising a first semiconductor layer of a first doping type, an active layer, and a second semiconductor layer of a second doping type; - Wherein, the second semiconductor layer includes a main emitting surface layer portion; - A contact layer disposed on the first semiconductor layer, opposite at least a first portion of the active layer; - A structured contact layer disposed on the second semiconductor layer, opposite to a second portion of the active layer; - Wherein, the first portion and the second portion are spatially offset from each other in the lateral direction and are configured to increase the local charge carrier density in the active region of the active layer that is shared with or adjacent to the first and second portions of the active layer; wherein The active region is defined by the projection of the overlapping section of the first portion and the second portion onto the active layer.

2. The optoelectronic device according to claim 1, wherein... - The active region is defined by the projection of the mutually facing edges of the contact layer and the structured contact layer onto the active layer; and / or - The active region is formed by a closed structure, particularly a ring or polygon, which surrounds one of the first portion and the second portion and is surrounded by the corresponding other of the first portion and the second portion; and / or - The active layer includes a region larger than that of the contact layer.

3. The optoelectronic device according to any one of the preceding claims, wherein, The structured contact layer forms a closed structure surrounding the main emitting surface layer portion, particularly annular or polygonal.

4. The optoelectronic device according to any one of the preceding claims, wherein - The second semiconductor layer is at least partially recessed in the region of the main emitting surface layer portion; and / or - The second semiconductor layer includes a highly doped current-diffusing sublayer disposed partially opposite a second portion of the active layer, wherein optionally, the thickness of the highly doped current-diffusing sublayer opposite at least a first portion of the active layer is reduced; and / or -in, The active layer forms a closed structure, particularly a ring or polygon, wherein the central portion comprises a material different from the material of the active layer.

5. The optoelectronic device according to any one of the preceding claims further includes a dielectric material covering the sidewalls of the contact layer, the first semiconductor layer, and the active region, and optionally, wherein, The metal of the metal contact element that contacts the contact layer is deposited on a portion of the dielectric material.

6. The optoelectronic device according to any one of the preceding claims further includes a first auxiliary electrode, the first auxiliary electrode being conductive to one of the first semiconductor layer and the second semiconductor layer at a location outside a corresponding one of the first portion and the second portion.

7. The optoelectronic device of claim 6, further comprising a second auxiliary electrode, the second auxiliary electrode being conductive to the other of the first semiconductor layer and the second semiconductor layer at a location outside the respective first portion and the second portion; and / or wherein the first auxiliary electrode and / or the second auxiliary electrode form an annular structure surrounding a respective one of the first portion and the second portion.

8. The optoelectronic device according to any one of the preceding claims further comprises: - Dielectric gate material, the dielectric gate material being deposited on a sidewall portion of the active layer, the dielectric gate material extending partially onto an adjacent sidewall portion of at least one of the first semiconductor layer and the second semiconductor layer; - A metal contact, wherein the metal contact forms a conductive contact gate on the dielectric gate material.

9. The optoelectronic device according to claim 8, wherein... - The dielectric gate material is disposed on the circumferential inner sidewall of the active region; and / or - The dielectric gate material is disposed on the circumferential outer wall of the active layer.

10. The optoelectronic device according to any one of claims 8 to 9, wherein - The dielectric gate material is arranged to be substantially parallel to the direction of charge carrier diffusion during operation of the device; and / or - The dielectric gate material is arranged substantially perpendicular to the active region.

11. A method for processing an optoelectronic device, comprising: - Provides a mesa-etched layer stack having a first semiconductor layer of a first doping type, a second semiconductor layer of a second doping type, and an active layer therebetween; - A contact layer is deposited on the first semiconductor layer opposite to at least a first portion of the active layer; - Re-bond the layer stack and remove the substrate to expose the second semiconductor layer; - A structured contact layer is deposited on the second semiconductor layer opposite to a second portion of the active layer, such that at least a portion of the surface of the second semiconductor layer opposite to the contact layer is exposed; -The steps of depositing contact layers and structuring contact layers are performed such that the layers are laterally offset from each other in space to increase the local charge carrier density in the active region of the active layer that is shared or adjacent to the first and second portions of the active layer. in The active region is defined by the projection of the overlapping section of the first portion and the second portion onto the active layer.

12. The method of claim 11, wherein - The active layer includes a region larger than the region of the contact layer; and / or - The active region is defined by the projection of the mutually facing edges of the contact layer and the structured contact layer onto the active layer; and / or - The active region is formed by a closed structure, particularly a ring or polygon, which surrounds one of the first part and the second part and is surrounded by the corresponding other of the first part and the second part.

13. The method according to any one of claims 11 to 12, further comprising recessing the surface of the second semiconductor layer opposite to the contact layer to form a recess, and removing at least one of the following: - Part of a highly doped current distribution layer that is part of the second semiconductor layer; -A portion of the active layer; - A portion of the first semiconductor layer opposite to the contact layer.

14. The method according to any one of claims 11 to 13, wherein, The steps for providing the mesa-etched layer include the following: - Depositing dielectric material on the sidewalls of the first semiconductor layer and the active layer, and optionally on a portion of the second semiconductor layer; and optionally... - Deposit a metal contact material on the dielectric material.

15. The method according to any one of claims 11 to 14, further comprising the step of: A first auxiliary electrode that conducts electricity to one of the first semiconductor layer and the second semiconductor layer is deposited at a location outside a corresponding one of the first portion and the second portion; Optionally, the first auxiliary electrode can be deposited as a ring-shaped structure surrounding a corresponding one of the first portion and the second portion.

16. The method of claim 15, further comprising the step of: A second auxiliary electrode that conducts electricity to the other of the first semiconductor layer and the second semiconductor layer is deposited at a location outside the corresponding first and second portions; Optionally, the second auxiliary electrode can be deposited as a ring-shaped structure surrounding a corresponding one of the first portion and the second portion.

17. The method according to any one of claims 11 to 16, further comprising: - A dielectric gate material is deposited on a sidewall portion of the active layer, the dielectric gate material extending partially onto an adjacent sidewall portion of at least one of the first semiconductor layer and the second semiconductor layer; - A metal contact is deposited on the dielectric gate material to form a conductive contact gate.

18. The method of claim 17, wherein - The dielectric gate material is disposed on the circumferential inner sidewall of the active region; and / or - The dielectric gate material is disposed on the circumferential outer wall of the active layer.

19. The method according to claim 17 or 18, wherein - The dielectric gate material is arranged substantially parallel to the diffusion direction of the charge carriers during operation of the device; and / or - The dielectric gate material is arranged substantially perpendicular to the active region.

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