Register mapping processing method and device, processor and computer equipment

Abstract

The invention provides a register mapping processing method and device, a processor and computer equipment. The method comprises the steps that bit width comparison is conducted on a first architecture register and a second architecture register and a physical register; and under the condition that the sum of the bit width of the first architecture register and the bit width of the second architecture register is not greater than the bit width of the physical register, mapping the first architecture register to a first bit field of the physical register, and mapping the second architecture register to a second bit field of the physical register. According to the method, the space utilization rate of the physical register can be improved, the probability of register renaming blockage caused by insufficiency of the physical register is reduced, and then the performance of the processor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the computer technical field, and particularly relates to a register mapping processing method and device, a processor and a computer device. BACKGROUND

[0002] In the running process of a superscalar processor, the processing flow of an instruction usually includes the processes of instruction fetching, decoding, register renaming, execution and submission. The register renaming is to map an architectural register in an instruction set to a physical register.

[0003] In some cases, the bit width of a physical register is greater than that of an architectural register. If one architectural register is mapped to a physical register with a greater bit width, the physical register space will be wasted to some extent, the consumption of the physical register will be accelerated, and when there is no idle physical register, the register renaming cannot be performed, thus causing the processor to be blocked and the performance of the processor to be reduced. SUMMARY

[0004] Based on the above technical status, the present application provides a register mapping processing method and device, a processor and a computer device, which can improve the space utilization rate of a physical register, reduce the probability of register renaming blocking caused by insufficient physical registers, and thus improve the performance of a processor.

[0005] The first aspect of the present application provides a register mapping processing method, comprising:

[0006] Comparing the bit widths of a first architectural register and a second architectural register with a physical register;

[0007] In a case where the sum of the bit widths of the first architectural register and the second architectural register is not greater than the bit width of the physical register, mapping the first architectural register to a first bit segment of the physical register, and mapping the second architectural register to a second bit segment of the physical register.

[0008] In some implementation manners, the first architectural register and the second architectural register are architectural registers of the same type.

[0009] In some implementation manners, the first architectural register and the second architectural register are architectural registers corresponding to the same instruction.

[0010] In some implementation manners, after the first architectural register is mapped to the first bit segment of the physical register, and the second architectural register is mapped to the second bit segment of the physical register, the method further comprises:

[0011] generating a mapping position identifier, the mapping position identifier being used to identify a mapping bit segment of the first architectural register and / or the second architectural register in the physical register.

[0012] In some implementations, after mapping the first architectural register to a first bit segment of the physical register, and mapping the second architectural register to a second bit segment of the physical register, the method further comprises:

[0013] generating a mapping number identifier, the mapping number identifier being used to identify a number of architectural registers mapped to the physical register.

[0014] In some implementations, the method further comprises:

[0015] releasing the physical register in a case that data in the first bit segment and the second bit segment are respectively committed.

[0016] In some implementations, after mapping the first architectural register to a first bit segment of the physical register, and mapping the second architectural register to a second bit segment of the physical register, the method further comprises: generating a mapping number identifier, the mapping number identifier being used to identify a number of architectural registers mapped to the physical register.

[0017] The releasing the physical register in a case that data in the first bit segment and the second bit segment are respectively committed comprises:

[0018] counting a number of bit segments of the physical register in which data is committed during a process that data in the physical register is committed.

[0019] releasing the physical register in a case that the number of bit segments of the physical register in which data is committed is equal to the mapping number identifier.

[0020] In some implementations, the counting a number of bit segments of the physical register in which data is committed during a process that data in the physical register is committed comprises:

[0021] decreasing the mapping number identifier by 1 and / or increasing the number of bit segments of the physical register in which data is committed by 1 each time a bit segment of the physical register in which data is committed during a process that data in the physical register is committed.

[0022] The releasing the physical register in a case that the number of bit segments of the physical register in which data is committed is equal to the mapping number identifier comprises:

[0023] In a case where the mapping number identifier is equal to 0, and / or the number of bit segments in which data in the physical register is committed is equal to an initial value of the mapping number identifier, the physical register is released.

[0024] The second aspect of the present application provides a register mapping processing apparatus, comprising:

[0025] The comparison processing unit is configured to perform bit width comparison between the first architecture register and the second architecture register and the physical register.

[0026] The mapping processing unit is configured to, in a case where the sum of the bit width of the first architecture register and the bit width of the second architecture register is not greater than the bit width of the physical register, map the first architecture register to a first bit segment of the physical register, and map the second architecture register to a second bit segment of the physical register.

[0027] The third aspect of the present application provides a processor configured to perform the above-mentioned register mapping processing method.

[0028] The fourth aspect of the present application provides a computer device comprising the above-mentioned processor.

[0029] The register mapping processing method provided by the present application performs bit width comparison between the architecture registers to be mapped and the physical register in the register mapping process. When the bit width of the physical register is sufficient to map multiple architecture registers, multiple architecture registers can be mapped to the same physical register, thereby improving the space utilization of the physical register, reducing the probability of register renaming jamming problem caused by insufficient physical registers, and facilitating improvement of the processor performance. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0031] Figure 1 A flowchart of a register mapping processing method provided by an embodiment of the present application.

[0032] Figure 2 A structural diagram of a register mapping processing apparatus provided by an embodiment of the present application.

[0033] Figure 3 A structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical scheme provided in the embodiments of the present application is suitable for a working scenario of register renaming during the running of a processor. By using the technical scheme, the storage space of physical registers can be more fully utilized, the probability of register renaming blockage due to insufficient physical registers can be reduced, and the performance of the processor can be improved.

[0035] A superscalar processor is a processor capable of executing multiple instructions simultaneously in one clock cycle. It realizes parallel processing by pipelining instructions and using multiple execution units. Specifically, the instruction processing flow of a superscalar processor usually includes the following stages: instruction fetching, decoding, register renaming, scheduling, execution, write-back, and commit.

[0036] Register renaming refers to mapping the architectural registers required for executing instructions to physical registers, so as to avoid pipeline blockage caused by the contention for register resources among multiple instructions executed in parallel.

[0037] During register renaming, the processor maps the architectural registers of an instruction to a physical register, and the data generated in the subsequent execution of the instruction is written to the physical register. When the instruction is executed, the data in the physical register corresponding to the instruction is committed. In the above process, the mapping relationship between the architectural registers and the physical registers of each instruction is recorded in a register mapping table.

[0038] Under normal circumstances, the architectural registers and the physical registers are in a one-to-one mapping relationship, that is, one architectural register is mapped to one physical register. In some cases, the bit width of a physical register is greater than that of an architectural register. In this case, if one architectural register is mapped to a physical register with a greater bit width, the entire space of the physical register will not be actually used, which causes a certain degree of waste of physical register space and accelerates the consumption of physical registers. When there is no idle physical register, register renaming cannot be performed, which causes processor blockage and reduces the performance of the processor.

[0039] To solve the above technical problems, the embodiments of the present application provide a register mapping scheme, which can realize many-to-one mapping between the architectural registers and the physical registers, thereby improving the space utilization of the physical registers, reducing the probability of register renaming blockage due to insufficient physical registers, and improving the performance of the processor.

[0040] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort are within the scope of the present application.

[0041] The embodiment of the present application first proposes a register mapping processing method, which is applied to a processor, specifically, applied to a superscalar processor using instruction pipeline technology, as shown in Figure 1 The method comprises the following steps.

[0042] S101, comparing the bit widths of the first architecture register and the second architecture register and the physical register.

[0043] The first architecture register and the second architecture register mentioned above refer to different architecture registers that need to be mapped to the physical register at the current time.

[0044] In the embodiment of the present application, the first architecture register and the second architecture register mentioned above are different architecture registers corresponding to the same instruction. The first architecture register and the second architecture register can be one architecture register or the sum of multiple architecture registers, and the number of the architecture registers is not limited in the embodiment of the present application.

[0045] For example, in the working process of the instruction pipeline, the processor obtains an instruction through the fetch operation, and then determines that the instruction needs two architecture registers, i.e., the first architecture register and the second architecture register, after decoding the instruction. At this time, when the processor performs the next register renaming operation in the pipeline, the first architecture register and the second architecture register are the architecture registers that need to be mapped to the physical register at the current time.

[0046] In other embodiments, the first architecture register and the second architecture register mentioned above can also be the architecture registers corresponding to different instructions, respectively. For example, in the process of parallel execution of instructions by the processor, multiple instructions can be obtained at a certain time of fetching, such as the first instruction and the second instruction. Then, through the decoding operation, it is determined that the first instruction needs to apply the first architecture register and the second instruction needs to apply the second architecture register. Then, in the subsequent register renaming stage, the first architecture register and the second architecture register mentioned above are the architecture registers that need to be mapped to the physical register at the current time.

[0047] In the embodiments of the present application, the first architecture register and the second architecture register are architecture registers of the same type, for example, the first architecture register and the second architecture register are both integer type architecture registers, or the first architecture register and the second architecture register are both floating point type architecture registers.

[0048] The physical register is a physical register selected by the processor from a plurality of physical registers for performing the current register mapping operation.

[0049] When the processor executes to the register renaming stage, a physical register is selected from the idle physical registers for mapping the current architecture register to be mapped to the physical register. Therefore, in the embodiments of the present application, when the processor runs to the register renaming stage, the architecture register to be mapped and the physical register for mapping the architecture register are first determined.

[0050] In the embodiments of the present application, when the processor performs mapping on the first architecture register and the second architecture register, a physical register is first selected from the idle physical registers, and then the bit width of the first architecture register, the bit width of the second architecture register and the bit width of the physical register are compared, specifically, whether the sum of the bit width of the first architecture register and the bit width of the second architecture register is greater than the bit width of the physical register.

[0051] If the sum of the bit width of the first architecture register and the bit width of the second architecture register is greater than the bit width of the physical register, it means that the first architecture register and the second architecture register cannot be simultaneously mapped to the physical register, at this time the processor can map any one of the first architecture register and the second architecture register to the physical register, and then select another physical register from the idle physical registers, and map the remaining architecture register of the first architecture register and the second architecture register to the physical register, so as to map the first architecture register and the second architecture register to the physical registers respectively through one-to-one mapping.

[0052] S102, in the case that the sum of the bit width of the first architecture register and the bit width of the second architecture register is not greater than the bit width of the physical register, mapping the first architecture register to the first bit segment of the physical register, and mapping the second architecture register to the second bit segment of the physical register.

[0053] Specifically, if it is determined through the comparison of step S101 that the sum of the bit width of the first architecture register and the bit width of the second architecture register is not greater than the bit width of the physical register, it means that the space of the physical register is sufficient to simultaneously map the first architecture register and the second architecture register.

[0054] In this case, the processor maps the first architecture register and the second architecture register to different bit segments of the same physical register, i.e., maps the first architecture register to a first bit segment of the physical register and maps the second architecture register to a second bit segment of the physical register. After the mapping is completed, the mapping relationship between the first architecture register, the second architecture register and the physical register is stored in the register mapping table.

[0055] The first bit segment and the second bit segment are two different bit segments in the physical register and are non-overlapping. The first bit segment and the second bit segment can be adjacent or non-adjacent, and the bit widths of the first bit segment and the second bit segment can be the same or different.

[0056] For example, assuming that the physical register is a 64-bit physical register, the first architecture register is a 32-bit architecture register, and the second architecture register is a 32-bit architecture register. The processor can map the first architecture register to the high 32 bits of the physical register and map the second architecture register to the low 32 bits of the physical register.

[0057] As can be seen from the above description, the register mapping processing method proposed in the embodiments of the present application compares the bit widths of the architecture registers to be mapped and the physical register during the register mapping process. When the bit width of the physical register is sufficient to map multiple architecture registers, the multiple architecture registers can be mapped to the same physical register, thereby improving the space utilization of the physical register, reducing the probability of register renaming congestion caused by insufficient physical registers, and facilitating the improvement of the performance of the processor.

[0058] In some embodiments, after the processor maps the first architecture register to the first bit segment of the physical register and maps the second architecture register to the second bit segment of the physical register, the processor further generates a mapping position identifier for identifying the mapping bit segment of the first architecture register and / or the second architecture register in the physical register.

[0059] Through the mapping position identifier, when the processor executes the instruction write-back and submission stage, the storage bit segment of the operation data corresponding to the instruction in the physical register can be determined through the mapping position identifier, and the instruction write-back and submission operation can be completed by reading and writing the corresponding bit segment.

[0060] In some embodiments, the first architecture register and the second architecture register can correspond to a mapping position identifier respectively. The mapping position identifier corresponding to the first architecture register is used to identify the mapping bit segment of the first architecture register in the physical register, and the mapping position identifier corresponding to the second architecture register is used to identify the mapping bit segment of the second architecture register in the physical register.

[0061] Supposing the physical register is a 64-bit physical register, the first architecture register is a 32-bit architecture register, and the second architecture register is a 32-bit architecture register, the processor maps the first architecture register to the high 32 bits of the physical register and maps the second architecture register to the low 32 bits of the physical register. At this time, the mapping position identifier can be a 1-bit identifier. The mapping position identifier corresponding to the first architecture register is 1, indicating that the first architecture register is mapped to the high 32 bits of the physical register. The mapping position identifier corresponding to the second architecture register is 0, indicating that the second architecture register is mapped to the low 32 bits of the physical register.

[0062] In some other embodiments, a mapping position identifier can also be used to represent the mapping bit segments of the first architecture register and the second architecture register in the physical register at the same time. Still taking the processor that maps the first architecture register to the high 32 bits of the physical register and maps the second architecture register to the low 32 bits of the physical register as an example, a 2-bit mapping position identifier can be used to represent the mapping bit segments of the first architecture register and the second architecture register in the physical register. For example, one bit of the 2-bit mapping position identifier is used to represent the mapping bit segment of the first architecture register in the physical register, and the other bit is used to represent the mapping bit segment of the second architecture register in the physical register. The value of the bit is used to represent whether the architecture register is mapped to the high 32 bits or the low 32 bits of the physical register. For example, the mapping position identifier is “10”. The bit corresponding to “1” is used to represent the mapping bit segment of the first architecture register in the physical register. The value of the bit is “1”, indicating that the first architecture register is mapped to the high 32 bits of the physical register. The bit corresponding to “0” is used to represent the mapping bit segment of the second architecture register in the physical register. The value of the bit is “0”, indicating that the second architecture register is mapped to the low 32 bits of the physical register.

[0063] Similarly, when more architecture registers are mapped to the same physical register, the mapping position identifier corresponding to the multiple architecture registers can have more bit positions, so that the mapping positions of the architecture registers in the physical register are represented by the values of the different bit positions. For example, when 3 architecture registers are mapped to the high bit, the middle bit and the low bit of the same physical register, a 6-bit mapping position identifier can be used to represent the mapping positions of the architecture registers in the physical register. Among them, the mapping position of each architecture register in the physical register is represented by 2 bits of the mapping position identifier. For example, assuming that the mapping position identifier is "000110", "00" in it represents that the first architecture register is mapped to the 0th bit segment of the physical register, that is, the low bit of the physical register, "01" in it represents that the second architecture register is mapped to the 1st bit segment of the physical register, that is, the middle bit of the physical register, and "10" in it represents that the third architecture register is mapped to the 3rd bit segment of the physical register, that is, the high bit of the physical register.

[0064] In some embodiments, after the processor maps the first architecture register to the first bit segment of the physical register and maps the second architecture register to the second bit segment of the physical register, the processor further generates a mapping number identifier used to identify the number of architecture registers mapped to the physical register.

[0065] For example, after the first architecture register is mapped to the first bit segment of the physical register and the second architecture register is mapped to the second bit segment of the physical register, it can be determined that there are 2 architecture registers mapped to the physical register, and the processor generates a mapping number identifier with a value of 2. Similarly, when N architecture registers are mapped to the same physical register, the processor generates a mapping number identifier corresponding to the physical register with a value of N, where N is a positive integer.

[0066] Through the above mapping number identifier, it can be determined how many architecture registers are mapped to a physical register, so that when the physical register is released, it can be determined according to the mapping number identifier that the physical register is released only after the data corresponding to each architecture register in the physical register is completely committed, so as to avoid the premature release of the physical register causing data loss. For example, when the value of the mapping number identifier corresponding to the physical register is N (N is a positive integer), it indicates that N architecture registers are mapped to the physical register, and when the physical register is released, it needs to be ensured that the data corresponding to the N architecture registers in the physical register are committed before the physical register is released.

[0067] In some embodiments, after the first architecture register is mapped to the first bit segment of the physical register and the second architecture register is mapped to the second bit segment of the physical register, the processor generates a mapping number identifier corresponding to the physical register with a value of 2.

[0068] When the physical register is released, it is required to determine that the data in the first bit segment and the second bit segment in the physical register has been submitted respectively before releasing the physical register.

[0069] In some embodiments, the processor, when releasing the physical register, detects whether the data in each bit segment in the physical register has been submitted according to the mapping quantity identifier of the physical register, and then determines whether to release the physical register.

[0070] For example, the processor determines that the first architectural register and the second architectural register are mapped to the physical register through the mapping quantity identifier of the physical register, and then, when releasing the physical register, the processor first determines whether the data in two bit segments in the physical register has been submitted, that is, whether the data corresponding to the two architectural registers mapped to the physical register has been submitted respectively, and releases the physical register in the case that the data in two bit segments in the physical register has been submitted.

[0071] In the above judgment process, the processor can further determine the mapping bit segment of each architectural register in the physical register in combination with the mapping position identifier corresponding to each architectural register mapped to the physical register. Then the processor determines whether the data corresponding to each architectural register has been submitted by detecting whether the data in the corresponding bit segment has been submitted.

[0072] In another embodiment, the processor counts the number of bit segments in which the data in the physical register has been submitted during the submission of the data in the physical register, that is, each time the data in a bit segment in the physical register is submitted, the number of bit segments in which the data in the physical register has been submitted is incremented by 1.

[0073] When the number of bit segments in which the data in the physical register has been submitted is equal to the mapping quantity identifier corresponding to the physical register, it can be determined that the data corresponding to each architectural register mapped to the physical register has been submitted respectively, and the physical register can be released at this time.

[0074] For example, the processor can count the number of bit segments in which the data has been submitted by modifying the value of the mapping quantity identifier corresponding to the physical register, and / or count the number of bit segments in which the data in the physical register has been submitted separately.

[0075] For example, in the processor, dup is used as the mapping quantity identifier, and the value of dup is the number of architectural registers mapped to the physical register, and the value of pending represents the number of bit segments in which the data in the physical register has been submitted.

[0076] In the process of committing the data in the physical register, the value of dup is decremented by 1 and / or the value of pending is incremented by 1 each time the data in a bit segment in the physical register is committed.

[0077] Based on the above operation, in the process of committing the data in the physical register, when the value of dup is equal to 0, it can be determined that the data in the mapping bit segments corresponding to the respective architectural registers in the physical register have all been committed, and at this time the physical register can be released.

[0078] Alternatively, when the value of pending is equal to the initial value of dup, that is, the value of pending is equal to the total number of architectural registers mapped to the physical register, it can be determined that the data in the mapping bit segments corresponding to the respective architectural registers in the physical register have all been committed, and at this time the physical register can be released.

[0079] The above embodiment can ensure that the physical register is released only after all the data in the physical register is committed when multiple architectural registers are mapped to the same physical register in the process of releasing the physical register, thereby avoiding data loss due to premature release of the physical register when the architectural register is in a many-to-one mapping relationship with the physical register.

[0080] Corresponding to the above-mentioned register mapping processing method, an embodiment of the present application also provides a register mapping processing device, which can be applied to a processor, as shown in Figure 2 The device comprises:

[0081] A comparison processing unit 100 is configured to perform bit width comparison on the first architectural register and the second architectural register and the physical register.

[0082] A mapping processing unit 110 is configured to, in the case where the sum of the bit widths of the first architectural register and the second architectural register is not greater than the bit width of the physical register, map the first architectural register to a first bit segment of the physical register, and map the second architectural register to a second bit segment of the physical register.

[0083] In some implementations, the first architectural register and the second architectural register are architectural registers of the same type.

[0084] In some implementations, the first architectural register and the second architectural register are architectural registers corresponding to the same instruction.

[0085] In some implementations, after mapping the first architectural register to the first bit segment of the physical register and mapping the second architectural register to the second bit segment of the physical register, the mapping processing unit 110 is further configured to:

[0086] generate a mapping position identifier, the mapping position identifier being used to identify a mapping bit segment of the first architectural register and / or the second architectural register in the physical register.

[0087] In some implementations, after mapping the first architectural register to a first bit segment of the physical register, and mapping the second architectural register to a second bit segment of the physical register, the mapping processing unit 110 is further configured to:

[0088] generate a mapping number identifier, the mapping number identifier being used to identify a number of architectural registers mapped to the physical register.

[0089] In some implementations, the mapping processing unit 110 is further configured to:

[0090] release the physical register in a case that data in the first bit segment and the second bit segment is respectively committed.

[0091] In some implementations, after mapping the first architectural register to a first bit segment of the physical register, and mapping the second architectural register to a second bit segment of the physical register, the mapping processing unit 110 is further configured to generate a mapping number identifier, the mapping number identifier being used to identify a number of architectural registers mapped to the physical register.

[0092] The mapping processing unit 110 releases the physical register in a case that data in the first bit segment and the second bit segment is respectively committed, including:

[0093] count a number of bit segments of the physical register in which data is committed during a process that data in the physical register is committed;

[0094] release the physical register in a case that the number of bit segments of the physical register in which data is committed is equal to the mapping number identifier.

[0095] In some implementations, the mapping processing unit 110 counts a number of bit segments of the physical register in which data is committed during a process that data in the physical register is committed, including:

[0096] decrease the mapping number identifier by 1 and / or increase the number of bit segments of the physical register in which data is committed by 1 each time a bit segment of the physical register in which data is committed during the process that data in the physical register is committed;

[0097] release the physical register in a case that the number of bit segments of the physical register in which data is committed is equal to the mapping number identifier.

[0098] In a case where the mapping number identifier is equal to 0, and / or the number of bit segments in which data is committed in the physical register is equal to the initial value of the mapping number identifier, the physical register is released.

[0099] The register mapping processing apparatus provided by the embodiment belongs to the same application concept as the register mapping processing method provided by the embodiments of the present application, can execute the register mapping processing method provided by any of the embodiments of the present application, and has the function modules and beneficial effects corresponding to the execution method. Technical details not described in the embodiment can be found in the specific processing content of the register mapping processing method provided by the embodiments of the present application, which will not be described here.

[0100] The functions implemented by the comparison processing unit 100 and the mapping processing unit 110 above can be implemented by the same or different processors, and the embodiments of the present application are not limited.

[0101] It should be understood that the units in the above apparatus can be implemented in the form of processor calling software. For example, the apparatus includes a processor connected with a memory, the memory stores instructions, and the processor calls the instructions stored in the memory to implement any of the above methods or to implement the functions of the units of the apparatus. The processor can be a general processor, such as a CPU or a microprocessor, and the memory can be an internal memory of the apparatus or an external memory of the apparatus. Alternatively, the units in the apparatus can be implemented in the form of hardware circuit. The functions of some or all of the units can be implemented by designing the hardware circuit. The hardware circuit can be understood as one or more processors. For example, in one implementation, the hardware circuit is an ASIC, and the functions of some or all of the units are implemented by designing the logical relationship of elements in the circuit. For another example, in another implementation, the hardware circuit can be implemented by a PLD. Taking an FPGA as an example, it can include a large number of logic gate circuits, and the connection relationship between the logic gate circuits is configured by a configuration file, so as to implement the functions of some or all of the units. All the units of the above apparatus can be implemented in the form of processor calling software, or all the units can be implemented in the form of hardware circuit, or part of the units are implemented in the form of processor calling software, and the remaining part is implemented in the form of hardware circuit.

[0102] In the embodiments of the present application, the processor is a circuit with signal processing capability. In one implementation, the processor can be a circuit with instruction reading and running capability, such as a CPU, a microprocessor, a GPU, or a DSP, etc. In another implementation, the processor can implement certain functions through a logic relationship of a hardware circuit, which is fixed or can be reconfigured. For example, the processor is an ASIC or a PLD implemented hardware circuit, such as an FPGA, etc. In the reconfigurable hardware circuit, the processor loads a configuration document to implement the hardware circuit configuration. It can be understood that the processor loads instructions to implement the functions of the above units.

[0103] It can be seen that each unit in the above apparatus can be one or more processors (or processing circuits) configured to implement the above methods, such as a CPU, a GPU, a NPU, a TPU, a DPU, a microprocessor, a DSP, an ASIC, an FPGA, or a combination of at least two of these processor forms.

[0104] In addition, each unit in the above apparatus can be integrated together or independently. In one implementation, the units are integrated together to implement a SOC. The SOC can include at least one processor for implementing any of the above methods or the functions of the units of the apparatus. The at least one processor can be different, such as including a CPU and an FPGA, a CPU and an artificial intelligence processor, a CPU and a GPU, etc.

[0105] Another embodiment of the present application also proposes a processor configured to perform the register mapping processing method described in any of the above embodiments. The specific processing process of the processor when performing the above method can refer to the description of the above method embodiments. In the embodiments of the present application, the processor described above is a superscalar processor using instruction pipeline technology.

[0106] Another embodiment of the present application also proposes a computer device including the processor described in the above embodiments, so that the processor in the computer device can perform the register mapping processing method described in any of the above embodiments.

[0107] Another embodiment of the present application also proposes an electronic device, as shown in Figure 3 The device includes:

[0108] a memory 200 and a processor 210;

[0109] The memory 200 is connected with the processor 210, and is configured to store programs.

[0110] The processor 210 is configured to implement the register mapping method disclosed in any of the above embodiments by running the program stored in the memory 200.

[0111] Specifically, the electronic device can further include a bus, a communication interface 220, an input device 230, and an output device 240.

[0112] The processor 210, the memory 200, the communication interface 220, the input device 230, and the output device 240 are connected to each other through the bus.

[0113] The bus can include a path for transmitting information between the components of the computer system.

[0114] The processor 210 can be a general-purpose processor, such as a central processing unit (CPU), a microprocessor, or the like, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs of the present application. It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0115] The processor 210 can include a main processor and can further include a baseband chip, a modem, and the like.

[0116] The memory 200 stores programs for executing the technical solutions of the present application, and can also store operating systems and other key services. Specifically, the program can include program code, and the program code includes computer operation instructions. More specifically, the memory 200 can include read-only memory (ROM), other types of static storage devices that can store static information and instructions, random access memory (RAM), other types of dynamic storage devices that can store information and instructions, disk storage, flash, and the like.

[0117] The input device 230 can include a device that receives data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor, and the like.

[0118] The output device 240 can include a device that allows information to be output to a user, such as a display screen, a printer, a speaker, and the like.

[0119] The communication interface 220 can include any transceiver-type device for communicating with other devices or communication networks, such as an Ethernet network, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0120] The processor 210 executes the programs stored in the memory 200 and invokes other devices, which can be used to implement each step of any of the register mapping processing methods provided by the above-described embodiments.

[0121] The computer device and the electronic device described in the above embodiments can be specifically a personal computer, a server, a smart terminal, a smart handheld device, a wearable device, etc.

[0122] The embodiments of the present application also propose a chip, which includes a processor and a data interface, the processor reads and runs the programs stored on the memory through the data interface to execute the register mapping processing method introduced in any of the above-described embodiments, and the specific processing process and its beneficial effects can be referred to the above-described embodiments of the register mapping processing method.

[0123] In addition to the above method and device, the embodiments of the present application can also be a computer program product, which includes computer program instructions, the computer program instructions make the processor execute the steps in the register mapping processing method described in any of the above-described embodiments of the present application when the processor runs.

[0124] The computer program product can be written in any combination of one or more programming languages to perform the operations of the embodiments of the present application, including an object-oriented programming language, such as Java, C++, etc., and a conventional procedural programming language, such as "C" language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0125] In addition, the embodiments of the present application can also be a storage medium, which stores a computer program, the computer program is executed by the processor to execute the steps in the register mapping processing method described in any of the above-described embodiments of the present application.

[0126] For each method embodiment described above, for the sake of simplicity, the method embodiments are described as a series of acts. But those skilled in the art will appreciate that the method embodiments are not limited by the order of acts, as some steps could occur in other orders or concurrently with each other. Moreover, those skilled in the art will appreciate that described acts could be implemented other ways, such as at least partially in hardware, and some acts could be implemented as other acts or steps.

[0127] It should be noted that each of the embodiments described in the specification is merely exemplary embodiments, and the key points of each embodiment are different from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the related parts can be referred to the part of the method embodiments.

[0128] The steps in the method embodiments of the present application can be adjusted, combined and reduced in sequence according to actual needs. The technical features described in the embodiments can be replaced or combined.

[0129] The modules and sub-modules in the device and terminal of the embodiments of the present application can be combined, divided and reduced according to actual needs.

[0130] In several embodiments provided by the present application, it should be understood that the disclosed terminal, device and method can be implemented by other ways. For example, the terminal embodiments described above are only schematic, for example, the division of modules or sub-modules is only a logical function division, and actual implementation can have another division way, for example, a plurality of sub-modules or modules can be combined or integrated into another module, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0131] The modules or sub-modules described as separate components can or can not be physically separated, and the components of the modules or sub-modules can or can not be physical modules or sub-modules, that is, they can be located in one place, or can be distributed to a plurality of network modules or sub-modules. Some or all modules or sub-modules can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0132] In addition, each functional module or sub-module in each embodiment of the present application can be integrated in one processing module, or each module or sub-module can exist physically alone, or two or more modules or sub-modules can be integrated in one module. The integrated module or sub-module can be realized in the form of hardware or in the form of a software functional module or sub-module.

[0133] Those skilled in the art will further appreciate that the functions or steps of the examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or any combination thereof. To clearly illustrate the interchangeability of hardware and software, various examples have been described generally in terms of their functionality or steps. Whether such functionality or steps are implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

[0134] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0135] Finally, it needs to be pointed out that, in this document, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or equipment including the element.

[0136] The above description of disclosed embodiments enables one of ordinary skill in the art to make and use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A register mapping processing method, characterized in that, include: Compare the bit width of the first architecture register, the second architecture register, and the physical register; If the sum of the bit width of the first architecture register and the bit width of the second architecture register is not greater than the bit width of the physical register, the first architecture register is mapped to the first bit segment of the physical register, and the second architecture register is mapped to the second bit segment of the physical register.

2. The method according to claim 1, characterized in that, The first architecture register and the second architecture register are architecture registers of the same type.

3. The method according to claim 1, characterized in that, The first architecture register and the second architecture register are architecture registers corresponding to the same instruction.

4. The method according to claim 1, characterized in that, After mapping the first architecture register to the first bit segment of the physical register, and mapping the second architecture register to the second bit segment of the physical register, the method further includes: Generate a mapping location identifier, which is used to identify the mapping bit field of the first architecture register and / or the second architecture register in the physical register.

5. The method according to any one of claims 1 to 4, characterized in that, After mapping the first architecture register to the first bit segment of the physical register, and mapping the second architecture register to the second bit segment of the physical register, the method further includes: Generate a mapping quantity identifier, which is used to identify the number of architecture registers mapped to the physical register.

6. The method according to any one of claims 1 to 4, characterized in that, The method further includes: The physical register is released when the data in the first segment and the second segment are committed respectively.

7. The method according to claim 6, characterized in that, After mapping the first architecture register to the first bit segment of the physical register, and mapping the second architecture register to the second bit segment of the physical register, the method further includes: generating a mapping quantity identifier, the mapping quantity identifier being used to identify the number of architecture registers mapped to the physical register; When the data in the first segment and the second segment are respectively committed, releasing the physical register includes: During the process of committing data in the physical register, the number of bit fields of data committed in the physical register is counted; The physical register is released if the number of data segments committed in the physical register is equal to the number of mapping identifiers.

8. The method according to claim 7, characterized in that, During the process of committing data in the physical register, the number of bit fields committed in the physical register is counted, including: During the process of data being committed in the physical register, whenever a bit field in the physical register is committed, the mapping count identifier is decremented by 1, and / or the number of bit fields in the physical register that are committed is incremented by 1; Releasing the physical register when the number of data fields committed in the physical register equals the mapping quantity identifier includes: The physical register is released when the mapping quantity identifier is equal to 0 and / or the number of data segments committed in the physical register is equal to the initial value of the mapping quantity identifier.

9. A register mapping processing apparatus, characterized in that, include: The comparison processing unit is used to perform bit-width comparisons between the first architecture register, the second architecture register, and the physical register; The mapping processing unit is configured to map the first architecture register to the first bit segment of the physical register, and to map the second architecture register to the second bit segment of the physical register, provided that the sum of the bit width of the first architecture register and the bit width of the second architecture register is not greater than the bit width of the physical register.

10. A processor, characterized in that, The processor is configured to perform the register mapping processing method as described in any one of claims 1 to 8.

11. A computer device, characterized in that, Includes the processor as described in claim 10.

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