Probe processor-oriented verification and test integrated platform

Abstract

The invention relates to a verification and test integrated platform for a probe processor, and belongs to the technical field of processor verification and test. A probe processor adopts a self-defined probe instruction and a special probe operator unit, and a traditional verification and test mode is difficult to consider the requirements of module-level verification and system-level test. The UVM verification system, the test system and the management module are integrated, and unified management of verification and test is achieved. The UVM verification system is based on a UVM architecture, a virtual interface is associated with a to-be-tested unit (such as a probe operator, GPIO, UART and the like) of a probe processor through a forced binding mechanism, and module-level verification is achieved. The test system is responsible for compiling test codes into machine codes and loading the machine codes to the probe processor by starting the read-only memory, and system-level test is executed by the probe processor. And the management module adopts an automatic script to realize intelligent switching between verification and test modes, so that the probe processor is suitable for different test scenes, the test efficiency is improved, and the environmental redundancy is reduced. According to the method, the reusability of the test case is improved, the test consistency is ensured, the resource utilization rate is optimized, the automation degree and efficiency of verification are improved, and the method is suitable for efficient verification and test of probe processors and similar architecture chips.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processor verification and testing technology, in particular to a verification and testing integrated platform for probe processor. BACKGROUND

[0002] With the rapid development of technology, the demand for solving complex problems is increasing. Especially in NP-complete problems and other high computational complexity problems, traditional electronic computers often have difficulty in efficient solving. In order to cope with this challenge, Professor Xu and his team developed a probe processor (CN119248353A), which uses a unique probe operation method to solve all solutions of a problem in one calculation process, thereby significantly improving the calculation efficiency and providing an effective calculation scheme for solving NP-complete problems.

[0003] The probe processor is a complex system on a chip (SoC) that integrates a central processing unit (CPU) and a co-processing unit, and is equipped with a set of specific probe operator units to perform probe calculation tasks. In order to support this calculation mode, the probe processor introduces a series of custom probe instructions, which are used to control the calculation behavior of the probe operator unit and realize efficient data parallel computing. The calculation accuracy and execution efficiency of the probe operator unit directly determine the correctness of the probe instruction and the overall computing ability of the processor. Therefore, during the development of the probe processor, it is necessary to perform module-level verification on the probe operator unit and system-level testing on the probe instruction to ensure the functional correctness and performance optimization of the entire probe computing system.

[0004] Existing verification and testing systems usually run independently, resulting in inefficient reuse of test cases for module-level verification and system-level testing, and poor compatibility between different systems. The use of different testing tools and platforms increases the workload of test case adaptation and modification, thereby reducing the overall verification efficiency. In addition, the existing verification and testing process lacks effective resource sharing and unified standardized process, resulting in low utilization of hardware and software resources, complex debugging process, and difficult problem positioning, which further affects the verification efficiency and testing quality.

[0005] Therefore, there is an urgent need for a verification and testing integrated platform for probe processor to improve the reusability of test cases, optimize resource utilization, and simplify the debugging process, thereby improving the efficiency and quality of probe processor verification. SUMMARY

[0006] The application relates to a verification and test integrated platform for a probe processor, aiming at solving the problems of poor test case reusability, low resource utilization and complex debugging in the existing probe processor verification and test process. By integrating a UVM verification system and a test system and combining a test management and mode switching mechanism, unified management of module-level verification and system-level test is realized, and the efficiency and flexibility of verification and test are improved.

[0007] In order to achieve the above-mentioned purpose, the application provides a technical scheme: a verification and test integrated platform for a probe processor, the platform comprising a UVM verification system, a test system and a management module.

[0008] The UVM verification system is based on the UVM methodology, and through a virtual interface and a forced binding mechanism, the UVM component is connected with a unit under test of the probe processor, so that module-level verification is realized.

[0009] The test system is used for compiling test code into machine code executable by the probe processor through a compiler, and loading the machine code into the probe processor through a read-only memory, so that the CPU loads and executes instructions, and system-level test is realized.

[0010] The management module is used for dynamically selecting a test mode through a script, so that the probe processor is suitable for different verification and test requirements, wherein the test mode comprises a UVM verification mode and a code test mode.

[0011] The UVM verification system and the test system share the same unit under test, i.e. the probe processor, and successfully realize the efficient fusion of module-level verification and system-level test. By using the UVM verification system and the test system, the two systems are respectively used for functional verification requirements of the probe processor in different scenes, so that the problems of non-uniform module-level and system-level test environment, redundant design and resource waste in the traditional method are avoided.

[0012] The UVM verification system and the test system share a test case database, the database stores functional configuration and excitation data of the unit under test, so that the UVM verification system and the test system can share part of test vectors, so as to reduce the repeated design of test cases.

[0013] On one hand, the connection relationship of the platform is as follows:

[0014] The to-be-tested unit, i.e. the operator unit in the probe processor, is connected with the input virtual interface component and the output virtual interface component in the UVM verification system, data flows from the input virtual interface component to the to-be-tested unit, and data flows from the to-be-tested unit to the output virtual interface component; the to-be-tested unit is connected with the model module and the data dump module in the test system, data flows from the to-be-tested unit to the model module and the data dump module; the start-up read-only memory in the to-be-tested unit is connected with the compiler and the test bench in the test system, data flows from the compiler and the test bench to the start-up read-only memory.

[0015] The mode selection unit of the management module is connected with each environment class in the UVM verification system, data flows from the mode selection unit to each environment class; the mode selection unit is connected with the stimulus generator in the test system, data flows from the mode selection unit to the stimulus generator; the mode selection unit is connected with the to-be-tested unit, data flows from the mode selection unit to the to-be-tested unit. The test control unit of the management module is connected with the to-be-tested unit, data flows from the test control unit to the to-be-tested unit.

[0016] On the other hand, the UVM verification system constructs a modular verification environment based on the UVM methodology, defines a plurality of environment classes Env, encapsulates input Agent, output Agent and custom virtual interface components, etc. The UVM components are directly connected with the probe processor interface through the custom virtual interface, and module-level verification is performed. The input Agent contains a driver, a monitor and a transaction generator, is used to generate a test data stream, excite the probe interface, and collect signal data in the communication process; the output Agent is used to capture output data of the to-be-tested unit interface in real time, sends a score board to compare actual output with expected results, supports coverage collection and functional coverage analysis; the virtual interface uses a forced binding mechanism to connect the UVM virtual interface to the probe interface inside the probe processor through the configuration mechanism of UVM, and realizes functional testing without modifying the RTL code.

[0017] On the other hand, the test system contains an instruction loading module, a CPU execution module, a model module, a checking module, a test bench module and a data dump module; the instruction loading module is used to store machine code generated by compiling test code into a start-up read-only memory; the CPU execution module is used to automatically run the RISC-V machine code in the start-up read-only memory and execute test instructions after resetting; the model module is used to provide a software reference model to simulate the expected behavior of the probe processor; the checking module is used to compare test results with expected results to ensure test accuracy; the data dump module is used to collect key data in the CPU execution process, and store or output the data for analysis; the test bench module is used to provide test stimulus and drive the CPU to execute test code.

[0018] The clock (Clock) and reset (Reset) signals are sent to the probe processor through the test bench module, a test program is loaded to the start read-only memory, the probe processor is directly run and actual test results are generated, system-level test is completed, correctness of the processor and the unit under test in a real running environment is ensured, and system-level coverage of the test is improved.

[0019] On the other hand, an important feature of the platform is to adopt unified control logic, to select verification and test modes through scripts, to realize seamless switching of module-level verification and system-level test, and to avoid the problem of repeated test environment construction. In addition, the application supports RISC-V DV to generate instruction flow, and further improves the verification automation level and efficiency.

[0020] On the other hand, as Figure 2 shown, the verification process of the application specifically includes the following steps:

[0021] S201 selects a unit under test, selects the unit under test according to conditional compilation, writes a test case, and generates the test case through an excitation generator, then initializes the configuration of the unit under test, and stores the generated functional configuration data in a memory for subsequent test reuse;

[0022] S202 selects a mode, selects to execute UVM verification or code test according to the setting of a management module, and by default, UVM verification is preferentially executed;

[0023] S203 executes UVM module-level verification, including defining a virtual interface of the unit under test, and connecting the virtual interface with an interface of the unit under test through a forced binding mechanism, to ensure that the UVM environment can directly control and monitor signals of the unit under test, to provide a simulation environment consistent with real hardware. During the verification process, a sequence generator generates a test sequence, and sends the test sequence to the unit under test through a driver to drive the unit under test to run, a monitor collects output data of the unit under test in real time, and transmits the output data to a score board for comparison and analysis, to finally generate UVM verification results;

[0024] S204 executes system-level test, writes a test case for the unit under test according to the functional configuration in the memory, and uses a RISC-V cross-compilation tool chain to compile the test case into RISC-V machine code recognizable by the probe processor, to generate an executable binary file. The test bench sends clock and reset signals to the unit under test, and loads the machine code to the start read-only memory. The probe processor reads and executes the machine code from the start read-only memory to drive the unit under test, a detection module monitors interface signals, memory data or software logs of the unit under test, and compares them with expected results to generate test results;

[0025] S205 determines whether the test passes based on the verification results. If the verification is correct, the test is terminated; if the verification fails, the cause of the error is analyzed based on the logs, and the stimulus generator configuration is adjusted before the test is repeated.

[0026] This invention provides an efficient, flexible, and economical integrated platform for probe processor verification and testing, suitable for RISC-V-based probe processor verification and testing. This platform not only improves UVM verification efficiency but also enhances testing operability, supporting flexible switching between various testing scenarios, and providing an innovative and systematic solution for probe processor and system design and verification. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the architecture of an integrated verification and testing platform for probe processors in this invention;

[0028] Figure 2 This is a schematic diagram of the verification and testing process of an integrated verification and testing platform for probe processors in this invention;

[0029] Figure 3 This is a schematic diagram of the verification and testing process using the probe operator unit as the unit under test in an embodiment of the present invention; Detailed Implementation

[0030] In this embodiment, to more clearly illustrate the purpose, technical solution, and advantages of the present invention, a probe operator unit is selected as an example unit under test, and C code testing is selected as an example testing method. The present invention will be further described in detail with reference to the accompanying drawings and embodiments. It should be understood that this embodiment is only used to explain the present invention and does not constitute a limitation thereof.

[0031] like Figure 1 As shown, an integrated verification and testing platform for probe processors includes a UVM verification system, a testing system, and a management module. Among them,

[0032] The UVM verification system comprises a reference model, a score board, an input agent, an output agent, a stimulus generator, an input virtual interface and an output virtual interface; wherein the output agent comprises a monitor O, and the input agent comprises a sequence generator, a driver and a monitor I; the stimulus generator is responsible for defining operations and transactions; the virtual interface connects signals between UVM transactions and probe processors through a forced binding mechanism; the sequence generator is responsible for scheduling the execution of test sequences, and passes transactions to the driver; the driver acquires transactions and converts them into hardware signals to drive the probe processor; the monitor monitors the output signals of the probe processor, generates corresponding transactions to capture and record the output, and performs verification checks; the reference model simulates design behavior and compares it with the design to ensure that the design meets the specifications; and the score board records and compares actual output with expected output to perform result checks.

[0033] The test system comprises a stimulus generator, a model module, a check module, a test bench module and a data dump module; wherein the model module simulates the expected behavior of the probe processor, the check module compares test results with expected results to ensure test accuracy; the data dump module collects key data for analysis; and the test bench module provides test stimuli to drive the CPU to execute test code.

[0034] The management module controls the switching of the verification mode of the test system and the UVM verification system, and selects verification functions through scripts.

[0035] In this embodiment, the verification object of the probe processor-oriented verification and test integrated platform is the probe operator unit of the probe processor. By combining UVM verification and code testing, efficient integration of module-level verification and system-level testing is achieved, and redundant design and resource waste caused by different module-level and system-level test environments in traditional methods are avoided. The platform selects the unit under test through conditional compilation, and writes test cases that adapt to different verification requirements. In the UVM verification mode, the stimulus generator generates the configuration sequence of the unit under test, and connects the virtual interface of the UVM component and the interface of the unit under test in the RTL design through the forced binding mechanism, to realize functional testing without modifying the RTL code. In the test mode, the test system sends clock and reset signals through the test bench, loads the compiled RISC-V machine code into the start read-only memory for the CPU to execute, to realize system-level testing based on the processor. This method ensures the consistency of the UVM verification and test environment, improves the test coverage, reduces test resource waste, and enhances the verification and test efficiency of the probe processor and the unit under test.

[0036] In the embodiment, the probe processor-oriented verification and test integration platform can generate various configurations conforming to the functions of the unit under test through the stimulus generator in the UVM environment of the unit under test, and save the configurations in the memory. When the management module is switched to the test mode, the system reads the previously generated configuration data from the memory, generates corresponding test cases based on the data, and ensures that the operation of the unit under test in the test is consistent with the function configuration in the UVM verification. After the test code is compiled and converted into RISC-V machine code, it is loaded into the start read-only memory for execution by the probe processor, realizing the system-level test based on the processor. The method realizes unified configuration management of the UVM verification and test method, avoids the inconsistency of the function configuration in the two test modes, reduces the workload of manually writing test cases, and improves the automation degree and coverage of the test. Through the reuse of the test configuration, the application ensures that the verification and test process of the probe processor is more efficient and accurate, and is suitable for the verification requirements of various peripherals and probe operator units.

[0037] In the embodiment, as shown in Figure 3 A probe processor-oriented verification and test integration method can include the following processing steps:

[0038] S301 Conditional compilation and probe operator configuration, select the probe operator to be verified through conditional compilation, and define the transaction class related to the probe operator in the UVM verification system. These transaction classes are used to describe the input, output operation and state change of the probe operator. The stimulus generator writes test cases according to the verification requirements of the unit under test, and stores all generated function configuration data in the memory. These data will be reused in the subsequent steps to improve the efficiency and consistency of the test.

[0039] S302 Select verification mode and initialize connection, according to the selection of the management module, the platform decides to execute UVM verification or C code test. If UVM verification is selected, the virtual interface of the probe operator defined in UVM is connected to the probe operator interface in the probe processor through the forced binding mechanism. Then, the sequence generator reads the previously stored test cases from the memory, and transmits the data to the probe operator input interface of the probe processor through the driver, and drives the device to perform function operation.

[0040] S303 Monitoring and data capture, in the UVM verification mode, the monitor O in the output Agent is responsible for real-time monitoring of the signals of the probe operator output interface in the probe processor. The monitor O will capture the output signals of the probe operator interface, and transmit the signals to the score board for further data processing and comparison analysis. In this way, the platform can ensure that the behavior of the probe operator is consistent with the expectation.

[0041] S304 Scoreboard result analysis, the Scoreboard compares the output data received from the monitor O with the predefined reference data for consistency. If the output signal matches the expected result, it indicates that the probe operator functions normally. If a mismatched signal is detected, the Scoreboard records error information and feeds it back to the UVM verification environment for further debugging and analysis.

[0042] S305 C code test preparation and compilation, when performing C code testing, first read the functional configuration data related to the probe operator from the memory, and then write the corresponding C code test cases. The C code contains operations on the probe operator interface, such as setting input and output values. Use the RISC-V cross-compilation tool chain to convert the C code into RISC-V machine code that the probe processor can recognize, and generate the corresponding binary executable file.

[0043] S306 Start C code test system and load machine code, through the test bench module, the system loads the compiled RISC-V machine code into the probe processor's startup read-only memory, and sends the clock and reset signals to the probe processor through the test bench. This process simulates the hardware startup process, ensuring that the probe processor can correctly load and execute the machine code after startup.

[0044] S307 Execute C code test, the probe processor loads and executes the RISC-V machine code in the startup read-only memory, driving the probe operator to perform interactive testing. During testing, the probe processor will interact with the probe operator according to the instructions in the C code, simulating the functional operation in the real hardware environment.

[0045] S308 Data detection and result analysis, the detection module monitors the output of the probe processor in real time, collects the signals or memory data of the probe operator interface, and compares them with the expected results. The detection module generates a test report by comparing with the reference results. If there is a mismatch or error, the report will provide detailed error information to help developers further analyze and debug the problem.

[0046] From this embodiment, it can be seen that the method has the advantages of integrating verification and testing. Integrating UVM verification and code testing in the same platform supports module-level verification and system-level testing, avoiding redundant design caused by different environments, thereby improving verification efficiency. At the same time, the method has flexible test mode selection, users can switch between UVM verification and code testing according to demand through the management module, ensuring the best verification effect in different test scenarios.

[0047] In addition, the method uses a forced binding mechanism to connect the UVM virtual interface with the DUT interface of the DUT, avoids modifying the RTL code, and completes the UVM cascade test, thereby enhancing the adaptability of the test. The test cases generated by the stimulus generator, in combination with the memory configuration data multiplexing mechanism, not only improve the test coverage, but also reduce the repetitive work of manually writing test vectors.

[0048] In order to improve the debugging efficiency, the method also introduces a log analysis mechanism, which can quickly detect errors and feed back to the stimulus generator for optimization adjustment, so that the test cases have self-adaptive adjustment capability, accelerating problem positioning and repair. In the test mode, the probe processor directly executes the RISC-V machine code in the startup read-only memory, drives the DUT to interact, thereby simulating the real hardware running environment, providing more valuable test results, and helping to discover system-level problems in advance.

[0049] In summary, the method not only improves the automation, flexibility and test efficiency of verification, but also reduces the waste of test resources and improves the accuracy of verification, and is suitable for the efficient verification and test requirements of the probe processor.

Claims

1. A verification and testing integrated platform for probe processors, characterized in that, The platform includes a UVM verification system, a testing system, and a management module; in: The UVM verification system is based on the UVM methodology and connects the UVM components to the test unit interface of the probe processor through a virtual interface and a forced binding mechanism to achieve module-level verification. The testing system is used to compile test code into machine code executable by the probe processor through a compiler, load it into the probe processor through a read-only memory, and then load and execute the instructions by the CPU to achieve system-level testing. The management module is used to control the dynamic selection of test modes through scripts, so that the probe processor can be adapted to different verification and testing needs, wherein the test modes include UVM verification mode and code testing mode. The UVM verification system and the testing system share the same device under test, namely the probe processor; The UVM verification system and the testing system share a test case database, which stores functional configuration and stimulus data for the unit under test. This allows the UVM verification system and the testing system to share some test vectors, thereby reducing the duplication of test case design.

2. The integrated verification and testing platform for probe processors according to claim 1, characterized in that, The platform's connectivity is as follows: The unit under test, i.e., the operator unit in the probe processor, is connected to the input virtual interface component and the output virtual interface component in the UVM verification system. Data flows from the input virtual interface component to the unit under test, and from the unit under test to the output virtual interface component. It is also connected to the model module and the data dump module in the test system. Data flows from the unit under test to the model module and the data dump module. The boot read-only memory in the unit under test is connected to the compiler and the test bench in the test system. Data flows from the compiler and the test bench to the boot read-only memory. The mode selection unit of the management module is connected to each environment class in the UVM verification system, and data flows from the mode selection unit to each environment class; it is also connected to the stimulus generator in the test system, and data flows from the mode selection unit to the stimulus generator; and it is connected to the unit under test (DUT), and data flows from the mode selection unit to the DUT. The test control unit of the management module is connected to the DUT, and data flows from the test control unit to the DUT.

3. The integrated verification and testing platform for probe processors according to claim 1, characterized in that, The UVM verification system includes a virtual interface component, an excitation generator component, a driver component, a monitor component, and a scoreboard component; wherein, The virtual interface module is used to bind the virtual interface in the UVM environment to the interface of the probe processor through a forced binding mechanism, so as to realize the direct control and monitoring of the unit under test by UVM. The excitation generator component is used to generate UVM test cases that meet the functional requirements of the unit under test; the driver component is used to receive the test cases and send corresponding excitation signals to the unit under test to drive the unit under test to run. The monitoring component is used to collect signals from the output interface of the unit under test during operation in real time and transmit them to the scoring board component. The scoreboard component is used to compare the collected data with reference data and generate UVM verification results.

4. The integrated verification and testing platform for probe processors according to claim 1, characterized in that, The testing system includes an instruction loading module, a CPU execution module, a model module, an inspection module, a test bench module, and a data dumping module; wherein, The instruction loading module is used to store the machine code converted from the test code into the boot read-only memory; The CPU execution module is used to automatically run the RISC-V machine code in the startup read-only memory and execute test instructions after a reset. The model module is used to provide a software reference model to simulate the expected behavior of the unit under test. The inspection module is used to compare the test results with the expected results to ensure the accuracy of the test. The data dumping module is used to collect key data during CPU execution and store or output it for analysis. The test bench module is used to provide test stimuli and drive the CPU to execute test code.

5. The integrated verification and testing platform for probe processors according to claim 1, characterized in that, The management module includes a mode selection unit and a test control unit; wherein... The mode selection unit is used to dynamically switch between the test system and the UVM verification system based on script configuration, so that the probe processor can be used for different test requirements. The test control unit is used to coordinate the execution process of the selected test mode to ensure that the test system and the UVM verification system do not test the same unit under test at the same time, so as to avoid resource conflicts.

6. The integrated verification and testing platform for probe processors according to claims 2 to 4, characterized in that, The verification and testing process of the platform includes the following steps: S201 Select the unit to be tested, select the unit to be tested according to the conditional compilation, write test cases, generate test cases through the stimulus generator, then initialize the configuration of the unit to be tested, and store the generated functional configuration data in the memory for reuse in subsequent tests; S202 Select Mode: Based on the settings of the management module, select to perform UVM verification or code testing. By default, UVM verification is performed first. The S203 performs UVM module-level verification, including defining the virtual interface of the unit under test (DUT) and connecting it to the DUT interface through a forced binding mechanism. This ensures that the UVM environment can directly control and monitor the DUT signals, providing a simulation environment consistent with real hardware. During verification, a sequence generator generates test sequences and sends them to the DUT via a driver to drive its operation. The monitor collects the DUT's output data in real time and transmits it to a scoring board for comparison and analysis, ultimately generating the UVM verification results. The S204 performs system-level testing. Based on the functional configuration in the memory, it writes test cases for the unit under test (DUT) and uses a RISC-V cross-compilation toolchain to compile them into RISC-V machine code recognizable by the probe processor, generating an executable binary file. The test bench sends clock and reset signals to the DUT and loads the machine code into the boot ROM. The probe processor reads and executes the machine code from the boot ROM to drive the DUT. The detection module monitors the DUT's interface signals, memory data, or software logs and compares them with expected results to generate test results. S205 determines whether the test passes based on the verification results. If the verification is correct, the test is terminated; if the verification fails, the cause of the error is analyzed based on the logs, and the stimulus generator configuration is adjusted before the test is repeated.

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