Bandwidth expansion circuit, chip and receiver

Abstract

The invention discloses a bandwidth expansion circuit, a chip and a receiver, and belongs to the technical field of analog integrated circuits. The bandwidth expansion circuit comprises a signal compensation equalization module, a first bandwidth boosting module and a second bandwidth boosting module, the signal compensation equalization module is used for carrying out equalization amplification on a high-frequency component in the received first signal and outputting an equalized and amplified second signal; the second bandwidth boosting module is used for feeding back the extracted low-frequency component to the output end of the signal compensation equalization module so as to lower the low-frequency component in the second signal; the first bandwidth boosting module is used for offsetting high-frequency attenuation of the capacitive load on the second signal after the low-frequency component is reduced, and sending a third signal after offsetting the high-frequency attenuation through the signal output end; and the second bandwidth boosting module is also used for extracting a low-frequency component from the third signal. Through the combination of various technologies of compensating channel attenuation, counteracting capacitance influence, lowering low-frequency components and the like, the effective improvement of the circuit bandwidth is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of analog integrated circuit technology, in particular to a bandwidth expansion circuit, a chip and a receiver. BACKGROUND

[0002] In the field of analog integrated circuit technology, due to the loss of the medium and material of the channel in the transmission process of high-speed serial signals, the circuit bandwidth is insufficient, which changes the amplitude and phase of the transmitted high-speed serial signals, especially causes the high-frequency components of the high-speed serial signals to be sharply attenuated, thereby increasing the inter-symbol interference and causing the bit error rate to increase, affecting the accuracy of data transmission. SUMMARY

[0003] The present application provides a bandwidth expansion circuit, a chip and a receiver for improving the circuit bandwidth.

[0004] In a first aspect, a bandwidth expansion circuit is provided, which comprises a signal compensation equalization module, a first bandwidth improvement module and a second bandwidth improvement module.

[0005] The signal compensation equalization module is configured to receive a first signal through a signal input end, equalize and amplify high-frequency components in the first signal, and output a second signal after equalization and amplification, wherein the high-frequency components are signal components with a frequency greater than a first threshold.

[0006] The second bandwidth improvement module is configured to feed back the extracted low-frequency components to the output end of the signal compensation equalization module to suppress low-frequency components in the second signal, wherein the low-frequency components are signal components with a frequency less than a second threshold.

[0007] The first bandwidth improvement module is configured to offset the high-frequency attenuation of the second signal after suppressing the low-frequency components due to the capacitive load, and send a third signal after offsetting the high-frequency attenuation through a signal output end, wherein the capacitive load includes at least one of a load capacitor, an AC coupling capacitor or a parasitic capacitor connected subsequently to the first bandwidth improvement module.

[0008] The second bandwidth improvement module is further configured to extract low-frequency components from the third signal.

[0009] In a possible implementation, the second bandwidth improvement module comprises a differential amplifier, a low-pass filter and a converter.

[0010] The differential amplifier is configured to buffer and amplify the third signal, and output the third signal after buffer amplification.

[0011] The low-pass filter is configured to extract low-frequency components from the third signal after buffer amplification and filter out high-frequency components.

[0012] The converter is configured to cancel the low frequency component of the second signal output by the signal compensation and equalization module with the low frequency component extracted by the low pass filter.

[0013] In a possible implementation, the second signal is a first voltage signal, and the third signal is a second voltage signal; the first bandwidth boosting module comprises a transconductance amplifier and a transimpedance amplifier.

[0014] The transconductance amplifier is configured to convert the input first voltage signal into a current signal and buffer the current signal to the transimpedance amplifier in the subsequent stage.

[0015] The transimpedance amplifier is configured to convert the input current signal into the second voltage signal and cancel the high frequency attenuation of the current signal caused by the capacitive load.

[0016] In a possible implementation, the transimpedance amplifier comprises an active inductance structure for changing the response of a specific frequency component in the current signal, and the specific frequency component is determined based on the frequency component attenuated by the capacitive load.

[0017] In a possible implementation, the transimpedance amplifier comprises a cross-coupled capacitance structure for generating a negative capacitance, and the negative capacitance cancels part of the positive capacitance in the bandwidth extension circuit.

[0018] In a possible implementation, the signal compensation and equalization module comprises at least one continuous-time linear equalizer, and the at least one continuous-time linear equalizer is configured to perform different degrees of equalization amplification on corresponding high frequency components in the first signal.

[0019] In a possible implementation, the second signal is a second signal with adjusted gain, and the signal compensation and equalization module further comprises a variable gain amplifier, and the variable gain amplifier is configured to adjust the gain of the signal output by the at least one continuous-time linear equalizer according to the amplitude requirement of the subsequent load circuit.

[0020] In a possible implementation, the first signal is a differential signal, the positive output end of the second bandwidth boosting module is connected to the positive output end of the signal compensation and equalization module, and the negative output end of the second bandwidth boosting module is connected to the negative output end of the signal compensation and equalization module.

[0021] The second aspect further provides a chip, and the chip comprises the bandwidth extension circuit according to the first aspect.

[0022] The third aspect further provides a receiver, and the receiver comprises the bandwidth extension circuit according to the first aspect.

[0023] The technical scheme provided in the application can bring at least the following beneficial effects:

[0024] In the bandwidth expansion circuit, the three modules of the signal compensation equalization module, the first bandwidth boosting module and the second bandwidth boosting module are included, the compensation equalization module is used for compensating channel attenuation, the first bandwidth boosting module is used for offsetting the influence of the capacitor, and the second bandwidth boosting module is used for reducing low-frequency components, so that through the reasonable combination of multiple technologies, the high-frequency attenuation in the channel transmission process can be compensated, the influence of the subsequent capacitor load can be reduced, and the circuit bandwidth can be further improved by reducing the low-frequency components, the effective improvement of the circuit bandwidth can be realized, the risk of inter-symbol interference is reduced, the bit error rate is reduced, and the accuracy of data transmission is improved. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical scheme in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0026] Figure 1 is a structure schematic diagram of an equalization circuit provided in the related technology of the embodiments of the application;

[0027] Figure 2 is a structure schematic diagram of a bandwidth expansion circuit provided in the embodiments of the application;

[0028] Figure 3 is a structure schematic diagram of another bandwidth expansion circuit provided in the embodiments of the application;

[0029] Figure 4 is a structure schematic diagram of a variable gain amplifier provided in the embodiments of the application;

[0030] Figure 5 is a structure schematic diagram of a transconductance amplifier provided in the embodiments of the application;

[0031] Figure 6 is a structure schematic diagram of a transimpedance amplifier provided in the embodiments of the application;

[0032] Figure 7 is a structure schematic diagram of a low-frequency equalizer provided in the embodiments of the application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical scheme and advantages of the application more clear, the embodiments of the application will be further described in detail below with reference to the drawings.

[0034] With the development of current high-speed serial communication, continuous time linear equalizer (CTLE) plays a crucial role in the receiver (RX) with non return to zero (NRZ) structure, 4-level pulse amplitude modulation (PAM4) and analog-to-digital converter (ADC) combined with digital signal processor (DSP) structure.

[0035] CTLE is an equalization technology used in high-speed serial data communication, usually located in the analog front end of the signal chain at the receiving end. CTLE compensates for the attenuation of high-frequency components caused by limited channel bandwidth by attenuating low-frequency components and amplifying high-frequency components, so as to reduce the intersymbol interference caused by the attenuation of high-frequency components.

[0036] Among them, the attenuation of high-frequency components will cause the edges of the transmitted signal to become slow and the eye diagram to close. The slow signal edge means that the rising edge and the falling edge of the signal become smooth and no longer steep, and the rising and falling time becomes longer. Eye diagram closure means that the "eye" part of the eye diagram or the whole eye height decreases to close or is unclear. The eye diagram is a graph formed by aligning and superimposing a plurality of symbol waveforms of a digital signal according to a time reference, that is, the eye diagram is a time-domain signal carrying transmission information superimposed. The size of the "eye" opening of the eye diagram reflects the strength of the intersymbol interference. If the eye diagram is closed or unclear, it usually indicates that the system has strong intersymbol interference, which seriously affects the transmission quality and stability of the signal.

[0037] In related technologies, for example Figure 1 As shown, the CTLE adopts a differential pair structure based on source degeneration resistance and capacitance. The CTLE includes a differential pair transistor (indicated by M1 and M2 in Figure 1 ) and a parallel RC array (indicated by Rs and Cs in Figure 1 ). M1 and M2 are two transistors with the same characteristics, for example, M1 and M2 are metal-oxide-semiconductor (MOS) field effect transistors. The MOS field effect transistor can be referred to as MOS transistor.

[0038] The gates of M1 and M2 are connected to the negative input end (indicated by IN in Figure 1 ) and the positive input end (indicated by IN+ in Figure 1(represented by IP in Chinese); the sources of M1 and M2 are connected to the parallel Rs and Cs, and the parallel Rs and Cs pass through a current source ( Figure 1 The M1 and M2 terminals are connected to ground; the drains of M1 and M2 are connected to the positive output terminals of the differential signal, respectively. Figure 1 (represented by OP1 in the middle) and negative output terminal ( Figure 1 (represented by ON1 in the diagram), and then connected to other subsequent circuit modules. OP1 and ON1 are connected via a resistor pair ( Figure 1 (Represented by R1 and R2) are connected to the power supply VDD. This differential structure can effectively suppress common-mode noise signals, improve the circuit's anti-interference capability and signal quality.

[0039] The RC array includes variable source degradation resistors Rs and source degradation capacitors Cs. Different RC combinations result in different equalization effects. For example, with the same Cs, a larger source Rs results in lower low-frequency gain; conversely, a larger source Cs with the same Rs results in higher high-frequency gain, i.e., a higher boost effect. In this embodiment, adjusting the values ​​of Rs and Cs can change the frequency response (or frequency response) of the CTLE circuit, thereby equalizing and compensating for the high-frequency components of the signal after it has passed through the channel. The frequency response refers to the output characteristics of the CTLE circuit for signals of different frequencies, expressed as curves showing the amplitude and phase of the output signal changing with frequency.

[0040] For example, since the high-frequency response of the system is enhanced when the frequency of the input signal is close to the zero point, mitigating the effect of channel attenuation, the amplitude of the output signal is compensated. Therefore, by adjusting the values ​​of Rs and Cs to adjust the position of the zeros and poles in the frequency response curve of the CTLE circuit, the CTLE circuit can obtain a suitable gain boost within a specific high-frequency range, thereby achieving a frequency response boost effect, that is, amplifying the high-frequency components, increasing the high-frequency gain of the circuit, and thus ensuring a flattened frequency response and improving signal quality. Here, gain is the ratio of the output signal amplitude to the input signal amplitude. If the circuit's gain for high-frequency components is greater than its gain for low-frequency components, the high-frequency components are amplified; conversely, if the high-frequency gain is lower than the low-frequency gain, the high-frequency signal is attenuated.

[0041] However, the capacitive load has a strong bypass effect on the high frequency band of the signal, which increases the attenuation of the high frequency signal. The capacitive load includes at least one of the load capacitance connected after the CTLE circuit, the AC coupling capacitance, or the parasitic capacitance directly or equivalently grounded. For example, when the signal frequency is high, the equivalent impedance of the capacitive load is small, which is approximately short-circuit, at this time, the high frequency signal is easy to "lose" through the capacitor, resulting in a decrease in the gain of the circuit to the high frequency signal, that is, high frequency attenuation occurs; when the signal frequency is low, the equivalent impedance of the capacitive load is large, which is approximately open circuit, at this time, the low frequency signal is difficult to "lose" through the capacitor, and the gain of the circuit to the low frequency signal is close to the direct current gain. That is, the capacitive load significantly attenuates the high frequency signal, while the attenuation of the low frequency signal is small.

[0042] Therefore, for the RX with a large capacitive load, the attenuation of the high frequency signal is increased due to the influence of the capacitive load, which limits the expansion of the circuit bandwidth. For example, in the RX of the ADC+DSP structure, the number of subsequent samplers is large, resulting in a large load capacitance. That is, the boost effect achieved by adjusting the zero point is weakened by the adverse effects of the capacitive load, resulting in that the bandwidth of the CTLE circuit after flattening the signal frequency response is severely limited in the case of subsequent large capacitive load.

[0043] The embodiment of the present application provides a bandwidth expansion circuit which not only compensates for the high frequency attenuation caused by the limited channel bandwidth, but also more effectively improves the circuit bandwidth. Referring to Figure 2 , Figure 2 The structure diagram of the bandwidth expansion circuit provided by the embodiment of the present application is shown in the figure. The bandwidth expansion circuit includes a signal compensation equalization module 01, a first bandwidth improvement module 02, and a second bandwidth improvement module 03. The signal compensation equalization module 01 is connected with the first bandwidth improvement module 02, and the second bandwidth improvement module 03 is connected in reverse parallel between the output and the input of the first bandwidth improvement module 02, forming a feedback path. The signal compensation equalization module 01 receives a first signal through a signal input end IN, and the first signal is a signal which is attenuated in high frequency caused by channel transmission. The first bandwidth improvement module 02 is connected at the rear stage of the signal compensation equalization module 01, and the first bandwidth improvement module 02 sends a third signal through a signal output end OUT.

[0044] The signal compensation equalization module 01 is used for receiving the first signal through the signal input end IN, equalizing and amplifying the high frequency component in the first signal, and outputting the second signal after equalizing and amplifying, so as to compensate for the high frequency attenuation of the first signal in the channel transmission process. For example, the channel is composed of a lossy medium, so that the signal transmission through the channel will cause attenuation, including amplitude and phase attenuation or change. Therefore, by compensating for the attenuation, the edge of the signal waveform can be restored, the opening degree of the eye diagram is increased, and the purpose of signal frequency response flattening equalization is achieved.

[0045] Since a signal is a physical quantity (such as current, voltage, sound wave, etc.) varying with time or space, the signal frequency represents the speed of periodic change of the signal, and the unit is hertz (Hz). The frequency component refers to the composition of different frequencies after the signal is decomposed in the frequency domain. The time domain signal can be converted into a frequency domain representation by Fourier transform and other methods, so that high, medium and low frequency components can be separated. Alternatively, the high frequency component is a signal component with a frequency greater than a first threshold, the medium frequency component is a signal component with a frequency less than the first threshold and greater than a second threshold, and the low frequency component is a signal component with a frequency less than the second threshold. The values of the first threshold and the second threshold can be flexibly defined, for example, the first threshold is 100 kilohertz (kHz), and the second threshold is 1000 Hz.

[0046] The signal compensation equalization module 01 can be used to equalize and amplify only the high frequency component in the first signal; or to equalize and amplify the high frequency component, the medium frequency component and the low frequency component in the first signal, for example, to adjust the gain of the high frequency, low frequency and medium frequency components to achieve equalization of the circuit. The gain of the high frequency or medium frequency component can be automatically selected relative to the gain of the low frequency component by a related adaptive algorithm according to the type of the channel, so as to form a reasonable boost degree to achieve the effect of adapting to different channels by enhancing the frequency response of the high frequency component. That is, the adaptive gain control of the high frequency or medium frequency component is essentially to perceive the influence of the channel on different frequencies in real time through an algorithm, and dynamically adjust the gain ratio of the high frequency or medium frequency component based on the low frequency component, so as to realize power equalization of each frequency component at the receiving end and improve the reliability and efficiency of signal transmission.

[0047] Alternatively, the signal compensation equalization module 01 includes at least one continuous time linear equalizer, which is used to amplify the corresponding high frequency component in the first signal to different degrees to compensate for signal attenuation under different losses, so that the equalization effect of the signal under different losses can be adapted, and the signal can be recovered. For example, a plurality of continuous time linear equalizers are connected in series to form a multi-stage compensation structure. The first continuous time linear equalizer receives the first signal and equalizes and amplifies the first high frequency component in the first signal. The second continuous time linear equalizer equalizes and amplifies the second high frequency component in the signal output by the first continuous time linear equalizer, and so on. The last continuous time linear equalizer outputs the signal after appropriate equalization.

[0048] The continuous-time linear equalizer is a signal processing technology based on linear filtering principle. By adjusting the gain (amplification or attenuation) of different frequency components, the continuous-time linear equalizer compensates for the frequency-selective distortion (such as attenuation) introduced in the channel transmission process, thereby recovering the original characteristics of the signal. The core feature of the continuous-time linear equalizer is to maintain the linear relationship between the input and output signals, without introducing new frequency components (i.e., without nonlinear distortion). Exemplarily, the continuous-time linear equalizer can be the CTLE described above.

[0049] In a possible implementation, the second signal output by the signal compensation equalization module 01 is a second signal after gain adjustment. In this case, the signal compensation equalization module 01 is further configured to adjust the gain of the first signal after amplification of the high-frequency component, so as to match the amplitude requirement of the subsequent load circuit for the first signal after gain adjustment. For example, the signal compensation equalization module 01 further includes a variable gain amplifier (VGA) connected to the back end of the last-stage continuous-time linear equalizer. The variable gain amplifier is configured to adjust the gain of the signal output by at least one continuous-time linear equalizer according to the amplitude requirement of the subsequent load circuit for the signal, so as to achieve a reasonable swing.

[0050] The variable gain amplifier is a signal amplifier capable of dynamically adjusting the gain according to the input signal amplitude or an external control signal. The core function is to stabilize the output signal in the target voltage range while maintaining the integrity of the signal. Therefore, by adjusting the gain through the variable gain amplifier, the output signal amplitude can be maintained within the optimal working range of the subsequent circuit.

[0051] The first bandwidth boosting module 02 is configured to offset the high-frequency attenuation of the input signal of the first bandwidth boosting module 02 caused by the capacitive load, and send the third signal after offsetting the high-frequency attenuation through the signal output end OUT. The second bandwidth boosting module 03 is configured to extract a low-frequency component from the output signal of the first bandwidth boosting module 02, and suppress the low-frequency component in the output signal of the signal compensation equalization module 01 through feedback offsetting of the low-frequency component. The feedback offsetting refers to inputting the low-frequency component to the output end of the compensation equalization module 01 in reverse, so that the low-frequency component input in reverse can offset the low-frequency component in the output signal of the compensation equalization module 01.

[0052] In the embodiment of the present application, the input signal of the first bandwidth boosting module 02 is the signal after the low-frequency component in the output signal of the signal compensation and equalization module 01 is suppressed by the second bandwidth boosting module 03. The second bandwidth boosting module 03 is configured to feed back the extracted low-frequency component to the output end of the signal compensation and equalization module 01 to suppress the low-frequency component in the second signal output by the signal compensation and equalization module 01; the first bandwidth boosting module 02 is configured to offset the high-frequency attenuation of the second signal after the low-frequency component is suppressed by the capacitive load, and send the third signal after the high-frequency attenuation is offset through the signal output end OUT; and the second bandwidth boosting module 03 is further configured to extract the low-frequency component from the third signal output by the first bandwidth boosting module 02.

[0053] The capacitive load includes at least one of the load capacitor connected to the first bandwidth boosting module 02, the input AC coupling capacitor, or the parasitic capacitor directly or equivalently grounded. As known from the foregoing, the capacitive load can significantly attenuate the high-frequency signal, so that the high-frequency component compensated by the signal compensation and equalization module 01 is attenuated again. Therefore, the embodiment of the present application offsets the influence of the capacitive load by the first bandwidth boosting module 02 to improve the bandwidth expansion effect.

[0054] Optionally, the second signal is a first voltage signal, and the third signal is a second voltage signal; and the first bandwidth boosting module 02 includes a transconductance amplifier (GM) and a transimpedance amplifier (TIA). The transconductance amplifier is configured to convert the input first voltage signal into a current signal and buffer the current signal to the transimpedance amplifier in the subsequent stage; and the transimpedance amplifier is configured to convert the input current signal into a second voltage signal and offset the high-frequency attenuation of the current signal by the capacitive load to improve the circuit performance. The transconductance gain of the transconductance amplifier is the ratio of the output current to the input voltage, and the transimpedance gain of the transimpedance amplifier is the ratio of the output voltage to the input current.

[0055] In a possible implementation, the transimpedance amplifier includes an active inductance structure for changing the response of a specific frequency component in the current signal, and the specific frequency component is determined based on the frequency component attenuated by the capacitive load. Therefore, the active inductance structure introduces a zero point in the frequency response curve of the output signal of the signal compensation and equalization module 01 to offset the influence of the pole introduced by the capacitive load in the frequency response curve. The active inductance structure is a circuit structure for simulating the inductance characteristics of an active device (such as a transistor), which is mainly used to expand the signal bandwidth. In a high-speed serial interface, the active inductance is connected to a head-to-tail inverter through a normally open transmission gate to form an equivalent inductance, thereby expanding the signal bandwidth.

[0056] Optionally, a cross-coupled capacitor structure is included in the transimpedance amplifier to generate a negative capacitance, which offsets part of the positive capacitance in the bandwidth extension circuit, i.e., offsets part of the positive capacitance in the signal transmission link, thereby improving the high-frequency capability of the circuit. The positive capacitance allows current to flow into the capacitor when the voltage rises, while the negative capacitance allows current to flow out of the capacitor when the voltage rises. Therefore, the positive and negative capacitances are opposite, and connecting the negative and positive capacitances in parallel can offset each other, so that the equivalent capacitance after offsetting is reduced or even zero, thereby reducing the loss of the capacitor at high frequencies and extending the bandwidth of the circuit. For example, the negative capacitance can be a Miller negative capacitance.

[0057] Optionally, the second bandwidth boosting module 03 includes a differential amplifier, a low-pass filter, and a converter. The differential amplifier is configured to buffer and amplify the high-frequency components in the output signal of the first bandwidth boosting module 02, e.g., buffer and amplify the third signal, and output the buffered and amplified third signal. The low-pass filter is configured to extract the low-frequency components in the output signal of the differential amplifier and filter out the high-frequency components, e.g., extract the low-frequency components in the buffered and amplified third signal and filter out the high-frequency components. The converter is configured to inversely offset the low-frequency components extracted by the low-pass filter and the low-frequency components in the output signal of the signal compensation equalization module 01 to reduce the low-frequency components in the output signal of the signal compensation equalization module 01.

[0058] For example, the second bandwidth boosting module 03 can adopt the structure of a low-frequency equalizer (LFEQ). The core idea of the LFEQ is to actively offset part of the low-frequency signal through a low-frequency negative feedback network, introduce a left half-plane zero point in the transfer function, and reduce the low-frequency frequency response, thereby releasing the bandwidth.

[0059] In one possible implementation, the transmitted signal is a differential signal, i.e., the first signal is a differential signal. The second bandwidth boosting module 03 inversely injects the low-frequency components into the input end of the first bandwidth boosting module 02, i.e., the signal output by the positive output end of the second bandwidth boosting module 03 is coupled to the negative input end of the first bandwidth boosting module 02 and subtracted from the original signal at the negative input end. The signal output by the negative output end of the second bandwidth boosting module 03 is coupled to the positive input end of the first bandwidth boosting module 02 and subtracted from the original signal at the positive input end. The input end of the first bandwidth boosting module 02 is the output end of the signal compensation equalization module 01, so the positive output end of the second bandwidth boosting module 03 is connected to the positive output end of the signal compensation equalization module 01, and the negative output end of the second bandwidth boosting module 03 is connected to the negative output end of the signal compensation equalization module 01.

[0060] In summary, the bandwidth expansion circuit provided by the embodiments of the present application can compensate for high-frequency attenuation in the channel transmission process, alleviate the influence of the subsequent capacitive load, and further improve the circuit bandwidth by depressing low-frequency components, thereby solving the problem that the wideband performance cannot be effectively improved under a single technology, i.e., effectively improving the circuit bandwidth.

[0061] Exemplarily, referring to Figure 3 , the bandwidth expansion circuit includes a CTLE, a VGA, a GM, a TIA, and an LFEQ. The CTLE, the VGA, the GM, and the TIA are connected in series in sequence, the input end of the LFEQ is connected to the output end of the TIA, and the output end of the LFEQ is connected to the input end of the GM. In the scenario of transmitting a differential signal, the negative output end of the CTLE is connected to the positive input end of the VGA, and the positive output end of the CTLE is connected to the negative input end of the VGA; the negative output end of the VGA is connected to the positive input end of the GM, and the positive output end of the VGA is connected to the negative input end of the GM; the negative output end of the GM is connected to the positive input end of the TIA, and the positive output end of the GM is connected to the negative input end of the TIA; the negative output end of the TIA is connected to the positive input end of the LFEQ, and the positive output end of the TIA is connected to the negative input end of the LFEQ; and the negative output end of the LFEQ is connected to the positive input end of the GM, and the positive output end of the LFEQ is connected to the negative input end of the GM.

[0062] The CTLE is configured to compensate for high-frequency components to compensate for the loss of an equalization channel. The circuit structure and working principle of the CTLE can be referred to the related description shown in Figure 1 , which will not be described herein again.

[0063] The VGA is configured to adjust the gain to amplify the input signal to a proper amplitude. Optionally, the VGA includes a differential pair circuit. The differential pair circuit includes two transistors (e.g., MOS tubes or bipolar junction transistors (BJTs)) with matched characteristics, the sources (or emitters) of the two transistors are connected together and grounded through a tail current source. The input signal is applied to the gates (or bases) of the two transistors in a differential form, and the output signal is obtained from the voltage difference between the two drains (or collectors).

[0064] Exemplarily, the circuit structure of the VGA is as shown in Figure 4As shown. Among them, the two transistors constituting the differential pair structure are NMOS tube NM1 and NMOS tube NM2, which is also called N-type MOS tube. The NMOS tube is turned on when the gate voltage is high, and is turned off when the gate voltage is low. The drain of NM1 is connected to the power supply VDD through resistor R3, and the drain of NM2 is connected to the power supply VDD through resistor R4. The source of NM1 and NM2 is connected together and grounded through the tail current source It. The gate of NM1 is connected to the positive output Op1 of the CTLE circuit, and the gate of NM2 is connected to the negative output On1 of the CTLE. The drain of NM1 is also connected to the negative output On2 of the VGA, and the drain of NM2 is also connected to the positive output Op2 of the VGA.

[0065] Thus, in the VGA, by changing the current size of the tail current source It, the gain state of the whole circuit can be changed, but it will not affect the bandwidth of the whole circuit. The load resistance of the amplifier is connected with the output of the feedback LFEQ module to offset the low frequency component of the signal in the VGA output, thereby forming a zero point.

[0066] The GM is used to convert the voltage signal of the VGA output into a current signal, and the TIA is used to convert the current signal output by the GM into a voltage signal. The combination of GM and TIA is called GM-TIA, and the circuit structure of GM-TIA is based on the inverter.

[0067] Exemplarily, the circuit structure of the GM is as shown in Figure 5 . Among them, the GM includes PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, NMOS tube NM3, NMOS tube NM4 and NMOS tube NM5. The PMOS tube is also called P-type MOS tube, and the PMOS tube is turned on when the gate voltage is low, and is turned off when the gate voltage is high. The gate of PM1 is connected to the bias voltage Vbiasp1, the source of PM1 is connected to the power supply VDD, and the drain of PM1, the source of PM2 and the source of PM3 are connected together. The gate of NM5 is connected to the bias voltage Vbiasn1, the source of NM5 is grounded, and the drain of NM5, the source of NM3 and the source of NM4 are connected together. Among them, the bias voltage is used for the MOS tube to work in the appropriate area (such as saturation region), to generate appropriate bias current to ensure the stable operation of the circuit.

[0068] Continuing to refer to Figure 5 , the gate of PM2 and the gate of NM3 are connected to the negative output On2 of the VGA, and the gate of PM3 and the gate of NM4 are connected to the positive output Op2 of the VGA. The drain of PM2 and the drain of NM3 are connected to the positive output Op3 of the GM, and the drain of PM3 and the drain of NM4 are connected to the negative output On3 of the GM, forming a push-pull structure. Thus, by changing the gate voltage to control the source current, the transconductance function of voltage to current conversion is realized.

[0069] Exemplarily, the circuit structure of the TIA is as shown in Figure 6 . In the TIA, there are PMOS transistor PM4, PMOS transistor PM5, PMOS transistor PM6, NMOS transistor NM6, NMOS transistor NM7 and NMOS transistor NM8. The gate of PM4 is connected to bias voltage Vbiasp2, the source of PM4 is connected to power supply VDD, and the drain of PM4, the source of PM5 and the source of PM6 are connected together. The gate of NM8 is connected to bias voltage Vbiasn2, the source of NM8 is connected to ground, and the drain of NM8, the source of NM6 and the source of NM7 are connected together. The gate of PM5 and the gate of NM6 are connected to the negative output On3 of the GM, and the gate of PM6 and the gate of NM7 are connected to the positive output Op3 of the GM. The drain of PM5 and the drain of NM6 are connected to the positive output Op4 of the TIA, and the drain of PM6 and the drain of NM7 are connected to the negative output On4 of the TIA.

[0070] Continuing as shown in Figure 6 , the gate and the drain of PM5 are further connected to resistor Rt1, and the gate and the drain of NM7 are further connected to resistor Rt2, thereby forming an Active-Inductor structure. The Active-Inductor structure can effectively introduce a zero point to offset the influence of a large-capacitance load in the subsequent stage, thereby playing a major role in expanding the bandwidth of the circuit. In addition, the drain of PM5 and the gate of PM6 are further connected to capacitor Ct1, and the drain of NM7 and the gate of NM6 are further connected to capacitor Ct2, thereby adding a cross-coupled capacitor structure to the TIA to offset a part of the input capacitance according to the Miller negative capacitance principle, thereby further reducing the influence of the capacitance and improving the high-frequency performance of the circuit, which is one of the effective methods to improve the overall bandwidth.

[0071] The LFEQ is used to return a low-frequency signal to reduce the low-frequency frequency response of the VGA circuit. Exemplarily, the circuit structure of the LFEQ is as shown in Figure 7 . In the LFEQ, there are a differential amplification circuit, a low-pass filter circuit and a transconductance stage current conversion circuit. The differential amplification circuit includes NMOS transistor NM9, NMOS transistor NM10, resistor R5, resistor R6, resistor Rs`, current source I3 and current source I4; the low-pass filter circuit includes resistor Rfb and capacitor Cfb; and the transconductance stage current conversion circuit includes NMOS transistor NM11, NMOS transistor NM12 and current source It`.

[0072] The gate of the NM9 and the gate of the NM10 in the differential amplifier circuit are connected with the negative input end On4 and the positive input end Op4 of the TIA respectively, and the structure of the differential amplifier circuit can refer to the foregoing relevant description, which will not be described again. The circuit structure of the low-pass filter circuit is a first-order low-pass filter based on RC, wherein R refers to Figure 7 the resistance Rfb shown in the figure, and C refers to Figure 7 the capacitor Cfb shown in the figure. The last transconductance stage current conversion circuit is connected with the positive output end Op5 and the negative output end On5 of the LFEQ through the structure of the differential pair tube.

[0073] Therefore, according to the second-level module of the LFEQ shown in Figure 7 , the analog signal in the signal output by the TIA can be buffered through a differential amplifier, then the low-frequency component in the signal output by the TIA can be extracted through a first-order low-pass filter based on RC, and then the extracted low-frequency component can be offset with the output of the VGA through a transconductance stage, so as to realize the introduction of another zero point, thereby further improving the bandwidth of the circuit.

[0074] In summary, to realize the circuit performance of wideband and high speed is not achieved at one stroke, and cannot rely on only a single circuit technology, but needs to consider and combine multiple effective technologies reasonably and carefully, and realize the finally required wideband performance. The embodiments of the present application combine multiple wideband technologies to use multiple technologies to improve the performance of the circuit. First, the source degeneration CLET of the first stage is used to generate boost compensation and flatten the frequency response. The VGA of the second stage is used to adjust the gain of the signal of the previous stage. The GM-TIA of the third stage is used to generate a zero point to neutralize the capacitance of the next stage, and also introduces the Miller negative capacitance technology to effectively improve the bandwidth of the circuit. The LFEQ of the last stage returns the low-frequency signal to lower the low-frequency frequency response of the VGA circuit, thereby further realizing the generation of a zero point of the circuit and further improving the wideband of the circuit.

[0075] The embodiments of the present application also provide a chip, which includes Figure 2 the bandwidth expansion circuit shown in any one of the preceding embodiments 1 to 3. Exemplarily, the chip can be a receiver (RX) chip deployed at the receiving end of a high-speed serial signal. It can be understood that the chip has basically the same technical effects as the bandwidth expansion circuit, and therefore the technical effects of the chip will not be described again for the purpose of brevity.

[0076] The embodiments of the present application also provide a receiver, which includes Figure 2 the bandwidth expansion circuit shown in any one of the preceding embodiments 1 to 3. For example, the chip described above includes the receiver, and therefore the chip includes Figure 2or any one of 3. It can be understood that the receiver has substantially the same technical effects as the bandwidth extension circuit described above, and therefore the technical effects of the receiver are not repeated here for the purpose of brevity.

[0077] The terms "first", "second", "third", and "fourth" and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the descriptive terms used herein are to be interpreted in the context as describing a particular embodiment and under no circumstances are to be taken to mean exclusive arrangements. Furthermore, the terms "comprise", "have", "contain" and "include" and any variations thereof used in this description and in the claims are intended to cover both the case where only the stated elements are present and the case where additional elements are present.

[0078] The above description is only some optional embodiments of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A bandwidth extension circuit, characterized by, The bandwidth expansion circuit comprises a signal compensation equalization module, a first bandwidth boosting module and a second bandwidth boosting module; The signal compensation equalization module is configured to receive a first signal through a signal input end, equalize and amplify high-frequency components in the first signal, and output a second signal equalized and amplified, wherein the high-frequency components are signal components with a frequency greater than a first threshold. The second bandwidth boosting module is configured to feed back the extracted low-frequency components to an output end of the signal compensation equalization module to suppress low-frequency components in the second signal, wherein the low-frequency components are signal components with a frequency less than a second threshold. The first bandwidth boosting module is configured to offset high-frequency attenuation of the second signal after the low-frequency components are suppressed, and send a third signal after the high-frequency attenuation is offset through a signal output end, wherein the capacitive load comprises at least one of a load capacitor, an AC coupling capacitor or a parasitic capacitor connected subsequently to the first bandwidth boosting module. The second bandwidth boosting module is further configured to extract low-frequency components from the third signal.

2. The circuit of claim 1, wherein, The second bandwidth boosting module comprises a differential amplifier, a low-pass filter and a converter. The differential amplifier is configured to buffer and amplify the third signal and output the third signal after the buffer amplification. The low-pass filter is configured to extract low-frequency components from the third signal after the buffer amplification and filter out high-frequency components. The converter is configured to offset the low-frequency components extracted by the low-pass filter and the low-frequency components in the second signal output by the signal compensation equalization module in a reverse manner.

3. The circuit of claim 1, wherein, The second signal is a first voltage signal, and the third signal is a second voltage signal; the first bandwidth boosting module comprises a transconductance amplifier and a transimpedance amplifier. The transconductance amplifier is configured to convert the input first voltage signal into a current signal and buffer the current signal to the transimpedance amplifier in the subsequent stage. The transimpedance amplifier is configured to convert the input current signal into the second voltage signal and offset high-frequency attenuation of the current signal by the capacitive load.

4. The circuit of claim 3, wherein, The transimpedance amplifier comprises an active inductance structure for changing the response of specific frequency components in the current signal, wherein the specific frequency components are determined based on the frequency components attenuated by the capacitive load.

5. The circuit of claim 3, wherein, The transimpedance amplifier comprises a cross-coupled capacitor structure for generating a negative capacitance to offset part of the positive capacitance in the bandwidth expansion circuit.

6. The circuit according to any of claims 1-5, characterized in that The signal compensation equalization module comprises at least one continuous-time linear equalizer configured to equalize and amplify corresponding high-frequency components in the first signal to different degrees.

7. The circuit of claim 6, wherein, The second signal is a second signal after gain adjustment, and the signal compensation equalization module further comprises a variable gain amplifier configured to adjust the gain of the signal output by the at least one continuous-time linear equalizer according to the amplitude requirement of the subsequent load circuit.

8. The circuit according to any of claims 1-5, characterized in that The first signal is a differential signal, a positive output end of the second bandwidth boosting module is connected with a positive output end of the signal compensation equalization module, and a negative output end of the second bandwidth boosting module is connected with a negative output end of the signal compensation equalization module.

9. A chip, characterized by The chip comprises the bandwidth extension circuit according to any one of claims 1-8.

10. A receiver, characterized by The receiver comprises the bandwidth extension circuit according to any one of claims 1-8.

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