Integrated solution for NAND deep contact gap fill

Abstract

A method of filling a via having a necking point includes performing a pre-cleaning process to remove a residue from an exposed surface of a metal layer at a bottom of the via formed within a dielectric layer and having a necking point protruding within the via and to restore an inner surface of the via; performing a selective deposition process to partially fill the via with a metal fill material from an exposed surface of the metal layer below the necking point; performing a liner deposition process to form a liner layer on the exposed inner surface of the via; and performing a metal filling process to fill the through hole with a metal filling material.

Description

TECHNICAL FIELD

[0001] Embodiments herein are directed to methods used in electronic device manufacturing, and more specifically, to processes for high quality tungsten (W) fill of deep contact gaps in NAND devices. BACKGROUND

[0002] Tungsten (W) is widely used in integrated circuit (IC) device manufacturing to form conductive features where relatively low electrical resistance and relatively high electromigration resistance are desired. For example, tungsten can be used as a metal fill material to form source contacts, drain contacts, metal gate fill, gate contacts, interconnects (e.g., horizontal features formed in the surface of a dielectric material layer), and vias (e.g., vertical features formed through a dielectric material layer to connect other interconnect features disposed above and below it). Due to its relatively low resistivity, tungsten is also commonly used to form interconnects at the M0 level of an IC device, as well as for bit lines and word lines that address individual memory cells in the memory cell array of a three-dimensional NAND (3D NAND) device.

[0003] In future generations of NAND devices, metal contact structures will move from single-tier tapered structures to multi-tier structures with landing pads. Conventional deposition processes, such as chemical vapor deposition (CVD), have shown challenges in filling deep contact gaps, such as multi-tier structures with landing pads, with tungsten, resulting in voids or seams in the filled tungsten.

[0004] Accordingly, there is a need for processes that can fill deep contact gaps in NAND devices with tungsten (W) to form high quality interconnects. SUMMARY

[0005] Embodiments of the present disclosure provide a method of filling a via having a necking point. The method includes performing a pre-clean process to remove residue from an exposed surface of a metal layer at a bottom of the via and to restore an inner surface of the via, wherein the via is formed within a dielectric layer and has a necking point protruding within the via; performing a selective deposition process to partially fill the via with a metal fill material from the exposed surface of the metal layer below the necking point; performing a liner deposition process to form a liner layer on the exposed inner surface of the via; and performing a metal fill process to fill the via with the metal fill material.

[0006] Embodiments of the present disclosure provide a method of filling a via having a necking point. The method includes performing a liner deposition process to form a liner layer on exposed interior surfaces of the via, wherein the via is formed within a dielectric layer and has a necking point protruding within the via; performing a liner pullback process to remove the liner layer above the necking point; performing a selective deposition process to partially fill the via with a metal fill material from exposed surfaces of the liner layer below the necking point; and performing a metal fill process to fill the via with the metal fill material.

[0007] Embodiments of the present disclosure provide a method of filling a via having a necking point. The method includes performing a liner deposition process to form a liner layer on exposed interior surfaces of the via, wherein the via is formed within a dielectric layer and has a necking point protruding within the via; performing a liner pullback process to remove the liner layer above the necking point; performing a selective deposition process to partially fill the via with a metal fill material from exposed surfaces of the liner layer below the necking point; and performing a metal fill process to fill the via with the metal fill material. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to enable a fuller understanding of the above-mentioned features of the present disclosure, a more complete description of the present disclosure can be had by reference to the following detailed description, some embodiments of which are illustrated in the accompanying drawings. It is to be noted, however, that the accompanying drawings show only example embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure can admit to other equally effective embodiments.

[0010] Figure 1 is a schematic top view of a multi-chamber processing system 100 in accordance with one or more embodiments of the present disclosure.

[0011] Figure 2 is a schematic diagram of a middle-of-line (MEOL) portion of an exemplary semiconductor structure in accordance with one or more embodiments of the present disclosure.

[0012] Figure 3 depicts a process flow diagram of a method of filling a via of a landing pad structure in a semiconductor structure in accordance with a first embodiment of the present disclosure.

[0013] Figure 4A , Figure 4B , Figure 4C and Figure 4D are cross-sectional diagrams of portions of a semiconductor structure corresponding to various states of the method of Figure 3 .

[0014] Figure 5 depicts a process flow diagram of a method of filling a via of a landing pad structure in a semiconductor structure in accordance with a second embodiment of the present disclosure.

[0015] Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D and Figure 6E are cross-sectional views of portions of a semiconductor structure corresponding to various states of the method of Figure 5

[0016] Figure 7 depicts a process flow diagram of a method of filling a via of a landing pad structure in a semiconductor structure according to a third embodiment of the disclosure.

[0017] Figure 8A 、 Figure 8B 、 Figure 8C and Figure 8D are cross-sectional views of portions of a semiconductor structure corresponding to various states of the method of Figure 7

[0018] For ease of understanding, the same reference numbers have been used in the various drawings to designate the same elements. It is contemplated that elements and features of one embodiment can be beneficially incorporated into other embodiments without further recitation. DETAILED DESCRIPTION

[0019] Embodiments herein relate to methods used in electronic device manufacturing, and more specifically, to processes for high quality tungsten (W) fill of deep contact gaps in NAND devices.

[0020] The methods disclosed herein include filling a high aspect ratio via having a necking point with tungsten (W), starting with a selective deposition of tungsten (W) to fill the via from a bottom surface of the via (e.g., tungsten (W), titanium nitride (TiN)) below the necking point, and ending with a metal fill of tungsten (W) to fill the rest of the via. In the selective deposition, the via is filled with tungsten (W) from the bottom surface of the via in a bottom-up manner without forming any voids or seams within the metal fill material.

[0021] Processing system example

[0022] Figure 1 ​​is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates in the processing system 100 can be processed in the various chambers and transferred between the chambers without exposing the substrates to the ambient environment outside the processing system 100 (e.g., such as the atmospheric ambient environment that can be present in a semiconductor foundry). For example, substrates can be processed in the various chambers and transferred between the chambers while maintaining a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without breaking the low pressure or vacuum environment between the various processes performed on the substrates in the processing system 100. Thus, the processing system 100 can provide an integrated solution for some processing of substrates.

[0023] In Figure 1 In the illustrated example, the factory interface 102 includes a dock station 132 and factory interface robots 134 to facilitate transfer of substrates. The dock station 132 is adapted to receive one or more front opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed on one end of the respective factory interface robot 134 adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0024] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 148, 150 coupled to the holding chambers 116, 118 and respective ports 152, 154 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 can be, for example, slit valve openings with slit valves for passing substrates therethrough by the transfer robots 112, 114 and provide a seal between the respective chambers to prevent gas from passing between the respective chambers. Generally, any port is open when a substrate is being transferred therethrough. Otherwise, the port is closed.

[0025] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 134 transfers a substrate from a FOUP 136 through the port 140 or 142 to the load lock chamber 104 or 106. The gas and pressure control system then evacuates the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 with an internal low pressure or vacuum environment (possibly including an inert gas). Thus, the evacuation of the load lock chamber 104 or 106 facilitates the transfer of a substrate between, for example, an atmospheric environment of the factory interface 102 and a low pressure or vacuum environment of the transfer chamber 108.

[0026] With a substrate in the evacuated load lock chamber 104 or 106, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 through the port 144 or 146 to the transfer chamber 108. The transfer robot 112 can then transfer the substrate through respective ports 152, 154 to any of the processing chambers 120, 122 and / or between the processing chambers for processing, and through respective ports 148, 150 to the holding chambers 116, 118 and / or between the holding chambers for holding to await further transfer. Similarly, the transfer robot 114 can access a substrate in the holding chamber 116 or 118 through the port 156 or 158, and can transfer the substrate through respective ports 160, 162, 164, 166 to any of the processing chambers 124, 126, 128, 130 and / or between the processing chambers for processing, and through respective ports 156, 158 to the holding chambers 116, 118 and / or between the holding chambers for holding to await further transfer. The transfer and holding of substrates within and between the various chambers can be performed in the low pressure or vacuum environment provided by the gas and pressure control system.

[0027] The processing chambers 120, 122, 124, 126, 128, 130 can be any appropriate chamber for processing a substrate. In some examples, the processing chamber 120 can be capable of performing an etch process, the processing chamber 122 can be capable of performing a cleaning process, and the processing chambers 126, 128, 130 can be capable of performing respective epitaxial growth processes.

[0028] The system controller 168 is coupled to the processing system 100 for controlling the processing system 100 or components thereof. For example, the system controller 168 can control the operation of the processing system 100 using direct controls to the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 or through controls to the controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 implements data collection and feedback from the respective chambers to coordinate the performance of the processing system 100.

[0029] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuits 174. The CPU 170 can be one of any form of general purpose processor that can be used in an industrial setting. The memory 172, or non-transitory computer readable medium, is accessible by the CPU 170 and can be one or more memory such as random access memory (RAM), read only memory (ROM), magnetic disk, hard drive, or any other form of local or remote digital storage. The support circuits 174 are coupled to the CPU 170 and can include cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein can be implemented in general by the CPU 170 executing computer instruction code stored in the memory 172 (or the memory of a particular processing chamber) as, for example, software routines. When the computer instruction code is executed by the CPU 170, the CPU 170 controls the chambers to perform processes according to the various methods.

[0030] Other processing systems can have other configurations. For example, more or fewer processing chambers can be incorporated with the transfer means. In the example shown, the transfer means includes transfer chambers 108, 110 and holding chambers 116, 118. In other embodiments, the transfer means can be implemented as more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) in a processing system.

[0031] Example semiconductor structure

[0032] Figure 2 is a schematic illustration of an exemplary semiconductor structure 200, which can be a three-dimensional NAND (3D NAND) device with metal contacts.

[0033] The semiconductor structure 200 can include a first level LI including a metal layer 202 within a first dielectric layer 204 formed on a substrate 206, and a second level L2 including an interconnect 208 within a landing pad 210 having a via 212 formed within a stack of a second dielectric layer 214 and a third dielectric layer 216 formed on the second level L2. Within the landing pad 210, a liner layer 218 can be formed around the interconnect 208. The via 212 can have a width between about 160 nm and about 240 nm and a depth between about 5 pm and about 20 pm. Due to etching through the second dielectric layer 214 and the third dielectric layer 216 to form the via 212, the landing pad 210 can have a pinch point 220 near the interface between the second dielectric layer 214 and the third dielectric layer 216. The pinch point 220 can protrude within the via 212 by between about 100 nm and about 120 nm. The third dielectric layer 216 can have a thickness between about 800 nm to about 1.2 pm. When formed by a conventional deposition process, such as chemical vapor deposition (CVD), the interconnect 208 formed within the via 212 can have a void 208V below the pinch point 220.

[0034] The term "substrate" as used herein refers to a layer of material upon which subsequent processing operations are performed and includes the surface to be cleaned. The substrate 206 can be a silicon-based material or any suitable insulating or conductive material, as desired. The substrate 206 can include materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped poly silicon, doped or undoped silicon wafers and patterned or non-patterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0035] The metal layer 202 and the interconnect 208 can be formed from tungsten (W), tungsten carbide (WC), tungsten nitride (WN), or molybdenum (Mo).

[0036] The first dielectric layer 204, the second dielectric layer 214, and the third dielectric layer 216 can each be formed from a dielectric material such as silicon oxide (SiO2) or silicon nitride (Si3N4).

[0037] The liner layer 218 can be formed from titanium nitride (TiN) or tungsten (W).

[0038] Metal fill

[0039] Figure 3 A process flow diagram of a method 300 of filling a via of a landing pad structure in a semiconductor structure, such as the semiconductor structure 200 shown, is depicted in accordance with a first embodiment of the present disclosure. Figure 2 A process flow diagram of a method 300 of filling a via of a landing pad structure in a semiconductor structure, such as the semiconductor structure 200 shown, is depicted in accordance with a first embodiment of the present disclosure.Figure 4A , Figure 4B , Figure 4C and Figure 4D are cross-sectional views of the semiconductor structure 200 corresponding to various states of the method 300. It is understood that Figure 4A , Figure 4B , Figure 4C and Figure 4D only show partial schematic views of the semiconductor structure 200, and the semiconductor structure 200 can contain any number of transistor portions and additional materials having aspects as shown in the figures. It is also noted that although the method shown in Figure 3 is described in sequence, other process sequences containing one or more operations that have been omitted and / or added, and / or have been rearranged in another desired order, fall within the scope of embodiments of the disclosure provided herein.

[0040] As shown in Figure 4A , the semiconductor structure 200 includes a first level containing a metal layer 202 within a first dielectric layer 204 formed on a substrate 206, and a second level L2 containing a stack of a second dielectric layer 214 and a third dielectric layer 216, with a via 212 formed on the first level L1. At the bottom of the via 212, a surface 202S of the metal layer 202 is exposed. An interconnect 208 (not shown in Figure 4A ) is to be formed within the via 212.

[0041] Near the interface between the second dielectric layer 214 and the third dielectric layer 216, a necking point 220 is formed within the via 212 due to etching through the second dielectric layer 214 and the third dielectric layer 216 to form the via 212. The via 212 can have a width between about 160 nm and about 240 nm and a depth between about 5 pm and about 20 pm. The necking point 220 can protrude within the via 212 by between about 100 nm and about 120 nm at a height between about 250 nm and about 300 nm from the bottom of the via, corresponding to the thickness of the third dielectric layer 216.

[0042] The metal layer 202 and the interconnect 208 can be formed of tungsten (W) or molybdenum (Mo). The first dielectric layer 204, the second dielectric layer 214, and the third dielectric layer 216 can each be formed of a dielectric material such as silicon oxide (Si02) or silicon nitride (Si3N4).

[0043] The method 300 begins at block 310, where a pre-clean process is performed to remove residue from the exposed surface 202S of the metal layer 202 and to restore the inner surface of the via 212 (e.g., the exposed surfaces of the second dielectric layer 214 and the third dielectric layer 216 within the via 212).

[0044] During fabrication at the second level L2, the semiconductor structure 200 can be exposed to air or other oxidizing environments, and thus the surface 202S of the metal layer 202 can oxidize. In addition, the etching process used to form the via 212 within the stack of the second dielectric layer 214 and the third dielectric layer 216 can also leave residues, such as chlorine residues or fluorine residues, on the surface 202S of the metal layer 202, or damage the surfaces of the second dielectric layer 214 and the third dielectric layer 216 within the via 212. Accordingly, the surface 202S of the metal layer 202, the surfaces of the second dielectric layer 214 and the third dielectric layer 216 within the via 212 are pre-cleaned to form the interconnect 208 prior to filling the via 212 from the bottom surface of the via 212 (the surface 202S of the metal layer 202).

[0045] The pre-cleaning process can include a chemical soak process to selectively remove metal oxides (e.g., tungsten oxide (WO x )) from the surface 202S of the metal layer 202, where the surface 202S of the metal layer 202 is soaked in a precursor (e.g., tungsten fluoride (WF6), hydrogen (H2)) provided in a CVD / ALD processing chamber, such as the processing chamber 124, 126, 128, or 130 shown, in a pulsed flow or a continuous flow. Figure 1 The pre-cleaning process to selectively remove metal oxides (e.g., tungsten oxide (WO x )) from the surface 202S of the metal layer 202 can be a plasma process using a plasma formed from a process gas including a hydrogen (H2) containing gas. The plasma process can be an inductively coupled plasma (ICP) process performed in a processing chamber, such as the processing chamber 124, 126, 128, or 130 shown, or a capacitively coupled plasma (CCP) process performed in a processing chamber, such as the processing chamber 124, 126, 128, or 130 shown. Figure 1 Figure 1 The pre-cleaning process to selectively remove metal oxides (e.g., tungsten oxide (WO x )) from the surface 202S of the metal layer 202 can be a plasma process using a plasma formed from a process gas including a hydrogen (H2) containing gas. The plasma process can be an inductively coupled plasma (ICP) process performed in a processing chamber, such as the processing chamber 124, 126, 128, or 130 shown, or a capacitively coupled plasma (CCP) process performed in a processing chamber, such as the processing chamber 124, 126, 128, or 130 shown.

[0046] The pre-cleaning process to restore the exposed surfaces of the second dielectric layer 214 and the third dielectric layer 216 within the via 212 can include a plasma treatment process using a plasma formed from a process gas including an oxygen (O2) containing gas. The plasma treatment process can be a capacitively coupled plasma (CCP) process performed in a processing chamber, such as the processing chamber 124, 126, 128, or 130 shown. The plasma treatment process can be an inductively coupled plasma (ICP) process performed in a processing chamber, such as the processing chamber 124, 126, 128, or 130 shown. Figure 1 Figure 1 The pre-cleaning process to restore the exposed surfaces of the second dielectric layer 214 and the third dielectric layer 216 within the via 212 can include a plasma treatment process using a plasma formed from a process gas including an oxygen (O2) containing gas. The plasma treatment process can be a capacitively coupled plasma (CCP) process performed in a processing chamber, such as the processing chamber 124, 126, 128, or 130 shown. The plasma treatment process can be an inductively coupled plasma (ICP) process performed in a processing chamber, such as the processing chamber 124, 126, 128, or 130 shown.

[0047] In block 320, a selective deposition process is performed to partially fill the via 212 with a metal fill material 402 from the exposed surface 202S of the metal layer 202 below the necking point 220, as shown in FIG. 3B. The metal fill material 402 can be tungsten (W) or molybdenum (Mo). Figure 4B

[0048] In the selective deposition process, the metal fill material 402 selectively grows on the exposed surface 202S of the metal layer 202 without on the sidewalls of the via 212 (e.g., silicon nitride (Si3N4) or silicon oxide (Si02)), and thus the via 212 is filled with the metal fill material 402 from the bottom surface 202S of the via 212 in a bottom-up manner without forming any voids or seams within the metal fill material 402.

[0049] The selective deposition process can include a chemical vapor deposition (CVD) process using tungsten (W)-containing precursors (such as tungsten hexafluoride (WF6) and hydrogen (H2)) in a processing chamber (such as the processing chamber 126 shown in FIG. 1A), as shown in FIG. 3B. Figure 1 The flow rate ratio of the tungsten (W)-containing precursors to the hydrogen (H2) carrier gas can be between about 0.001 and about 0.007 to ensure the deposition selectivity of tungsten (W) on the metal layer 202 (e.g., tungsten (W)).

[0050] The selective deposition process is performed at a temperature between about 300 °C and about 500 °C.

[0051] In block 330, a liner deposition process is performed to form a liner layer 218 on the exposed inner surface of the via 212, as shown in FIG. 3C. The liner layer 218 can be formed of titanium nitride (TiN) or tantalum nitride (TaN) and is used as a nucleation layer in block 340 on which the metal fill material 402 (such as tungsten (W)) grows in a subsequent metal fill process. Figure 4C

[0052] The liner deposition process can include an atomic layer deposition (ALD) process performed in a processing chamber (such as the processing chambers 124, 126, 128, or 130 shown in FIG. 1A), as shown in FIG. 3C, in which a metal-containing precursor including titanium (Ti) and a nitrogen-containing precursor are alternately delivered to the semiconductor structure 200. In some embodiments, the metal-containing precursor is purged before the nitrogen-containing precursor is delivered. Examples of the metal-containing precursor including titanium (Ti) are inorganic compounds of titanium (Ti), such as titanium chloride (TiCl4), and organometallic compounds of titanium (Ti), such as tetrakis(dimethylamido)titanium (TDMAT, [(CH3)2N]4Ti). Examples of the nitrogen-containing precursor are ammonia (NH3), diazene (N2H2), and hydrazine (N2H4). Figure 1

[0053] ​​​In block 340, a metal fill process is performed to fill the via 212 with a metal fill material 402, such as tungsten (W), to form the interconnect 208, as shown in Figure 4D

[0054] In the metal fill process, the metal fill material 402 grows from the liner layer 218 deposited on the inner surface of the via 212. The metal fill process can include a chemical vapor deposition (CVD) process using a tungsten (W)-containing precursor, such as tungsten hexafluoride (WF6) and a hydrogen (H2)-containing carrier gas, in a process chamber, such as the process chamber 126 shown in Figure 1 Additionally, pulses of a nitrogen-containing gas, such as nitrogen (N2) radicals, ammonia (NH3), or nitrogen fluoride (NF3), can be added between the deposition of tungsten (W) to inhibit deposition of tungsten (W) on the field (e.g., on the second dielectric layer 214) so that the tungsten (W) grows conformally from the liner layer 218 without forming seams.

[0055] The metal fill process is performed at a temperature between about 350 °C and about 500 °C, at a flow rate of the tungsten (W)-containing precursor between about 200 seem and about 800 seem, and a flow rate of the hydrogen (H2)-containing carrier gas between about 2000 seem and about 8000 seem.

[0056] Figure 5 A process flow diagram of a method 500 of filling a via of a landing pad structure in a semiconductor structure, such as the semiconductor structure 200 shown in Figure 2 The same reference numbers are used for substantially the same components as in the first embodiment, and the description of the duplicate components can be omitted. Figure 6A Figure 6B Figure 6C Figure 6D Figure 6E are cross-sectional views of the semiconductor structure 200 corresponding to various states of the method 500. It is to be understood that Figure 6A Figure 6B Figure 6C Figure 6D Figure 6E are only partial schematic views of the semiconductor structure 200, and the semiconductor structure 200 can contain any number of transistor portions and additional materials having aspects as shown in the figures. It is also noted that while the method shown in Figure 5 is described in sequence, other process sequences containing one or more operations that have been omitted and / or added, and / or rearranged in another desired order, fall within the scope of the embodiments of the disclosure provided herein.

[0057] ​​​​​​​​​Method 500 begins at block 510, where a liner deposition process is performed to form a liner layer 602 on exposed inner surfaces of the via 212, as shown in Figure 6A This liner deposition process is performed prior to the selective deposition process to fill the via 212 below the necking point 220, and thus the liner layer 602 is formed on the inner surfaces of the via 212 above and below the necking point 220. The liner layer 602 can be formed of titanium nitride (TiN) or tantalum nitride (TaN).

[0058] The liner deposition process in block 510 is similar or identical to the liner deposition process in block 330.

[0059] In block 520, a liner pullback process is performed to remove the liner layer 602 above the necking point 220, as shown in Figure 6B

[0060] The liner pullback process can include a wet etch process or a dry etch process in an etch chamber, such as the processing chamber 122 shown in Figure 1

[0061] In block 530, an optional pre-clean process is performed to restore the inner surfaces of the via 212 (e.g., the exposed surfaces of the second dielectric layer 214 within the via 212) that are damaged in the liner pullback process in block 520. The pre-clean process in block 530 is similar or identical to the pre-clean process in block 310.

[0062] In block 540, a selective deposition process is performed to partially fill the via 212 with a metal fill material 402 (such as tungsten (W)) from exposed surfaces of the liner layer 602 at the bottom of the via 212 below the necking point 220, as shown in Figure 6C

[0063] In the selective deposition process, the metal fill material 402 selectively grows on the exposed surfaces of the liner layer 602 without on the sidewalls of the via 212 (e.g., silicon nitride (Si3N4) or silicon oxide (SiO2)), and thus the via 212 below the necking point 220 is filled with the metal fill material 402 without forming any voids or seams within the metal fill material 402.

[0064] The selective deposition process in block 540 is similar or identical to the selective deposition process in block 320.

[0065] In block 550, a liner deposition process is performed to form a liner layer 218 on exposed inner surfaces of the via 212, as shown in Figure 6D The liner deposition process in block 550 is similar or identical to the liner deposition process in block 330.

[0066] ​​​In block 560, a metal fill process is performed to fill the via 212 with a metal fill material 402, such as tungsten (W), to form an interconnect 208, as shown in Figure 6E The metal fill process is similar or identical to the metal fill process in block 340.

[0067] Figure 7 A process flow diagram of a method 700 of filling a via of a landing pad structure in a semiconductor structure, such as the semiconductor structure 200 shown in Figure 2 The same reference numbers are used for substantially similar components as the first and second embodiments, and the description of the repeated components can be omitted. Figure 8A 、 Figure 8B 、 Figure 8C and Figure 8D are cross-sectional views of the semiconductor structure 200 corresponding to various states of the method 700. It is understood that Figure 8A 、 Figure 8B 、 Figure 8C and Figure 8D are only partial schematic views of the semiconductor structure 200, and the semiconductor structure 200 can contain any number of transistor portions and additional materials having aspects as shown in the figures. It is also noted that although the methods shown in Figure 7 are described in sequence, other process sequences containing one or more operations that have been omitted and / or added, and / or have been rearranged in another desired order, fall within the scope of embodiments of the disclosure provided herein.

[0068] The method 700 begins in block 710, where a liner deposition process is performed to form a liner layer 602 on the exposed inner surfaces of the via 212, as shown in Figure 6A The liner deposition process in block 710 is the same as the liner deposition process in block 510.

[0069] In block 720, a liner pullback process is performed to remove the liner layer 602 above the necking point 220, as shown in Figure 6B The liner pullback process in block 720 is the same as the liner pullback process in block 520.

[0070] In block 730, a fluorine-free tungsten (FFW) growth process is performed to selectively form a metal cap layer 802 on the exposed surfaces of the liner layer 602, as shown in Figure 8A The metal cap layer 802 can be formed of tungsten having a thickness of between about and about (e.g., about formed of tungsten (W) having a thickness of 10-20 A, and used as a nucleation layer on which a metal fill material 402 (such as tungsten (W)) is grown in a subsequent selective deposition process.

[0071] The FFW growth process can include a chemical vapor deposition (CVD) process or atomic layer deposition (ALD) in which the surface of the liner layer 602 is soaked in a precursor containing tungsten chloride (WCl6) gas provided in a pulsed flow in a processing chamber (such as the processing chamber 122) shown. Figure 1

[0072] In block 740, an optional pre-clean process is performed to restore the inner surface of the via 212 (e.g., the exposed surface of the second dielectric layer 214 within the via 212) that was damaged in the liner pullback process in block 720. The pre-clean process in block 740 is similar or identical to the pre-clean process in block 310.

[0073] In block 750, a selective deposition process is performed to partially fill the via 212 with a metal fill material 402 (such as tungsten (W)) from the exposed surface of the metal cap layer 802 at the bottom of the via 212 below the necking point 220, as shown. Figure 8B

[0074] In the selective deposition process, the metal fill material 402 is selectively grown on the exposed surface of the metal cap layer 802 without on the sidewalls of the via 212 (e.g., silicon nitride (Si3N4) or silicon oxide (SiO2)), and thus the via 212 below the necking point 220 is filled with the metal fill material 402 without forming any voids or seams within the metal fill material 402.

[0075] The selective deposition process in block 750 is similar or identical to the selective deposition process in block 320.

[0076] In block 760, a liner deposition process is performed to form the liner layer 218 on the exposed inner surface of the via 212, as shown. The liner deposition process in block 760 is similar or identical to the liner deposition process in block 330. Figure 8C

[0077] In block 770, a metal fill process is performed to fill the via 212 with a metal fill material 402 (e.g., tungsten (W)) to form the interconnect 208, as shown. The metal fill process is similar or identical to the metal fill process in block 340. Figure 8D

[0078] ​​​​Embodiments described herein provide a system and method for filling high aspect ratio vias with a necking point with tungsten (W) without forming voids or seams. The method includes selective deposition of tungsten (W) to fill the via from a bottom surface of the via (e.g., tungsten (W), titanium nitride (TiN)) below the necking point, and a metal fill of tungsten (W) to fill the remainder of the via. In the selective deposition, the via is filled with tungsten (W) from the bottom surface of the via in a bottom-up manner without forming any voids or seams within the metal fill material.

[0079] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments can be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A method of filling a via having a necking point, the method comprising: performing a pre-clean process to remove residue from an exposed surface of a metal layer at a bottom of a via and to restore an inner surface of the via, wherein the via is formed within a dielectric layer and has a necking point protruding within the via; performing a selective deposition process to partially fill the via with a metal fill material from the exposed surface of the metal layer below the necking point; performing a liner deposition process to form a liner layer on an exposed inner surface of the via; and performing a metal fill process to fill the via with the metal fill material.

2. The method of claim 1, wherein: the via has a width between 160 nm and 240 nm and a depth between 5 pm and 20 pm, and the necking point protrudes within the via by between 100 nm and 120 nm at a height between 800 nm and 1.2 pm from the bottom of the via.

3. The method of claim 1, wherein: the metal fill material comprises tungsten (W) or molybdenum (Mo), the liner layer comprises titanium nitride (TiN), and 4. The method of claim 1, wherein the pre-clean process comprises a chemical soak process in which the exposed surface of the metal layer is soaked in a precursor comprising tungsten fluoride (WF6) or hydrogen (H2) provided in a processing chamber. The dielectric layer includes silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), hafnium-containing materials, zirconium-containing materials, aluminum-containing materials, lanthanum-containing materials, or combinations thereof.

5. The method of claim 1, wherein the pre-clean process comprises an inductively coupled plasma (ICP) process that uses a plasma formed from a process gas comprising a hydrogen (H2)-containing gas.

6. The method of claim 1, wherein the pre-clean process comprises a plasma treatment process that uses a plasma formed from a process gas comprising an oxygen (O2)-containing gas.

7. The method of claim 1, wherein the selective deposition process comprises a chemical vapor deposition (CVD) process using a tungsten (W)-containing precursor and a hydrogen (H2)-containing carrier gas at a flow rate ratio of the tungsten (W)-containing precursor to the hydrogen (H2)-containing carrier gas between 0.001 and 0.

007.

8. The method of claim 1, wherein the metal fill process comprises a chemical vapor deposition (CVD) process using a tungsten (W)-containing precursor, a hydrogen (H2)-containing carrier gas, and a nitrogen-containing gas.

9. A method of filling a via having a necking point, the method comprising: performing a liner deposition process to form a liner layer on an exposed inner surface of a via, wherein the via is formed within a dielectric layer and has a necking point protruding within the via; performing a liner pullback process to remove the liner layer above the necking point; performing a selective deposition process to partially fill the via with a metal fill material from an exposed surface of the liner layer below the necking point; and performing a metal fill process to fill the via with the metal fill material.

10. The method of claim 9, wherein the metal fill material comprises tungsten (W) or molybdenum (Mo), ​ ​ the liner layer includes titanium nitride (TiN), and The dielectric layer includes silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), hafnium-containing materials, zirconium-containing materials, aluminum-containing materials, lanthanum-containing materials, or combinations thereof.

11. The method of claim 9, further comprising: performing a pre-cleaning process to restore an inner surface of the via prior to the selective deposition process.

12. The method of claim 11, wherein the pre-cleaning process includes a plasma treatment process that uses a plasma formed from a process gas that includes an oxygen (O2) containing gas.

13. The method of claim 9, wherein the selective deposition process includes a chemical vapor deposition (CVD) process that uses a tungsten (W) containing precursor and a hydrogen (H2) containing carrier gas at a flow rate ratio of the tungsten (W) containing precursor to the hydrogen (H2) containing carrier gas that is between 0.001 and about 0.

007.

14. The method of claim 9, wherein the metal fill process includes a chemical vapor deposition (CVD) process that uses a tungsten (W) containing precursor, a hydrogen (H2) containing carrier gas, and a nitrogen containing gas.

15. A method of filling a via having a necking point, the method comprising: performing a liner deposition process to form a liner layer on an exposed inner surface of a via, wherein the via is formed within a dielectric layer and has a necking point that protrudes within the via; performing a liner pullback process to remove the liner layer over the necking point; performing a fluorine free tungsten (FFW) growth process to selectively form a metal cap layer on an exposed surface of the liner layer; performing a selective deposition process to partially fill the via with a metal fill material from an exposed surface of the metal cap layer below the necking point; and performing a metal fill process to fill the via with the metal fill material.

16. The method of claim 15, wherein the metal fill material includes tungsten (W) or molybdenum (Mo), the liner layer includes titanium nitride (TiN), and The dielectric layer includes silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), hafnium-containing materials, zirconium-containing materials, aluminum-containing materials, lanthanum-containing materials, or combinations thereof.

17. The method of claim 15, further comprising: performing a pre-cleaning process to restore an inner surface of the via prior to the selective deposition process.

18. The method of claim 17, wherein the pre-cleaning process includes a plasma treatment process that uses a plasma formed from a process gas that includes an oxygen (O2) containing gas.

19. The method of claim 15, wherein the selective deposition process includes a chemical vapor deposition (CVD) process that uses a tungsten (W) containing precursor and a hydrogen (H2) containing carrier gas at a flow rate ratio of the tungsten (W) containing precursor to the hydrogen (H2) containing carrier gas that is between 0.001 and 0.

007.

20. The method of claim 15, wherein the metal fill process includes a chemical vapor deposition (CVD) process that uses a tungsten (W) containing precursor, a hydrogen (H2) containing carrier gas, and a nitrogen containing gas.

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