Failure oscillation interval determination method, temperature control method and related equipment

Abstract

The invention provides a failure oscillation interval determination method, a temperature control method and related equipment, and the method comprises the steps: setting the width of a failure oscillation interval as the ith width at an ith test stage, obtaining the current chip temperature of a processor according to a preset period interval, and executing an error integral temperature control strategy to obtain a current frequency point corresponding to the current chip temperature, taking the current frequency point as an operation frequency point of the processor in the current period; monitoring whether the current chip temperature exceeds the target temperature or not in the ith test stage; if not, determining the target width of the failure oscillation interval according to the ith width, and further determining the lower limit of the failure oscillation interval. By formulating the failure oscillation interval when the error integral temperature control strategy is executed, when the chip temperature is in the failure oscillation interval, the updating of the integral error is stopped, so that the adjustment amplitude of the temperature is changed, the chip temperature is prevented from oscillating up and down near the target temperature, or the oscillation amplitude is reduced.

Description

Technical Field

[0001] This invention relates to the field of chip temperature control, and more specifically, to a method for determining the failure oscillation range, a temperature control method, and related equipment. Background Technology

[0002] With the widespread adoption of smart technology and the internet, electronic devices such as mobile phones and computers are increasingly used in our lives, bringing great convenience. Among these devices, the processor is a crucial component, and its operating state directly affects the entire device. When a processor operates in a high-performance, high-power mode, it often overheats, potentially causing damage. Therefore, when the processor temperature is too high, it's necessary to reduce power consumption to cool it down, which inevitably leads to a decrease in processor performance.

[0003] To address this, an error integral temperature control strategy was introduced to regulate the temperature of the chip containing the processor. However, when executing this strategy, the temperature fluctuates around the target temperature, which can lead to situations where the chip temperature exceeds the target temperature, thus affecting the chip's safety. Summary of the Invention

[0004] The purpose of this invention is to provide a method for determining the failure oscillation range, a temperature control method, and related equipment to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a method for determining a failure oscillation range, the method comprising: In the i-th test phase, the width of the failure oscillation interval is set to the i-th width. The current chip temperature of the processor is obtained according to the preset period interval. If the current chip temperature reaches the effective temperature starting point, the error integral temperature control strategy is executed to obtain the current frequency point corresponding to the current chip temperature, and the current frequency point is used as the operating frequency point of the processor in the current period. Wherein, the effective temperature start point is the temperature start point at which the error integral temperature control strategy takes effect under the current ambient temperature. The effective temperature start point does not exceed the lower limit of the failure oscillation range. The upper limit of the failure oscillation range is the target temperature. The target temperature is the steady-state temperature corresponding to the target frequency point under the current ambient temperature. The target frequency point is the highest frequency point among the frequency points whose steady-state temperature is lower than the maximum temperature under the current ambient temperature. i is greater than or equal to 1, and the first width is 0, and the i-th width is less than the (i+1)-th width. Monitor whether the current chip temperature exceeds the target temperature during the i-th test phase; If the current chip temperature exceeds the target temperature, then set i = i + 1 and repeat the i-th test. If the current chip temperature does not exceed the target temperature, the i-th width is used to determine the target width of the failure oscillation range, and then the lower limit of the failure oscillation range is determined.

[0006] Secondly, embodiments of the present invention provide a temperature control method, the method comprising: When the current chip temperature is lower than the effective temperature start point, the processor maintains its highest supported frequency point. The effective temperature start point is the temperature start point at which the error integral temperature control strategy takes effect under the current ambient temperature. The effective temperature start point is lower than the target temperature. The target temperature is the steady-state temperature corresponding to the target frequency point under the current ambient temperature. The target frequency point is the highest frequency point among the frequency points whose corresponding steady-state temperature is lower than the maximum temperature under the current ambient temperature. When the current chip temperature reaches the effective temperature starting point, an error integral temperature control strategy is executed based on the failure oscillation target range to obtain the current frequency point corresponding to the current chip temperature; Wherein, the failure oscillation target range is the failure oscillation range obtained based on the above-mentioned failure oscillation range determination method; The current frequency is used as the operating frequency of the processor in the current cycle.

[0007] Thirdly, embodiments of the present invention provide a device for determining a failure oscillation range, the device comprising: The first processing unit is used to set the width of the failure oscillation interval to the i-th width in the i-th test phase, obtain the current chip temperature of the processor according to a preset period interval, and if the current chip temperature reaches the effective temperature starting point, execute the error integral temperature control strategy to obtain the current frequency point corresponding to the current chip temperature, and use the current frequency point as the operating frequency point of the processor in the current period. Wherein, the effective temperature start point is the temperature start point at which the error integral temperature control strategy takes effect under the current ambient temperature. The effective temperature start point does not exceed the lower limit of the failure oscillation range. The upper limit of the failure oscillation range is the target temperature. The target temperature is the steady-state temperature corresponding to the target frequency point under the current ambient temperature. The target frequency point is the highest frequency point among the frequency points whose steady-state temperature is lower than the maximum temperature under the current ambient temperature. i is greater than or equal to 1, and the first width is 0, and the i-th width is less than the (i+1)-th width. The first processing unit is also used to monitor whether the current chip temperature exceeds the target temperature in the i-th test phase; if the current chip temperature exceeds the target temperature, then set i=i+1 and repeat the i-th test. The second processing unit is used to determine the target width of the failure oscillation range by determining the i-th width if the current chip temperature does not exceed the target temperature, and then determine the lower limit of the failure oscillation range.

[0008] Fourthly, embodiments of the present invention provide a storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method.

[0009] Fifthly, embodiments of the present invention provide an electronic device, the electronic device comprising: a processor and a memory, the memory being used to store one or more programs; when the one or more programs are executed by the processor, the above-described method is implemented.

[0010] Compared to existing technologies, the failure oscillation range determination method, temperature control method, and related equipment provided in this invention, in the i-th test phase, set the width of the failure oscillation range to the i-th width, acquire the current chip temperature of the processor at preset periodic intervals, and if the current chip temperature reaches the effective temperature starting point, execute an error integral temperature control strategy to obtain the current frequency point corresponding to the current chip temperature, and use the current frequency point as the processor's operating frequency point in the current period; monitor whether the current chip temperature exceeds the target temperature in the i-th test phase; if the current chip temperature does not exceed the target temperature, then determine the target width of the failure oscillation range with the i-th width, and thus determine the lower limit of the failure oscillation range. By defining the failure oscillation range when executing the error integral temperature control strategy, updates to the integral error are stopped when the chip temperature is within the failure oscillation range, thereby changing the temperature adjustment range and preventing the chip temperature from oscillating around the target temperature, or reducing the oscillation amplitude.

[0011] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0014] Figure 2 This is a flowchart illustrating the method for determining the failure oscillation range provided in an embodiment of the present invention.

[0015] Figure 3 This is a schematic flowchart of the temperature control method provided in an embodiment of the present invention.

[0016] Figure 4 This is a schematic diagram of a unit of the failure oscillation range determination device provided in an embodiment of the present invention.

[0017] In the diagram: 10-Processor; 11-Memory; 12-Bus; 13-Communication interface; 601-First processing unit; 602-Second processing unit. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0020] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0022] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0023] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0024] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] This invention provides an electronic device, which may be a mobile phone, tablet computer, laptop computer, or desktop computer, etc. Please refer to... Figure 1 This is a schematic diagram of the structure of an electronic device. The electronic device includes a processor 10, a memory 11, and a bus 12. The processor 10 and the memory 11 are connected via the bus 12. The processor 10 is used to execute executable modules, such as computer programs, stored in the memory 11.

[0026] Processor 10 can be an integrated circuit chip with signal processing capabilities. During implementation, the steps of the failure oscillation range determination method and the temperature control method can be completed through integrated logic circuits in the hardware or software instructions within processor 10. Processor 10 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0027] The memory 11 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage.

[0028] Bus 12 can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. Figure 1 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus 12 or one type of bus 12.

[0029] The memory 11 is used to store programs, such as programs corresponding to the failure oscillation range determination device and the temperature control device. The failure oscillation range determination device and the temperature control device include at least one software function module that can be stored in the memory 11 in the form of software or firmware or embedded in the operating system (OS) of the electronic device. After receiving the execution instruction, the processor 10 executes the program to implement the failure oscillation range determination method and the temperature control method.

[0030] The electronic device provided in this embodiment of the invention may further include a communication interface 13. The communication interface 13 is connected to the processor 10 via a bus.

[0031] It should be understood that, Figure 1 The structure shown is only a partial schematic diagram of the electronic device; the electronic device may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 1 The components shown can be implemented using hardware, software, or a combination thereof.

[0032] The method for determining the failure oscillation range provided in this embodiment of the invention can be applied to, but is not limited to, [various applications]. Figure 1 For the specific process of the electronic devices shown, please refer to [link / reference]. Figure 2 The methods for determining the failure oscillation range include S10, S20, S30, and S40, which are explained in detail below.

[0033] S10, in the i-th test phase, the width of the failure oscillation interval is set to the i-th width, and the current chip temperature of the processor is obtained according to the preset period interval. If the current chip temperature reaches the effective temperature starting point, the error integral temperature control strategy is executed to obtain the current frequency point corresponding to the current chip temperature, and the current frequency point is used as the operating frequency point of the processor in the current period.

[0034] The effective temperature start point is the temperature start point at which the error integral temperature control strategy takes effect under the current ambient temperature (different ambient temperatures correspond to different effective temperature start points). The effective temperature start point does not exceed the lower limit of the failure oscillation range. The upper limit of the failure oscillation range is the target temperature. The target temperature is the steady-state temperature corresponding to the target frequency point under the current ambient temperature. The target frequency point is the highest frequency point among the frequency points whose corresponding steady-state temperature is lower than the maximum temperature under the current ambient temperature. i is greater than or equal to 1, and the first width is 0. The i-th width is less than the (i+1)-th width. The (i+1)-th width = the preset width difference. The preset width difference can be 1°.

[0035] When the current chip temperature reaches the effective starting temperature, the error integral temperature control strategy is executed. It does not wait until the temperature reaches the target temperature to start the temperature control strategy. This avoids the processor's temperature from exceeding the target temperature significantly due to the lag in temperature regulation caused by the late intervention of temperature control. It ensures that the processor can maintain high power consumption while the temperature is within a safe range, thus ensuring the processor's high performance.

[0036] S20: Monitor whether the current chip temperature exceeds the target temperature during the i-th test phase. If the current chip temperature exceeds the target temperature, proceed to S30; otherwise, proceed to S40.

[0037] S30, let i=i+1.

[0038] After S30, the i-th width can be determined, and the i-th test can be repeated. That is, the width of the failure oscillation interval is set to the i-th width during the i-th test phase. The current chip temperature of the processor is obtained according to the preset period interval. If the current chip temperature reaches the effective temperature starting point, the error integral temperature control strategy is executed to obtain the current frequency point corresponding to the current chip temperature, and the current frequency point is used as the operating frequency point of the processor in the current cycle.

[0039] S40, determine the target width of the failure oscillation interval by determining the i-th width, and then determine the lower limit of the failure oscillation interval.

[0040] In this embodiment of the invention, by defining the failure oscillation range when executing the error integral temperature control strategy, the update of the integral error is stopped when the chip temperature is in the failure oscillation range, thereby changing the temperature adjustment range and avoiding the chip temperature from oscillating around the target temperature, or reducing the oscillation range.

[0041] In one alternative implementation, the failure oscillation range determination method further includes: during the i-th test phase, if the current chip temperature is lower than the effective temperature starting point, the processor maintains its highest supported frequency.

[0042] Based on the preceding text, regarding the content in S10, this embodiment of the invention also provides an optional implementation method, please refer to the following. Executing an error integral temperature control strategy to obtain the current frequency point corresponding to the current chip temperature includes: S101, S102, S103, S104, and S106, which are specifically described below.

[0043] S101 determines the current temperature difference and scaling factor based on the target temperature and the current chip temperature.

[0044] Current temperature difference = target temperature - current chip temperature, proportional term factor = (target temperature - current chip temperature) × proportional parameter.

[0045] If the proportional term parameter is 200, the target temperature is 85 degrees Celsius, and the current temperature is 82 degrees Celsius, then the proportional term factor is (85-82)*200=600. Therefore, the calculated proportional term matching power consumption is (85-82)*200=600mW.

[0046] S102, determine whether the current chip temperature is within the failure oscillation range. If the current chip temperature is within the failure oscillation range, proceed to S103; if the current chip temperature is not within the failure oscillation range, proceed to S104.

[0047] S103, set the current temperature difference to 0.

[0048] S104: Accumulate the historical integration error based on the current temperature difference to obtain the current integration error.

[0049] Among them, the historical integral error is the integral error obtained from the last temperature measurement. The first integral error after the current chip temperature reaches the current effective temperature starting point is the current temperature difference at this time, which is the temperature difference between the target temperature and the current chip temperature.

[0050] Current integration error = historical integration error + current temperature difference. The historical integration error is 0 when the current chip temperature reaches the current effective temperature threshold.

[0051] S104 will be executed after S103.

[0052] S106, determine the current frequency point based on the current integral error, the proportional term factor, and the target power consumption; where the target power consumption is the matching power consumption corresponding to the target frequency point.

[0053] In one optional implementation, after accumulating the historical integral error based on the current temperature difference to obtain the current integral error, the error integral temperature control strategy is executed to obtain the current frequency point corresponding to the current chip temperature, which further includes: S105, as follows.

[0054] S105, determine whether the current integration error exceeds the integration error range. If it does, adjust the current integration error to bring it within the integration error range. If it does not exceed the range, the current integration error does not need to be adjusted.

[0055] When the current integral error is less than the lower boundary of the integral error range, the lower boundary of the integral error range is taken as the current integral error; when the current integral error is greater than the upper boundary of the integral error range, the upper boundary of the integral error range is taken as the current integral error, so that it remains within the integral error range. If the current integral error is not adjusted, excessive integral accumulation may occur, leading to situations where the system temperature and power consumption limits are too low or the temperature instantaneously exceeds the control limits. In this embodiment of the invention, integral error range control is introduced to prevent excessive integral accumulation from causing control overshoot, reduce temperature overshoot, and lower safety risks.

[0056] Based on the foregoing, regarding the content of S106, this embodiment of the invention also provides an optional implementation method. S106 determines the current frequency point based on the current integral error, the proportional term factor, and the target power consumption, including: S106-1, S106-2, and S106-3, which are described in detail below.

[0057] S106-1, Obtain the error matching power consumption corresponding to the current integration error.

[0058] S106-2, obtain the proportional term matching power consumption corresponding to the proportional term factor.

[0059] S106-3 determines the current frequency point based on the target power consumption, error matching power consumption, and proportional term matching power consumption.

[0060] Optionally, the target power consumption, error matching power consumption, and proportional term matching power consumption are obtained as the total power consumption. Then, the system static power consumption is subtracted from the total power consumption to obtain the dynamic power consumption. The dynamic power consumption is compared with the corresponding power consumption of each supported frequency point, and the frequency point with the largest power consumption less than the dynamic power consumption is found and used as the current frequency point.

[0061] The temperature control method provided in this embodiment of the invention can be applied to, but is not limited to, [various applications]. Figure 1 For the specific process of the electronic devices shown, please refer to [link / reference]. Figure 3 The temperature control methods include S51, S52 and S53, which are described in detail below.

[0062] S51, when the current chip temperature is lower than the effective temperature start point, the processor maintains its highest supported frequency point. Here, the effective temperature start point is the temperature start point at which the error integral temperature control strategy takes effect under the current ambient temperature. The effective temperature start point is lower than the target temperature. The target temperature is the steady-state temperature corresponding to the target frequency point under the current ambient temperature. The target frequency point is the highest frequency point among the frequency points whose corresponding steady-state temperature is lower than the maximum temperature under the current ambient temperature.

[0063] It operates at the highest frequency point directly during the low-temperature stage, without performance suppression during the temperature rise stage, maintaining the best power consumption and optimal performance.

[0064] S52, when the current chip temperature reaches the effective temperature starting point, executes an error integral temperature control strategy based on the failure oscillation target range to obtain the current frequency point corresponding to the current chip temperature.

[0065] Among them, the failure oscillation target range is the failure oscillation range obtained based on the failure oscillation range determination method described above.

[0066] S53 uses the current frequency as the processor's operating frequency in the current cycle.

[0067] Optionally, in S52, when the current chip temperature reaches the effective temperature starting point, an error integral temperature control strategy is executed based on the failure oscillation target range to obtain the current frequency point corresponding to the current chip temperature, including: S521 to S526, which are described in detail below.

[0068] S521 determines the current temperature difference and scaling factor based on the target temperature and the current chip temperature.

[0069] Current temperature difference = target temperature - current chip temperature, proportional term factor = (target temperature - current chip temperature) × proportional parameter.

[0070] S522, determine whether the current chip temperature is within the failure oscillation target range. If the current chip temperature is within the failure oscillation target range, execute S523; if the current chip temperature is not within the failure oscillation target range, execute S524.

[0071] S523 sets the current temperature difference to 0.

[0072] S524, accumulate the historical integration error based on the current temperature difference to obtain the current integration error.

[0073] Among them, the historical integral error is the integral error obtained from the last temperature measurement. The first integral error after the current chip temperature reaches the current effective temperature starting point is the current temperature difference at this time, which is the temperature difference between the target temperature and the current chip temperature.

[0074] Current integration error = historical integration error + current temperature difference. The historical integration error is 0 when the current chip temperature reaches the current effective temperature threshold.

[0075] S524 will also be executed after S523.

[0076] S525: Determine whether the current integration error exceeds the integration error range. If it does, adjust the current integration error to bring it within the integration error range. If it does not exceed the range, the current integration error does not need to be adjusted.

[0077] S526, determine the current frequency point based on the current integral error, the proportional term factor, and the target power consumption; where the target power consumption is the matching power consumption corresponding to the target frequency point.

[0078] Please see Figure 4 , Figure 4 The present invention provides a failure oscillation range determination device and a temperature control device, which are optionally applied to the electronic equipment described above.

[0079] The failure oscillation range determination device includes: a first processing unit 601 and a second processing unit 602.

[0080] The first processing unit 601 is used to set the width of the failure oscillation range to the i-th width in the i-th test phase, obtain the current chip temperature of the processor according to the preset period interval, and if the current chip temperature reaches the effective temperature starting point, execute the error integral temperature control strategy to obtain the current frequency point corresponding to the current chip temperature, and use the current frequency point as the operating frequency point of the processor in the current period.

[0081] Wherein, the effective temperature start point is the temperature start point at which the error integral temperature control strategy takes effect under the current ambient temperature. The effective temperature start point does not exceed the lower limit of the failure oscillation range. The upper limit of the failure oscillation range is the target temperature. The target temperature is the steady-state temperature corresponding to the target frequency point under the current ambient temperature. The target frequency point is the highest frequency point among the frequency points whose corresponding steady-state temperature is lower than the maximum temperature under the current ambient temperature. i is greater than or equal to 1, and the first width is 0, and the i-th width is less than the (i+1)-th width.

[0082] The first processing unit 601 is also used to monitor whether the current chip temperature exceeds the target temperature in the i-th test phase; if the current chip temperature exceeds the target temperature, then set i=i+1 and repeat the i-th test.

[0083] The second processing unit 602 is used to determine the target width of the failure oscillation range by determining the i-th width if the current chip temperature does not exceed the target temperature, and then determine the lower limit of the failure oscillation range.

[0084] Optionally, the first processing unit 601 may perform other steps in the above method embodiments.

[0085] It should be noted that the failure oscillation range determination device provided in this embodiment can execute the method flow shown in the above method flow embodiment to achieve the corresponding technical effect. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments.

[0086] This invention also provides a storage medium storing computer instructions and programs. When read and executed, these instructions and programs perform the failure oscillation range determination method and temperature control method described above. The storage medium may include memory, flash memory, registers, or a combination thereof.

[0087] The following provides an electronic device, which may be a mobile phone, tablet computer, laptop computer, or desktop computer, etc. Figure 1 As shown, the above-described failure oscillation range determination method and temperature control method can be implemented. Specifically, the electronic device includes: a processor 10, a memory 11, and a bus 12. The processor 10 may be a CPU. The memory 11 is used to store one or more programs, which, when executed by the processor 10, execute the failure oscillation range determination method and temperature control method of the above embodiments.

[0088] In summary, the failure oscillation range determination method, temperature control method, and related equipment provided by this invention, in the i-th test phase, set the width of the failure oscillation range to the i-th width, acquire the current chip temperature of the processor at preset periodic intervals, and if the current chip temperature reaches the effective temperature starting point, execute an error integral temperature control strategy to obtain the current frequency point corresponding to the current chip temperature, and use the current frequency point as the processor's operating frequency point in the current period; monitor whether the current chip temperature exceeds the target temperature in the i-th test phase; if the current chip temperature does not exceed the target temperature, then determine the target width of the failure oscillation range with the i-th width, thereby determining the lower limit of the failure oscillation range. By defining the failure oscillation range when executing the error integral temperature control strategy, updates to the integral error are stopped when the chip temperature is within the failure oscillation range, thereby changing the temperature adjustment range and preventing the chip temperature from oscillating around the target temperature, or reducing the oscillation amplitude.

[0089] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0090] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for determining the failure oscillation range, characterized in that, The method includes: In the i-th test phase, the width of the failure oscillation interval is set to the i-th width. The current chip temperature of the processor is obtained according to the preset period interval. If the current chip temperature reaches the effective temperature starting point, the error integral temperature control strategy is executed to obtain the current frequency point corresponding to the current chip temperature, and the current frequency point is used as the operating frequency point of the processor in the current period. Wherein, the effective temperature start point is the temperature start point at which the error integral temperature control strategy takes effect under the current ambient temperature. The effective temperature start point does not exceed the lower limit of the failure oscillation range. The upper limit of the failure oscillation range is the target temperature. The target temperature is the steady-state temperature corresponding to the target frequency point under the current ambient temperature. The target frequency point is the highest frequency point among the frequency points whose steady-state temperature is lower than the maximum temperature under the current ambient temperature. i is greater than or equal to 1, and the first width is 0, and the i-th width is less than the (i+1)-th width. Monitor whether the current chip temperature exceeds the target temperature during the i-th test phase; If the current chip temperature exceeds the target temperature, then set i = i + 1 and repeat the i-th test. If the current chip temperature does not exceed the target temperature, the i-th width is used to determine the target width of the failure oscillation range, and then the lower limit of the failure oscillation range is determined.

2. The method for determining the failure oscillation range as described in claim 1, characterized in that, The method includes: During the i-th test phase, if the current chip temperature is lower than the effective temperature starting point, the processor will maintain its highest supported frequency.

3. The method for determining the failure oscillation range as described in claim 1, characterized in that, The execution error integral temperature control strategy, to obtain the current frequency point corresponding to the current chip temperature, includes: Determine the current temperature difference and scaling factor based on the target temperature and the current chip temperature; Determine whether the current chip temperature is within the failure oscillation range; If the current chip temperature is in the failure oscillation range, set the current temperature difference to 0; If the current chip temperature is not in the failure oscillation range, the historical integral error is accumulated based on the current temperature difference to obtain the current integral error; The current frequency point is determined based on the current integral error, the proportional term factor, and the target power consumption; wherein, the target power consumption is the matching power consumption corresponding to the target frequency point; The current frequency is used as the operating frequency of the processor in the current cycle.

4. The method for determining the failure oscillation range as described in claim 3, characterized in that, After accumulating the historical integral error based on the current temperature difference to obtain the current integral error, the step of executing the error integral temperature control strategy to obtain the current frequency point corresponding to the current chip temperature further includes: Determine whether the current integration error exceeds the integration error range. If it does, adjust the current integration error to bring it within the integration error range. If it does not exceed the range, the current integration error does not need to be adjusted.

5. The method for determining the failure oscillation range as described in claim 3, characterized in that, Determining the current frequency point based on the current integral error, the scaling factor, and the target power consumption includes: Obtain the error matching power consumption corresponding to the current integration error; Obtain the proportional term matching power consumption corresponding to the proportional term factor; The current frequency point is determined based on the target power consumption, the error matching power consumption, and the proportional term matching power consumption.

6. A temperature control method, characterized in that, The method includes: When the current chip temperature is lower than the effective temperature start point, the processor maintains its highest supported frequency point. The effective temperature start point is the temperature start point at which the error integral temperature control strategy takes effect under the current ambient temperature. The effective temperature start point is lower than the target temperature. The target temperature is the steady-state temperature corresponding to the target frequency point under the current ambient temperature. The target frequency point is the highest frequency point among the frequency points whose corresponding steady-state temperature is lower than the maximum temperature under the current ambient temperature. When the current chip temperature reaches the effective temperature starting point, an error integral temperature control strategy is executed based on the failure oscillation target range to obtain the current frequency point corresponding to the current chip temperature; Wherein, the failure oscillation target range is the failure oscillation range obtained based on the failure oscillation range determination method according to any one of claims 1-5; The current frequency is used as the operating frequency of the processor in the current cycle.

7. A device for determining the failure oscillation range, characterized in that, The device includes: The first processing unit is used to set the width of the failure oscillation interval to the i-th width in the i-th test phase, obtain the current chip temperature of the processor according to a preset period interval, and if the current chip temperature reaches the effective temperature starting point, execute the error integral temperature control strategy to obtain the current frequency point corresponding to the current chip temperature, and use the current frequency point as the operating frequency point of the processor in the current period. Wherein, the effective temperature start point is the temperature start point at which the error integral temperature control strategy takes effect under the current ambient temperature. The effective temperature start point does not exceed the lower limit of the failure oscillation range. The upper limit of the failure oscillation range is the target temperature. The target temperature is the steady-state temperature corresponding to the target frequency point under the current ambient temperature. The target frequency point is the highest frequency point among the frequency points whose steady-state temperature is lower than the maximum temperature under the current ambient temperature. i is greater than or equal to 1, and the first width is 0, and the i-th width is less than the (i+1)-th width. The first processing unit is also used to monitor whether the current chip temperature exceeds the target temperature in the i-th test phase; if the current chip temperature exceeds the target temperature, then set i=i+1 and repeat the i-th test. The second processing unit is used to determine the target width of the failure oscillation range by determining the i-th width if the current chip temperature does not exceed the target temperature, and then determine the lower limit of the failure oscillation range.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-6.

9. An electronic device, characterized in that, include: Processor and memory, the memory being used to store one or more programs; When the one or more programs are executed by the processor, the method as described in any one of claims 1-6 is implemented.

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