Heuristic layout method and system for wafer-level chip architecture design

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a wafer-level chip architecture design-oriented heuristic layout method and system, and the method comprises the steps: core particle combination exploration: taking an exchange chip as a center, and generating a plurality of core particle combinations according to the core particle type, the interface type and the communication protocol consistency; a kernel in-group layout algorithm: performing multi-objective optimization layout on each core particle combination based on a genetic algorithm, wherein optimization objectives comprise area utilization rate, total wiring length and corner number; and wafer overall performance evaluation: copying and expanding the core group layout to the whole wafer, calculating a comprehensive performance index, and outputting a plurality of wafer layouts with the highest comprehensive performance index. According to the method, the wafer-level chip layout architecture with the smallest area, the shortest line length, the lowest corner number, the highest computing power and the lowest cost can be efficiently explored in limited time, the chip design efficiency is improved, and the design cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a heuristic layout method and system for wafer-level chip architecture design. Background Technology

[0002] As chip manufacturing processes approach their physical limits and Moore's Law becomes unsustainable, wafer-level chips, with their higher integration density, have emerged as a potential new direction for development. The high integration density of wafer-level chips leads to an exponential increase in the number of chips, making the layout of these numerous chips a significant challenge.

[0003] Existing traditional placement algorithms, such as simulated annealing and knapsack algorithms, typically start placement from the bottom left corner, optimizing only for the minimum area and neglecting the interconnections between particles. This leads to unreasonable placement results that differ significantly from manual placement. Furthermore, they cannot simultaneously optimize multiple objectives such as line length and routing rationality. Summary of the Invention

[0004] To address the NP-hard problem of combination and layout caused by the large number of chips, this invention proposes a heuristic layout method and system for wafer-level chip architecture design. This method can efficiently explore the optimal architecture layout scheme that satisfies area and wiring constraints while taking into account the weights of computing power and cost within a limited time.

[0005] To achieve the above objectives, the technical solution adopted is:

[0006] This invention provides a heuristic layout method for wafer-level chip architecture design, comprising the following steps:

[0007] Chip assembly exploration: Centered on the switching chip, multiple chip assemblies are generated based on chip type, interface type, and communication protocol consistency.

[0008] Core group layout algorithm: Based on genetic algorithm, multi-objective optimization layout is performed on each core combination. The optimization objectives include area utilization, total wiring length and number of corners;

[0009] Overall wafer performance evaluation: The core layout is replicated and extended to the entire wafer, the overall performance index is calculated, and the wafer layouts with the highest overall performance index are output.

[0010] According to the heuristic layout method for wafer-level chip architecture design of the present invention, the chip assembly exploration further includes:

[0011] An abstract model is created for each chip, recording its size, type, number of interfaces, communication protocol type, interface location, computing power indicators, and cost;

[0012] Centered on the switching core, the main control core and accelerator core are selected based on their number of interfaces and communication protocol type to generate all possible core combinations.

[0013] According to the heuristic placement method for wafer-level chip architecture design of the present invention, the placement algorithm within the core group further includes:

[0014] Chromosomal gene encoding: The coordinates, rotation angle, and interface connection relationships of each corelet are encoded as genes;

[0015] Fitness calculation: The fitness value is obtained by detecting core overlap and boundary crossing, calculating the area of ​​the enclosing rectangle, obtaining the total wiring length and number of corners by A* routing, and then normalizing and weighting the sum.

[0016] Genetic operations: Through selection, crossover, and mutation, the population is iteratively optimized to output the layout scheme with the best fitness.

[0017] According to the heuristic layout method for wafer-level chip architecture design of the present invention, in the chromosome gene encoding, the gene of each individual is composed of the coordinates, rotation angle and interface connection relationship of the core, and each individual represents a complete layout scheme composed of multiple cores, wherein the rotation angle is 0°, 90°, 180° or 270°.

[0018] According to the heuristic layout method for wafer-level chip architecture design of the present invention, the fitness calculation further includes:

[0019] Detect whether there is overlap of core particles or whether the core particle coordinates exceed the maximum illumination area. If the above occurs, increase the penalty coefficient in the fitness.

[0020] Calculate the minimum bounding rectangle area for all core particles;

[0021] The shortest path length between core particles is calculated using the A* algorithm. In addition to the traditional line length optimization objective, the A* algorithm also adds the optimization objective of the number of corners.

[0022] According to the heuristic placement method for wafer-level chip architecture design of the present invention, the fitness calculation formula is further as follows:

[0023] Fitness=W_a×Area_norm+W_w×WireLength_norm+Penalty

[0024] Where W_a and W_w are the area weight and line length weight, respectively; Penalty is the penalty coefficient; Area_norm is the normalized area, obtained by dividing the area by the maximum illuminated area; WireLength_norm is the normalized line length, i.e., WireLength_norm = (Current_WL - Optimal_WL) / Current_WL, where Optimal_WL is the theoretical shortest line length estimate, Current_WL is the actual line length in the current layout scheme, and Current_WL includes corner penalties.

[0025] According to the heuristic layout method for wafer-level chip architecture design of the present invention, the selection in the genetic operation adopts a random competition method, in which several individuals are randomly selected each time to compete, and the one with the best fitness enters the next generation;

[0026] The crossover operation in the genetic operation adopts a segmented gene recombination method, traversing each parent individual and randomly pairing it with another mother individual, and performing the crossover operation with a preset probability. If the crossover is not triggered, the parent is directly copied.

[0027] In the genetic operation, each individual undergoes mutation with a preset probability; if a mutation is triggered, all its core genes are traversed to perform coordinate mutation, angle mutation, and interface mutation.

[0028] According to the heuristic layout method for wafer-level chip architecture design of the present invention, the coordinate variation is: the x or y coordinate of the chip is randomly shifted within the coordinate range of [-1, +1]; the angle variation is: the rotation angle is randomly selected from {0°, 90°, 180°, 270°}; and the interface variation is: the interface connecting to the target chip is randomly switched.

[0029] According to the heuristic layout method for wafer-level chip architecture design of the present invention, the overall wafer performance evaluation further includes:

[0030] Calculate the width and height of the minimum rectangular area of ​​a single core group, and calculate the maximum number that it can be replicated and expanded in the vertical and horizontal directions of the wafer to obtain the number of core groups;

[0031] Calculate the overall computing power and cost of a single core group based on the computing power and cost parameters of each core.

[0032] Multiply the overall computing power and cost of a single core group by the number of core groups to obtain the overall computing power and cost of the wafer.

[0033] The overall computing power and cost of the wafer are normalized and weighted to obtain the comprehensive performance index of the layout.

[0034] Furthermore, the present invention also provides a heuristic placement system for wafer-level chip architecture design, comprising:

[0035] The chip assembly exploration module is used to generate multiple chip assemblies based on the switching chip, the chip type, the interface type, and the consistency of the communication protocol.

[0036] The core group layout algorithm module is used to perform multi-objective optimization layout of each core particle combination based on a genetic algorithm. The optimization objectives include area utilization, total wiring length, and number of corners.

[0037] The overall wafer performance evaluation module is used to replicate and extend the core group layout to the entire wafer, calculate the overall performance index, and output the wafer layouts with the highest overall performance index.

[0038] The beneficial effects achieved by adopting the above technical solution are:

[0039] 1. From the perspective of layout optimization effect, this method achieves multi-objective collaborative optimization. It optimizes key layout elements such as area, line length, and number of wiring corners. Through a multi-objective optimization heuristic layout algorithm developed based on genetic algorithm, the layout results can reach a better state in these elements during the layout exploration within the core group. At the same time, considering core-particle overlap and coordinate out-of-bounds situations in fitness calculation and increasing the penalty coefficient can effectively reduce unreasonable layouts and make the layout more in line with actual needs.

[0040] 2. In terms of efficiency improvement, it effectively solves the NP-hard problem of combination and placement caused by a large number of chips. Existing traditional placement algorithms are difficult to handle the placement of a large number of chips in a limited time. However, this invention, through step-by-step chip combination exploration, core group placement, and overall wafer performance evaluation, combined with the characteristics of heuristic algorithms, can efficiently explore placement schemes in a limited time, significantly improving chip design efficiency.

[0041] 3. In terms of cost control and performance balance, it can output the optimal architecture layout scheme by comprehensively considering computing power and cost weights. By calculating, normalizing and assigning corresponding coefficients to the computing power and cost of individual core groups and the entire wafer, a comprehensive performance index is obtained, thereby selecting layouts with high computing power and reasonable cost. This helps to reduce the overall design and production costs while improving chip performance. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments of the present invention will be briefly described below. The drawings are merely illustrative of some embodiments of the present invention and are not intended to limit the scope of the present invention to all embodiments.

[0043] Figure 1This is a flowchart illustrating a heuristic layout method for wafer-level chip architecture design according to an embodiment of the present invention. Detailed Implementation

[0044] The exemplary solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art.

[0045] To address the challenge of excessive chip combination and layout possibilities during wafer-level chip architecture design, this invention provides a heuristic layout method for wafer-level chip architecture design. This method optimizes area, trace length, and the number of trace corners to output the optimal single-core group layout within a limited time. The single-core group layout is then extended to the entire wafer, and by considering both computing power and cost, the optimal wafer-level chip architecture is output. Figure 1 As shown, it specifically includes the following three steps:

[0046] Step S101, Chip Combination Exploration: Centered on the switching chip, multiple chip combinations are generated through combination exploration based on chip type, interface type, and communication protocol consistency.

[0047] (1) Abstract model each core particle, and each core particle is abstracted into an object containing the following attributes:

[0048] Dimensions (length, width); Type: switch / master / accelerator; Number of interfaces; Communication protocol types supported by the interfaces: such as PCIE, UCIE, AXI, CXL, SRIO; Location of the interface on the chip: [coordinates x, y]; Computing power index (Tops); Cost.

[0049] (2) Generate core assembly

[0050] Centered on the switching chip, chip clusters are combined according to their capabilities (maximum number of interfaces). Each chip cluster combination consists of one switching chip, a main control chip, and multiple accelerator chips; the basis for restricting whether chips can interconnect is whether the communication protocols of the chip interfaces are consistent.

[0051] ① Traverse each swap core. Once the swap core is determined, its number of interfaces determines the maximum number of cores that can be combined.

[0052] ② Based on the communication protocol type of the interface of the switching core, the cores are filtered to select the master control cores and accelerator cores that support the communication protocol. At this time, two sets are obtained: the master control core set (master control cores can be of various types, such as master control A, master control B, master control C, etc.) and the accelerator core set.

[0053] ③ Enumerate and combine the cores in the accelerator core set. The number of each combination ranges from 1 to the number of exchange core interfaces - 2 (the master control core occupies one interface, and the interconnection with other core groups occupies one interface).

[0054] ④ After obtaining all the accelerator core combinations, iterate through the master control core set and generate a combination with each master control core.

[0055] ⑤ Each combination, plus the exchangeable core, becomes a complete combination.

[0056] ⑥ Repeat the above steps to enumerate all core particles, generating multiple permutations and combinations, thereby obtaining all possible core particle combinations.

[0057] Step S102, Core group layout algorithm: Based on the genetic algorithm, perform multi-objective optimization layout for each core group combination. The optimization objectives include area utilization, total wiring length and number of corners.

[0058] This step involves exploring the layout within each core group for each core-particle combination generated in step S101. This embodiment of the invention develops a multi-objective optimization heuristic layout algorithm based on a genetic algorithm, considering area, line length, and the number of wiring corners. The specific details are as follows:

[0059] (1) Problem Modeling and Parameter Definition

[0060] Layout space: bounded by the maximum illuminated area of ​​the wafer (rectangular area)

[0061] Objects to be laid out: Combinations of multiple types of core particles. Each core particle has attributes including fixed length and width, adjustable coordinates (x, y), rotatable angles (0°, 90°, 180°, 270°), and reconfigurable interface connections.

[0062] Optimization goal:

[0063] Area utilization: Minimize the area of ​​the rectangle surrounded by the core clusters. Total wiring length: Minimize the total length of all interconnects and the number of corners. Constraints: No core overlap, no boundary violations, and interface connectivity.

[0064] (2) Chromosomal gene encoding

[0065] The first step in a genetic algorithm is to encode the problem using genes. In the wafer-level chip layout problem, each individual (chromosome) in the genetic algorithm is set as a complete layout scheme composed of multiple cores. Each individual's information includes the length, width, coordinates, interface, and rotation of each core. Except for the length and width, which are fixed values, the remaining information needs to be explored. Therefore, each individual's gene consists of coordinates, interface, and rotation. The gene structure is: storing each core's (x-coordinate, y-coordinate, rotation angle, interface connection relationship) in core number order; gene degrees of freedom: coordinates, angle, and interface can all be evolved and adjusted.

[0066] (3) Initial population generation

[0067] N individuals are randomly generated (N is the number of populations set by the user); within each individual: the type of core particle is determined by user input or a random combination; the coordinates of each core particle are randomly distributed within the maximum range of the layout (referring to the maximum illumination area); the rotation angle is randomly selected from {0°, 90°, 180°, 270°}; the interface connection relationship between core particles is randomly initialized.

[0068] (4) Fitness calculation (multi-objective weighted)

[0069] The calculation process is as follows: detect core overlap and boundary crossing, calculate the area of ​​the enclosing rectangle, obtain the total wiring length and number of corners using A* routing, and then obtain the fitness value by normalization and weighted summation.

[0070] ① Penalty:

[0071] The system checks for overlapping cores or core coordinates exceeding the maximum illumination area. If either occurs, a penalty coefficient is added to the fitness calculation. The formula is as follows:

[0072] Penalty = Number of overlapping core pairs × Penalty coefficient P1 + Number of out-of-bounds cores × Penalty coefficient P2

[0073] ② Calculate the area of ​​the enclosing rectangle: Calculate the area of ​​the smallest enclosing rectangle for all core particles.

[0074] ③ Total wire length:

[0075] When calculating an individual's fitness, its line length is obtained through a routing algorithm. First, the core layout within the current individual is converted into a grid maze, and then the A* algorithm is used to obtain the shortest line length between cores. The A* algorithm is also a heuristic algorithm, which, in addition to the traditional line length optimization objective, also adds an optimization objective for the number of corners (adding an extra cost coefficient when the movement direction changes).

[0076] Path exploration using an improved A* algorithm:

[0077] When exploring a path and evaluating candidate positions for the next step, if a candidate position changes in the x or y direction compared to the current position, the candidate position incurs an additional 3 points of cost.

[0078] The fitness calculation formula is:

[0079] Fitness=W_a×Area_norm+W_w×WireLength_norm+Penalty

[0080] Where W_a and W_w are the area weight and line length weight, respectively; Penalty is the penalty coefficient.

[0081] Area_norm is the normalized area. The normalization process is: Area_norm = Area / maximum illuminated area.

[0082] WireLength_norm is the normalized wire length. The normalization process is: WireLength_norm = (Current_WL - Optimal_WL) / Current_WL, where Optimal_WL is the theoretical shortest wire length estimate and Current_WL is the actual wire length in the current layout scheme.

[0083] A lower fitness value indicates that the layout is closer to the optimization goal. Specifically: shorter cable length: shorter total cabling length results in less signal delay and better performance. Fewer corners: smoother cabling paths lead to better signal integrity. Higher area utilization: smaller layout area results in lower cost.

[0084] (5) Genetic operations: The population is iteratively optimized through selection, crossover, and mutation to output the layout scheme with the best fitness.

[0085] ① Selection (random competition method)

[0086] Each time, three individuals are randomly selected to compete, and the one with the best fitness enters the next generation, until a sufficient population size is selected.

[0087] ② Crossover (segmented gene recombination)

[0088] Each individual is used as a parent, and then a random individual is selected as the mother. There is a probability that two individuals will cross over to generate a new individual. If no crossover occurs, the parent is returned. Specifically, the process is as follows: Each parent individual is randomly paired with another mother; crossover is performed with a probability P_c (user-defined); a crossover point k∈[0, total number of kernels] is randomly generated; the new individual equals the first k kernel genes of the parent plus the last (total number of kernels - k) kernel genes of the mother; if crossover is not triggered, the parent is directly copied.

[0089] ③ Variation (Three-factor perturbation)

[0090] Each individual is iterated over, and each individual has a probability of mutation, the value of which is set by the user. If mutation occurs: the x and y coordinates of each core particle change randomly; each core particle rotates randomly; the interface connecting each core particle to exchange core particles changes randomly. Specifically, each individual mutates with probability P_m (user-defined); if mutation is triggered, all its core particle genes are iterated over:

[0091] Coordinate variation: The x or y coordinate of the core is randomly shifted within the range of [-1, +1]; Angle variation: The rotation angle is randomly selected from {0°, 90°, 180°, 270°} (including the possibility that 0° may remain unchanged); Interface variation: The interface connecting to the target core is randomly switched.

[0092] ④ Iterative optimization

[0093] After selection, crossover, and mutation, the fitness of each individual is recalculated, and the population with the best fitness is retained. The next iteration then begins from the selection stage. The process stops when the user-preset maximum number of iterations is reached.

[0094] ⑤ Output of the optimal solution

[0095] After reaching the maximum number of iterations, the layout algorithm will stop and output the layout schemes corresponding to the N (user-defined) individuals with the lowest (optimal) fitness in the last generation population, including the precise coordinates, rotation angles and interface connections of each core.

[0096] It is worth noting that, since line length weights are added when calculating fitness and each computed core is connected to a swapped core, the layout results will converge towards a layout in which the swapped core is placed in the center and other cores are arranged around the swapped core during the iteration process.

[0097] Step S103: Overall wafer performance evaluation: Copy and extend the core group layout to the entire wafer, calculate the overall performance index, and output the wafer layouts with the highest overall performance index.

[0098] ① Traverse the optimal layout of all core combinations (calculated according to step S102) and perform an overall performance evaluation for each layout.

[0099] ② Calculate the width and height of the minimum rectangle of this layout: The width is obtained by subtracting the minimum x-coordinate from the maximum x-coordinate of all core particles within the layout; the height is obtained by subtracting the minimum y-coordinate from the maximum y-coordinate. The formula is expressed as follows:

[0100] Width = (max(x) i +wi )-min(x i ))

[0101] Height = (max(y) i +h i )-min(y i ))

[0102] To ensure the safety distance between core particles, the width and height will be increased by the minimum spacing in the horizontal and vertical directions, respectively.

[0103] ③ Divide the width and height of the wafer by the width and height of a single core group, respectively, to obtain the number of core groups that can be placed on the wafer with this layout result.

[0104] ④ Calculate the overall computing power and cost of a single core group based on the computing power and cost parameters of each core.

[0105] ⑤ Multiply the overall computing power and cost of a single core group by the number of core groups to obtain the overall computing power and cost of the wafer.

[0106] ⑥ Normalize the overall computing power and cost of the wafer, and multiply them by the computing power coefficient and cost coefficient respectively to obtain the comprehensive performance index of this layout:

[0107]

[0108] Among them, W P W c These are the weighting coefficients for computing power and cost, respectively, Perf. total Cost total These represent the overall computing power and cost of the wafer, respectively, and Perf. max Cost max These are maximum computing power and cost, respectively.

[0109] Ultimately, the N wafer layouts with the highest overall performance index are output for users to choose from.

[0110] Corresponding to the above method, this embodiment also discloses a heuristic placement system for wafer-level chip architecture design, including:

[0111] The chip assembly exploration module is used to generate multiple chip assemblies based on the switching chip, the chip type, the interface type, and the consistency of the communication protocol.

[0112] The core group layout algorithm module is used to perform multi-objective optimization layout of each core particle combination based on a genetic algorithm. The optimization objectives include area utilization, total wiring length, and number of corners.

[0113] The overall wafer performance evaluation module is used to replicate and extend the core group layout to the entire wafer, calculate the overall performance index, and output the wafer layouts with the highest overall performance index.

[0114] Unless otherwise specifically stated, the components, steps, numerical expressions, and values ​​described in these embodiments do not limit the scope of the invention.

[0115] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0116] The units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations are not considered to be beyond the scope of this invention.

[0117] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This invention is not limited to any particular combination of hardware and software.

[0118] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features within the technical scope disclosed in the present invention; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A heuristic layout method for wafer-level chip architecture design, characterized in that, Includes the following steps: Chip assembly exploration: Centered on the switching chip, multiple chip assemblies are generated based on chip type, interface type, and communication protocol consistency. Core group layout algorithm: Based on genetic algorithm, multi-objective optimization layout is performed on each core combination. The optimization objectives include area utilization, total wiring length and number of corners; Overall wafer performance evaluation: The core layout is replicated and extended to the entire wafer, the overall performance index is calculated, and the wafer layouts with the highest overall performance index are output.

2. The heuristic layout method for wafer-level chip architecture design according to claim 1, characterized in that, The core assembly exploration includes: An abstract model is created for each chip, recording its size, type, number of interfaces, communication protocol type, interface location, computing power indicators, and cost; Centered on the switching core, the main control core and accelerator core are selected based on their number of interfaces and communication protocol type to generate all possible core combinations.

3. The heuristic layout method for wafer-level chip architecture design according to claim 1, characterized in that, The kernel group layout algorithm includes: Chromosomal gene encoding: The coordinates, rotation angle, and interface connection relationships of each corelet are encoded as genes; Fitness calculation: The fitness value is obtained by detecting core overlap and boundary crossing, calculating the area of ​​the enclosing rectangle, obtaining the total wiring length and number of corners by A* routing, and then normalizing and weighting the sum. Genetic operations: Through selection, crossover, and mutation, the population is iteratively optimized to output the layout scheme with the best fitness.

4. The heuristic layout method for wafer-level chip architecture design according to claim 3, characterized in that, In the chromosome gene encoding, the gene of each individual is composed of the coordinates, rotation angle and interface connection relationship of the core. Each individual represents a complete layout scheme composed of multiple cores, where the rotation angle is 0°, 90°, 180° or 270°.

5. The heuristic layout method for wafer-level chip architecture design according to claim 3, characterized in that, The fitness calculation specifically includes: Detect whether there is overlap of core particles or whether the core particle coordinates exceed the maximum illumination area. If the above occurs, increase the penalty coefficient in the fitness. Calculate the minimum bounding rectangle area for all core particles; The shortest path length between core particles is calculated using the A* algorithm. In addition to the traditional line length optimization objective, the A* algorithm also adds the optimization objective of the number of corners.

6. The heuristic placement method for wafer-level chip architecture design according to claim 5, characterized in that, The fitness calculation formula is as follows: Fitness=W_a×Area_norm+W_w×WireLength_norm+Penalty Where W_a and W_w are the area weight and line length weight, respectively; Penalty is the penalty coefficient; Area_norm is the normalized area, obtained by dividing the area by the maximum illuminated area; WireLength_norm is the normalized line length, i.e., WireLength_norm = (Current_WL - Optimal_WL) / Current_WL, where Optimal_WL is the theoretical shortest line length estimate, Current_WL is the actual line length in the current layout scheme, and Current_WL includes corner penalties.

7. The heuristic layout method for wafer-level chip architecture design according to claim 3, characterized in that, The selection process in the genetic operation adopts a random competition method, in which several individuals are randomly selected each time to compete, and the one with the best fitness enters the next generation; The crossover operation in the genetic operation adopts a segmented gene recombination method, traversing each parent individual and randomly pairing it with another mother individual, and performing the crossover operation with a preset probability. If the crossover is not triggered, the parent is directly copied. In the genetic operation, each individual undergoes mutation with a preset probability; if a mutation is triggered, all its core genes are traversed to perform coordinate mutation, angle mutation, and interface mutation.

8. The heuristic layout method for wafer-level chip architecture design according to claim 7, characterized in that, The coordinate variation is: the x or y coordinate of the core particle is randomly shifted within the coordinate range of [-1, +1]; the angle variation is: the rotation angle is randomly selected from {0°, 90°, 180°, 270°}; the interface variation is: the interface connecting to the target core particle is randomly switched.

9. The heuristic layout method for wafer-level chip architecture design according to claim 1, characterized in that, The overall performance evaluation of the wafer includes: Calculate the width and height of the minimum rectangular area of ​​a single core group, and calculate the maximum number that it can be replicated and expanded in the vertical and horizontal directions of the wafer to obtain the number of core groups; Calculate the overall computing power and cost of a single core group based on the computing power and cost parameters of each core. Multiply the overall computing power and cost of a single core group by the number of core groups to obtain the overall computing power and cost of the wafer. The overall computing power and cost of the wafer are normalized and weighted to obtain the comprehensive performance index of the layout.

10. A heuristic placement system for wafer-level chip architecture design, characterized in that, include: The chip assembly exploration module is used to generate multiple chip assemblies based on the switching chip, the chip type, the interface type, and the consistency of the communication protocol. The core group layout algorithm module is used to perform multi-objective optimization layout of each core particle combination based on a genetic algorithm. The optimization objectives include area utilization, total wiring length, and number of corners. The overall wafer performance evaluation module is used to replicate and extend the core group layout to the entire wafer, calculate the overall performance index, and output the wafer layouts with the highest overall performance index.

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