Electric energy quality adjusting device and method

Abstract

The invention discloses an electric energy quality adjusting device and method, and relates to the technical field of power electronics and electric energy quality control, and the method comprises the following steps: connecting a three-level topological inverter of a series structure with a transformer, adjusting the amplitude and phase of an output voltage in real time, and achieving the voltage compensation and power flow adjustment between AC ports in a power supply system; and starting the three-level topological inverter with the parallel structure, detecting the load side current, and separating and extracting the reactive current component, the harmonic current component and the three-phase unbalanced current. According to the invention, through cooperative control of a series-parallel topological structure, integrated adjustment of multi-dimensional electric energy quality parameters such as voltage, reactive power, harmonic waves and imbalance is realized; an ARM + FPGA dual-core control architecture and an electronic bypass mechanism are adopted, so that the response speed and the operation stability of the system are remarkably improved; in combination with P + repetitive control and PI control strategies, the harmonic compensation precision and the bus voltage control capability are improved, and the method has good adaptivity and real-time performance.

Description

Technical Field

[0001] This invention relates to the fields of power electronics and power quality control technology, specifically to a power quality regulation device and method. Background Technology

[0002] With the integration of new energy sources into the grid, the widespread application of nonlinear loads, and the increasing complexity of distribution networks, power quality problems are becoming increasingly serious. Issues such as voltage fluctuations, three-phase imbalance, harmonic pollution, and reactive power fluctuations significantly affect the stability of power system operation and the reliability of power supply on the user side. To address these problems, academia and engineering have developed various power quality management technologies, among which active power filters (APF), static var generators (SVG), and dynamic voltage restorers (DVR) based on power electronics technology have become major research and application areas.

[0003] Currently, some high-end applications employ Flexible AC Transmission Systems (FACTS) or Flexible DC Transmission Systems (VSC-HVDC) technologies to achieve voltage control and power flow regulation. However, most existing solutions are functionally limited and often confined to specific problems (such as filtering harmonics or compensating reactive power only). Some solutions achieve reactive power and harmonic compensation through parallel structures, but they struggle to simultaneously achieve voltage amplitude regulation and power flow control, especially in variable power supply environments where they cannot provide rapid response and comprehensive multi-dimensional power quality regulation capabilities.

[0004] The existing technology has the following shortcomings: The existing power quality regulation methods mainly have the following shortcomings: (1) Fragmented functions and lack of unified and coordinated control. Most devices can only deal with problems in one dimension. For example, SVG is only applicable to reactive power compensation, and APF focuses on harmonic control. However, they are often inadequate when it is necessary to solve voltage deviation, frequency deviation and imbalance at the same time. In addition, most of these devices rely on a single control module, which makes it difficult to achieve multi-module coordinated operation. The overall system response speed and compensation accuracy are limited.

[0005] (2) Lagging control response and poor system stability. Due to the large communication delay between the control logic and the actuator, or the unoptimized hardware structure, the existing system is unstable under sudden power grid events (such as faults and impact loads), and may even fail to compensate or falsely trigger protection actions. Some low-end devices use traditional PID controllers, which are difficult to cope with complex situations where multiple disturbances coexist, lack adaptive adjustment capabilities, and affect the stability and safety of continuous system operation.

[0006] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to provide a power quality regulation device and method. Through coordinated control of series and parallel topologies, this invention achieves integrated regulation of multi-dimensional power quality parameters such as voltage, reactive power, harmonics, and imbalance. By adopting an ARM+FPGA dual-core control architecture and electronic bypass mechanism, the system response speed and operational stability are significantly improved. By combining P+ repetitive control and PI control strategies, the harmonic compensation accuracy and bus voltage control capability are improved, and the device exhibits good adaptability and real-time performance, thereby solving the problems mentioned in the background technology.

[0008] To achieve the above objectives, the present invention provides the following technical solution: a power quality regulation method, comprising the following steps: By connecting a three-level topology inverter with a series structure to a transformer, the output voltage amplitude and phase are adjusted in real time to achieve voltage compensation and power flow regulation between AC ports in the power supply system. Start the three-level topology inverter with parallel structure, detect the load side current, and separate and extract the reactive current component, harmonic current component and three-phase unbalanced current. The extracted reactive, harmonic, and unbalanced current commands are respectively processed using a control strategy combining PI control and repetitive control to generate compensation current commands and drive the parallel inverter to output compensation current to the grid. Based on a dual-core control platform, an ARM processing module is used for sampling, system power calculation, control command generation and communication with the host computer, and an FPGA module is used to realize PWM control signal generation, hardware fault diagnosis and IO logic processing. When the dual-core control platform detects overvoltage, overcurrent, or control anomalies, it activates the electronic bypass path composed of bidirectional anti-parallel thyristors to achieve converter bypass protection within one millisecond, ensuring continuous system operation. The dual-core control platform adopts a main loop plus interrupt scheduling architecture. All control modules are independently coded to achieve real-time parallel scheduling between functional modules, thereby improving the control response speed and overall stability of the dual-core control platform.

[0009] Preferably, the output voltage range of the three-level inverter with series structure is 0 to 420 volts. By controlling the amplitude and phase angle of the input voltage on the primary side of the transformer, the output voltage is adjusted in real time to counteract transient voltage drops or overvoltage disturbances in the power supply system. The transformer adopts a YN / open circuit connection method, has a 230-volt input and 58-volt output capability, and effectively isolates voltage disturbance coupling between different sides; The PWM signal on the input side of the transformer is adjusted by a dual-core control platform, so that the output voltage is accurately maintained within the range of ±5 volts of the set reference value, ensuring the quality of voltage waveform and the accuracy of power flow direction control.

[0010] Preferably, the load-side current is continuously collected by a dual-core control platform, and harmonic current, unbalanced components and reactive power components are extracted using hardware filters and FPGA preprocessing modules. The sampling frequency is not less than 20kHz. The load distortion source is accurately restored by calculating the difference between the bridge-side current sampling signals ICA, ICB, ICC and the grid-side currents IA, IB, IC. Then, dual-channel hardware filtering is used to extract each harmonic component, with the error of each channel controlled within 1%. The amplitude normalization and phase correction process is completed by the ARM module and FPGA module in the dual-core control platform, providing accurate input for the subsequent generation of compensation current.

[0011] Preferably, the ARM module uses a 32-bit processor for data acquisition of voltage and current signals, setting of target parameters, management of error thresholds, and communication with the host computer. The FPGA module runs on an independent clock system, performs fast Fourier transform operations, real-time voltage and current calculations, PWM modulation signal generation, fault signal identification and protection response logic processing based on the acquired data, and realizes bidirectional communication with the human-machine interface terminal through RS485 bus. The FPGA module runs on an independent clock system, responsible for PWM signal generation, overvoltage and overcurrent protection hardware response, IGBT signal drive logic generation, and all external IO control and edge detection, improving the response speed to sub-millisecond level during sudden power grid disturbances and ensuring the synchronous stability of control commands and execution actions.

[0012] Preferably, reactive current compensation is based on improved instantaneous power theory, harmonic compensation is based on FFT fast frequency domain extraction combined with repetitive control strategy, and three-phase imbalance compensation is achieved based on instantaneous symmetrical coordinate transformation and negative sequence component reverse injection method. All compensation current control strategies have fixed calculation logic preset in the FPGA, while the ARM only transmits the target value and dynamically corrects the error threshold value. The repetitive controller cycle is 20 control cycles, the error threshold is controlled within 1%, and the reference command value is recalibrated every 200ms to ensure real-time tracking capability under stable system operation.

[0013] Preferably, the specific steps for harmonic current command extraction and output compensation current generation are as follows: The current signals in the three-phase AC system are acquired using a high-precision sampling module, ensuring that the sampling frequency is not less than 10 times the PWM update frequency of the dual-core control platform to capture all harmonic components. The sampled data is then sent to the FPGA module to perform a fast Fourier transform operation, as shown in the following formula: In the formula, and The results obtained after Fourier analysis are respectively the first The coefficients of the cosine and sine terms corresponding to the second harmonic. It is the first The amplitude of the second harmonic; The amplitudes of third and higher harmonic components are extracted to determine the actual energy level of each frequency component, based on a pre-set harmonic limit threshold. Calculate the degree of exceedance for each frequency component to obtain the error amount. The calculation expression is as follows: In the formula, It sets the maximum allowable amplitude limit for harmonics. It means the first The difference between the subharmonic and the preset maximum allowable amplitude of the dual-core control platform; To achieve fast and stable compensation current output, the following is introduced: Repeated control strategy, The repetitive control strategy balances response speed and steady-state error control, and the control output is as follows: In the formula, It is the current moment. The generated first The target compensation current for subharmonics. It is the proportional gain coefficient. It is the compensation current command generated in the previous cycle. It is the repeat cycle of the controller. The error occurred in the previous cycle. The integral term within.

[0014] Preferably, the electronic bypass switch is composed of two sets of anti-parallel thyristors with a response time of less than 1 millisecond; when the fault detection module identifies that the bus overvoltage or overcurrent exceeds the critical value, it immediately triggers the bypass command and locks all PWM signal outputs through the controller logic to prevent re-excitation; The electronic bypass circuit is equipped with a fusible fuse and a surge suppression capacitor, which can restore the voltage to the set tolerance range within 30ms and ensure that the load is continuously powered without interruption, significantly improving the fault resilience and protection self-recovery capability of the dual-core control platform.

[0015] Preferably, the task scheduling strategy of the dual-core control platform is based on a main loop + interrupt structure, with the main loop executing sampling command scheduling, power calculation, and data recording management; The main interrupt channel is used to handle medium-to-high priority events, including PWM updates, voltage and current error feedback correction, and fault interrupt handling. All interrupt channels have independent priority identifiers and interrupt nesting capabilities. The highest priority is the fault response processing channel, ensuring that the dual-core control platform can switch to protection mode and activate bypass logic within 10 microseconds when the voltage or current of the dual-core control platform changes drastically, preventing overload damage.

[0016] Preferably, the control process for real-time adjustment of the output voltage amplitude and phase using a three-level topology inverter connected to a transformer in series is as follows: First, the voltages at both ends of the DC bus are sampled synchronously with high precision to obtain the upper and lower voltages. Then, the average voltage of the DC bus and the voltage difference between the two ends are calculated using the following formula: In the formula, It is the positive terminal voltage of the DC bus. It is the voltage at the negative terminal of the DC bus. It is the average voltage of the DC bus. It is the DC bus voltage difference; To maintain the bus voltage stable near the target value, a PI control algorithm is used to adjust the output voltage command, and its control output is as follows: In the formula, The target voltage is set on the DC bus. It is a direct voltage regulator control output command. It is the integral gain of the PI controller; To suppress unbalanced voltage across the bus, a voltage equalization control signal is calculated. Rapid equalization is achieved by proportionally controlling the voltage difference across the two ends, as shown in the following formula: In the formula, It is the proportional coefficient for pressure equalization control. It is a voltage equalization control command; Based on direct voltage regulation control output command and voltage equalization control commands The synthesized PWM modulation reference signal is given by the following formula: In the formula, It is the final PWM control signal.

[0017] Preferably, a power quality conditioning device includes a series voltage regulation and power flow regulation module, a multi-dimensional current analysis and extraction module, a dual-core control and signal processing module, a compensation current generation and inverter drive module, a fast fault bypass protection module, and a dispatch control and module management module. The series voltage regulation and power flow regulation module uses a three-level topology inverter connected to a transformer in series to adjust the output voltage amplitude and phase in real time, thereby realizing voltage compensation and power flow regulation between AC ports in the power supply system. The multi-dimensional current analysis and extraction module starts the three-level topology inverter with parallel structure, detects the load-side current, and separates and extracts the reactive current component, harmonic current component, and three-phase unbalanced current. The dual-core control and signal processing module is based on a dual-core control platform. It uses an ARM processing module for sampling, system power calculation, control command generation and communication with the host computer, and an FPGA module for PWM control signal generation, hardware fault diagnosis and IO logic processing. The compensation current generation and inverter drive module uses a control strategy combining PI control and repetitive control to generate compensation current commands from the extracted reactive, harmonic and unbalanced current commands, and drives the parallel inverter to output compensation current to the grid. The fast fault bypass protection module activates the electronic bypass path composed of bidirectional anti-parallel thyristors when the dual-core control platform detects overvoltage, overcurrent, or control abnormalities, achieving converter bypass protection within one millisecond and ensuring continuous system operation. The scheduling control and module management module of the dual-core control platform adopts a main loop plus interrupt scheduling architecture. All control modules are independently coded to realize real-time parallel scheduling between functional modules, thereby improving the control response speed and overall stability of the dual-core control platform.

[0018] The technical effects and advantages provided by the present invention in the above technical solution are as follows: This invention organically combines series and parallel topologies, along with high-performance transformers and inverter modules, to achieve coordinated regulation of multiple power quality parameters, including voltage amplitude, reactive power, harmonic current, and three-phase imbalance. Compared to the traditional approach of using multiple independent devices to address power quality issues separately, this method unifies scheduling and control on a single platform, simplifying the system architecture and significantly improving the coordination and response efficiency of regulation. It is particularly suitable for environments with high power quality requirements, such as industrial power distribution systems and new energy grid-connected scenarios, achieving the goal of one-stop, multi-dimensional power quality management.

[0019] This invention employs an ARM+FPGA dual-core control architecture, combined with modular programming and a main loop + interrupt scheduling mechanism, to achieve system control with strong real-time performance and high fault self-diagnosis capabilities. The ARM module handles high-level control and communication tasks, while the FPGA module is responsible for low-level PWM control and hardware protection logic. Combined with an electronic bypass switch, system fault isolation can be achieved within 1 millisecond, effectively preventing cascading failures. This control strategy solves the problems of delayed response and frequent false triggering in existing systems under dynamic disturbances or extreme operating conditions, significantly improving the operational stability and reliability of the regulating device.

[0020] This invention introduces a P+ repetitive controller and a PI composite control strategy in its control algorithm, enabling precise real-time tracking and compensation of harmonic currents and achieving stable and balanced regulation of the DC bus voltage. Through frequency domain extraction and controller fusion, it not only improves the system's ability to identify multiple harmonic components but also ensures rapid synchronous response between the compensation current and interference signals, reducing system steady-state error. The addition of the PI controller ensures stable operation of the DC bus voltage under load fluctuations, effectively improving the power system's energy efficiency, output quality, and disturbance rejection capability. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0022] Figure 1 This is a flowchart of a power quality regulation method according to the present invention. Figure 2 This is a schematic diagram of a power quality regulation device according to the present invention. Detailed Implementation

[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art.

[0024] Example 1 This embodiment 1 provides the following: Figure 1 The power quality regulation method shown includes the following steps: By connecting a three-level topology inverter with a series structure to a transformer, the output voltage amplitude and phase are adjusted in real time to achieve voltage compensation and power flow regulation between AC ports in the power supply system. The three-level inverter with series structure has an output voltage range of 0 to 420 volts. By controlling the amplitude and phase angle of the input voltage on the primary side of the transformer, the output voltage is adjusted in real time to counteract transient voltage drops or overvoltage disturbances in the power supply system. The transformer adopts a YN / open circuit connection method, has a 230-volt input and 58-volt output capability, effectively isolates voltage disturbance coupling between different sides, and improves system stability; The PWM signal on the input side of the transformer is adjusted by a dual-core control platform, so that the output voltage is accurately maintained within the range of ±5 volts of the set reference value, ensuring the quality of voltage waveform and the accuracy of power flow direction control.

[0025] Start the three-level topology inverter with parallel structure, detect the load side current, and separate and extract the reactive current component, harmonic current component and three-phase unbalanced current. The dual-core control platform continuously collects the load-side current and uses hardware filters and FPGA preprocessing modules to extract harmonic current, unbalanced components and reactive components. The sampling frequency is not less than 20kHz. The load distortion source is accurately restored by calculating the difference between the bridge-side current sampling signals ICA, ICB, ICC and the grid-side currents IA, IB, IC. Then, dual-channel hardware filtering is used to extract the harmonic components (3rd, 5th, and 7th), with the error of each channel controlled within 1%. The amplitude normalization and phase correction process is completed by the ARM module and FPGA module in the dual-core control platform, providing accurate input for the subsequent generation of compensation current.

[0026] Based on a dual-core control platform, an ARM processing module is used for sampling, system power calculation, control command generation and communication with the host computer, and an FPGA module is used to realize PWM control signal generation, hardware fault diagnosis and IO logic processing. The ARM module uses a 32-bit processor for data acquisition of voltage and current signals, target parameter setting, error threshold management, and communication with the host computer. The FPGA module runs on an independent clock system, performs fast Fourier transform operations, real-time voltage and current calculations, PWM modulation signal generation, fault signal identification and protection response logic processing based on the acquired data, and realizes bidirectional communication with the human-machine interface terminal through RS485 bus. The FPGA module runs on an independent clock system, responsible for PWM signal generation, overvoltage and overcurrent protection hardware response, IGBT signal drive logic generation, and all external IO control and edge detection, improving the response speed to sub-millisecond level during sudden power grid disturbances and ensuring the synchronous stability of control commands and execution actions.

[0027] The extracted reactive, harmonic, and unbalanced current commands are respectively processed using a control strategy combining PI control and repetitive control to generate compensation current commands and drive the parallel inverter to output compensation current to the grid. Reactive current compensation is based on improved instantaneous power theory, harmonic compensation uses FFT fast frequency domain extraction combined with repetitive control strategy, and three-phase imbalance compensation is achieved based on instantaneous symmetrical coordinate transformation and negative sequence component reverse injection method. All compensation current control strategies have fixed calculation logic preset in the FPGA, while the ARM only transmits the target value and dynamically corrects the error threshold value. The repetitive controller cycle is 20 control cycles, the error threshold is controlled within 1%, and the reference command value is recalibrated every 200ms to ensure real-time tracking capability under stable system operation.

[0028] The specific steps for extracting harmonic current commands and generating output compensation current are as follows: The current signals in the three-phase AC system are acquired through a high-precision sampling module, ensuring that the sampling frequency is not less than 10 times the PWM update frequency of the dual-core control platform to capture all harmonic components. The sampled data is then sent to the FPGA module to perform a Fast Fourier Transform (FFT) operation, as shown in the following formula: In the formula, and The results obtained after Fourier analysis are respectively the first The coefficients of the cosine and sine terms corresponding to the second harmonic. It is the first The amplitude of the second harmonic; the unit is also ampere (A). These two coefficients reflect the amplitude of the third harmonic. The phase distribution characteristics of the subharmonics are extracted from the original current waveform using FFT transformation. It is the first The amplitude of a subharmonic is a scalar measure of the current harmonic intensity, measured in amperes (A). The system needs to monitor whether a certain subharmonic amplitude is being measured. Exceeding the limit will trigger the compensation mechanism; The amplitudes of third and higher harmonic components are extracted to determine the actual energy level of each frequency component, based on a pre-set harmonic limit threshold. Calculate the degree of exceedance for each frequency component to obtain the error amount. The calculation expression is as follows: , In the formula, This sets the maximum allowable amplitude limit for harmonics, also known as the "harmonic threshold," measured in amperes (A). This value is set based on power quality standards (such as IEEE 519 or national standards), for example, the third harmonic must not exceed 5% of the fundamental current. It means the first The difference between the subharmonic and the preset maximum allowable amplitude of the dual-core control platform, i.e., the "excess limit", is measured in amperes (A). This value determines whether the compensation process is initiated. Harmonic compensation should only be activated when the limits are exceeded to avoid wasting system resources and causing erroneous adjustments.

[0029] To achieve fast and stable compensation current output, the following is introduced: Repeated control strategy, The repetitive control strategy balances response speed and steady-state error control, and the control output is as follows: In the formula, It is the current moment. The generated first The target compensation current for the second harmonic is measured in amperes (A). This value will be directly used to control the output of the parallel inverter, driving it to inject the corresponding compensation current. This is the proportional gain coefficient, a controller adjustment parameter with no unit. It determines the direct impact of the current error on the output control quantity; proper adjustment can improve the system response speed. It is the compensation current command generated in the previous cycle. As the core part of the "repetitive control" module, it is used to reuse periodic errors and improve control stability under dynamic disturbances. This is the controller's repetition period, measured in seconds (s). It's a time constant fixed in the dual-core control platform and is typically a multiple of the system's PWM period, for example, 1ms. The error occurred in the previous cycle. The integral term within reflects the cumulative amount of harmonic deviation over the past control cycle and is used to suppress static error.

[0030] The first term is proportional gain control, the second term is historical integral cumulative error, and the third term is to realize repeated tracking of previous cycle error. The three terms work together to generate high-precision harmonic current compensation commands.

[0031] Ultimately, the compensation current command is converted into a PWM signal in real time via the FPGA and driven by the inverter to inject the required harmonic current into the power grid, thereby achieving active suppression of harmonic sources. This method not only improves the frequency domain compensation efficiency of the system but also has adaptive adjustment capabilities, making it suitable for fine harmonic management in dynamically changing power grid environments.

[0032] The P+ repetitive control strategy is a composite control method that combines proportional control (P control) and repetitive control, specifically designed to handle periodic disturbances, such as harmonic current compensation in power systems.

[0033] The P+ repetitive control strategy is a control method for rapidly suppressing periodic errors. Its core lies in combining the rapid response capability of proportional control with the complete elimination of periodic errors by repetitive control, making it suitable for current harmonic compensation scenarios. This means that the control quantity at the current moment is determined not only by the proportional gain (P part) but also by referencing the control error from the previous cycle (repetitive part), forming a dynamic control mechanism with "memory." Its function is to accurately identify and track recurring harmonic components in the current and dynamically adjust the output current to achieve effective compensation and avoid long-term system deviation accumulation. In specific implementation, the system first extracts the error amplitude of the target harmonic through a fast Fourier transform, then the controller calculates the compensation current command. Its structure typically includes a proportional term, a historical integral term, and a periodic feedback term, and is ultimately converted into a PWM signal to drive the inverter, injecting precise reverse harmonics into the grid, effectively eliminating periodic interference and improving power quality.

[0034] This invention accurately extracts harmonic components from the current using Fast Fourier Transform (FFT), determines whether a harmonic exceedance has occurred based on a set harmonic threshold, and dynamically generates a compensation current command upon detection of an exceedance by introducing a proportional-plus-repetitive (P+R) control algorithm. This control method not only responds quickly to harmonic changes but also continuously tracks periodic disturbances, significantly improving the stability and robustness of harmonic suppression. Finally, the compensation current is injected into the power grid through PWM control, achieving proactive management of harmonic issues in power quality and enhancing the cleanliness and reliability of the system under complex operating conditions. This invention addresses the problems of poor suppression accuracy, response delay, and weak anti-interference capability of traditional PID control in multi-frequency harmonic environments, representing a key innovation at the control strategy level.

[0035] When the dual-core control platform detects overvoltage, overcurrent, or control anomalies, it activates the electronic bypass path composed of bidirectional anti-parallel thyristors to achieve converter bypass protection within one millisecond, ensuring continuous system operation. The electronic bypass switch is composed of two sets of anti-parallel thyristors, with a response time of less than 1 millisecond. When the fault detection module identifies that the bus overvoltage or overcurrent exceeds the critical value, it immediately triggers the bypass command and locks all PWM signal outputs through the controller logic to prevent re-excitation. The electronic bypass circuit is equipped with a fusible fuse and a surge suppression capacitor, which can restore the voltage to the set tolerance range within 30ms and ensure that the load is continuously powered without interruption, significantly improving the fault resilience and protection self-recovery capability of the dual-core control platform.

[0036] The dual-core control platform adopts a main loop plus interrupt scheduling architecture. All control modules are independently coded to realize real-time parallel scheduling among functional modules such as harmonic extraction, voltage phase-locking, voltage equalization and regulation, and fault protection, thereby improving the control response speed and overall stability of the dual-core control platform. The "main loop plus interrupt scheduling architecture" is a common program execution structure in embedded control systems. Its core idea is to use a continuously running main loop within the main control program to handle periodic tasks, while simultaneously responding to urgent or high-priority events through an interrupt mechanism. The main loop is responsible for performing routine control tasks such as data sampling, communication management, and parameter updates, while interrupt scheduling, triggered by hardware or timers, is used for real-time processing of critical operations such as PWM updates, protection logic responses, and input signal detection. This architecture significantly improves the response speed, reliability, and system stability of the control system by separating non-real-time and real-time tasks, achieving parallel task scheduling and response priority optimization. It is suitable for power quality regulation devices with high real-time requirements.

[0037] The task scheduling strategy of the dual-core control platform is based on a main loop + interrupt structure. The main loop executes sampling command scheduling, power calculation, and data recording management. The main interrupt channel is used to handle medium-to-high priority events, including PWM updates, voltage and current error feedback correction, and fault interrupt handling. All interrupt channels have independent priority identifiers and interrupt nesting capabilities. The highest priority is the fault response processing channel, ensuring that the dual-core control platform can switch to protection mode and activate bypass logic within 10 microseconds when the voltage or current of the dual-core control platform changes drastically, preventing overload damage.

[0038] The control process for real-time adjustment of the output voltage amplitude and phase using a three-level topology inverter connected to a transformer in series is as follows: First, the voltages at both ends of the DC bus are sampled synchronously with high precision to obtain the upper and lower voltages. Then, the average voltage of the DC bus and the voltage difference between the two ends are calculated using the following formula: In the formula, It is the positive terminal voltage of the DC bus, representing the real-time voltage value measured between the positive terminal of the DC bus and ground. It is often used to represent the potential of the upper part of the DC-side capacitor array. This is the DC bus negative terminal voltage, representing the real-time voltage value measured between the DC bus negative terminal and ground. It typically reflects the potential of the lower capacitor bank or DC converter module. This is the average DC bus voltage, used to characterize the steady-state voltage value of the entire DC bus system. It serves as a target reference for the dual-core control platform when adjusting the output voltage. This is the DC bus voltage difference, reflecting the degree of voltage imbalance between the capacitor banks at both ends of the bus, and is the main adjustment basis for the voltage equalization control circuit. If it is positive, it means that the positive voltage is higher than the negative voltage, and vice versa; Average voltage is used to represent the stability index of system power supply, while voltage difference reflects the imbalance caused by uneven capacitor distribution or transient impact.

[0039] To maintain the bus voltage stable near the target value, a PI control algorithm is used to adjust the output voltage command. This control method has automatic error integration correction capability, and its control output is as follows: In the formula, The target voltage for the DC bus is a preset ideal supply voltage value, which serves as the reference value for PI regulation control. For example, in a 400V system, it is often set to 400V or 405V. It is a direct voltage regulator control output command, an adjustment signal calculated by a PI (proportional-integral) controller, reflecting the current voltage error of the system and applying adjustment to stabilize the DC bus voltage. It is the integral gain of the PI controller, used to eliminate the steady-state error of the system. The larger the value, the faster the elimination speed, but too fast integration may lead to overshoot. To suppress unbalanced voltage across the bus, a voltage equalization control signal is calculated. Rapid equalization is achieved by proportionally controlling the voltage difference across the two ends, as shown in the following formula: In the formula, It is the proportional coefficient for voltage equalization control, which controls the voltage equalization adjustment rate and is used to dynamically balance the voltage difference between the positive and negative terminals, ensuring the stable operation of the DC bus capacitor bank. It is a voltage equalization control command. The voltage correction amount is calculated based on the voltage difference between the two ends multiplied by the equalization ratio coefficient. It is used to adjust the PWM waveform so that the voltages of the two capacitor banks tend to be consistent. This signal is input to the drive system through a separate channel, providing additional equalizing force, thereby significantly reducing the problem of unbalanced charging and discharging between capacitors in the DC bus.

[0040] Based on direct voltage regulation control output command and voltage equalization control commands The synthesized PWM modulation reference signal is given by the following formula: In the formula, It is the final PWM control signal, which is the final control command after comprehensively considering the steady state of the voltage and the balance of the capacitor voltage. It is then passed to the PWM generation module to realize pulse width modulation control of the IGBT output.

[0041] This signal is input to the series inverter control module, which adjusts the output pulse width in real time to achieve dual control of the DC bus: voltage stabilization and voltage balancing, thereby improving the energy quality and reliability of the DC side of the system. It is suitable for the precision control requirements of high-power dynamic converter devices.

[0042] This embodiment integrates series and parallel power electronic topologies to construct a comprehensive power quality regulation system for addressing various common power system problems. In the device, the series module, primarily responsible for voltage regulation and power flow control, consists of a three-level voltage-source inverter and an isolated series transformer. It possesses a voltage regulation capability from 0 to 420 volts and can quickly respond to sudden voltage drops and surges in the power grid. The series transformer uses a YN / open-circuit configuration to improve the electrical isolation between the module and the main grid, while also enhancing the flexibility of output voltage regulation. This module can precisely control the amplitude and phase angle of the phase voltage, achieving real-time adjustment and stable control of power flow between AC ports.

[0043] On the other hand, the parallel module, also based on a three-level inverter structure, is located on the load side of the system and is mainly responsible for the dynamic compensation of reactive current, harmonic current, and three-phase unbalanced current in the system. By sampling the load current signals (IA, IB, IC, etc.) and grid-side current signals in real time, the system uses the FPGA to perform preprocessing and filtering to separate various distorted current sources. Then, the controller generates corresponding reverse compensation commands and injects compensation current, thereby achieving dynamic restoration of the power waveform. The entire control logic is based on a closed-loop structure, combined with instantaneous reactive power theory and coordinate transformation algorithms to ensure high-precision compensation performance.

[0044] The main circuit control of the entire device relies on a coordinated control strategy and hardware architecture. The series and parallel modules can operate independently or jointly under different operating conditions, and seamless switching is achieved through unified scheduling by the system management module. Especially when multiple power quality problems overlap (such as voltage drops accompanied by severe harmonics), this structure can adjust various parameters separately, ultimately achieving multiple objectives simultaneously, including voltage stability, reactive power balance, harmonic suppression, and imbalance correction. Compared with traditional single-function devices, this structure has high integration and is suitable for complex power consumption scenarios such as industrial loads, data centers, and electric vehicle charging stations, greatly improving grid operating efficiency and terminal power supply reliability.

[0045] This embodiment focuses on improving the response speed and control stability of the control system in actual operation. It achieves layered optimization of the control algorithm and execution instructions by introducing a dual-core collaborative control architecture of ARM and FPGA. The ARM, as the upper-level main control unit, undertakes all tasks such as signal sampling, communication protocol parsing, data storage, control instruction calculation and distribution. It has powerful general-purpose computing capabilities and interface expansion capabilities, supports communication protocols such as Modbus and RS485, and can realize data interaction with human-machine interfaces (HMIs), host computer systems, and remote monitoring platforms.

[0046] As the core of the underlying execution control, the FPGA module, with its independently operating logic units and high-speed clock drive, is responsible for PWM waveform generation, current sampling synchronization processing, overvoltage and overcurrent protection logic judgment, and control signal output. Especially in the event of sudden power grid disturbances such as impact loads, system switching, and fault tripping, the FPGA can complete the judgment of electrical parameters and trigger protection actions within microseconds, significantly improving the real-time performance and reliability of the system protection.

[0047] The system control adopts a "main loop + interrupt handling" software architecture. The ARM-side main loop completes timed sampling and data processing, while various high-priority events (such as fault detection, PWM updates, etc.) are handled by the interrupt channel, ensuring reasonable control priorities and efficient task scheduling. The interrupt nesting management mechanism allows the system to process multiple tasks in parallel during operation, further improving the system's dynamic response capability.

[0048] Furthermore, all control modules of the system are deployed independently, enabling fault tolerance and modular upgrades. For example, harmonic compensation can be enabled on demand without affecting reactive power or voltage control logic. The system is also equipped with EEPROM for storing operational data, fault history records, and control parameters, supporting system self-recovery after power outages and remote operation and maintenance. This structure not only ensures the real-time performance and accuracy of power quality control but also achieves a high degree of modularity and scalability in the system's hardware and software, meeting the future trend of intelligent development of power quality equipment.

[0049] This embodiment aims to achieve high-precision dynamic adjustment of various dimensions of power quality through optimized control algorithms, with a particular focus on two key control objectives: harmonic current compensation and bus voltage stabilization. The system control strategy employs a P+ repetitive control and PI composite control architecture, used for frequency domain dynamic current compensation and steady-state DC voltage control, respectively.

[0050] The harmonic compensation section first utilizes the FFT algorithm within the FPGA to extract high-frequency components per cycle, obtaining the main harmonic components (3rd, 5th, 7th, etc.) in the three-phase current through high-speed sampling. Subsequently, the frequency components are fed into a P+ repetitive controller, which uses a proportional gain plus periodic integral feedback structure to generate compensation commands for each harmonic. Compared to traditional PID control, P+ repetitive control is more suitable for handling periodic errors, effectively suppressing high-order harmonics in the output current, and bringing the control error close to zero. The compensation current is injected into the grid in real time by the inverter to achieve power waveform restoration.

[0051] The direct voltage regulation and voltage equalization control section measures the voltage across the bus terminals, calculates the average voltage and voltage difference, and inputs this data to the PI controller and voltage equalization compensation channel. The PI controller adjusts the overall system voltage based on the average voltage deviation, while the voltage equalization channel adjusts the voltage difference in each segment according to the terminal voltage difference, forming a two-stage control loop. This control method exhibits good stability and self-recovery capability when dealing with conditions such as uneven bus capacitance and instantaneous impact load changes.

[0052] To enhance control performance, the system also introduces a model-based parameter pre-setting mechanism to optimize and match controller parameters under different load types and grid characteristics. This, combined with a fault detection channel, switches to protection mode or a soft-start procedure in abnormal conditions, improving system robustness and operational safety. This composite control strategy maintains stable and rapid regulation performance even in complex power environments characterized by severe harmonics, drastic voltage fluctuations, and frequent dynamic load changes. It effectively fills the gaps in dynamic accuracy and steady-state error control of traditional control algorithms, demonstrating significant engineering application value.

[0053] This invention organically combines series and parallel topologies, along with high-performance transformers and inverter modules, to achieve coordinated regulation of multiple power quality parameters, including voltage amplitude, reactive power, harmonic current, and three-phase imbalance. Compared to the traditional approach of using multiple independent devices to address power quality issues separately, this method unifies scheduling and control on a single platform, simplifying the system architecture and significantly improving the coordination and response efficiency of regulation. It is particularly suitable for environments with high power quality requirements, such as industrial power distribution systems and new energy grid-connected scenarios, achieving the goal of one-stop, multi-dimensional power quality management.

[0054] This invention employs an ARM+FPGA dual-core control architecture, combined with modular programming and a main loop + interrupt scheduling mechanism, to achieve system control with strong real-time performance and high fault self-diagnosis capabilities. The ARM module handles high-level control and communication tasks, while the FPGA module is responsible for low-level PWM control and hardware protection logic. Combined with an electronic bypass switch, system fault isolation can be achieved within 1 millisecond, effectively preventing cascading failures. This control strategy solves the problems of delayed response and frequent false triggering in existing systems under dynamic disturbances or extreme operating conditions, significantly improving the operational stability and reliability of the regulating device.

[0055] This invention introduces a P+ repetitive controller and a PI composite control strategy in its control algorithm, enabling precise real-time tracking and compensation of harmonic currents and achieving stable and balanced regulation of the DC bus voltage. Through frequency domain extraction and controller fusion, it not only improves the system's ability to identify multiple harmonic components but also ensures rapid synchronous response between the compensation current and interference signals, reducing system steady-state error. The addition of the PI controller ensures stable operation of the DC bus voltage under load fluctuations, effectively improving the power system's energy efficiency, output quality, and disturbance rejection capability.

[0056] Example 2 This embodiment 2 provides, as follows: Figure 2 The power quality conditioning device shown includes a series voltage regulation and power flow regulation module, a multi-dimensional current analysis and extraction module, a dual-core control and signal processing module, a compensation current generation and inverter drive module, a fast fault bypass protection module, and a scheduling control and module management module. The series voltage regulation and power flow regulation module uses a three-level topology inverter connected to a transformer in series to adjust the output voltage amplitude and phase in real time, thereby realizing voltage compensation and power flow regulation between AC ports in the power supply system. The multi-dimensional current analysis and extraction module starts the three-level topology inverter with parallel structure, detects the load-side current, and separates and extracts the reactive current component, harmonic current component, and three-phase unbalanced current. The dual-core control and signal processing module is based on a dual-core control platform. It uses an ARM processing module for sampling, system power calculation, control command generation and communication with the host computer, and an FPGA module for PWM control signal generation, hardware fault diagnosis and IO logic processing. The compensation current generation and inverter drive module uses a control strategy combining PI control and repetitive control to generate compensation current commands from the extracted reactive, harmonic and unbalanced current commands, and drives the parallel inverter to output compensation current to the grid. The fast fault bypass protection module activates the electronic bypass path composed of bidirectional anti-parallel thyristors when the dual-core control platform detects overvoltage, overcurrent, or control abnormalities, achieving converter bypass protection within one millisecond and ensuring continuous system operation. The scheduling control and module management module of the dual-core control platform adopts a main loop plus interrupt scheduling architecture. All control modules are independently coded to realize real-time parallel scheduling between functional modules, thereby improving the control response speed and overall stability of the dual-core control platform.

[0057] The power quality regulation method provided in Embodiment 1 of the present invention is implemented by the power quality regulation device described above. For details of the specific method and process of the power quality regulation device, please refer to Embodiment 1 of the power quality regulation method described above, which will not be repeated here.

[0058] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0059] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

[0060] It should be noted that, in this document, the use of relational terms such as "first" and "second" is merely for distinguishing one entity or operation from another, and does not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0061] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0062] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0063] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0064] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0065] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0066] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0067] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A power quality regulation method, characterized in that, Includes the following steps: By connecting a three-level topology inverter with a series structure to a transformer, the output voltage amplitude and phase are adjusted in real time to achieve voltage compensation and power flow regulation between AC ports in the power supply system. Start the three-level topology inverter with parallel structure, detect the load side current, and separate and extract the reactive current component, harmonic current component and three-phase unbalanced current. The extracted reactive, harmonic, and unbalanced current commands are respectively processed using a control strategy combining PI control and repetitive control to generate compensation current commands and drive the parallel inverter to output compensation current to the grid. Based on a dual-core control platform, an ARM processing module is used for sampling, system power calculation, control command generation and communication with the host computer, and an FPGA module is used to realize PWM control signal generation, hardware fault diagnosis and IO logic processing. When the dual-core control platform detects overvoltage, overcurrent, or control abnormalities, it activates the electronic bypass path composed of bidirectional anti-parallel thyristors. The dual-core control platform adopts a main loop plus interrupt scheduling architecture, and all control modules are independently coded.

2. The power quality regulation method according to claim 1, characterized in that, The three-level inverter with series structure has an output voltage range of 0 to 420 volts. By controlling the amplitude and phase angle of the input voltage on the primary side of the transformer, the output voltage is adjusted in real time to counteract transient voltage drops or overvoltage disturbances in the power supply system. The transformer adopts a YN / open circuit connection method, has a 230-volt input and 58-volt output capability, and effectively isolates voltage disturbance coupling between different sides; The PWM signal on the input side of the transformer is adjusted by a dual-core control platform, so that the output voltage is accurately maintained within the range of ±5 volts of the set reference value, ensuring the quality of voltage waveform and the accuracy of power flow direction control.

3. The power quality regulation method according to claim 1, characterized in that, The dual-core control platform continuously collects the load-side current and uses hardware filters and FPGA preprocessing modules to extract harmonic current, unbalanced components and reactive components. The sampling frequency is not less than 20kHz. The load distortion source is accurately restored by calculating the difference between the bridge-side current sampling signals ICA, ICB, ICC and the grid-side currents IA, IB, IC. Then, dual-channel hardware filtering is used to extract each harmonic component; The amplitude normalization and phase correction process is completed by the ARM module and FPGA module in the dual-core control platform, providing accurate input for the subsequent generation of compensation current.

4. The power quality regulation method according to claim 1, characterized in that, The ARM module uses a 32-bit processor for data acquisition of voltage and current signals, target parameter setting, error threshold management, and communication with the host computer. The FPGA module runs on an independent clock system, performs fast Fourier transform operations, real-time voltage and current calculations, PWM modulation signal generation, fault signal identification and protection response logic processing based on the acquired data, and realizes bidirectional communication with the human-machine interface terminal through RS485 bus. The FPGA module operates on an independent clock system for PWM signal generation, overvoltage and overcurrent protection hardware response, IGBT signal drive logic generation, and all external I / O control and edge detection.

5. The power quality regulation method according to claim 1, characterized in that, Reactive current compensation is based on improved instantaneous power theory, harmonic compensation uses FFT fast frequency domain extraction combined with repetitive control strategy, and three-phase imbalance compensation is achieved based on instantaneous symmetrical coordinate transformation and negative sequence component reverse injection method. All compensation current control strategies have fixed calculation logic preset in the FPGA, while the ARM only transmits the target value and dynamically corrects the error threshold value. The repetitive controller cycle is 20 control cycles, the error threshold is controlled within 1%, and the reference command value is recalibrated every 200ms to ensure real-time tracking capability under stable system operation.

6. The power quality regulation method according to claim 1, characterized in that, The specific steps for extracting harmonic current commands and generating output compensation current are as follows: The current signals in the three-phase AC system are acquired using a high-precision sampling module, ensuring that the sampling frequency is not less than 10 times the PWM update frequency of the dual-core control platform to capture all harmonic components. The sampled data is then sent to the FPGA module to perform a fast Fourier transform operation, as shown in the following formula: In the formula, and The results obtained after Fourier analysis are respectively the first The coefficients of the cosine and sine terms corresponding to the second harmonic. It is the first The amplitude of the second harmonic; The amplitudes of third and higher harmonic components are extracted to determine the actual energy level of each frequency component, based on a pre-set harmonic limit threshold. Calculate the degree of exceedance for each frequency component to obtain the error amount. The calculation expression is as follows: In the formula, It sets the maximum allowable amplitude limit for harmonics. It means the first The difference between the subharmonic and the preset maximum allowable amplitude of the dual-core control platform; To achieve fast and stable compensation current output, the following is introduced: Repeated control strategy, The repetitive control strategy balances response speed and steady-state error control, and the control output is as follows: In the formula, It is the current moment. The generated first The target compensation current for subharmonics. It is the proportional gain coefficient. It is the compensation current command generated in the previous cycle. It is the repeat cycle of the controller. The error occurred in the previous cycle. The integral term within.

7. The power quality regulation method according to claim 1, characterized in that, The electronic bypass switch is composed of two sets of thyristors connected in reverse parallel. When the fault detection module identifies that the bus overvoltage or overcurrent exceeds the critical value, it immediately triggers a bypass command and locks all PWM signal outputs through the controller logic to prevent re-excitation. The electronic bypass path is equipped with a fusible fuse and a surge suppression capacitor.

8. The power quality regulation method according to claim 1, characterized in that, The task scheduling strategy of the dual-core control platform is based on a main loop plus interrupt structure. The main loop executes sampling command scheduling, power calculation, and data recording management. The main interrupt channel is used to handle medium-to-high priority events, including PWM updates, voltage and current error feedback correction, and fault interrupt handling. All interrupt channels have independent priority identifiers and interrupt nesting capabilities, with the highest priority being the fault response processing channel.

9. The power quality regulation method according to claim 1, characterized in that, The control process for real-time adjustment of the output voltage amplitude and phase using a three-level topology inverter connected to a transformer in series is as follows: First, the voltages at both ends of the DC bus are sampled synchronously with high precision to obtain the upper and lower voltages. Then, the average voltage of the DC bus and the voltage difference between the two ends are calculated using the following formula: In the formula, It is the positive terminal voltage of the DC bus. It is the voltage at the negative terminal of the DC bus. It is the average voltage of the DC bus. It is the DC bus voltage difference; To maintain the bus voltage stable near the target value, a PI control algorithm is used to adjust the output voltage command, and its control output is as follows: In the formula, The target voltage is set on the DC bus. It is a direct voltage regulator control output command. It is the integral gain of the PI controller; To suppress unbalanced voltage across the bus, a voltage equalization control signal is calculated. Rapid equalization is achieved by proportionally controlling the voltage difference across the two ends, as shown in the following formula: In the formula, It is the proportional coefficient for pressure equalization control. It is a voltage equalization control command; Based on direct voltage regulation control output command and voltage equalization control commands The synthesized PWM modulation reference signal is given by the following formula: In the formula, It is the final PWM control signal.

10. A power quality conditioning device for implementing the power quality conditioning method according to any one of claims 1-9, characterized in that, It includes a series voltage regulation and power flow control module, a multi-dimensional current analysis and extraction module, a dual-core control and signal processing module, a compensation current generation and inverter drive module, a fast fault bypass protection module, and a scheduling control and module management module. The series voltage regulation and power flow regulation module uses a three-level topology inverter connected to a transformer in series to adjust the output voltage amplitude and phase in real time, thereby realizing voltage compensation and power flow regulation between AC ports in the power supply system. The multi-dimensional current analysis and extraction module starts the three-level topology inverter with parallel structure, detects the load-side current, and separates and extracts the reactive current component, harmonic current component, and three-phase unbalanced current. The dual-core control and signal processing module is based on a dual-core control platform. It uses an ARM processing module for sampling, system power calculation, control command generation and communication with the host computer, and an FPGA module for PWM control signal generation, hardware fault diagnosis and IO logic processing. The compensation current generation and inverter drive module uses a control strategy combining PI control and repetitive control to generate compensation current commands from the extracted reactive, harmonic and unbalanced current commands, and drives the parallel inverter to output compensation current to the grid. The fast fault bypass protection module activates the electronic bypass path composed of bidirectional anti-parallel thyristors when the dual-core control platform detects overvoltage, overcurrent, or control abnormalities, achieving converter bypass protection within one millisecond and ensuring continuous system operation. The scheduling control and module management module of the dual-core control platform adopts a main loop plus interrupt scheduling architecture. All control modules are independently coded to realize real-time parallel scheduling between functional modules, thereby improving the control response speed and overall stability of the dual-core control platform.

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