Improved E1 link PTP time service device

Abstract

The invention relates to an improved E1 link PTP (Precision Time Protocol) timing device. According to the device, a PSoC processor is selected, a PTP protocol is operated on a CPU at the PS end of the processor, an AXI 1G / 2.5 G Ethernet Subsystem IP core responsible for processing MAC of the Ethernet is used in a BD, and a PTP message receiving and sending processing module communicates with a GMII interface of the IP core through the GMII interface; the E1 transceiving processing module completes HDB3 encoding and decoding and mutual conversion between serial data and parallel data, and Ethernet data of a PTP message are sent in full time slots of an E1 link. PL logic resources are adopted in the PSoC processor to optimize hardware design of E1 link PTP time service, a physical Ethernet interface is not adopted for transmitting and receiving PTP messages through the processor, and the influence of uncertain transmitting and receiving delay of a PHY chip on time service precision is reduced.

Description

Technical Field

[0001] This application relates to the field of precision time synchronization technology, and in particular to an improved E1 link PTP time synchronization device. Background Technology

[0002] In the field of time and frequency synchronization, there are many methods, such as BeiDou satellite time synchronization, DC B code, fiber optic B code, NTP network, longwave, and shortwave time synchronization. Any time synchronization method needs to consider the accuracy of the synchronization; the higher the accuracy, the better the application prospects. E1 link PTP (Precision Time Protocol) time synchronization is also a common method. This method uses E1 links to carry PTP service data and follows the IEEE 1588 V2 protocol. Accuracy is a crucial indicator for E1 link PTP time synchronization, and the requirements for accuracy are constantly improving. Currently, E1 link PTP time synchronization accuracy has evolved from typically better than ≤10µs in the past to typically better than ≤1µs now.

[0003] Currently, the conventional methods for E1 link PTP time synchronization are as follows: Figure 1 As shown, the hardware currently mainly uses ARM processors and protocol converters to implement the IEEE 1588v2 scheme. The protocol function is simple to implement, but the timing accuracy of the E1 link PTP is limited by the hardware implementation scheme, and it is difficult to improve the timing accuracy. The hardware design has limitations in improving the timing accuracy.

[0004] The software primarily runs 1588v2 software on the protocol stack or operating system, employing the existing E1 protocol converter principle. When PTP packet transmission occurs, the ARM processor sends the PTP packet to the protocol converter via the Ethernet interface. The protocol converter then forwards the PTP packet from the Ethernet packet to the E1 link. When PTP packet reception occurs, the protocol converter receives the PTP packet from the E1 link, converts it into Ethernet packets, and sends it to the ARM processor. The ARM processor receives the PTP packet and performs corresponding software processing and time synchronization calculations. The local clock uses a standard 65.536MHz crystal oscillator, which is divided by the FPGA of the protocol converter to provide a frequency of 2.048MHz for use by the E1 transceiver control module. The local clock is also used for PTP packet timestamp correction or to generate the timestamp required for PTP packets, and is adjusted and aligned using an external time base 1PPS signal.

[0005] PTP time synchronization on E1 links employs a mature protocol converter that enables bidirectional data conversion between E1 and Ethernet interfaces. Leveraging the mature PTP network time synchronization technology of ARM processors, the ARM processor connects to the Ethernet interface of the protocol converter via its Ethernet interface to achieve PTP time synchronization on E1 links. However, because the E1 line transmission rate is only 2.048 Mbit / s and is a fixed rate, while the Ethernet port transmission rate is 1000 / 100 / 10 Mbit / s, and Ethernet data transmission is intermittent and bursty, the data transmission rate mismatch when PTP Ethernet packets are transmitted to the E1 link results in random time slots for PTP packets. The time slot interval is 3.91 µs. According to the PTP protocol principle, random time slots are equivalent to network latency. The inherent uncertainty of PTP timing, with latency jitter at the microsecond level due to protocol converters, severely impacts PTP timing accuracy, far exceeding the current technical specification of ≤1µs for E1 links. According to the PTP protocol principle, the closer the timestamp of a PTP packet is to the underlying hardware, the higher the PTP timing accuracy. Currently, conventional E1 link PTP timestamps are placed at the MAC layer of the ARM processor, the physical layer of the PHY chip, or the application layer. The lack of timestamps at the underlying E1 link hardware level negatively affects the accuracy of E1 link PTP timing.

[0006] Currently, conventional E1 link PTP timing devices typically use a 65.536MHz quartz crystal as the frequency source to provide signal timing functionality. However, the crystal oscillator frequency is greatly affected by aging and temperature changes, leading to significant timing errors and impacting timing accuracy.

[0007] Conventional E1 master time synchronization devices use a 1PPS time base to provide the local clock. The method for synchronizing the time base in an E1 master time synchronization device is to update the nanosecond count value of the local time based on the clock frequency at the rising edge of the 1PPS time base. Firstly, the adjustment accuracy of the local time is limited by the clock frequency. Secondly, the 1PPS time base itself is subject to jitter. Aligning with the 1PPS time base by continuously adjusting the count value every second can lead to insufficient local clock adjustment accuracy or jitter, thus affecting E1 time synchronization accuracy. This synchronization method also affects the time synchronization accuracy of E1 slave time synchronization devices, and the time synchronization accuracy testing of E1 master-slave time synchronization devices is not straightforward.

[0008] Conventional E1 timing devices use an Ethernet-to-E1 protocol converter for connection. Both the timing device and the protocol converter use PHY chips. The PHY chip is used in both the E1 timing device and the E1 protocol converter, and the uncertain latency of a single PHY chip can introduce an impact of 20-70 nanoseconds. A total of four PHY chips are used in the E1 master-slave timing device link. Considering nanosecond-level timing accuracy, the presence of multiple PHY chips in the hardware circuitry for E1 timing can significantly impact timing accuracy.

[0009] Based on protocol converter technology, when PTP packets are converted and sent from Ethernet to E1 link, the Ethernet PTP packets first need to be identified and parsed. The transmission delay Δt1 of the PTP event message in the protocol converter is measured to calculate the link delay. Then, delay compensation is performed based on the timestamp carried in the event message. In the delay request-response mechanism, the transmission timestamp T1 is adjusted to (T1 + Δt1). This technology can only eliminate the impact of the protocol converter on timing accuracy; it cannot improve the PTP timing accuracy of the E1 link. Even though the ARM processor runs the PTP protocol and implements IEEE 1588v2 with time stamping at the physical layer, resulting in highly accurate timestamp recording, the latency jitter between the two PHY chips connected via Ethernet cannot be eliminated, as the chip's impact on timing accuracy is several tens of nanoseconds. When PTP packets are forwarded and received from the E1 link to the Ethernet, it is necessary to measure the delay Δt2 from the received E1 packet to the Ethernet forwarding. The timestamp of the PTP event message needs to be adjusted to (T2-Δt2). E1 link PTP timing uses protocol converter technology. Measuring and correcting delay within the protocol converter improves timing accuracy at the microsecond level. However, for nanosecond-level timing accuracy, the master and slave devices need to be connected via two protocol converters. Hardware latency jitter within the protocol converters, as well as measurement accuracy and errors within the protocol converters, all negatively impact timing accuracy. Therefore, improving E1 link PTP timing accuracy is the main problem this invention aims to solve, considering nanosecond-level timing accuracy. Summary of the Invention

[0010] Therefore, it is necessary to provide an improved E1 link PTP timing device to address the aforementioned technical problems.

[0011] An improved E1 link PTP timing device includes a PSoC processor, a clock driver module, and an E1 interface module.

[0012] The PL terminal of the PSoC processor is used to measure the time difference between the 1PPS time base and the PTP1588 clock, and obtain the time difference measurement result. It is also used to multiply the reference clock by a PLL and use it as the reference for the PTP1588 clock. Based on the PTP1588 clock reference and the 1PPS time base, the PTP1588 clock is established. It is also used to send and receive Ethernet data of PTP protocol messages using the AXI 1G / 2.5G Ethernet Subsystem IP core. The PTP packet transceiver module and the E1 codec processing module are used to convert the Ethernet data and E1 link data of the PTP protocol messages to each other. In the E1 codec processing module, the received and transmitted PTP messages are re-timestamped according to the PTP1588 clock and the timestamp is recorded.

[0013] The ARM processor on the PS side of the PSoC processor is used to run the PTP protocol and process the AXI 1G / 2.5G Ethernet Subsystem IP core for Ethernet MAC to receive PTP protocol data; it is also used to communicate with the PL side through the AXI4_Lite bus; the DDR3 memory controller on the PS side of the PSoC processor is used to receive and store TOD inputs and transmit the TOD inputs to the ARM processor.

[0014] The clock driver module is used to drive the PTP1588 clock output.

[0015] The E1 interface module is used to send and receive E1 link data.

[0016] In one embodiment, the device further includes an external PLL frequency multiplier module, a temperature-controlled crystal oscillator, a level conversion module, and a DAC module.

[0017] The PS-side ARM processor of the PSoC processor is connected to the DAC module, the DAC module is connected to the voltage control terminal of the thermostatic crystal oscillator, the output terminal of the thermostatic crystal oscillator is connected to the level conversion module, and the level conversion module is connected to the external PLL frequency multiplier module.

[0018] The PLL frequency multiplier module is used to provide the operating clock to the PL terminal of the PSoC processor, and also to provide a reference clock.

[0019] In one embodiment, the PL side of the PSoC processor includes: a 1PPS time difference measurement IP core, an internal PLL frequency multiplier IP core, a PTP1588 clock IP core with an AXI4_Lite bus interface, and a protocol conversion IP core.

[0020] The 1PPS time difference measurement IP core is used to measure the time difference between the 1PPS time base and the PTP1588 clock, obtain the time difference measurement result, and transmit the time difference measurement result to the ARM processor on the PS side via the AXI4_Lite bus.

[0021] The internal PLL multiplier IP core is used to multiply the output of the external PLL multiplier module by PLL and use it as a reference for the PTP1588 clock, and to transmit the PTP1588 clock reference to the PTP1588 clock IP core.

[0022] The PTP1588 clock IP core is used to establish the PTP1588 clock based on the PTP1588 clock reference and the 1PPS time base.

[0023] The protocol conversion IP core is used to communicate with the AXI 1G / 2.5G Ethernet Subsystem IP core through the GMII interface, and to send and receive data on the E1 link through the E1 interface. It is also used to convert PTP protocol packets between MAC and E1 protocols. When sending Ethernet data, it encapsulates PTP protocol packets into serial interface data of a preset format, so as to realize the full-time slot transmission of Ethernet data of PTP messages on the E1 link.

[0024] The ARM processor on the PS side of the PSoC processor is also used to adjust and compensate the PTP1588 clock IP core.

[0025] In one embodiment, the specific steps by which the ARM processor on the PS side of the PSoC processor adjusts and compensates the PTP1588 clock IP core include: During the initial power-on phase of the device, the ARM processor on the PS side of the PSoC processor directly adjusts and modifies the second domain of the PTP1588 clock IP core via the AXI4_Lite bus.

[0026] After the device is working stably, the ARM processor on the PS side of the PSoC processor reads the time difference measurement results from the 1PPS time difference measurement IP core through the AXI4_Lite bus, and adjusts the nanoseconds of the PTP1588 clock IP core according to the time difference measurement results through the AXI4_Lite bus.

[0027] Based on the time difference measurement results, the DAC module is controlled by the EMO, and finally the temperature-controlled crystal oscillator is tamed by the PID algorithm to compensate for the nanosecond fractional domain of the PTP1588 clock IP core.

[0028] In one embodiment, the protocol conversion IP core includes a PTP message transmission and reception processing module and an E1 encoding and decoding processing module.

[0029] When sending Ethernet packets: The PTP message transceiver processing module and the E1 codec processing module parse the Ethernet packets received from the AXI 1G / 2.5GEthernet Subsystem IP core through the GMII interface to obtain HDB3 code data. In the E1 codec processing module, event messages that meet the PTP protocol type are re-timestamped according to the PTP1588 clock. After the timestamp is applied, the CRC32 check is recalculated, and the timestamp is stored in the PTP1588 clock register. The PS-side ARM processor of the PSoC processor reads the transmission timestamp of the PTP event message through the AXI4_Lite bus, and then sends the HDB3 code data to the E1 link through the E1 interface module.

[0030] When receiving Ethernet packets: The E1 codec processing module receives HDB3 code data from the E1 interface module. It parses the PTP event message, records the reception time of the event message according to the PTP1588 clock, and stores the reception time in the PTP1588 clock register. The PS-side ARM processor reads the reception timestamp of the PTP event message via the AXI4_Lite bus. The E1 codec processing module restores the parsed Ethernet packet data from serial data to parallel data and sends it to the PTP message transceiver processing module's buffer. Then, the PTP message transceiver processing module sends the Ethernet packet data to the AXI 1G / 2.5G Ethernet Subsystem IP core.

[0031] In one embodiment, the serial interface data in the preset format is: a pre-frame flag, an Ethernet frame, and a post-frame flag.

[0032] An Ethernet frame includes: an HDLC frame header, an Ethernet frame start delimiter, a destination address, a source address, a protocol type, PTP message data, a CRC32 checksum, and an HDLC frame header.

[0033] Pre-frame and post-frame flags are not allowed to appear within a frame; they are implemented using 0-bit insertion.

[0034] In one embodiment, the temperature-controlled crystal oscillator is a 10MHz temperature-controlled crystal oscillator with a frequency stability on the order of E-12.

[0035] In one embodiment, the external PLL frequency multiplier module includes a first PLL frequency multiplier module and a second PLL frequency multiplier module.

[0036] The first PLL frequency multiplier module is used to multiply the signal output from the temperature-controlled crystal oscillator to a first frequency signal, providing a working clock for the protocol conversion IP core.

[0037] The second PLL frequency multiplier module is used to multiply the signal output by the temperature-controlled crystal oscillator to a second frequency signal, and transmit the second frequency information to the 1PPS time difference measurement IP core as a working clock. It also transmits the second frequency information to the internal PLL frequency multiplier IP core as a reference clock.

[0038] In one embodiment, when the device is the main time synchronization device: the 1PPS time base is standard time information input from the TOD.

[0039] When the device is a slave timekeeping device: the 1PPS time reference is output from the master timekeeping device.

[0040] The improved E1 link PTP timing device described above utilizes a PSoC processor. The PTP protocol runs on the CPU at the processor's PS end, and the BD uses an AXI 1G / 2.5G Ethernet Subsystem IP core responsible for handling Ethernet MAC. The PTP packet transceiver processing module communicates with the IP core via the GMII interface. The E1 transceiver processing module performs HDB3 encoding / decoding and serial-to-parallel data conversion, transmitting the Ethernet data of the PTP packets across all time slots of the E1 link. The hardware design for E1 link PTP timing is optimized by using PL logic resources within the PSoC processor. The processor does not use a physical Ethernet interface for PTP packet transmission and reception, reducing the impact of PHY chip transmission / reception delay uncertainty on timing accuracy. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of an existing E1 link PTP time synchronization device. Figure 2 This is a structural block diagram of an improved E1 link PTP timing device in one embodiment; Figure 3 This is a schematic block diagram of an improved E1 link PTP timing device in another embodiment; Figure 4 This is a schematic diagram illustrating the generation and use of the PTP1588 clock in another embodiment; Figure 5 This is a schematic diagram of the clock timing composition of the PTP1588 in another embodiment; Figure 6 This is a schematic diagram of the E1 link PTP timing accuracy system test system in another embodiment; Figure 7 This is a schematic diagram of the synchronization accuracy of the E1 master time synchronization device in another embodiment; Figure 8 This is a schematic diagram of the timing accuracy of the E1 master-slave clock device in another embodiment. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0043] E1 link PTP time synchronization uses the 1588v2 protocol to transmit Ethernet PTP packets over the E1 link, enabling E1 master and slave time synchronization devices to achieve frequency and phase synchronization. The E1 master and slave time synchronization devices achieve synchronization through message exchange. To improve the accuracy of E1 link PTP time synchronization, the accuracy of synchronization between the E1 master time synchronization device and the time base must first be addressed. The higher the synchronization accuracy between the E1 master time synchronization device and the time base using PTP time synchronization, the higher the time synchronization accuracy will be. Next, the impact of the variable time slots for PTP message transmission on the E1 link on time synchronization accuracy must be addressed, as well as the impact of nanosecond-level latency jitter caused by conventional hardware components on time synchronization accuracy.

[0044] There are three key technical aspects to improving the timing accuracy of the E1 link PTP. First, after counting the master-slave time deviation using the PTP message protocol, frequency synchronization between the master and slave needs to be achieved. This involves establishing a PTP1588 clock within the FPGA on the PSoC processor's PL side to improve the synchronization accuracy between the PTP1588 clock and the 1PPS time base, as well as the synchronization accuracy within seconds between the master and slave clocks. Second, addressing the impact of link latency jitter caused by the mismatch between the Ethernet packets in the PTP messages and the 2M link transmission rate when the ARM processor on the PS side runs the IEEE 1588v2 protocol. Third, reducing the impact of device latency uncertainty on timing accuracy.

[0045] In one embodiment, such as Figure 2 As shown, an improved E1 link PTP timing device is provided, which includes: a PSoC processor 10, a clock driver module 20, and an E1 interface module 30.

[0046] The PL terminal of the PSoC processor 10 is used to measure the time difference between the 1PPS time base and the PTP1588 clock, and obtain the time difference measurement result; it is also used to multiply the reference clock by a PLL and use it as a reference for the PTP1588 clock, and establish the PTP1588 clock based on the PTP1588 clock reference and the 1PPS time base; it is also used to send and receive Ethernet data of PTP protocol messages using the AXI 1G / 2.5G EthernetSubsystem IP core, and to convert the Ethernet data and E1 link data of PTP protocol messages to each other using the PTP packet transceiver module and the E1 codec processing module. In the E1 codec processing module, the received and transmitted PTP messages are re-timestamped according to the PTP1588 clock and the timestamp is recorded.

[0047] Specifically, the PTP1588 clock established internally at the PL end of the PSoC processor 10 is used to time-stamp PTP messages in the E1 transceiver module. The time-stamping is performed at the E1 serial data transceiver layer, which reduces the impact of device delay uncertainty and further improves the PTP timing accuracy of the E1 link.

[0048] The 1PPS time reference of the PTP1588 clock output and the 1PPS time reference of the standard time are measured by TDC using the FPGA logic resources of the PSoC processor 10. The temperature-controlled crystal oscillator is tamed by the TDC measurement results, which improves the synchronization accuracy between the E1 timing master clock and the time reference. Improving the synchronization accuracy of the E1 timing master clock and the adjustment accuracy of the PTP1588 clock can improve the PTP timing accuracy of the E1 link.

[0049] The ARM processor on the PS side of the PSoC processor 10 is used to run the PTP protocol and process the AXI1G / 2.5G Ethernet Subsystem IP core of Ethernet MAC to receive PTP protocol data; it is also used to communicate with the PL side through the AXI4_Lite bus. The DDR3 memory controller on the PS side of the PSoC processor is used to receive and store TOD inputs and transmit the TOD inputs to the ARM processor.

[0050] The clock driver module 20 is used to drive the PTP1588 clock output.

[0051] E1 interface module 30 is used to send and receive E1 link data.

[0052] Specifically, PTP is a protocol for time synchronization over a network, and the PTP network timing technology implemented by ARM processors is already very mature. To improve the PTP timing accuracy of the E1 link, without changing the condition that IEEE 1588v2 runs on the ARM processor through the lwip protocol stack or operating system, it is necessary to optimize the hardware design to reduce the impact of device delay uncertainty on timing accuracy. The hardware design improvements include: (1) Selecting a PSoC processor, with IEEE 1588v2 running on the ARM processor at the PS end of the PSoC processor 10, without modifying the 1588v2 software, and sending and receiving PTP protocol message data packets through MAC (Media Access Control). (2) Calling the AXI 1G / 2.5GEthernet Subsystem IP core in the Block Design of the PSoC processor 10, which implements the hardware function of Ethernet MAC, and the physical interface is selected as the GMII interface. (3) Fix the MAC rate to 1000 Mbit / s on the lwip protocol stack or operating system, use a 125 MHz clock, and make the MAC data an 8-bit byte data stream to facilitate the subsequent parallel-to-serial conversion of Ethernet PTP packets and E1 link data. (4) Design GMII and E1 interface protocol conversion modules on the PL end. The GMII interface of the protocol conversion module is connected to the AXI 1G / 2.5G Ethernet Subsystem IP core, and the E1 interface module is used for 2M data transmission and reception.

[0053] Compared to using dedicated ARM processors and FPGA chips, the PSoC processor 10 can integrate processing, completing the conversion of PTP protocol data packets between MAC and E1 protocols at the PL end. This hardware design method is very convenient for handling data transmission across clock domains. The PTP message transceiver processing module transmits and receives Ethernet data of PTP protocol messages through the GMII interface from the AXI 1G / 2.5G Ethernet Subsystem IP core, optimizing the hardware design of the Ethernet interface PHY chip and reducing the impact of PHY chip delay uncertainty on timing accuracy.

[0054] In the improved E1 link PTP timing device described above, the device uses a PSoC processor, with the PTP protocol running on the CPU at the processor's PS end. The BD uses an AXI 1G / 2.5G EthernetSubsystem IP core responsible for handling Ethernet MAC. The PTP packet transceiver processing module communicates with the IP core's GMII interface. The E1 transceiver processing module completes HDB3 encoding / decoding and serial-to-parallel data conversion, transmitting the Ethernet data of the PTP packets across all time slots of the E1 link. The hardware design for E1 link PTP timing is optimized by using PL logic resources within the PSoC processor. The processor does not use a physical Ethernet interface for transmitting and receiving PTP packets, reducing the impact of PHY chip transmission / reception delay uncertainty on timing accuracy.

[0055] In one embodiment, such as Figure 3 The device also includes an external PLL frequency multiplier module, a temperature-controlled crystal oscillator, a level conversion module, and a DAC module.

[0056] The PS-side ARM processor of the PSoC processor is connected to the DAC module, the DAC module is connected to the voltage control terminal of the thermostatic crystal oscillator, the output terminal of the thermostatic crystal oscillator is connected to the level conversion module, and the level conversion module is connected to the external PLL frequency multiplier module.

[0057] The PLL frequency multiplier module is used to provide the operating clock to the PL terminal of the PSoC processor, and also to provide a reference clock.

[0058] Specifically, the temperature-controlled crystal oscillator is multiplied to 65.536MHz to provide a stable, low-jitter clock for the E1 encoding and decoding, and the temperature-controlled crystal oscillator is multiplied to 125MHz to provide a clock for the PTP message transceiver processing module.

[0059] A temperature-controlled crystal oscillator with a frequency stability of E-12 is used. The PTP1588 clock is provided with a frequency reference through external frequency multiplication and PLL multiplication inside the PSoC processor. A high-stability and high-precision PTP1588 clock is established inside the FPGA, which can provide high-resolution timestamps for PTP messages.

[0060] The E1 timing slave clock directly adjusts the master-slave time deviation of the PTP1588 clock via the AXI4-lite bus. The intrasecond deviation is improved by compensating for the PTP1588 clock and disciplining the temperature-controlled crystal oscillator to improve the synchronization accuracy of the E1 timing master-slave clock. Under the conditions of short-distance and symmetrical delay in E1 link transmission, the long-term operation performance can be better than ≤100ns, which is far higher than the current industry requirements for the accuracy of E1 link PTP timing.

[0061] In one embodiment, such as Figure 3As shown, the PL side of the PSoC processor includes: a 1PPS time difference measurement IP core, an internal PLL frequency multiplier IP core, a PTP1588 clock IP core with an AXI4_Lite bus interface, and a protocol conversion IP core.

[0062] The 1PPS time difference measurement IP core is used to measure the time difference between the 1PPS time base and the PTP1588 clock, obtain the time difference measurement result, and transmit the time difference measurement result to the ARM processor on the PS side via the AXI4_Lite bus.

[0063] The internal PLL multiplier IP core is used to multiply the output of the external PLL multiplier module by PLL and use it as a reference for the PTP1588 clock, and to transmit the PTP1588 clock reference to the PTP1588 clock IP core.

[0064] The PTP1588 clock IP core is used to establish the PTP1588 clock based on the PTP1588 clock reference and the 1PPS time base.

[0065] The protocol conversion IP core is used to communicate with the AXI 1G / 2.5G Ethernet Subsystem IP core through the GMII interface, and to send and receive data on the E1 link through the E1 interface. It is also used to convert PTP protocol packets between MAC and E1 protocols. When sending Ethernet data, it encapsulates PTP protocol packets into serial interface data of a preset format, so as to realize the full-time slot transmission of Ethernet data of PTP messages on the E1 link.

[0066] The ARM processor on the PS side of the PSoC processor is also used to adjust and compensate the PTP1588 clock IP core.

[0067] Specifically, by measuring the time difference at a high precision of 1PPS at the PL end, a temperature-controlled crystal oscillator is tamed. Utilizing the short-term stability characteristics of the temperature-controlled crystal oscillator, a high-precision, low-jitter PTP1588 clock is established. The ARM processor at the PS end directly adjusts and modifies the PTP1588 clock in the second domain via the AXI4_Lite bus, and performs time difference compensation in the nanosecond domain. For nanosecond domains exceeding the compensation accuracy, the method of taming the temperature-controlled crystal oscillator is used to synchronize the frequency and time of the master and slave clocks. By establishing the PTP1588 clock at the PL end, the synchronization accuracy and timing accuracy of the E1 timing device can be further improved.

[0068] In one embodiment, the specific steps by which the ARM processor on the PS side of the PSoC processor adjusts and compensates the PTP1588 clock IP core include: During the initial power-on phase of the device, the ARM processor on the PS side of the PSoC processor directly adjusts and modifies the second domain of the PTP1588 clock IP core via the AXI4_Lite bus.

[0069] After the device is working stably, the ARM processor on the PS side of the PSoC processor reads the time difference measurement results from the 1PPS time difference measurement IP core through the AXI4_Lite bus, and adjusts the nanoseconds of the PTP1588 clock IP core according to the time difference measurement results through the AXI4_Lite bus.

[0070] Based on the time difference measurement results, the DAC module is controlled by the EMO, and finally the temperature-controlled crystal oscillator is tamed by the PID algorithm to compensate for the nanosecond fractional domain of the PTP1588 clock IP core.

[0071] Specifically, improving the PTP timing accuracy of the E1 link requires establishing a high-precision PTP1588 clock for processing PTP message timestamps. The frequency source of the PTP1588 clock must consider frequency stability and clock jitter. The PTP1588 clock also needs to address the synchronization accuracy with the time reference; insufficient synchronization will affect timing accuracy. The generation and use of the PTP1588 clock are as follows... Figure 4 As shown, a 10MHz thermostatic crystal oscillator with frequency stability in the E-12 range is used as the frequency source of the E1 timing device. The 10MHz output of the thermostatic crystal oscillator is multiplied to 125MHz externally by a PLL. The internal PLL clock IP core is called at the PL end to multiply the 125MHz to 400MHz as a reference for the PTP1588 clock. The generation and use of the PTP1588 clock of the E1 main timing device is as follows: (1) Design an IP core for 1PPS time difference measurement with an AXI4_Lite bus interface at the PL end. The 1PPS time difference measurement adopts the time interval measurement (TDC) method to measure the intrasecond deviation between the 1PPS output of the PTP1588 clock and the 1PPS time reference. (2) Design a PTP1588 clock IP core with an AXI4_Lite bus interface at the PL end, and provide a port output to the E1 transceiver processing module for the E1 transceiver processing module to add time stamps to the PTP messages. (3) The PTP1588 clock uses a 48-bit second field, a 32-bit nanosecond field, and a nanosecond fractional field, such as Figure 5 The diagram shows the clock time composition of the PTP1588.

[0072] During the initial power-up phase of the E1 time synchronization device, the PS-side ARM processor converts the standard time information input from TOD into the total number of seconds in Coordinated Universal Time (UTC) after the rising edge of the 1PPS time base. This is then directly adjusted to change the second domain of the PTP1588 clock IP core via the AXI4_Lite bus. Once the E1 time synchronization device is operating stably, the value of the second domain register is simply read from the AXI4_Lite bus and compared with the standard time. The IP core's second domain register value is only readjusted when there are changes in seconds. The PS-side ARM processor reads the deviation between the PTP1588 clock and the 1PPS time base within seconds from the 1PPS time difference measurement IP core via the AXI4_Lite bus. Then, it compensates for and adjusts the nanosecond domain of the PTP1588 clock IP core via the AXI4_Lite bus. The PTP1588 clock frequency reference is 400MHz, and the nanosecond domain compensation adjustment accuracy is 2.5 nanoseconds. The 1PPS time difference measurement IP core achieves a measurement accuracy of 50 picoseconds. Nanosecond fractional-domain adjustment is achieved by the PS-side ARM processor controlling the DAC module via EMIO, and finally using a PID algorithm to discipline the cryogenic crystal oscillator, ensuring nanosecond-level time synchronization between the 1PPS signal output from the PTP1588 clock and the 1PPS time reference signal. After the E1 main time synchronization device's PTP1588 clock is accurately synchronized with the standard time, subsequent adjustments to the PTP1588 clock can be reduced by disciplining the cryogenic crystal oscillator.

[0073] In one embodiment, the protocol conversion IP core includes a PTP message transmission and reception processing module and an E1 encoding and decoding processing module.

[0074] When sending Ethernet packets: The PTP message transceiver processing module and the E1 codec processing module parse the Ethernet packets received from the AXI 1G / 2.5GEthernet Subsystem IP core through the GMII interface to obtain HDB3 code data. In the E1 codec processing module, event messages that meet the PTP protocol type are re-timestamped according to the PTP1588 clock. After the timestamp is applied, the CRC32 check is recalculated, and the timestamp is stored in the PTP1588 clock register. The PS-side ARM processor of the PSoC processor reads the transmission timestamp of the PTP event message through the AXI4_Lite bus, and then sends the HDB3 code data to the E1 link through the E1 interface module.

[0075] When receiving Ethernet packets: The E1 codec processing module receives HDB3 code data from the E1 interface module. It parses the PTP event message, records the reception time of the event message according to the PTP1588 clock, and stores the reception time in the PTP1588 clock register. The PS-side ARM processor reads the reception timestamp of the PTP event message via the AXI4_Lite bus. The E1 codec processing module restores the parsed Ethernet packet data from serial data to parallel data and sends it to the PTP message transceiver processing module's buffer. Then, the PTP message transceiver processing module sends the Ethernet packet data to the AXI 1G / 2.5G Ethernet Subsystem IP core.

[0076] In one embodiment, the serial interface data in the preset format is: a pre-frame flag, an Ethernet frame, and a post-frame flag.

[0077] An Ethernet frame includes: an HDLC frame header, an Ethernet frame start delimiter, a destination address, a source address, a protocol type, PTP message data, a CRC32 checksum, and an HDLC frame header.

[0078] Pre-frame and post-frame flags are not allowed to appear within a frame; they are implemented using 0-bit insertion.

[0079] Specifically, IEEE 1588v2 runs on the lwip protocol stack or operating system at the PS end. Without modifying the software operating mechanism, it requires the conversion between Ethernet frame format data and the E1 protocol. During protocol conversion, the data transmission rate of the Ethernet frame format does not match the E1 link rate. This rate mismatch will cause link latency jitter. A one-slot deviation on the link will result in a 3.91µs delay. Uncertainty: A clock jitter of 2.048MHz produces 488 nanoseconds. Jitter is addressed by the PTP protocol through calculation of link latency. Uncertainty and jitter exist, which greatly affect the accuracy of time synchronization. When PTP message data is encapsulated into Ethernet packets for transmission and reception on the E1 link, in order to reduce the impact of link delay jitter caused by the random transmission time slots of PTP messages on the E1 link and to make the most of the effective bandwidth of E1, PTP messages are transmitted in all time slots of E1. The data transmission format of the E1 link is shown in Table 1.

[0080] Table 1 E1 Link Transmission Data Format

[0081] On the PS-side lwip protocol stack or operating system, PTP packet data is processed and transmitted / received in Ethernet frame format. When sending Ethernet data from the "AXI 1G / 2.5G Ethernet Subsystem" IP core, the PTP packet transceiver module and E1 codec processing module convert the Ethernet data sent by the IP core into serial interface data that meets E1 communication requirements. The serial data conforms to the High-Level Data Link Control (HDLC) protocol. Each frame has a flag code 0x7E at the beginning and end, used for frame start and end indications and frame synchronization. The flag code is not allowed to appear inside the frame to avoid ambiguity. To ensure the uniqueness of the flag code while maintaining the transparency of the data within the frame, a "0-bit insertion method" can be used. The "0-bit insertion method" is simple in principle and well-suited for hardware implementation. When sending Ethernet packets, the PTP packet transceiver module parses the Ethernet packets, re-timestamps event messages that meet the PTP protocol type according to the PTP1588 clock, recalculates the CRC32 checksum after timestamping, and stores the timestamp in the PTP1588 clock register. The PS-side ARM processor can read the sending timestamp of the PTP event message through the AXI4_Lite bus, and then send the HDB3 code data to the E1 link through the E1 interface circuit. When receiving Ethernet packets, the E1 codec processing module receives HDB3 code data from the E1 interface circuit. The E1 codec processing module parses the PTP event message, records the reception time of the event message according to the PTP1588 clock, and stores the reception time in the PTP1588 clock register. The PS-side ARM processor can read the reception timestamp of the PTP event message via the AXI4_Lite bus. The E1 codec processing module restores the parsed Ethernet packet data from serial data to parallel data and sends it to the PTP message transceiver processing module buffer. Then, it sends the Ethernet packet data to the "AXI 1G / 2.5G Ethernet Subsystem" IP core. By transmitting the Ethernet data of the PTP message in the full time slot of the E1 link, and the E1 link codec re-timestamps and records the timestamps of the transmitted and received PTP messages according to the PTP1588 clock, the impact of inconsistent hardware transmission link delay and jitter from the PTP protocol layer to the HDB3 code transceiver position is resolved, further improving the PTP timing accuracy of the E1 link.

[0082] In one embodiment, the temperature-controlled crystal oscillator is a 10MHz temperature-controlled crystal oscillator with a frequency stability on the order of E-12.

[0083] In one embodiment, the external PLL frequency multiplier module includes a first PLL frequency multiplier module and a second PLL frequency multiplier module.

[0084] The first PLL frequency multiplier module is used to multiply the signal output from the temperature-controlled crystal oscillator to a first frequency signal, providing a working clock for the protocol conversion IP core.

[0085] The second PLL frequency multiplier module is used to multiply the signal output by the temperature-controlled crystal oscillator to a second frequency signal, and transmit the second frequency information to the 1PPS time difference measurement IP core as a working clock. It also transmits the second frequency information to the internal PLL frequency multiplier IP core as a reference clock.

[0086] In one embodiment, when the device is the main time synchronization device: the 1PPS time base is standard time information input from the TOD.

[0087] When the device is a slave timekeeping device: the 1PPS time reference is output from the master timekeeping device.

[0088] Specifically, the E1 slave clock generation and usage method of the PTP1588 timing device is similar to that of the master timing device, except that the TOD input is converted into the master-slave time deviation value counted through the PTP protocol. The second and nanosecond domains of the PTP1588 clock IP core can be directly adjusted via the AXI4_Lite bus. For the part exceeding the nanosecond domain compensation accuracy, a PID algorithm is used to discipline the temperature-controlled crystal oscillator to achieve nanosecond-level time synchronization.

[0089] In a verification embodiment, a test system is constructed to test and verify the E1 link PTP timing accuracy. The constructed E1 link PTP timing accuracy test system is as follows: Figure 6 As shown, the 1PPS clock output of the PTP1588 of the E1 timing device is output externally through the BNC interface, which is very convenient for testing the timing accuracy and synchronization accuracy.

[0090] (1) The pulse distribution amplifier distributes and amplifies the 1PPS time base to 16 outputs. The channel consistency of the pulse distribution amplifier output is better than ≤30ps. One of them is used as the external reference 1PPS input of the 16-channel time interval counter, and the other is used as the 1PPS time base input of the master clock.

[0091] (2) The E1 timing master clock device acquires the standard time through the TOD input, and then the software adjusts the local time of the PTP1588 clock according to the standard time. Using the 1PPS time reference output by the distribution amplifier, the software adjusts the synchronization accuracy between the 1PPS output of the PTP1588 clock and the 1PPS time reference. The phase difference between the 1PPS output of the PTP1588 clock of the E1 timing master clock device and the 1PPS time reference of the standard time is as follows: Figure 7As shown, the phase difference test result (standard deviation: 6.23ns) is the synchronization accuracy between the E1 timing master clock device and the 1PPS time reference of the standard time.

[0092] (3) The 16-channel time interval counter has a measurement accuracy better than ≤50ps, channel consistency better than ≤50ps, and a measurement resolution of 1ps. An external reference of 10MHz is used as the frequency source input for the counter to improve measurement accuracy. The 16-channel time interval counter allows observation and measurement of the phase difference between the 1PPS clock output of the E1 timing master clock device and the 1PPS time reference of the standard time. The phase difference test result represents the synchronization accuracy between the E1 timing master clock device and the 1PPS time reference of the standard time. The synchronization accuracy of the E1 master timing device is as follows: Figure 7 As shown. Simultaneously, the 1PPS output from the E1 timing slave clock device PTP1588 is connected to a counter. The phase difference between the 1PPS outputs of the E1 timing master and slave clock devices PTP1588 can be observed and measured from the counter. The phase difference test result (standard deviation: 45.23ns) represents the time synchronization accuracy of the E1 timing master and slave clock devices. The timing accuracy of the E1 master and slave clock devices is as follows: Figure 8 As shown.

[0093] (4) The SyncEdge time and frequency synchronization analyzer is used to test whether the master and slave clocks are synchronized in seconds, and can determine whether the E1 link PTP time synchronization is working properly.

[0094] By modifying the configuration of the E1 timing device to use an E2E mode delay mechanism and Ethernet packet encapsulation method, the master-slave timing accuracy of the E1 timing device was measured using a one-step method. Figure 8 As shown, the timing accuracy is within 260 nanoseconds. Further testing verified the stability and reliability of the PTP timing on the E1 link of this device, and the master-slave timing accuracy testing is convenient. The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the scope of protection of this application.

Claims

1. An improved E1 link PTP timing device, characterized in that, The device includes: a PSoC processor, a clock drive module, and an E1 interface module; The PL terminal of the PSoC processor is used to measure the time difference between the 1PPS time base and the PTP1588 clock, and obtain the time difference measurement result; it is also used to multiply the reference clock by a PLL and use it as the reference for the PTP1588 clock, and establish the PTP1588 clock based on the PTP1588 clock reference and the 1PPS time base; it is also used to send and receive Ethernet data of PTP protocol messages using the AXI 1G / 2.5G EthernetSubsystem IP core, and to convert the Ethernet data and E1 link data of the PTP protocol messages to each other using the PTP packet transceiver module and the E1 codec processing module. In the E1 codec processing module, the received and transmitted PTP messages are re-timestamped according to the PTP1588 clock and the timestamp is recorded. The ARM processor on the PS side of the PSoC processor is used to run the PTP protocol and process the AXI 1G / 2.5G Ethernet Subsystem IP core of Ethernet MAC to receive PTP protocol data; it is also used to communicate with the PL side through the AXI4_Lite bus; the DDR3 memory controller on the PS side of the PSoC processor is used to receive and store TOD inputs and transmit the TOD inputs to the ARM processor. The clock driving module is used to drive the PTP1588 clock output. The E1 interface module is used to send and receive E1 link data.

2. The apparatus according to claim 1, characterized in that, The device also includes an external PLL frequency multiplier module, a temperature-controlled crystal oscillator, a level conversion module, and a DAC module; The PS-side ARM processor of the PSoC processor is connected to the DAC module, the DAC module is connected to the voltage-controlled terminal of the thermostatic crystal oscillator, the output terminal of the thermostatic crystal oscillator is connected to the level conversion module, and the level conversion module is connected to the external PLL frequency multiplier module. The PLL frequency multiplier module is used to provide a working clock to the PL terminal of the PSoC processor, and also to provide the reference clock.

3. The apparatus according to claim 2, characterized in that, The PSoC processor's PL side includes: a 1PPS time difference measurement IP core, an internal PLL frequency multiplier IP core, a PTP1588 clock IP core with an AXI4_Lite bus interface, and a protocol conversion IP core; The 1PPS time difference measurement IP core is used to measure the time difference between the 1PPS time base and the PTP1588 clock, obtain the time difference measurement result, and transmit the time difference measurement result to the ARM processor at the PS end through the AXI4_Lite bus; The internal PLL multiplier IP core is used to multiply the output of the external PLL multiplier module by PLL and use it as a reference for the PTP1588 clock, and to transmit the PTP1588 clock reference to the PTP1588 clock IP core. The PTP1588 clock IP core is used to establish the PTP1588 clock based on the PTP1588 clock reference and the 1PPS time base. The protocol conversion IP core is used to communicate with the AXI 1G / 2.5G Ethernet Subsystem IP core through the GMII interface, and to send and receive data on the E1 link through the E1 interface; it is also used to convert PTP protocol data packets between MAC and E1 protocol, and when sending Ethernet data, it encapsulates the PTP protocol data packets into serial interface data of a preset format, so as to realize the full-time slot transmission of Ethernet data of PTP messages on the E1 link; The ARM processor on the PS side of the PSoC processor is also used to adjust and compensate the PTP1588 clock IP core.

4. The apparatus according to claim 3, characterized in that, The specific steps by which the ARM processor on the PS side of the PSoC processor adjusts and compensates the PTP1588 clock IP core include: During the initial power-on phase of the device, the ARM processor on the PS side of the PSoC processor directly adjusts and modifies the second domain of the PTP1588 clock IP core via the AXI4_Lite bus. After the device is working stably, the ARM processor on the PS side of the PSoC processor reads the time difference measurement result from the 1PPS time difference measurement IP core through the AXI4_Lite bus, and adjusts the nanosecond of the PTP1588 clock IP core according to the time difference measurement result through the AXI4_Lite bus. Based on the time difference measurement results, the DAC module is controlled by the EMO, and finally the temperature-controlled crystal oscillator is tamed by the PID algorithm to compensate the nanosecond fractional domain of the PTP1588 clock IP core.

5. The apparatus according to claim 3, characterized in that, The protocol conversion IP core includes: a PTP packet transceiver processing module and an E1 encoding / decoding processing module; When sending Ethernet packets: The PTP message transceiver processing module and the E1 codec processing module parse the Ethernet data packets received from the AXI 1G / 2.5G Ethernet Subsystem IP core through the GMII interface to obtain HDB3 code data. In the E1 codec processing module, event messages that meet the PTP protocol type are re-timestamped according to the PTP1588 clock. After the timestamp is applied, the CRC32 check is recalculated, and the timestamp is stored in the PTP1588 clock register. The PS-side ARM processor of the PSoC processor reads the transmission timestamp of the PTP event message through the AXI4_Lite bus, and then sends the HDB3 code data to the E1 link through the E1 interface module. When receiving Ethernet packets: The E1 codec processing module receives HDB3 code data from the E1 interface module. It parses the PTP event message, records the reception time of the event message according to the PTP1588 clock, and stores the reception time in the PTP1588 clock register. The PS-side ARM processor reads the reception timestamp of the PTP event message via the AXI4_Lite bus. The E1 codec processing module restores the parsed Ethernet packet data from serial data to parallel data and sends it to the PTP message transceiver processing module's buffer. Then, the PTP message transceiver processing module sends the Ethernet packet data to the AXI 1G / 2.5G Ethernet Subsystem IP core.

6. The apparatus according to claim 3, characterized in that, The serial interface data in the preset format consists of: a pre-frame flag, an Ethernet frame, and a post-frame flag. The Ethernet frame includes: HDLC frame header, Ethernet frame start delimiter, destination address, source address, protocol type, PTP message data, CRC32 checksum, and HDLC frame header; The pre-frame flag and post-frame flag are not allowed to appear within the frame; they are implemented using a 0-bit insertion method.

7. The apparatus according to claim 2, characterized in that, The temperature-controlled crystal oscillator is a 10MHz temperature-controlled crystal oscillator with a frequency stability on the order of E-12.

8. The apparatus according to claim 3, characterized in that, The external PLL frequency multiplier module includes a first PLL frequency multiplier module and a second PLL frequency multiplier module; The first PLL frequency multiplier module is used to multiply the signal output by the temperature-controlled crystal oscillator to a first frequency signal, providing a working clock for the protocol conversion IP core; The second PLL frequency multiplier module is used to multiply the signal output by the isothermal crystal oscillator to a second frequency signal, and transmit the second frequency information to the 1PPS time difference measurement IP core as a working clock, and also transmit the second frequency information to the internal PLL frequency multiplier IP core as a reference clock.

9. The apparatus according to claim 1, characterized in that, When the device is the main time synchronization device: the 1PPS time reference is standard time information input from the TOD; When the device is a slave timekeeping device: the 1PPS time reference is output from the master timekeeping device.

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