Ultrathin solar cell with selective polycrystalline silicon passivation contact and preparation method

Abstract

The invention discloses an ultrathin solar cell with selective polycrystalline silicon passivation contact and a preparation method thereof. The preparation method comprises the following steps: forming a boron-doped emitter on the surface of an N-type monocrystalline silicon wafer; performing ablation treatment on a partial region of the back surface of the silicon wafer to form a sunken structure; polishing and etching the back surface of the silicon wafer to form a plurality of patterned structures; preparing a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer on the back surface of the silicon wafer; removing the tunneling oxide layer and the doped polycrystalline silicon layer in the non-metal contact area on the back surface of the silicon wafer; according to the method, the silicon wafer cost can be saved, the manufactured ultrathin solar cell has good flexibility, the current value of the cell is increased, and more efficient transmission of carriers in the cell is facilitated.

Description

Technical Field

[0001] This invention belongs to the field of ultrathin solar cells, specifically relating to an ultrathin solar cell with selective polycrystalline silicon passivated contacts and its preparation method. Background Technology

[0002] The emergence of TOPCon tunneling oxide passivated contact solar cells has attracted significant attention to high-efficiency crystalline silicon solar cell technology. TOPCon cells use N-type silicon as the substrate material and consist of an ultrathin silicon oxide layer and a highly doped polycrystalline silicon layer. Because the tunneling potential of the tunneling oxide layer (4.5 eV) is higher than the electron tunneling potential (3.1 eV), it reduces carrier recombination between the metal electrode and silicon, making it easier for electrons to tunnel and be collected. Another function of the tunneling oxide layer is full-area passivation; its excellent passivation capability further improves the efficiency of TOPCon solar cells. Currently, the photoelectric conversion efficiency record for TOPCon cells has exceeded 26.5%.

[0003] Since 2023, the photovoltaic industry has faced overcapacity issues, and cost reduction and efficiency improvement have become the main themes of solar cell development. Research has shown that ultra-thin solar cells, which are one-third the thickness of conventional solar cells, have unique potential. While efficiently converting solar energy into electrical energy, they also achieve cost advantages through material savings. At the same time, ultra-thin solar cells have good flexibility and can be bent or rolled, which allows them to be installed on surfaces with various complex shapes. In addition, because the carrier transport path is shorter during the lifetime of ultra-thin solar cells, it helps to reduce the problem of shortened carrier lifetime caused by substrate defects.

[0004] Currently, advanced crystalline silicon solar cells generally have a thickness ranging from 110µm to 150µm. Based on different technological approaches, they can be broadly categorized into TOPCon, HJT, and BC types. TOPCon cells improve power generation efficiency by fabricating an ultrathin tunneling oxide layer and a highly doped polycrystalline silicon film in the metal electrode contact area to form a passivated contact structure. HJT cells passivate by depositing intrinsic amorphous silicon films and P / N-type amorphous silicon films on both the front and back sides, followed by the deposition of a transparent conductive film (TCO) for conductivity. BC cells increase current by placing all metal grid lines on the back of the cell, serving as a platform technology for upgrading TOPCon or HJT cells. Currently, TOPCon holds a mainstream position due to its low cost, high reliability, and high market acceptance.

[0005] Meanwhile, other studies have found that, based on HJT cells, by using low-damage continuous plasma vapor deposition to prevent passivation layer damage and combining it with laser transfer technology, high-efficiency solar cells of different thicknesses were fabricated. Compared to the baseline thickness of 125µm, the efficiency decreased by 0.25% for 106µm thickness, 0.31% for 84µm thickness, 0.62% for 74µm thickness, and 0.75% for 57µm thickness. The 57µm flexible ultrathin solar cell exhibited the highest power-to-weight ratio. This indicates that the efficiency decrease caused by cell thinning is not linear, and that cell thinning also reduces the weight and cost of the solar cell.

[0006] However, the existing methods for preparing this type of solar cell also have some problems: 1. Currently, only HJT batteries have the laboratory-scale manufacturing process for ultra-thin batteries. TOPCon, as the most mainstream type of solar cell, does not currently have the corresponding ultra-thin battery technology for mass production. 2. While reducing the thickness of crystalline silicon, ultra-thin batteries reduce the light absorption rate of the silicon wafer as the light-absorbing layer thins, leading to a decrease in battery current density and thus affecting the photoelectric conversion efficiency of solar cells. 3. Conventional TOPCon solar cell structures have a full-surface deposition of phosphorus-doped polycrystalline silicon on the back. While heavily doped polycrystalline silicon helps reduce the contact resistance between silicon and metal and improves the cell's fill factor, it also exhibits free carrier absorption, leading to severe parasitic absorption of long-wavelength photons and a decrease in current density. In ultra-thin cells, the thinner silicon wafer reduces light absorption, causing long-wavelength photons to undergo multiple reflections within the wafer, increasing the number of times they pass through the heavily doped polycrystalline silicon layer. Compared to TOPCon cells with normal-thickness silicon wafers, the parasitic absorption losses from the heavily doped polycrystalline silicon layer are further amplified in ultra-thin silicon TOPCon cells. Summary of the Invention

[0007] The purpose of this invention is to provide a method for fabricating ultrathin solar cells based on existing technology. This method can produce ultrathin solar cells with selective polycrystalline silicon passivation contacts. These cells have the characteristics of tunneling oxide layer + doped polycrystalline silicon passivation, filling the gap in the fabrication process of TOPCon cells for ultrathin solar cells.

[0008] The ultrathin solar cell fabricated by this invention differs from the polished back surface of conventional cells. Based on ultrathin crystalline silicon (20µm~100µm), this invention employs laser technology to create a patterned structural design on the back of the silicon substrate. This design can form a resonant cavity structure, which can effectively increase the effective optical path length of absorbed light within the cell. Through optical effects, it can enhance the current value of the solar cell and compensate for the negative impact of reduced cell thickness on the current value.

[0009] The method of this invention forms a selective polycrystalline silicon passivation contact structure on the back surface of a TOPCon cell. Unlike the conventional TOPCon cell structure that deposits phosphorus-doped polycrystalline silicon over the entire back surface, this method only sets a tunneling oxide layer and a doped polycrystalline silicon layer on the resonant cavity structure corresponding to the metallized region. This approach can effectively reduce the parasitic absorption of doped polycrystalline silicon and increase the current value. The conductivity type of doped polycrystalline silicon is equivalent to that of a metallic material, and this design is more conducive to the transport of charge carriers.

[0010] The objective of this invention can be achieved through the following measures: A method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts, the method comprising: A boron-doped emitter is formed on the surface of an N-type single-crystal silicon wafer; A partial ablation process is performed on the back surface of the silicon wafer to create a recessed structure. The back surface of the silicon wafer is polished and etched to form multiple patterned structures; A tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are fabricated on the back side of a silicon wafer; Remove the tunneling oxide layer and doped polysilicon layer from the non-metallic contact area on the back surface of the silicon wafer; Among them, the N-type single crystal silicon wafer is an ultra-thin crystalline silicon; the patterned structure includes a resonant cavity structure and a recessed structure. The resonant cavity structure is a protruding structure on the back surface of the silicon wafer, and the recessed structure is located between two adjacent resonant cavity structures; the resonant cavity structure includes a first resonant cavity and a second resonant cavity. The first resonant cavity is located in the metal contact area on the back surface of the silicon wafer, and the second resonant cavity and the recessed structure are located in the non-metal contact area on the back surface of the silicon wafer. The depth D of the first resonant cavity and the second resonant cavity are independently 0.5µm to 10µm, the width W of the protruding top of the first resonant cavity and the second resonant cavity are independently 20µm to 200µm, and the width S of the recessed structure is 50µm to 1000µm.

[0011] The thickness of the ultrathin crystalline silicon used in this invention is 20µm to 100µm. The term "ultrathin" in the ultrathin solar cell fabricated in this invention refers to the use of ultrathin crystalline silicon.

[0012] In a preferred embodiment, the depth D of the first resonant cavity and the second resonant cavity are independently 1µm to 5µm, the width W of the protruding top of the first resonant cavity and the second resonant cavity are independently 40µm to 100µm, and the width S of the recessed structure is 100µm to 1000µm. The depth D of each first resonant cavity and each second resonant cavity may be the same or different, the width W of the protruding top of each first resonant cavity and each second resonant cavity may be the same or different, and the width S of each recessed structure may be the same or different.

[0013] The method of this invention can form resonant cavity structures and recessed structures of uniform or non-uniform size on the back side of a silicon wafer. Specifically, the depth D of the protrusions in different resonant cavity structures may be the same or different, the width W of the top of the protrusions in different resonant cavity structures may be the same or different, and the width S of different recessed structures may be the same or different. Further, as... Figure 4 As shown, the battery back surface of the present invention is designed with a resonant structure based on light-harvesting capability. The depth (i.e., the height of the protrusion) D of each protrusion structure forming the resonant cavity structure can be the same or different, i.e., D1 = D2 or D1 ≠ D2. The top W of the protrusion of each protrusion structure forming the resonant cavity structure can also be the same or different, i.e., W1 = W2 or W1 ≠ W2. The width S of the recessed structure can be the same or different, i.e., S1 = S2 or S1 ≠ S2. Each resonant cavity structure is periodically distributed or aperiodically distributed.

[0014] In this invention, the number of second resonant cavities in a single non-metallic contact area on the back surface of the silicon wafer is n, and n≥2.

[0015] The method of the present invention further includes forming a passivation antireflection film on the front and back surfaces of a silicon wafer.

[0016] This method can also perform pretreatments such as texturing before forming the boron-doped emitter.

[0017] When preparing a boron-doped emitter, it can be formed directly on one surface of an N-type single-crystal silicon wafer; alternatively, the boron-doped emitter can be formed on both sides of an N-type single-crystal silicon wafer, and then the boron-doped emitter on one surface can be removed.

[0018] The present invention forms a recessed structure in a certain area of ​​the back surface of a silicon wafer by ablation treatment, wherein the ablation treatment can be carried out by laser ablation or by mask + dry etching process.

[0019] In this method, the laser used in the ablation process has a wavelength of 200–1200 nm, and the laser is at least one of picosecond or nanosecond lasers. Preferably, the laser is at least one of 355 nm ultraviolet laser, 532 nm green laser, 650 nm red laser, 820 nm near-infrared laser, or 1030 nm infrared laser; and the rectangular or square spot formed by the laser has a length of 100–500 µm, a width of 100–500 µm, a laser frequency of 50–300 kHz, a scanning speed of 5–25 m / s, and a laser energy density of 0.1–5 J / cm². 2 .

[0020] The front surface passivation antireflection film or the rear surface passivation antireflection film in this invention can be designed as a stacked film, that is, the passivation antireflection film adopts at least one of alumina, silicon nitride, silicon dioxide, and silicon oxynitride, preferably two; more preferably, a stacked design of alumina + silicon nitride passivation antireflection film is adopted.

[0021] In a preferred embodiment, the front or rear surface passivation antireflective film comprises an aluminum oxide layer and a silicon nitride layer. The aluminum oxide layer has a thickness of 1–10 nm, and the silicon nitride layer has a thickness of 20–50 nm.

[0022] In a preferred embodiment, the thickness of the tunneling oxide layer is 0.5 nm to 2.5 nm.

[0023] In a preferred embodiment, the thickness of the phosphorus-doped polycrystalline silicon layer is 60–200 nm.

[0024] This invention is based on the application of ultra-thin solar cells. After the boron diffusion process is completed on the silicon wafer, a patterned structure is formed on the entire back surface of the silicon wafer using laser technology and wet processing. This structure consists of a first resonant cavity, a second resonant cavity, and a recessed structure. This resonant structure effectively increases the reflection path length of absorbed light in the silicon substrate, thereby increasing the current value of the solar cell. Compared to the polished back surface of conventional cells, where long-wavelength light undergoes conventional specular reflection upon reaching the back surface, in this resonant structure, some long-wavelength light is trapped within the resonant structure, forming an additional reflection path (see appendix). Figure 10 Meanwhile, on the back of the battery structure, laser technology combined with wet processing is used to completely remove the doped polysilicon in the non-metallic grid area, reducing the negative impact of parasitic absorption of the doped polysilicon on the battery current value. In addition, the conductivity of the heavily doped polysilicon layer is similar to that of metal, and retaining some doped polysilicon in direct contact with the substrate silicon is more conducive to the transport of charge carriers.

[0025] This invention further provides a specific method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts, comprising the following steps: S1. Perform wet cleaning on N-type monocrystalline silicon wafers and create a textured surface; N-type monocrystalline silicon wafers are ultra-thin crystalline silicon. S2. Perform a double-sided boron diffusion process on the texturized silicon wafer to form a boron-doped emitter; S3. Use laser or dry etching with a mask to ablate a portion of the back surface of the silicon wafer to form a recessed structure; wherein the laser is used to process in a direction parallel to the fine gate, and the laser power is kept consistent or inconsistent to make the depth of the recessed structure consistent or inconsistent; the laser spot size is kept consistent or inconsistent to make the width of the recessed structure consistent or inconsistent. S4. Polish and etch the back surface of the silicon wafer to form multiple patterned structures. The patterned structures include resonant cavity structures and recessed structures. The resonant cavity structure is a protruding structure on the back surface of the silicon wafer, and the recessed structure is located between two adjacent resonant cavity structures. The resonant cavity structure includes a first resonant cavity and a second resonant cavity. The first resonant cavity is located in the metal contact area on the back surface of the silicon wafer, and the second resonant cavity and the recessed structure are located in the non-metallic contact area on the back surface of the silicon wafer. The number of second resonant cavities in a single non-metallic contact area is multiple. S5. Prepare a tunneling oxide layer and a phosphorus-doped polysilicon layer on the back side of the silicon wafer, and remove the tunneling oxide layer and phosphorus-doped polysilicon layer in the non-metallic contact area. S6. Form passivation and antireflection films on the front and back sides of the silicon wafer; S7, Printed and sintered metal electrodes.

[0026] In step S1, preferably, the ultrathin crystalline silicon is placed in a texturing device, and the surface damage layer of the silicon wafer caused by wire cutting is etched with sodium hydroxide solution at a reaction temperature of 70±10℃. Then, a random pyramid surface structure is generated by a wet chemical process using alkaline solution and texturing additives, and RCA wet cleaning is performed. The height of the obtained random pyramid is 0.5 to 2µm.

[0027] In step S2, preferably, the boron source used for boron diffusion is boron tribromide or boron trichloride, and the peak diffusion temperature is 1000-1100℃.

[0028] In step S3, preferably, a laser is used to ablate a portion of the back surface of the silicon wafer to form a recessed structure, thus pre-fabricating a patterned structure. The laser parameters used are as follows: the length of the laser spot is 100µm~500µm, and the width is 100µm~500µm; the wavelength of the laser is 200~1200nm; the laser is a picosecond laser or a nanosecond laser; the length and width of the rectangular or square laser spot formed are 100~500µm; the laser frequency is 50~300kHz; the scanning speed is 5~25m / s; and the laser energy density is 0.1~5J / cm².2 .

[0029] In step S3, another preferred method involves using a mask + dry etching process to ablate a portion of the back surface of the silicon wafer, forming a recessed structure and pre-fabricating a patterned structure. A specific method includes: after boron diffusion onto the silicon wafer, adding a graphite mask to partially cover the back surface of the wafer. The mask-covered portion represents the later raised resonant cavity region on the back surface, while the mask-cutout portion represents the later recessed region. Subsequently, reactive ion etching (RIE) is used to etch the mask-cutout region, while the portion containing the mask is protected from this process, ultimately forming... Figure 3 The structure is shown. Specific steps of dry etching: The boron-expanded silicon wafer is placed in the process chamber of a plasma equipment for plasma dry etching. The introduced gas is a fluorine-based gas such as CHF3, CF4, or SF6. The etching depth is 0.5µm to 10µm, preferably 1µm to 5µm.

[0030] In a preferred embodiment, step S4 includes: S41. Perform wet polishing on the back surface of the silicon wafer, using 3% to 10% HF to remove the BSG layer on the back and edges of the boron-expanded silicon wafer. S42. Polish and etch the back surface of the silicon wafer using a wet additive + KOH / NaOH + water solution at a reaction temperature of 60±10℃ to form a patterned structure with multiple resonant cavities. The depth D of each first resonant cavity and each second resonant cavity may be the same or different; the width W of the protruding top of each first resonant cavity and each second resonant cavity may be the same or different; and the width S of each recessed structure may be the same or different. The number of second resonant cavities in a single non-metallic contact area is n, and n≥2.

[0031] In a preferred embodiment, step S5 includes: S51. A tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are prepared on the back side of a silicon wafer; S52. A thin tunneling oxide layer is deposited on the back surface of a silicon wafer using low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition. The deposition reaction temperature is 400-600℃, and the thickness is selected from 0.5nm to 2.5nm. Under low-pressure conditions, silane is reacted on the back surface of the silicon wafer to deposit and grow an intrinsic polycrystalline silicon layer. The deposition reaction temperature of the intrinsic polycrystalline silicon is 500-650℃, and the thickness is selected from 60 to 200nm. S53. Phosphorus diffusion is carried out. During the phosphorus diffusion process, under oxygen conditions, phosphorus oxychloride is decomposed at high temperature to generate phosphorus pentachloride and phosphorus pentoxide. The generated phosphorus pentoxide reacts with silicon at the diffusion temperature to generate silicon dioxide and phosphorus atoms. The phosphorus atoms enter the intrinsic polycrystalline silicon layer to form a phosphorus-doped polycrystalline silicon layer. S54. Using laser technology and wet process, the excess tunneling oxide layer and doped polysilicon in the non-metallic contact area are removed, leaving only the metallized area with the tunneling oxide layer and doped polysilicon layer structure.

[0032] In step S6, preferably, a passivation antireflection film is formed on the front and back sides of the silicon wafer using a stacked film design; the passivation antireflection film uses at least one of alumina, silicon nitride, silicon dioxide, and silicon oxynitride. Preferably, a stacked design of alumina + silicon nitride passivation antireflection film is used.

[0033] In step S7, preferably, metal electrodes are printed and sintered on the front and back sides of the silicon wafer; wherein, the metal electrode grid lines are made of at least one of silver paste, silver-aluminum paste, aluminum, copper, titanium or nickel metal materials, the width of the fine metal grid lines on the front and back sides is 10-60µm, the height is 5-10µm, the spacing between the fine grid lines is 0.9-1.5mm, and the number is 150-250; the width of the main grid lines is 30-100µm, the height is 2-8µm, the spacing between the main grid lines is 10-20mm, and the number is 10-20; the sintering temperature is 700-850℃.

[0034] The present invention also includes an ultrathin solar cell with selective polycrystalline silicon passivated contacts prepared by the above method. Further, in this ultrathin solar cell, the N-type monocrystalline silicon wafer is ultrathin crystalline silicon; the metal contact area on the back of the silicon wafer is provided with, from the inside out, a tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, and a back surface passivation antireflection film, and the non-metallic contact area on the back of the silicon wafer is provided with a back surface passivation antireflection film.

[0035] In this ultrathin solar cell, the thickness of the ultrathin crystalline silicon is 20µm to 100µm; the depth D of the first resonant cavity and the second resonant cavity are 1µm to 5µm, respectively; the width W of the protruding top of the first resonant cavity and the second resonant cavity is 40µm to 100µm, respectively; and the width S of the recessed structure is 100µm to 1000µm.

[0036] The present invention also includes a photovoltaic module comprising a front encapsulation layer, a photovoltaic cell, and a back encapsulation layer, wherein the photovoltaic cell is an ultrathin solar cell with selective polycrystalline silicon passivated contacts prepared according to the method of the present invention.

[0037] In a preferred embodiment, a single patterned structure in the present invention includes a first resonant cavity, a plurality of second resonant cavities, and a plurality of recessed structures between the resonant cavities. The range of the single patterned structure includes an adjacent metal contact region and a non-metal contact region.

[0038] This invention employs a laser processing method to form a resonant cavity structure, resulting in a novel ultrathin solar cell structure with selective polycrystalline silicon passivated contacts. Based on an ultrathin cell thickness (20µm~100µm), this invention designs the TOPCon cell structure, offering advantages such as material savings and good flexibility. The design of the resonant structure on the back surface of the cell helps increase the conduction path of long-wavelength light within the cell structure, compensating for the negative impact of reduced thickness and a smaller light-absorbing layer on the cell current. The selective polycrystalline silicon passivated contact design on the back surface helps reduce parasitic absorption by doped polycrystalline silicon. This design retains the passivation structure composed of tunneling oxide layers and doped polycrystalline silicon on both sides of the first resonant cavity structure, which helps increase the carrier transport area and facilitates more efficient carrier transport.

[0039] By comparing three different TOPCon solar cell structures, the method of the present invention has the following advantages: ① This invention is based on the design of ultra-thin batteries. Compared with conventional thickness TOPCon batteries, ultra-thin solar cells have the advantage of saving silicon wafer costs. For example, the silicon wafer thickness used in conventional TOPCon batteries is 120~130 µm. If a thin silicon wafer material of 40 µm is used, the cost of silicon wafers can be reduced to 1 / 3 of the original. At the same time, ultra-thin solar cells have good flexibility and can be bent or rolled, making them more suitable for distributed scenarios such as industrial and commercial rooftops. ② The resonant structure fabricated on the back surface of the battery using this method can effectively increase the length of the reflection path of absorbed light in the silicon substrate, thereby increasing the battery's current value. Compared to the polished back surface of conventional batteries, where long-wavelength light undergoes conventional specular reflection upon reaching the back surface, in this structure, some mid-to-long-wavelength light is trapped within the resonant structure and undergoes multiple reflections. This can compensate for the negative impact on the battery current value caused by the reduction in battery thickness and the decrease in the light-absorbing layer (see Appendix). Figure 10 ); ③ In this method, the doped polysilicon in the non-metallized region on the back of the battery structure is dissolved to reduce the negative impact of parasitic absorption of the doped polysilicon on the battery current value. ④ This method retains the tunneling oxide layer + doped polysilicon structure of the resonant cavity in the corresponding metal grid region. For ultra-thin batteries, the retention of the passivation layer on both sides of the first resonant cavity structure increases the area for carrier transport, which is conducive to more efficient carrier transport. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the silicon wafer structure after texturing in step S1 of the present invention; Figure 2 This is a schematic diagram of the silicon wafer structure after double-sided boron diffusion in step S2 of the present invention; Figure 3 This is a schematic diagram of the silicon wafer structure after laser pre-fabrication of the resonant cavity structure in step S3 of the present invention; Figure 4 This is a schematic diagram of the patterned silicon wafer structure formed in step S4 of the present invention; Figure 5 This is a schematic diagram of the silicon wafer structure after the phosphorus-doped polycrystalline silicon layer is formed in step S5 of the present invention. Figure 6 This is a schematic diagram of the silicon wafer structure in step S5 of the present invention, showing the removal of the tunneling oxide layer and the doped polycrystalline silicon layer in the non-metallic contact area. Figure 7 This is a schematic diagram of the silicon wafer structure after the passivation antireflection film is formed in step S6 of the present invention; Figure 8 This is a diagram of a conventional TOPCon solar cell structure; Figure 9 This is a structural diagram of a TOPCon solar cell with selective polycrystalline silicon contacts under existing technology; Figure 10 This is an ultrathin solar cell structure with a patterned back surface to enhance light-harvesting capability and selective polycrystalline silicon passivation capability, as described in Embodiment 1 of the present invention. Figure 11 This is an ultrathin solar cell structure with a patterned back surface to enhance light-harvesting capability and selective polycrystalline silicon passivation capability, as described in Embodiment 2 of the present invention. In the figure, 1-N-type silicon substrate, 2-boron-doped emitter, 3-patterned structure, 31-first resonant cavity, 32-second resonant cavity, 33-recessed structure, 4-tunneling oxide layer, 5-phosphorus-doped polycrystalline silicon layer, 61-front surface passivation / antireflection film, 62-back surface passivation / antireflection film, 71-front surface metal electrode, 72-back surface metal electrode. Detailed Implementation

[0041] The present invention can be better understood from the following embodiments. However, those skilled in the art will readily understand that the descriptions in the embodiments are for illustrative purposes only and should not, and will not, limit the invention as detailed in the claims.

[0042] The TOPCon battery mentioned in this invention is officially called a tunnel oxide passivated contact solar cell.

[0043] like Figure 10-11 As shown, the ultrathin solar cell of the present invention includes an N-type monocrystalline silicon wafer, wherein the N-type monocrystalline silicon wafer is an ultrathin crystalline silicon with a thickness of 20µm to 100µm; the back side of the silicon wafer includes a metal contact area and a non-metal contact area.

[0044] A patterned structure 3 with multiple resonant cavities is formed on the back side of a silicon wafer using a boron-expanded laser and wet process. The patterned structure 3 includes multiple resonant cavity structures and multiple recessed structures 33. The resonant cavity structure is a protruding structure on the back surface of the silicon wafer, including a first resonant cavity 31 and a second resonant cavity 32. The recessed structure 33 is located between two adjacent resonant cavity structures and recessed into the silicon wafer. The first resonant cavity 31 is located in the metal contact area, and the second resonant cavity 32 and the recessed structure 33 are located in the non-metal contact area.

[0045] The depth D of the first and second resonant cavities is independently 1µm to 5µm, the width W of the protruding tops of the first and second resonant cavities is independently 40µm to 100µm, and the width S of the recessed structure is 100µm to 1000µm. The depth D of each first and second resonant cavity may be the same or different, the width W of the protruding tops of each first and second resonant cavity may be the same or different, and the width S of each recessed structure may be the same or different. Furthermore, with... Figure 4 For example, the depth (i.e., the height) D of the protrusions in each resonant cavity structure can be the same or different, i.e., D1 = D2 or D1 ≠ D2. The width W of the top of the protrusions in each protrusion structure forming the resonant cavity structure can also be the same or different, i.e., W1 = W2 or W1 ≠ W2. The width S of the recessed structure can be the same or different, i.e., S1 = S2 or S1 ≠ S2.

[0046] Within a single non-metallic contact region, the number of second resonant cavities is n, and n≥2.

[0047] The metal contact area on the back of the silicon wafer has a tunneling oxide layer 4 and a phosphorus-doped polycrystalline silicon layer 5 arranged sequentially from the inside to the outside. The thickness of the tunneling oxide layer 4 is 0.5 nm to 2.5 nm. The thickness of the phosphorus-doped polycrystalline silicon layer 5 is 60 nm to 200 nm.

[0048] A back-surface passivation antireflection film 62 is provided on the phosphorus-doped polycrystalline silicon layer 5 in the metal contact area on the back of the silicon wafer and on the non-metal contact area on the back of the N-type silicon wafer substrate.

[0049] A boron-doped emitter layer 2 and a front surface passivation antireflection film 61 are sequentially arranged from the inside to the outside on the front side of the silicon wafer.

[0050] The front or rear passivation antireflection film here adopts an aluminum oxide + silicon nitride passivation antireflection film stack design, that is, the passivation antireflection film includes an aluminum oxide layer and a silicon nitride layer, the thickness of the aluminum oxide layer is 1-10nm, and the thickness of the silicon nitride layer is 20-50nm.

[0051] A front surface metal electrode 71 is provided on the front side of the N-type silicon wafer substrate, and a back surface metal electrode 72 is provided in the metal contact area on the back side of the N-type silicon wafer substrate.

[0052] The present invention also includes a photovoltaic module comprising a front encapsulation layer, a photovoltaic cell, and a back encapsulation layer, wherein the photovoltaic cell is an ultrathin solar cell with selective polycrystalline silicon passivated contacts prepared by the method of the present invention.

[0053] Examples 1 and 2

[0054] A specific method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts includes the following steps: S1. Wet cleaning is performed on N-type monocrystalline silicon wafers to remove the damaged layer on the wafer surface, clean surface metal impurities and oil, and create a textured surface. The N-type monocrystalline silicon wafer has a thickness of 40µm and a resistivity of 1Ω*cm. The original silicon wafer is placed in a texturing device, and at a reaction temperature of 70±10℃, a 10% (v / v) sodium hydroxide solution is used to etch the damaged layer on the silicon wafer surface caused by wire cutting. The etched thickness on both sides is approximately 5µm. Then, a random pyramid surface texture is generated using a wet chemical process with an alkaline solution and texturing additives, followed by standard RCA wet cleaning. The resulting random pyramid height is approximately 0.5–2µm (see Appendix). Figure 1 (As shown).

[0055] S2. Perform a double-sided boron diffusion process on the texturized silicon wafer to form the surface emitter. The boron source used in the boron diffusion process is boron tribromide (BBr3) or boron trichloride (BCl3), and the peak diffusion temperature is 1000–1100℃. After the boron diffusion process, the sheet resistance of the boron emitter is obtained by a four-probe testing method, which is 100Ω / sq–250Ω / sq (see appendix). Figure 2 (As shown).

[0056] S3. A laser is used to ablate a portion of the back surface of the silicon wafer, forming a recessed structure and pre-fabricating a patterned structure. After double-sided boron diffusion on the silicon wafer, a laser is used to process the back surface of the wafer. The laser operates parallel to the fine gate direction, and the laser power can be kept constant or inconsistent. The depth of the formed recessed structure 33 is adjusted by adjusting the laser power, and the width of the recessed structure 33 is adjusted by controlling the laser spot size. The laser parameters used are as follows: the length and width of the laser spot are 100µm to 500µm; the wavelength of the laser is 200 to 1200nm, and it is at least one of picosecond or nanosecond lasers, such as ultraviolet lasers of 355nm, green lasers of 532nm, red lasers of 650nm, near-infrared lasers of 820nm, or infrared lasers of 1030nm; the length and width of the rectangular or square laser spot are 100 to 500µm; the laser frequency is 50 to 300kHz; the scanning speed is 5 to 25m / s; and the laser energy density is 0.1 to 5J / cm². 2 (See attached) Figure 3 (As shown).

[0057] S4. Wet polishing and etching of the battery back surface to form a patterned structure with multiple resonant cavities. The BSG layer on the back and edges of the boron-expanded silicon wafer is removed using 3%–10% HF. Then, a wet additive + KOH & NaOH + water solution (ratio 1:5:90) is used to polish and etch the silicon wafer back surface at a reaction temperature of 60±10℃. Due to surface modification, the laser-irradiated areas have poor corrosion resistance and are etched downwards to a certain depth. The un-laser-irradiated areas form the polished surface of the silicon substrate, ultimately forming a structure with multiple resonant cavities. The resonant cavities can be periodically or aperiodically distributed, and the depth or width of the downward protrusion of the silicon substrate can be consistent or inconsistent. The number of resonant cavities in a single non-metallized region is greater than or equal to two (see Appendix). Figure 4 (As shown). The resonant cavity structure includes a first resonant cavity and a second resonant cavity, with a recessed structure located between the two adjacent resonant cavity structures. The depth D of the first and second resonant cavities is independently within the range of 1µm to 5µm, the width W of the protruding tops of the first and second resonant cavities is independently within the range of 40µm to 100µm, and the width S of the recessed structure is within the range of 100µm to 1000µm.

[0058] S5. Preparation of selective tunneling oxide layer and doped polycrystalline silicon layer on the back surface. Low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) is used to deposit an ultrathin tunneling oxide layer on the back surface under high-temperature conditions with oxygen. The deposition reaction temperature is 400-600℃, and the thickness is selected to be 0.5nm-2.5nm. Under low-pressure conditions, silane (SiH4) reacts on the back surface of the silicon wafer to deposit and grow a polycrystalline silicon layer. The deposition reaction temperature of the intrinsic polycrystalline silicon is 500-650℃, and the thickness is selected to be 60-200nm. In the phosphorus diffusion process, under oxygen conditions, phosphorus oxychloride (POCl3) decomposes at high temperature to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5). The generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms (P). The phosphorus atoms enter the intrinsic polycrystalline silicon layer to form a phosphorus-doped polycrystalline silicon layer (see Appendix). Figure 5 (As shown). Next, using laser technology and a wet process, the excess doped polysilicon in the non-metallized region is removed, leaving only the tunneling oxide layer and doped polysilicon layer structure in the remaining metallized region. The laser parameters are the same as in step S3. (See Appendix) Figure 6 (As shown) S6. Deposition of passivation and antireflection films on the front and rear surfaces. The passivation and antireflection films on the front and rear surfaces adopt a stacked design of aluminum oxide and silicon nitride, wherein the thickness of aluminum oxide is 1-10 nm, the thickness of silicon nitride is 20-50 nm, and the refractive index of silicon nitride is 2.1-2.2 (see Appendix). Figure 7 (As shown).

[0059] S7. Metal electrode printing and sintering on the front and back surfaces. Metallized patterns are printed on the front and back surfaces (printing is done by screen printing or laser transfer, etc.). The metal grid lines can be made of silver paste, silver-aluminum paste, or other metal materials (aluminum, copper, titanium, nickel, etc.). The width of the fine metal grid lines on the front and back is 10-60µm, the height is 5-10µm, the spacing between the grid lines is 0.9-1.5mm, and the number is 150-250. The width of the main grid lines is 30-100µm, the height is 2-8µm, the spacing between the main grid lines is 10-20mm, and the number is 10-20. The sintering temperature is 700-850℃. Alternatively, a laser-assisted enhanced sintering process can be used to enhance contact and reduce contact resistivity.

[0060] During the fabrication process, the laser parameters in step S3 and the etching parameters in step S4 can be adjusted to form first resonant cavities, second resonant cavities, and recessed structures of different sizes.

[0061] In Example 1, with Figure 10For example, in this scheme, the depth and width of each resonant cavity are the same and they are periodically distributed. The number of second resonant cavities in a single non-metallized region is n=2; the widths of the protruding tops of the two second resonant cavities 32 in a single non-metallized region are W1 and W2, W1=W2=60µm; the depths of the two second resonant cavities in a single non-metallized region are D1 and D2, D1=D2=5µm; the widths of the two recessed structures in a single non-metallized region are S1 and S2, S1=S2=200µm (this product is marked as Example 1).

[0062] In Example 2, with Figure 11 For example, in this scheme, the depth and width of each resonant cavity are different and not periodically distributed. The number of second resonant cavities in a single non-metallized region is n=2; the widths of the protruding tops of the two second resonant cavities 32 in a single non-metallized region are W1 and W2, W1=30µm and W2=100µm; the depths of the two second resonant cavities in a single non-metallized region are D1 and D2, D1=2µm and D2=5µm; the widths of the two recessed structures in a single non-metallized region are S1 and S2, S1=100µm and S2=500µm (this product is marked as Example 2).

[0063] Example 3

[0064] A specific method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts includes the following steps: S1. Wet cleaning is performed on the N-type monocrystalline silicon wafer to remove the damaged layer on the wafer surface, clean surface metal impurities and oil stains, and create a textured surface on the front side. The N-type monocrystalline silicon wafer has a thickness of 40µm and a resistivity of 1Ω*cm. The original silicon wafer is placed in a texturing device, and at a reaction temperature of 70±10℃, a 10% sodium hydroxide solution is used to etch the front side of the silicon wafer, with an etching thickness of approximately 5µm. Then, a random pyramid surface texture is generated using a wet chemical process with an alkaline solution and texturing additives, followed by standard RCA wet cleaning. The resulting random pyramid height is approximately 0.5~2µm.

[0065] S2. Perform a boron diffusion process on the front side of the texturized silicon wafer to form a surface emitter. The boron source used in the boron diffusion process is boron tribromide (BBr3) or boron trichloride (BCl3), and the peak diffusion temperature is 1000-1100℃. After the boron diffusion process, the sheet resistance of the boron emitter is obtained by a four-probe test method, which is 100Ω / sq to 250Ω / sq.

[0066] S3. A mask + dry etching process is used to etch a region on the back surface of the silicon wafer to form a recessed structure. After boron diffusion on the silicon wafer, a graphite mask is added to the back surface to partially cover the area. The mask-covered portion forms the resonant cavity region that will later protrude on the back surface, while the mask-cleared portion forms the recessed region. Subsequently, reactive ion etching (RIE) is used to etch the mask-cleared areas, protecting the mask-covered portions from this process. Specific steps for dry etching: The boron-diffused silicon wafer is placed in the plasma equipment process chamber for plasma dry etching. CHF3 gas is introduced, and the etching depth is 0.5µm to 5µm.

[0067] S4. Etching treatment of the back surface of the battery to form a patterned structure with multiple resonant cavities. The back surface of the silicon wafer is polished and etched using a wet additive + KOH & NaOH + water solution (ratio 1:5:90) at a reaction temperature of 60±10℃. The mask cutout portion from the previous process is etched downwards to a certain depth, and the mask-covered portion forms the polished surface of the silicon substrate, ultimately forming a structure with multiple resonant cavities. The resonant cavities can be periodically or aperiodically distributed, and the depth or width of the downward protrusion of the silicon substrate can be consistent or inconsistent. The number of resonant cavities in a single non-metallized region is greater than or equal to two. The resonant cavity structure includes a first resonant cavity and a second resonant cavity, with a recessed structure located between two adjacent resonant cavity structures. The depth D of the first and second resonant cavities are independently in the range of 1µm to 5µm, the width W of the protruding tops of the first and second resonant cavities are independently in the range of 40µm to 100µm, and the width S of the recessed structure is in the range of 100µm to 1000µm.

[0068] The subsequent steps S5 to S7 are the same as in Example 1. By adjusting the mask width and dry etching depth in step S3 and the etching parameters in step S4, first resonant cavities, second resonant cavities, and recessed structures of different sizes are formed.

[0069] In this scheme, the depths and widths of the resonant cavities are different and not periodically distributed. The number of second resonant cavities in a single non-metallized region is n=2; the widths of the protruding tops of the two second resonant cavities 32 in a single non-metallized region are W1 and W2, W1=40µm and W2=90µm; the depths of the two second resonant cavities in a single non-metallized region are D1 and D2, D1=3µm and D2=6µm; the widths of the two recessed structures in a single non-metallized region are S1 and S2, S1=200µm and S2=600µm.

[0070] Comparative Example 1

[0071] Comparative Example 1 uses a 130µm silicon wafer as the substrate to fabricate a solar cell. The specific fabrication process is as follows: (1) Wet cleaning is performed on N-type monocrystalline silicon wafers to remove the damaged layer on the silicon wafer surface, clean the surface metal impurities and oil stains, and create a textured surface. The thickness of N-type monocrystalline silicon wafers is (40~150)µm, and the resistivity is 1Ω*cm. The original silicon wafer is placed in a texturing device, and at a reaction temperature of 70±10℃, a 10% sodium hydroxide solution is used to etch the damaged layer on the silicon wafer surface caused by wire cutting. The thickness of the etching on both sides is about 5µm. Then, a random pyramid surface texture is generated by a wet chemical process of alkaline solution + texturing additive, and standard RCA wet cleaning is performed. The height of the obtained random pyramid is about 0.5~2µm.

[0072] (2) A double-sided boron diffusion process is performed on the texturized silicon wafer to form a surface emitter. The boron source used in the boron diffusion process is boron tribromide (BBr3) or boron trichloride (BCl3), and the peak diffusion temperature is 1000-1100℃. After the boron diffusion process, the sheet resistance of the boron emitter is 100Ω / sq-250Ω / sq obtained by the four-probe test method.

[0073] (3) Wet polishing of the back surface. The BSG layer on the back and edge of the boron-expanded silicon wafer is removed by using an HF solution with a mass concentration of 3% to 10%. Then, the back surface of the silicon wafer is polished by a wet additive + KOH / NaOH + water solution (mass ratio of the three is 1:5:90). The reaction temperature is 60±10℃.

[0074] (4) A tunneling oxide layer and an intrinsic amorphous silicon layer are grown on the back surface of the battery; phosphorus diffuses to form a phosphorus-doped polycrystalline silicon structure. Low-pressure chemical vapor deposition (LPCVD) or ion-enhanced chemical vapor deposition (PECVD) is used to react and deposit an ultrathin tunneling oxide layer and a polycrystalline silicon layer on the back surface of the silicon wafer under low pressure conditions. The structural material of the ultrathin tunneling oxide layer is SiO2, the deposition reaction temperature is 400-600℃, and the thickness is selected from 0.5nm to 2.5nm. The deposition reaction temperature of intrinsic amorphous silicon is 500-650℃, and the thickness is selected from 60 to 200nm. In the phosphorus diffusion process, under oxygen conditions, phosphorus oxychloride (POCl3) decomposes at high temperature to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5). The generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms (P). The phosphorus atoms enter the intrinsic polycrystalline silicon layer to form a phosphorus-doped polycrystalline silicon layer with a thickness of 130nm.

[0075] (5) Wet treatment of battery surface. The PSG layer on the front side and edge of the phosphorus-expanded silicon wafer is removed by 3% to 10% HF. Then, the silicon wafer is polished and etched by a wet additive + KOH & NaOH + water solution (ratio 1:5:90) at a reaction temperature of 60±10℃.

[0076] (6) Deposition of passivation and antireflection films on the front and back surfaces. The passivation and antireflection films on the front and back surfaces adopt a stacked film design, which is a combination of two materials such as alumina, silicon nitride, silicon dioxide, and silicon oxynitride. Preferably, an alumina + silicon nitride passivation and antireflection film stacked design is adopted, wherein the preferred thickness of alumina is 1-10 nm, the preferred thickness of silicon nitride is 20-50 nm, and the refractive index of silicon nitride is 2.1-2.2.

[0077] (7) Printing and sintering of metal electrodes on the front and back surfaces. Metallized patterns are printed on the front and back surfaces (printing is done by screen printing or laser transfer, etc.). The metal grid lines can be made of silver paste, silver-aluminum paste or other metal materials (aluminum, copper, titanium, nickel, etc.). The width of the fine metal grid lines on the front and back is 10-60µm, the height is 5-10µm, the grid spacing is 0.9-1.5mm, and the number is 150-250. The width of the main grid lines is 30-100µm, the height is 2-8µm, the grid spacing is 10-20mm, and the number is 10-20. The sintering temperature is 700-850℃. Alternatively, a laser-assisted sintering process can be used to enhance contact and reduce contact resistivity.

[0078] Comparative Example 2

[0079] Comparative Example 2 uses a 40µm silicon wafer as the substrate to prepare a solar cell, and the other preparation methods are the same as those in Comparative Example 1.

[0080] Comparative Example 3

[0081] Comparative Example 3 uses a 40µm silicon wafer as the substrate to fabricate a solar cell. Other fabrication methods are the same as in Comparative Example 1, except that the following laser process is added between steps 4 and 5: Laser ablation forms a selective polycrystalline silicon layer. In the non-metallized regions, a laser ablation process is used to ablate these regions. The laser spot is rectangular or square, with a length and width of 100µm–500µm and a line spacing of 200µm–600µm. There is no overlap between the laser spots. A 100µm–500µm section is reserved in the main gate area for laser ablation. For the laser, a 200–600nm ultraviolet picosecond or nanosecond laser is used, preferably a 355nm violet laser or a 532nm green laser. The laser frequency is 50–300kHz, the laser scanning speed is 5–25m / s, and the laser energy density is 0.1–5J / cm². 2 .

[0082] Test case

[0083] The electrical performance of each batch of solar cells obtained in Examples 1 and 2 and Comparative Examples 1-3 was tested, and the results are shown in Table 1.

[0084] Comparative Example 1 shows a conventional TOPCon cell structure with a thickness of 130µm; Comparative Example 2 is a conventional TOPCon structure solar cell with a thickness of 40µm (see attached structure). Figure 8 ); Comparative Example 3 is a selectively passivated polycrystalline silicon solar cell with a thickness of 40µm in the prior art (structure shown in Appendix). Figure 9 ); Example 1 is a 40µm thick solar cell based on the selective polycrystalline silicon passivation structure designed in this invention, with the same resonant cavity depth and width, and a periodic distribution (see attached diagram for structure). Figure 10 ); Example 2 is a 40µm thick solar cell based on the selective polycrystalline silicon passivation structure designed in this invention, with different resonant cavity depths and widths, and not in a periodic distribution (see attached diagram for structure). Figure 11 ).

[0085] Table 1

[0086] In this table, the electrical performance data for each type of solution is the average data for a 100Pcs battery.

[0087] Analysis of Table 1 shows that: 1) Compared to Comparative Example 1, Comparative Examples 2 / 3 and Example 1 / 2 have fewer light-absorbing layers due to the thinning of the battery, which has a negative impact on the current density value of the battery; while Comparative Examples 2 / 3 and Example 1 / 2 have an advantage in cost as ultra-thin solar cells, and the open circuit voltage is improved due to fewer bulk defects.

[0088] 2) Compared with Comparative Examples 2 / 3, Embodiment 1 / 2 of the present invention produced a solar cell structure with selective polycrystalline silicon passivated contacts. The resonant structure on the back of the cell increases the propagation path length of light inside the cell through optical effects, thereby increasing the current density value.

[0089] 3) Compared with Example 1, the resonant structure produced in Example 2 has a non-periodic distribution pattern, which makes the propagation path of long-wavelength light inside the battery longer and can improve the current density value.

[0090] In summary, the method of the present invention can produce low-cost, high-efficiency ultrathin solar cells with selective polycrystalline silicon passivated contacts.

[0091] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications may still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions may be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts, characterized in that, The method includes: A boron-doped emitter is formed on the surface of an N-type single-crystal silicon wafer; A partial ablation process is performed on the back surface of the silicon wafer to form a recessed structure (33). The back surface of the silicon wafer is polished and etched to form multiple patterned structures (3); A tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are fabricated on the back side of a silicon wafer; Remove the tunneling oxide layer and doped polysilicon layer from the non-metallic contact area on the back surface of the silicon wafer; The N-type single-crystal silicon wafer is an ultra-thin crystalline silicon wafer; the patterned structure (3) includes a resonant cavity structure and a recessed structure (33), the resonant cavity structure is a protruding structure on the back surface of the silicon wafer, and the recessed structure (33) is located between two adjacent resonant cavity structures; the resonant cavity structure includes a first resonant cavity (31) and a second resonant cavity (32), the first resonant cavity (31) is located in the metal contact area on the back surface of the silicon wafer, and the second resonant cavity (32) and the recessed structure (33) are located in the non-metal contact area on the back surface of the silicon wafer; The depth D of the first resonant cavity (31) and the second resonant cavity (32) are independently 0.5µm to 10µm, the width W of the protruding top of the first resonant cavity (31) and the second resonant cavity (32) are independently 20µm to 200µm, and the width S of the recessed structure (33) is 50µm to 1000µm.

2. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 1, characterized in that, The thickness of the ultrathin crystalline silicon is 20µm to 100µm; the depth D of the first resonant cavity (31) and the second resonant cavity (32) is 1µm to 5µm respectively; the width W of the protruding top of the first resonant cavity (31) and the second resonant cavity (32) is 40µm to 100µm respectively; and the width S of the recessed structure (33) is 100µm to 1000µm.

3. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 1, characterized in that, The number of the second resonant cavities (32) in a single non-metallic contact area on the back surface of the silicon wafer is n, and n≥2.

4. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 1, characterized in that, The depth D of each of the first resonant cavities (31) and each of the second resonant cavities (32) is the same or different, the width W of the protruding top of each of the first resonant cavities (31) and each of the second resonant cavities (32) is the same or different, and the width S of each of the recessed structures (33) is the same or different.

5. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 1, characterized in that, The method also includes forming a passivation antireflection film on the front and back surfaces of the silicon wafer.

6. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 1, characterized in that, A partial ablation process is performed on the back surface of a silicon wafer using a laser or mask method; during the ablation process, the wavelength of the laser used is 200-1200 nm, and the laser is at least one of a picosecond laser or a nanosecond laser.

7. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 6, characterized in that, The laser is at least one of the following: a 355nm ultraviolet laser, a 532nm green laser, a 650nm red laser, an 820nm near-infrared laser, or a 1030nm infrared laser; and the rectangular or square spot formed by the laser has a length of 100-500µm, a width of 100-500µm, a laser frequency of 50-300kHz, a scanning speed of 5-25m / s, and an energy density of 0.1-5J / cm². 2 .

8. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 1, characterized in that, The method includes the following steps: S1. The N-type monocrystalline silicon wafer is wet-cleaned and textured; the N-type monocrystalline silicon wafer is an ultrathin crystalline silicon wafer. S2. Perform a double-sided boron diffusion process on the texturized silicon wafer to form a boron-doped emitter; S3. Using laser or dry etching with a mask, a portion of the back surface of the silicon wafer is ablated to form a recessed structure (33); wherein the laser is used in a direction parallel to the fine gate, and the laser power is kept consistent or inconsistent, so that the depth of the recessed structure (33) is consistent or inconsistent; the laser spot size is kept consistent or inconsistent, so that the width of the recessed structure (33) is consistent or inconsistent. S4. Polish and etch the back surface of the silicon wafer to form multiple patterned structures (3). The number of second resonant cavities (32) within a single non-metallic contact area is multiple; S5. Prepare a tunneling oxide layer and a phosphorus-doped polysilicon layer on the back side of the silicon wafer, and remove the tunneling oxide layer and phosphorus-doped polysilicon layer in the non-metallic contact area. S6. Form passivation and antireflection films on the front and back sides of the silicon wafer; S7, Printed and sintered metal electrodes.

9. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 8, characterized in that, In step S1, the ultrathin crystalline silicon is placed in a texturing device. At a reaction temperature of 70±10℃, the surface damage layer of the silicon wafer caused by wire cutting is etched with sodium hydroxide solution. Then, a random pyramid surface structure is generated by a wet chemical process using alkaline solution and texturing additives, and RCA wet cleaning is performed. The height of the obtained random pyramid is 0.5~2µm.

10. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 8, characterized in that, In step S2, the boron source used for boron diffusion is boron tribromide or boron trichloride, and the peak diffusion temperature is 1000–1100 °C.

11. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 8, characterized in that... In step S3, a portion of the back surface of the silicon wafer is ablated using laser or dry etching with a mask to form a recessed structure, thus pre-fabricating a patterned structure. The laser parameters used are as follows: the length and width of the laser spot are 100µm to 500µm; the wavelength of the laser is 200 to 1200nm; the laser is a picosecond or nanosecond laser; the length and width of the resulting rectangular or square laser spot are 100 to 500µm; the laser frequency is 50 to 300kHz; the scanning speed is 5 to 25m / s; and the laser energy density is 0.1 to 5J / cm². 2 .

12. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 8, characterized in that, Step S4 includes: S41. Perform wet polishing on the back surface of the silicon wafer, using 3% to 10% HF to remove the BSG layer on the back and edges of the boron-expanded silicon wafer. S42. Polish and etch the back surface of the silicon wafer using a wet additive + KOH / NaOH + water solution at a reaction temperature of 60±10℃ to form a patterned structure with multiple resonant cavities. The depth D of each of the first resonant cavities (31) and each of the second resonant cavities (32) is the same or different, the width W of the protruding top of each of the first resonant cavities (31) and each of the second resonant cavities (32) is the same or different, and the width S of each of the recessed structures (33) is the same or different; the number of the second resonant cavities (32) in a single non-metallic contact area is n, and n≥2.

13. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 8, characterized in that, Step S5 includes: S51. A tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are prepared on the back side of a silicon wafer; S52. A thin tunneling oxide layer is deposited on the back surface of a silicon wafer using low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition. The deposition reaction temperature is 400-600℃, and the thickness is selected from 0.5nm to 2.5nm. Under low-pressure conditions, silane is reacted on the back surface of the silicon wafer to deposit and grow an intrinsic polycrystalline silicon layer. The deposition reaction temperature of the intrinsic polycrystalline silicon is 500-650℃, and the thickness is selected from 60 to 200nm. S53. Phosphorus diffusion is carried out. During the phosphorus diffusion process, under oxygen conditions, phosphorus oxychloride is decomposed at high temperature to generate phosphorus pentachloride and phosphorus pentoxide. The generated phosphorus pentoxide reacts with silicon at the diffusion temperature to generate silicon dioxide and phosphorus atoms. The phosphorus atoms enter the intrinsic polycrystalline silicon layer to form a phosphorus-doped polycrystalline silicon layer. S54. Using laser technology and wet process, the excess tunneling oxide layer and doped polysilicon in the non-metallic contact area are removed, leaving only the metallized area with the tunneling oxide layer and doped polysilicon layer structure.

14. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 8, characterized in that, In step S6, a passivation antireflection film is formed on the front and back sides of the silicon wafer using a stacked film design; the passivation antireflection film is made of at least one of aluminum oxide, silicon nitride, silicon dioxide, and silicon oxynitride.

15. The method for fabricating an ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 8, characterized in that, In step S7, metal electrodes are printed and sintered on the front and back sides of the silicon wafer; wherein, the metal electrode grid lines are made of at least one of silver paste, silver-aluminum paste, aluminum, copper, titanium or nickel metal materials, the width of the fine metal grid lines on the front and back sides is 10-60µm, the height is 5-10µm, the spacing between the fine grid lines is 0.9-1.5mm, and the number is 150-250; the width of the main grid lines is 30-100µm, the height is 2-8µm, the spacing between the main grid lines is 10-20mm, and the number is 10-20; the sintering temperature is 700-850℃.

16. An ultrathin solar cell with selective polycrystalline silicon passivated contacts prepared by the method of any one of claims 1-14.

17. The ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 16, characterized in that, The N-type single crystal silicon wafer is an ultrathin crystalline silicon; the metal contact area on the back of the silicon wafer is provided with a tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer and a back surface passivation antireflection film in sequence from the inside to the outside, and the non-metal contact area on the back of the silicon wafer is provided with a back surface passivation antireflection film.

18. The ultrathin solar cell with selective polycrystalline silicon passivated contacts according to claim 16, characterized in that, The thickness of the ultrathin crystalline silicon is 20µm to 100µm; the depth D of the first resonant cavity (31) and the second resonant cavity (32) is 1µm to 5µm respectively; the width W of the protruding top of the first resonant cavity (31) and the second resonant cavity (32) is 40µm to 100µm respectively; and the width S of the recessed structure (33) is 100µm to 1000µm.

19. A photovoltaic module, characterized in that, It includes a front encapsulation layer, a photovoltaic cell, and a back encapsulation layer, wherein the photovoltaic cell is an ultrathin solar cell with selective polycrystalline silicon passivated contacts prepared by the method of any one of claims 1-14.

Images