4F2 vertical access transistor with reduced floating body effect

Abstract

The present technology includes a vertical cell dynamic random access memory (DRAM) array access transistor with improved hole distribution. The array includes a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels extending in a vertical direction orthogonal to the first direction and the second horizontal direction such that the plurality of bit lines intersect source / drain regions of the plurality of channels and the plurality of word lines intersect gate regions of the plurality of channels. Further, the array includes a p-doped bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, where the first channel is spaced apart from the second channel in a row extending in the second horizontal direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 495,028, filed April 7, 2023, entitled “4F2 DRAM WITH REDUCEDFLOATING BODY EFFECT”, and to U.S. Provisional Application No. 63 / 601,064, filed November 20, 2023, entitled “4F2 VERTICAL ACCESS TRANSISTOR WITH REDUCEDFLOATING BODY EFFECT”, the entire disclosure of which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] This disclosure generally describes 4F 2 Design of a two-dimensional dynamic random access memory array with vertical access transistors. More specifically, this disclosure describes a 4F array with reduced floating-body effect. 2 Memory array. Background Technology

[0004] With advancements in computing technology, computing devices are becoming smaller and possessing increased processing power. This necessitates increased storage and memory to meet the device's programming and computational needs. Reducing device size and increasing storage capacity is achieved by increasing the number of storage cells with smaller geometries.

[0005] Dynamic random-access memory (DRAM) architectures have shrunk over time. For example, the architecture of a single transistor and a single capacitor (1T-1C) DRAM cell has been successfully scaled down from 8F. 2 Size reduced to 6F 2 Size (where F is the smallest feature size). From 6F 2 Go to 4F 2 Further design modifications may help to further improve zonal density. (In 4F) 2 In DRAM designs, memory nodes (capacitors) and bit lines are located at the top and bottom of the vertical cell transistors, thus completely isolating the channel from the bulk. Due to this arrangement, and due to the bulk connection of the channel, for the current 8F... 2 Or 6F 2 The floating effect, which is not a problem for DRAM cell architecture, becomes 4F. 2 The main technical challenges of DRAM. Therefore, improvements are needed in this field. Summary of the Invention

[0006] This technology generally relates to a vertical-cell dynamic random access memory (DRAM) array with an improved aperture distribution. The array includes a plurality of bit lines arranged in a first horizontal direction. The array includes a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels extending in a vertical direction orthogonal to the first and second horizontal directions, such that the plurality of bit lines intersect the source / drain regions of the plurality of channels, and the plurality of word lines intersect the gate regions of the plurality of channels. The array includes p-doped bridges extending between a first channel and a second channel in the plurality of channels, wherein the first channel is spaced apart from the second channel in a row extending in the second horizontal direction.

[0007] In one embodiment, the p-doped bridge has a doping level greater than or about 1.6 times the doping levels of the first and second channels. In more embodiments, the array further includes a shallow trench isolation defined between the first and second channels, wherein the shallow trench isolation has a height extending from the first end to the second end. In still other embodiments, the p-doped bridge is disposed in the shallow trench isolation at about 20% to about 80% of the height of the shallow trench isolation. Additionally or alternatively, the array also includes at least a third channel among a plurality of channels spaced apart from the second channel in a row extending in a second horizontal direction, wherein the second p-doped bridge extends between the second and third channels. In a further embodiment, the array includes a body contact electrically connected to the p-doped bridge. Furthermore, in one embodiment, the body contact is connected to a bias voltage source. In more embodiments, the array also includes bit line contacts electrically connected to one or more of a plurality of bit lines, wherein the bit line contacts are electrically isolated from the body contacts. Additionally, in one embodiment, the device includes a second p-doped bridge extending between the first channel and the second channel among a plurality of channels.

[0008] Implementations of this technology also generally relate to vertical cell random access memory (DRAM) arrays. The array includes a plurality of bit lines arranged in a first horizontal direction. The array includes a plurality of word lines arranged in a second horizontal direction. The array includes a first plurality of spaced-apart channels in a first row extending in the second direction. The array includes a second plurality of spaced-apart channels in a second row extending in the second horizontal direction, wherein the first row and the second row are spaced apart. The array includes a plurality of p-doped bridges extending between adjacent channels in the first row and between adjacent channels in the second row. The array includes each of the channels extending in a vertical direction orthogonal to the first and second horizontal directions, such that the plurality of bit lines intersect the source / drain regions of the plurality of channels and the plurality of word lines intersect the gate regions of the plurality of channels.

[0009] In one embodiment, the array also includes shallow trench isolation defined between adjacent channels in each row, the shallow trench isolation having a height extending from a first end to a second end. In further embodiments, the array also includes second shallow trench isolation between adjacent channels in the first and second rows, and a gate formed along the outer surface of the second shallow trench isolation. In a further embodiment, the array includes conductive material covering each p-doped bridge. Additionally or alternatively, in an embodiment, the array includes at least one body contact in each row, each of the at least one body contact extending from a first end of the shallow trench isolation to the doped material in the corresponding shallow trench isolation.

[0010] This technology also includes a method for forming a vertical cell dynamic random access memory (DRAM) array. The method includes etching a substrate to form a plurality of shallow trench isolations and a plurality of vertically extending channels, the channels having a first source / drain region at a second end of the vertically extending channel. The method includes forming a dielectric in one or more of the shallow trench isolations. The method includes recessing the dielectric to a height within the one or more shallow trench isolations. The method also includes forming a protective pad in the one or more shallow trench isolations and bottom punching the bottom surface of the protective pad. The method includes recessing the dielectric to a second height within the one or more shallow trench isolations below the first height. The method includes forming p-doped bridges in the one or more shallow trench isolations, wherein the p-doped bridges contact the first and second sidewalls of the one or more shallow trench isolations exposed by the recess to the second height.

[0011] Implementations also include filling a dielectric material onto p-doped bridges in one or more shallow trench isolations. In further embodiments, the method includes forming a conductive material over the p-doped bridges. Additionally, in embodiments, the method includes epitaxially forming the p-doped bridges and depositing conductive material over the p-doped bridges. In embodiments, the method includes etching vias from the exposed surface of a vertical cell dynamic random access memory array into the conductive material in one or more shallow trench isolations in at least a portion of the shallow trench isolations. Implementations include metallizing the top surface of the conductive material and forming a conductive metal shield in the vias and above the exposed surface of the vertical cell dynamic random access memory array. In embodiments, the method includes forming an interlayer dielectric over the conductive metal shield and etching a second via through the interlayer dielectric to a bit line formed over a second source / drain region formed at a first end of a vertically extending channel, and an isolation via and conductive metal shield.

[0012] Compared to conventional systems and technologies, this technology offers several advantages. For example, the process and system can distribute vias across multiple channels, thereby reducing via accumulation effects. Furthermore, the process and system can significantly reduce 4F. 2Hole accumulation in the body of the DRAM device. These and other embodiments, along with their many advantages and features, are described in more detail below with reference to the accompanying drawings. Attached Figure Description

[0013] A further understanding of the nature and advantages of the disclosed technology can be achieved by referring to the remainder of the specification and the accompanying drawings.

[0014] Figure 1A The illustration shows a top plan view of an exemplary processing chamber according to an embodiment of the present technology.

[0015] Figure 1B It shows the familiar 4F 2 A top view of the memory array.

[0016] Figure 1C It shows the familiar 4F 2 A 3D view of the memory array.

[0017] Figure 2 The illustration shows the selection operation in the formation method according to an embodiment of the present technology.

[0018] Figure 3A The illustration shows a perspective view of a semiconductor structure having a dielectric material filler after the formation of a first shallow trench isolation according to an embodiment of the present technology.

[0019] Figure 3B The illustration shows a perspective view of a semiconductor structure with a recessed dielectric material according to an embodiment of the present technology.

[0020] Figure 3C The illustration shows a perspective view of a semiconductor structure with a protective pad according to an embodiment of the present technology.

[0021] Figure 3D The illustration shows a perspective view of a semiconductor structure with the bottom of the protective pad removed, according to an embodiment of the present technology.

[0022] Figure 3E The illustration shows a perspective view of a semiconductor structure with a dielectric material having back etched according to an embodiment of the present technology.

[0023] Figure 3F The illustration shows a perspective view of a semiconductor structure of a cleaned and exposed substrate according to an embodiment of the present technology.

[0024] Figure 3G The illustration shows a perspective view of a semiconductor structure having bridges formed between adjacent channels according to an embodiment of the present technology.

[0025] Figure 3HThe illustration shows a perspective view of a semiconductor structure having a filler formed above a bridge, according to an embodiment of the present technology.

[0026] Figure 4 The illustration shows the selection operation in the formation method according to an embodiment of the present technology.

[0027] Figure 5A The illustration shows a perspective view of a semiconductor structure having a conductive material formed above a bridge, according to an embodiment of the present technology.

[0028] Figure 5B The illustration shows a perspective view of a semiconductor structure of a conductive material with etch-back according to an embodiment of the present technology.

[0029] Figure 5C The illustration shows a perspective view of a semiconductor structure having a dielectric material filled on top of a conductive material according to an embodiment of the present technology.

[0030] Figure 5D The illustration shows a perspective view of a semiconductor structure having shallow trench isolation formed in the word line direction according to an embodiment of the present technology.

[0031] Figure 5E The illustration shows a perspective view of a semiconductor structure with bridge contact holes according to an embodiment of the present technology.

[0032] Figure 5F The illustration shows a perspective view of a semiconductor structure with bridge metallized contacts according to an embodiment of the present technology.

[0033] Figure 5G The illustration shows a perspective view of a semiconductor structure with main contacts according to an embodiment of the present technology.

[0034] Figure 5H The illustration shows a perspective view of a semiconductor structure with insulated bit line contact trenches according to an embodiment of the present technology.

[0035] Figure 5I The illustration shows a perspective view of a semiconductor structure with insulated bit line contacts according to an embodiment of the present technology.

[0036] Figure 6A The illustration shows a perspective view of a semiconductor structure having a first bridge formed according to an embodiment of the present technology.

[0037] Figure 6B The illustration shows a perspective view of a semiconductor structure having a doped layer formed above a first bridge according to an embodiment of the present technology.

[0038] Figure 6C The illustration shows a perspective view of a semiconductor structure having a second bridge formed above a first bridge according to an embodiment of the present technology.

[0039] Several accompanying drawings are included as schematic diagrams. It will be understood that the drawings are for illustrative purposes and are not considered to be to scale unless specifically stated otherwise. Furthermore, the drawings are provided to aid understanding and may not include all aspects or information compared to actual representations, and may include exaggerated material for illustrative purposes.

[0040] In the accompanying drawings, similar parts and / or features may have the same reference numerals. Additionally, parts of the same type may be distinguished by reference numerals followed by letters that differentiate them. If only the first reference numeral is used in this specification, the description applies to any of the similar parts having the same first reference numeral, regardless of the letters. Detailed Implementation

[0041] Historically, DRAM chip bit density has increased by approximately 25% between nodes. However, for recent generations, the trend of increasing bit density between nodes has slowed to around 20%, primarily due to the challenges of reducing cell area. Modern DRAM technology's cell design architecture is based on 6F. 2 Geometric structure, where "F" is the minimum feature size for a given technology node. From 6F 2 Go to 4F 2 Switching to a different cell architecture can result in a 33% increase in bit density at the same technology node. Furthermore, compared to 6F... 2 Compared to 4F 2 The patterning difficulty of DRAM has been significantly reduced. This is at least partly due to the fact that in 4F... 2 In DRAM designs, capacitors and bit lines are located at both ends of the vertical cell transistor, rather than at 6F. 2 They are tightly packed on the same side in DRAM.

[0042] However, 4F 2 DRAM design presents its own unique challenges. For example, 4F... 2 Memory cells have transistor channels positioned between bit lines and capacitor layers, without a shared substrate for connecting these channels, resulting in a floating body effect in these transistors. For example, the commonly known 4F... 2 DRAM access devices exhibit a shutdown leakage current problem. This shutdown leakage current is caused by the floating body effect, such as that attributed to the isolation channel at 4F. 2Hole accumulation occurs in the body of a DRAM device. Due to interband tunneling, electron hole pairs can form in the semiconductor channel, leading to gate-induced drain leakage (GIDL). While electrons can flow to the n-type source or drain regions of the transistor, the holes cannot. For 4F without substrate bonding... 2 In DRAM devices, vias have no path away from the channel and will continue to accumulate. Therefore, the floating body effect can cause the channel to be activated without gate activation, which ultimately translates into leakage current from capacitors or the data storage side of the device, as well as threshold voltage degradation over time.

[0043] An attempt has been made to provide body connectivity using buried body contact schemes. However, this approach can lead to gate overlap with the source / drain junction edge, allowing for drain leakage due to improper gate placement or limiting scalability to smaller sizes. Furthermore, this design can also produce high aspect ratio structures that challenge existing doping techniques.

[0044] This technology overcomes these and other problems by connecting two or more channels of vertically arranged transistors in corresponding row cells to one or more p-type bridges outside the source / drain regions of the transistors. That is, one or more p-type bridges between channels (e.g., extending along the gate or word line direction) provide a path for the via to move between channels when the gate is turned off, thereby reducing the impact of gate-induced leakage current and / or floating body effect on the channels. Furthermore, when the doping level is sufficient to prevent significant electron sharing between channels, the transistor on-current is unaffected when the channel is biased along the word line, and electrons continue to flow from the source to the drain. Therefore, this technology provides a reduction in floating body effect without compromising 4F. 2 The size or connectivity of the DRAM device. Furthermore, in embodiments, one or more bridges between adjacent channels in corresponding rows can also serve as connection points for the body contacts. Therefore, in embodiments, this technology provides adjacent channels to be locally connected together to provide a shared float, or even biased to a desired body potential. That is, by utilizing one or more body contacts, the float effect can be reduced or even eliminated without introducing inappropriate gate overlap near the source / drain junction edge.

[0045] Although the remaining disclosure will routinely identify the components used to form vertical cell dynamic random access memory (DRAM) arrays (such as 4F... 2The specific deposition and etching processes of DRAM devices will readily be understood, and these systems and methods are equally applicable to other DRAM devices, other devices subject to the buoyancy effect, their orientation, and the processes used to form such devices. Therefore, this technology should not be considered limited to use with such specific devices or individual systems. This disclosure will discuss a possible semiconductor device that may include one or more components, describing the use of one or more bridges according to embodiments of the present technology prior to additional variations and adjustments to this device.

[0046] Figure 1A A top plan view of a multi-chamber processing system 100, which may be specifically configured for implementation or operation according to some embodiments of the present technology, is shown. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on separate substrates (such as any number of semiconductor substrates) for forming semiconductor devices. The multi-chamber processing system 100 may include some or all of the following: a transfer chamber 106, a buffer chamber 108, single-wafer load locks 110 and 112 (although dual load locks may also be included), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. Single-wafer load locks 110 and 112 may include a heating element 113 and may be attached to the buffer chamber 108. Processing chambers 114, 116, 118, and 120 may be attached to the transfer chamber 106. Processing chambers 122 and 124 may be attached to the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be disposed between transfer chamber 106 and buffer chamber 108, and may facilitate transfer between robots 126 and 128. Platforms 102 and 104 may have access to both the transfer chamber and the buffer chamber, or the platforms may be selectively isolated from or sealed from the chambers to allow different operating pressures to be maintained between transfer chamber 106 and buffer chamber 108. Transfer platforms 102 and 104 may each include one or more tools 105, such as those for orientation or measurement operations.

[0047] The operation of the multi-chamber processing system 100 can be controlled by a computer system 130. The computer system 130 may include any means or combination of means configured to perform the operations described below. Thus, the computer system 130 may be a controller or array of controllers and / or a general-purpose computer configured with software stored on a non-transitory computer-readable medium, which, when executed, can perform the operations described with respect to the methods according to embodiments of the present technology. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps during the fabrication of a semiconductor structure. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform several substrate processing operations, including dry etching processes, cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and any number of other substrate processes.

[0048] Figure 1B and Figure 1C It shows the familiar 4F 2 Top view and perspective view of memory array 150. Memory array 150 may include a plurality of word lines 152 arranged in a first layer above a substrate. Word lines 152 may be conductive traces for selecting memory cells in memory array 150. Memory array 150 may also include a plurality of bit lines 154 arranged in a second layer above a substrate. The plurality of bit lines may be conductive traces for selecting memory cells in memory array 150. Activating one of the plurality of bit lines 154 and one of the plurality of word lines 152 can select an individual cell in memory array 150. The first layer and the second layer may include different metal layers formed at different times during the manufacturing process. For example, the first layer with word lines 152 may be formed on the second layer with bit lines 154 such that the two layers do not intersect.

[0049] Multiple vertical memory cells may be arranged above the intersection of multiple word lines 152 and multiple bit lines 154. Each of the multiple vertical memory cells may include a vertical transistor, which may be referred to as a vertical pillar transistor or a vertical column transistor. The channel material for the transistor may be formed from a single-crystal silicon pillar, or any other substrate discussed in more detail below. This silicon channel may be formed by etching the substrate. Each of the multiple vertical memory cells may also include a vertical capacitor 156. The vertical memory cell may be operated by storing charge on the vertical capacitor 156 to indicate a saved memory state. However, although Figure 1B and Figure 1CThe diagram illustrates an arrangement of vertical transistors and capacitors in a rectangular, generally orthogonal grid pattern (where "generally orthogonal" can be within approximately 10° of orthogonality, such as less than or about 7.5°, such as less than or about 5°, such as less than or about 2.5°, such as less than or about 1°, or any range or value between them; where "generally" can be used to similarly vary "vertical," "horizontal," and the like). It should be understood that other orientations may be considered for use in this technology. For example, in one embodiment, capacitors and vertical transistors may be spaced alternately in rows, these rows being offset by half the distance between the vertical transistors. That is, in one embodiment, the first row of memory cells may be regularly spaced in a first direction, and the second row of memory cells may also be regularly spaced in the first direction, but the second row of memory cells may be offset from the first row of memory cells, such as being approximately centered between the vertical transistors and capacitors in the first row. Figure 1B and Figure 1C Compared to the square pattern shown, this pattern can be referred to as a "honeycomb" or "hexagonal pattern". Therefore, it should be understood that any suitable orientation can be used in this technique.

[0050] This represents the familiar 4F 2 It is useful to compare the size of the unit cell region 166 of the memory array with that of a simple memory array described below. For example, the capacitor footprint 158 ​​can be defined as a circular region around each vertical capacitor 156. The capacitor footprint 158 ​​may include a horizontal cross-sectional area of ​​the capacitor extending outwards until this cross-sectional area contacts the capacitor area from the adjacent memory cell. Assume that the word line pitch 162 of the plurality of word lines 152 and the bit line pitch 164 of the plurality of bit lines 154 can be defined as 2F. This results in a total cross-sectional area of ​​4F for the unit cell region 166. 2 .

[0051] Figure 2 Exemplary operations in method 200 according to some embodiments of the present technology are illustrated. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 200 may include several optional operations, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, numerous operations are described to provide a broader range of structure formations, but such operations are not critical to the technology or may be performed by alternative methods that would be readily understood. Furthermore, although the method may describe a formation method perpendicular to the word line side of the structure to the bit line side of the structure, it should be understood that other orientations from the bit line to the word line side may be utilized.

[0052] Method 200 may include additional operations prior to the operations listed above. For example, additional processing operations may include forming a structure on a semiconductor substrate, which may include forming and removing material. The prior processing operations may be performed in a chamber in which method 200 is performed, or processing may be performed in one or more other processing chambers prior to delivering the substrate to a semiconductor processing chamber in which method 200 is performed. In any case, method 200 may, as appropriate, include a processing region of delivering the semiconductor substrate to a semiconductor processing chamber (such as processing chamber 100 described above, or other chambers that may include components as described above). The substrate may be deposited on a substrate support / transfer platform, which may be a base, such as substrate support 104, and may be placed in a processing region of the chamber, such as the processing region of processing chamber 120 described above. Method 200 describes in Figures 3A to 3H The operations illustrated in the diagram will be described in conjunction with the operation description of method 200. It will be understood that... Figures 3A to 3H Only partial schematic diagrams are shown, and the semiconductor substrate may include additional components, as well as alternative components, of any size or configuration shown in the drawings that may still benefit from aspects of this technology.

[0053] Method 200 may or may not involve optional operations to develop the semiconductor structure to a specific manufacturing operation. It will be understood that method 200 can be performed on any number of semiconductor structures 300 or substrates 302, such as Figures 3A to 3H The diagram illustrates an exemplary structure, including one on which selectively deposited materials can be formed. (See diagram for reference.) Figure 3A As shown, substrate 302 can be any number of materials, such as a substrate wafer or substrate made of silicon or silicon-containing materials, germanium, other substrate materials, and one or more materials that can be formed on the substrate during semiconductor processing.

[0054] In an embodiment, structure 300 may include a semiconductor substrate 302, comprising a host substrate, an epitaxial growth substrate, and / or a silicon-on-insulator wafer. As used herein, the term "semiconductor substrate" refers to a substrate wherein the entire substrate is made of a semiconductor material. The semiconductor substrate may include any suitable semiconductor material and / or a combination of semiconductor materials used to form the semiconductor structure. For example, the semiconductor layer may comprise one or more materials, such as crystalline silicon (e.g., Si). <100> or Si <111> The semiconductor substrate 300 comprises silicon oxide, strained silicon, germanium silicon, doped or undoped polycrystalline silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In one embodiment, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), germanium silicon (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 302 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although several examples of materials that can form a substrate are described herein, any material that can be used as a substrate falls within the spirit and scope of this disclosure on which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed.

[0055] In embodiments, the semiconductor material may be a doped material, such as n-doped silicon (n-Si) or p-doped silicon (p-Si). In embodiments, any suitable process (such as ion implantation) can be used to dope the substrate. As used herein, the term "n-type" refers to a semiconductor produced during manufacturing by doping an intrinsic semiconductor with an electron donor element. The term n-type derives from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of a well (or hole). In contrast to an n-type semiconductor, a p-type semiconductor has a larger hole concentration compared to the electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers.

[0056] like Figure 3AThe diagram illustrates a structure 300 comprising a substrate 302 having undergone source / drain 304 formation, shallow trench isolation 308 formation, and filling of a first dielectric material 306 within the shallow trench isolation 308. Furthermore, two or more walls 305 are formed between corresponding shallow trench isolations 308, wherein the walls 305 shown in this embodiment are spaced apart in rows extending horizontally parallel to the word line direction. In this embodiment, the formation of the source / drain 304 may include one or more ion implantations followed by a subsequent annealing activation process. The implantation process may be a single implantation or may include a series of multiple implantations. When using multiple implantations, each implantation may utilize the same ions or different ions. However, it should be understood that the source / drain regions 304 can be formed by any suitable process. Methods may include providing a semiconductor structure having a first source / drain region 304 with multiple vertical channels, and forming multiple word lines contacting the first source / drain regions. In summary, this process can incrementally form each stage of a transistor on top of a previously completed stage.

[0057] Furthermore, although various deposition and filling processes will be described, it should be understood that in embodiments, the semiconductor structure may be transferred to and between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for deposition and / or filling processes. These processing chambers include those for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or similar methods. Therefore, unless specifically stated otherwise, it should be understood that any one or more of the above methods may be utilized as known in the art. Similarly, the semiconductor structure can be transferred to and between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for etching, such as inductively coupled plasma (ICP) etching, reactive ion etching (RIE), capacitively coupled plasma (CCP) etching, or one or more of the like, as well as other etching processes known in the art.

[0058] Nevertheless, in operation 201, method 200 may include recessing the first dielectric material 306 into one or more shallow trench isolations 308 to a first recess height, such as Figure 3BAs shown in the diagram. For example, in one embodiment, substrate 302 may be loaded into load locks 110, 112 and transferred by robots 126, 128 to a processing chamber (such as processing chamber 114) where a first dielectric material 306 is recessed. It should be understood that the substrate may be transferred between each operation step, or only between a portion of the operation steps, since some operation steps may be performed in the same processing chamber. In one embodiment, the dielectric material may be recessed to approximately the midpoint of the respective shallow trench isolation 308. However, it should be understood that the first dielectric material 306 may be recessed to about 20% to about 80% of the height of each respective shallow trench isolation 308, such as from about 30% to about 70%, such as from about 40% to about 60%, such as from about 45% to about 55%, or any range or value therebetween. That is, each shallow trench isolation 308 defined between adjacent channels has a first end 307 and a second end (in Figure 3H (Illustrated more clearly in the diagram), and the groove height therebetween is defined. However, as discussed in more detail below, a greater recess height may be utilized in embodiments that include more than one p-bridge. Furthermore, the recess operation 201 may be performed by any method known in the art.

[0059] like Figure 3C As shown, after the recess operation 201, in operation 202, the protective pad 310 may be exposed in the first dielectric material 306 of the recess and the first sidewall 312 and second sidewall 314 of each shallow trench isolation 308 (in the exposed portion). Figure 3B (Illustrated more clearly in the middle) is formed above. The protective pad 310 can be formed of any dielectric material known in the art that has a different etch rate than the first dielectric material 306, such as silicon nitride, silicon oxynitride, silicon dioxide, or other similar materials. Additionally or alternatively, in embodiments, the protective pad 310 can be formed of the same material as the first dielectric material 306, but has a thickness to retain at least a portion of the protective pad 310 after the second recess operation 204. Nevertheless, as Figure 3D As shown, after the protective pad 310 is formed, the bottom 316 of the protective pad 310 can be etched away in operation 203 to expose the first dielectric material 306. This etching process that selectively removes the bottom surface can be referred to as "bottom punching," also known as anisotropic or directional etching. In embodiments, selective bottom etching or bottom punching can be performed by any etching process known in the art, such as reactive ion etching.

[0060] Nevertheless, after the bottom protective pad 310 is etched, the first dielectric material 306 can undergo a second recessing step in operation 204, such as Figure 3EAs shown in the diagram, the recess operation 204 can be selective for the first dielectric material 306 without removing the protective pad 310 from the first sidewall 312 and second sidewall 314 of the shallow trench isolation 308. That is, at least a portion of the protective pad 310 remains on the first sidewall 312 and second sidewall 314. In any case, the first dielectric material 306 is etched from a first height to a second height below the first height. By etching the first dielectric material 306 to the second height, the exposed portions 322 of the first sidewall 312 and the opposite second sidewall 314 are formed between the first dielectric material 306 and the bottom surface 318 of the protective pad 310 at the second height. In this embodiment, the second height is a distance below the first height to provide a robust contact area for the bridge 320.

[0061] Therefore, in the embodiment, the height difference from the first height to the second height, and / or the length of the exposed portions of the first sidewall 312 and the second sidewall 314, may be greater than or about 2 nm, such as greater than or about 4 nm, such as greater than or about 6 nm, such as greater than or about 8 nm, such as greater than or about 10 nm, such as greater than or about 12 nm, such as greater than or about 14 nm, such as greater than or about 16 nm, such as greater than or about 18 nm, such as greater than or about 20 nm, such as less than or about 50 nm, such as less than or about 45 nm, such as less than or about 40 nm, such as less than or about 35 nm, such as less than or about 30 nm, such as less than or about 25 nm, or any range or value between them. That is, in the embodiment, the distance and / or length may be selected to provide sufficient contact area for a robust electrical connection without being so large that the bridge 320 affects the total doping level of the corresponding wall 305.

[0062] Regardless of the height to which the dielectric material is etched, in operation 205, the exposed portions 322 of the first sidewall 312 and the opposing second sidewall 314 are cleaned as needed. Optional cleaning operation 205 may include a pre-cleaning operation and / or a surface damage removal operation. That is, in order to effectively distribute vias between channels, each bridge 320 must have a strong electrical connection to each of its adjacent walls 305. However, surface oxidation, damaged silicon from the recess operation 204, and other contaminants can prevent the bridges 320 from effectively merging with the first sidewall 312 and / or the second sidewall 314. Therefore, in an embodiment, operation 205 includes selectively removing surface damage (e.g., silicon damaged during the recess operation, if any) from the exposed portions 322 of the first sidewall 312 and the second sidewall, such as using isotropic etching processes, such as... Figure 3F As shown in the diagram. Isotropic etching processes (such as vapor phase etching) are available from Applied Materials (Selectra). TMThis process involves removing both doped and undoped silicon while retaining the dielectric material. In one embodiment, only one or more layers forming or adjacent to the exposed surface 322 are removed. In another embodiment, pre-cleaning (such as Siconi) is performed. TM Cleaning can remove any surface oxides present. However, in an embodiment, cleaning may not be necessary. That is, in an embodiment, method 200 may be performed entirely within the processing system 100 without removal from a vacuum, thereby limiting the formation of oxides and other surface defects after the oxides are removed by the recess operation 204. Additionally or alternatively, there may be no damaged silicon after the recess operation 204. Therefore, in an embodiment, both pre-cleaning and surface damage removal operations may be used, only one of the pre-cleaning and surface damage removal operations may be used, or neither pre-cleaning nor surface damage removal operations may be used.

[0063] In operation 206, method 200 further includes forming a p-doped bridge 320 between two adjacent walls 305 extending along a single row (e.g., the bridge 320 is formed along or parallel to the gate, which will be discussed in more detail below), such as Figure 3G As shown in the figure. In an embodiment, the p-doped bridge 320 may be formed of the same material as the two or more walls 305, or of a different material suitable for forming a p-doped bridge between adjacent walls 305, such as any substrate material or another material. However, in an embodiment, the p-doped bridge 320 has a higher doping level than the walls 305 adjacent to the corresponding bridge 320. That is, by utilizing a higher doping level than the walls 305 adjacent to the corresponding bridge, the charge shared between the walls 305 through the bridge 320 may be minimal or non-existent when the walls 305 are biased, because the voltage threshold is lower than the activation threshold of the bridge 320. Nevertheless, the doping level must not be significantly higher than the doping levels of the two or more walls 305, because the dopant may diffuse into the two or more walls 305, thereby raising the channel threshold above the bias voltage.

[0064] Therefore, in an embodiment, each of the bridges 320 may have a doping level greater than or about 1.6 times the doping level of the wall 305 adjacent to the corresponding bridge 320, such as greater than or about 1.8 times, such as greater than or about 2 times, such as greater than or about 2.2 times, such as greater than or about 2.4 times, such as greater than or about 2.6 times, such as greater than or about 2.8 times, such as greater than or about 3 times, such as less than or about 5 times, such as less than or about 4.8 times, such as less than or about 4.6 times, such as less than or about 4.4 times, such as less than or about 4.2 times, such as less than or about 4 times, such as less than or about 3.8 times, such as less than or about 3.6 times, such as less than or about 3.4 times, or any range or value between these.

[0065] In other words, in the implementation, the doping concentration of one or more p-doped bridges 320 may be greater than or about 5 x 10⁻⁶. 16 cm -3 Such as greater than or about 6x10 16 cm -3 Such as greater than or about 7x10 16 cm -3 Such as greater than or about 8x10 16 cm -3 Such as greater than or approximately 9x10 16 cm -3 Such as greater than or about 1x10 17 cm -3 Such as greater than or about 2x10 17 cm -3 Such as greater than or about 4x10 17 cm -3 Such as greater than or about 6x10 17 cm -3 Such as greater than or about 8x10 17 cm -3 Such as greater than or about 1x10 18 cm -3 Such as greater than or about 2x10 18 cm -3 Such as greater than or about 4x10 18 cm -3 Such as greater than or about 6x10 18 cm -3 Such as greater than or about 8x10 18 cm -3 Such as greater than or about 1x10 19 cm -3 Such as greater than or about 2x10 19 cm -3 Such as greater than or about 1x10 20 cm -3 Such as greater than or about 2x10 20 cm -3 Such as greater than or about 5x10 20 cm -3 or such as less than or about 1x10 22 cm -3 Such as less than or about 1x10 21 cm -3 , or any range or value between them.

[0066] That is, as discussed above, each bridge 320 can have a sufficient doping level to prevent significant charge sharing, for example, sufficient to provide a doping level of Vt above the gate threshold for the wall 305 adjacent to the corresponding bridge. Nevertheless, since each bridge 320 has a higher level of dopant than the adjacent wall 305, each bridge 320 can diffuse the dopant from the center of the corresponding bridge 320 toward and into the adjacent wall 305. This diffusion can thus create a dopant gradient from the wall 305 toward the center of each bridge 320. This phenomenon can improve aperture attraction, thereby reducing the floating body effect, because apertures can move from the problematic region of one or more walls 305 into the corresponding bridge 320, where apertures can be distributed across bridges 320, or move entirely along the bridging line between the connected bridges 320 and the wall 305, thus distributing apertures along a large area and dissipating such effects. However, if the doping level in one or more bridges 320 is too high compared to adjacent walls 305, the diffusion of the dopant can increase the doping level of one or more walls 305 to a level higher than the threshold of the wall 305. Therefore, in embodiments, the doping level of each bridge compared to adjacent walls 305 is carefully selected. In any case, this technology surprisingly finds that bridges 320 significantly reduce the floating body effect, such as by reducing channel potential increase and reducing turn-off leakage current.

[0067] Nevertheless, in embodiments, several different materials can be used for one or more bridges 320. For example, one or more bridges may include crystalline semiconductors, such as silicon, germanium, germanium-silicon, and / or other similar materials. In embodiments, bridges may be formed from crystalline silicon (such as single-crystal silicon in the embodiments), or any one or more of the semiconductor materials discussed above. These materials may also be used in the form of polycrystalline semiconductors. In embodiments, one or more bridges 320 may be formed by epitaxially growing epitaxial silicon on a recessed first dielectric material 306 in a shallow trench isolation 308 and merging the epitaxial layers until good contact with both the first sidewall 312 and the second sidewall 314 is achieved. Thus, in embodiments, this process may be referred to as a selective epitaxial deposition process. Alternatively, one or more bridges 320 may be formed by conformally filling the shallow trench isolation 308 with one or more polycrystalline semiconductor layers, or by depositing one or more polycrystalline semiconductor layers using other deposition methods known in the art. Regardless of the method used, it should be clear that material is deposited or grown for one or more bridges 320 to provide good electrical contact with the exposed portions 322 of both the first sidewall 312 and the second sidewall 314. However, in embodiments, one or more bridges 320 may not be completely merged or in contact with the first dielectric material 306, as long as they form strong electrical hole contacts with the first sidewall 312 and the second sidewall 314.

[0068] Furthermore, in this embodiment, the metal oxide can be used as one or more bridges 320. In this embodiment, the metal oxide can be physically connected to adjacent channels, but not electrically connected. In this way, the aperture can still attract the metal oxide without being electrically connected to adjacent channels.

[0069] In some implementations, one or more bridges 320 are formed only in a portion of the shallow trench isolation 308. For example, as Figure 3G As shown, one or more bridges 320 have a height slightly greater than the height of the exposed portion 322 and can thus extend into the protective pad 310. However, in an embodiment, one or more bridges 320 may have a height substantially the same as the height of the exposed portion 322. That is, although the shallow trench isolation 308 can be completely filled with the material of the bridges 320 above the first dielectric material 306, this embodiment may allow undue high electric fields in the upper regions of the shallow trench isolation 308 (such as in the source / drain regions if the protective pad 310 is not fully or uniformly formed).

[0070] Therefore, in embodiments, the thickness of one or more bridges 320 (measured from the bottom 324 to the top 326 of the bridge) may be greater than or about 2 nm, such as greater than or about 4 nm, such as greater than or about 6 nm, such as greater than or about 8 nm, such as greater than or about 10 nm, such as greater than or about 12 nm, such as greater than or about 14 nm, such as greater than or about 16 nm, such as greater than or about 18 nm, such as greater than or about 20 nm, such as greater than or about 25 nm, such as greater than or about 30 nm, such as less than or about 70 nm, such as less than or about 60 nm, such as less than or about 50 nm, such as less than or about 40 nm, such as less than or about 35 nm, or any range or value between them. That is, in embodiments, the thickness may be selected to provide sufficient contact area for a robust connection. However, as will be discussed in more detail below, in embodiments, such as when using two or more bridges, it may not be necessary to form a direct connection between one or more bridges and adjacent walls. In this implementation, cleaning and / or recessing operations 204 and / or 205 can be omitted. That is, without being bound by theory, the doping can be sufficiently tuned to achieve adequate pore distribution even without direct connection between the bridge and one or more channel walls.

[0071] Furthermore, as discussed above, in the embodiments, one or more bridges are formed at approximately the center point of two or more walls 305 (and thus the shallow groove isolation 308). That is, by utilizing bridges at approximately the center points of two or more walls 305, holes can be distributed in adjacent channels. However, it should be understood that in the embodiments, more than one bridge 320 can be used between two corresponding walls 305, and two or one of such bridges 320 may not be located at approximately the center point, as will be discussed below. Figures 6A to 6CFor a more detailed discussion, for example, since the first bridge 320 is located near the source / drain region 304, and the second bridge 320 is located near the second source / drain region of the semiconductor structure 300 (in... Figures 5A to 5I (Illustrated more clearly in the diagram) is formed. Nevertheless, regardless of the number of bridges utilized between the two respective channels, at least one of the bridges 320 may be formed in the shallow trench isolation 308 at a height of about 20% to about 80% of the height of each respective shallow trench isolation 308, such as from about 30% to about 70%, such as from about 40% to about 60%, such as from about 45% to about 55%, or any range or value therebetween.

[0072] After the p-shaped bridge is formed in operation 206, the remaining portion of the shallow trench isolation 308 above the bridge 320 can be filled in operation 207. Figure 3H The illustration shows the filling using a second dielectric material 332, which may be the same dielectric material as the first dielectric material 306, or a dielectric material similar to... Figure 3A The shallow trench isolation 308 is initially filled with a different dielectric material than the first and / or second dielectric material 332. In embodiments, the first and / or second dielectric material 332 may be any one or more dielectric materials, such as silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, combinations thereof, or other dielectric materials as known in the art, formed using any filling method described above and as known in the art. Although the following description will regularly discuss silicon oxide or silicon nitride as dielectric and / or spacer materials, it will be understood that any number of dielectric materials may be used in embodiments of the present technology, and the present technology should not be limited to any particular dielectric material in which features can be formed. Nevertheless, as will be discussed in more detail below, it should be understood that other materials may be used in operation 207.

[0073] In this implementation, after the fill operation 207, the semiconductor structure 300 can be re-entered into the vertical cell DRAM array (such as 4F). 2 The DRAM array follows a normal process flow and undergoes one or more further processing steps. For example, the semiconductor structure 300 may be planarized using polishing. Furthermore, the semiconductor structure may undergo one or more additional masking, etching, deposition, and / or filling steps to form a second set of rows orthogonal to the channel rows discussed above, as well as the formation of bit lines and second source / drain regions, which will be discussed in more detail below. However, as will be discussed in more detail below, in embodiments utilizing more than one p-bridge, operations 204-207 may be repeated as needed to form additional p-bridges.

[0074] Nevertheless, in implementations, the vertical cell DRAM array (such as 4F) is further reduced or even eliminated. 2The floating body effect in a DRAM array can be beneficial. Therefore, in an implementation, operation 207 may include filling the shallow trench isolation 308 above the bridge 320 with one or more conductive materials 440, such as... Figure 5A As shown in (e.g., as Figure 3G Operation 206 shown in the figure, then Figure 5A (See Operation 207 shown). In embodiments, filling with a conductive material (which may be a doped material, such as the same material as bridge 320 or any other conductive material as known in the art) can occur by epitaxially growing a conductive material (such as crystalline silicon in the embodiments) on bridge 320 in shallow trench isolation 308. Alternatively, the filling above one or more bridges 320 can be formed by conformally filling shallow trench isolation 308 with one or more conductive materials, or by depositing one or more conductive material layers using other deposition methods known in the art. Nevertheless, in embodiments, it should be understood that operation 207 can be optional, since bridge 320 itself can extend to the top surface 330 of the semiconductor structure without utilizing an additional filling step. Regardless of the formation method, the present art surprisingly finds that the formation of bridge 320 and conductive material 440 can be carried out in the same chamber, such as one of the processing chambers 114, 116, 118, 120, 122, and 124 discussed above. Therefore, in the embodiments, the epitaxial growth process and / or filling process of bridge 320 can be carried out in the same processing chamber as the epitaxial growth process and / or filling process of conductive material 440.

[0075] For example, Figure 4 Exemplary operations in method 400 according to some embodiments of the present technology are illustrated. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 400 may include several optional operations, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, numerous operations are described to provide a broader range of structure formations, but such operations are not critical to the technology or may be performed by alternative methods that would be readily understood. Method 400 describes in... Figures 5A to 5I The operations illustrated in the diagrams are explained in conjunction with the operation description of method 400. It will be understood that... Figures 5A to 5I Only partial schematic diagrams are shown, and the semiconductor substrate may include additional components, as well as alternative components, of any size or configuration as shown in the figures, that can still benefit from aspects of this technology.

[0076] For example, as discussed above, in an embodiment, operation 207 may include filling the bridge 320 with a conductive material different from the material of the bridge 320, or may include filling the shallow trench isolation 308 with the material of the bridge 320. However, it should be understood that in an embodiment, "different" may include a polycrystalline form of a single-crystal material, and vice versa (e.g., the bridge 320 is formed of crystalline silicon, and the doped material layer is formed of polycrystalline silicon). Nevertheless, operation 406 includes etch-back. Figure 5B The conductive material 440 shown in the figure and utilizing Figure 5C A second dielectric material 332 above the conductive material 440 fills the shallow trench isolation 308. The etchback of the conductive material 440 can be performed by methods described above or as known in the art. However, in this embodiment, the conductive material 440 is etched to a height below the top surface 442 of the wall 305. That is, as discussed above, in this embodiment, the conductive material 440 (and / or the material of the bridge 320) can interact with the wall 305 through any gaps or holes in the protective liner 310, where defects are more likely to occur at the top surface 442 of the wall 305. Therefore, in this embodiment, to reduce the possibility of a short circuit between the wall 305 and the material of the conductive material 440 / bridge 320, the material of the conductive material 440 / bridge 320 is etched back to a height below the top surface 442 of the wall 305.

[0077] therefore, Figure 5C The filling of operation 406 using a second dielectric material 332 is shown. This second dielectric material may be the same dielectric material as the first dielectric material 306 or a dielectric material similar to it. Figure 3A The shallow trench isolation 308 initially contains a different dielectric material than the first dielectric material. In an embodiment, the second dielectric material 332 may be any one or more dielectric materials formed using any filling method described above and known in the art, such as silicon oxide. As shown, after the etch-back and refill operation 406, the semiconductor structure 500 may also undergo planarization, such as polishing.

[0078] Next, operation 407 includes 4F utilizing any methods and techniques known in the art. 2 The standard process flow for DRAM arrays.

[0079] For example, Figure 5DThe etching of a shallow trench isolation 446 extending in a second horizontal direction, the formation of channels 448, and the deposition of a third dielectric material 450 are illustrated. That is, as discussed above regarding the formation of shallow trench isolation 308 between walls 305, a pattern or mask defining the second shallow trench isolation 446 can be used to form isolation between channels 448 formed by the etching process, which in this embodiment extend in rows parallel to or coplanar with word lines. The resulting channels 448 may have uniform or non-uniform widths and / or be substantially equal to the width of the walls 305. The second shallow trench isolation 446 can be used to isolate adjacent channels 448.

[0080] also, Figure 5D A third dielectric material 450 is shown formed along adjacent walls 305 and bridges 320 in a row extending in a first horizontal direction (e.g., such that the third dielectric material 450 is generally parallel to the word line direction). The third dielectric material 450 may be formed from a material such as SiO2 or other similar materials. For example, SiO may be oxidized from walls 305 and / or 448 to be used as dielectric material 450, or may be deposited as known in the art. Although this method is used, the third dielectric material typically extends along the outer periphery of the corresponding shallow trench isolation 446. The thickness of the dielectric material may be between about 1 nm and about 10 nm.

[0081] Figure 5E Various vertical cell DRAM arrays (such as 4F) formed thereon are shown. 2 Semiconductor structure 500 of a DRAM array component. For example, after forming a third dielectric material 450, gate metal 452 is typically formed on the third dielectric material 450 along the outer periphery of a shallow trench isolation 446. In embodiments, the gate metal may be a low-resistance metal, such as tungsten, titanium nitride, titanium, ruthenium, cobalt, molybdenum, the like, or combinations thereof. As shown, in embodiments, the gate metal 452 may be etched back beneath the first wall 305 and / or the second source / drain region 456 of the channel 448.

[0082] Spacer 454 has been formed in a second shallow trench isolation 446 between adjacent channels 448. Spacer 454 can be formed of any insulating material, such as SiO, SiN, dielectric, or other similar materials. In embodiments, spacer 454 can be filled using any method known in the art and subsequently etched back. For example, in embodiments, spacer 454 can be filled and etched back to the level below the first wall 305 and / or the second source / drain region 456 of channel 448 to provide a recess in gate metal 452, followed by a second filling with the same or a different insulating material. In some embodiments, a planarization process can be performed to create a flat surface on top of the stack for forming subsequent layers.

[0083] For example, as shown in the figure, a portion of wall 305 and / or 448 has undergone source / drain formation, thereby forming a second source / drain region 456 adjacent to the top 442 of the corresponding channel. As discussed above with respect to source / drain region 304, in an embodiment, the formation of the second source / drain 456 may include one or more ion implantations followed by a subsequent annealing process. The implantation process may be a single implantation or may include a series of multiple implantations. When using multiple implantations, each implantation may utilize the same ions or different ions. However, it should be understood that the second source / drain region 456 may be formed by any suitable process.

[0084] Furthermore, the second source / drain region 456 may undergo a metallization process (such as silicide) to form a cap 458. For example, a metal layer may be applied over the second source / drain region 456 and exposed to the silicide process. In embodiments, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, their metal-containing substances, their alloys, or combinations thereof. Therefore, the resulting cap 458 may be a metallization layer of any one or more of the above metals and channel materials (such as silicon). In this example only, the cap 458 layer may be titanium silicide, molybdenum silicide, or a combination thereof.

[0085] Nevertheless, the materials of the barrier layer 460 and one or more bit line layers 462 may be formed over a fully exposed top surface (e.g., the surface of the semiconductor structure 500 coplanar with the top surface 442, which serves as the top surface or exposed surface in this process step). The barrier layer 460 and bit line layers 462 may subsequently be etched during bit line formation to remove the materials of the barrier layer 460 and bit line layers 463 over the shallow trench isolation 308, while leaving sufficient material to cover and connect the corresponding cap 458, third dielectric material 450, and spacer layer 454 of the wall 305.

[0086] In some embodiments, the barrier layer 460 may be a nitride, oxynitride, carbonitride, and / or carbonitride of cobalt (Co), copper (Cu), nickel (Ni), ruthenium (Ru), manganese (Mn), silver (Ag), gold (Au), platinum (Pt), iron (Fe), molybdenum (Mo), rhodium (Rh), titanium (Ti), tantalum (Ta), silicon (Si), tungsten (W), or combinations thereof. Furthermore, the bit line 462 may be a material deposited using any suitable technique known in the art, such as one or more deposition or filling techniques discussed above. In some embodiments, the bit line 462 comprises one or more of tungsten (W), ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), or molybdenum (Mo). In some embodiments, the material of the bit line 462 is one or more of ruthenium or tungsten.

[0087] As shown, spacers 464 may be included along each bit line layer 462. Spacers 464 may be made of the same material as the protective pad 310. However, in embodiments, spacers 464 may involve any insulating material discussed for spacers 454 and may be applied according to any of the methods discussed, regardless of the material of the protective pad 310. In embodiments, spacers 464 may be applied as a conformal layer above the exposed surface of the semiconductor structure 500. Furthermore, a further dielectric material 466 may be filled between spacers 464. The further dielectric material 466 may be any one or more of the dielectric materials discussed above and may be filled according to any of the techniques previously discussed.

[0088] Nevertheless, the interlayer dielectric 468 is formed over the further dielectric material 466 and spacer 464, and the interlayer dielectric may be planarized prior to its formation. The interlayer dielectric 468 may be formed from any one or more of the dielectric materials discussed above using any application technique. For example, the interlayer dielectric 468 may be referred to as silicon nitride.

[0089] Regardless of the material and formation method of the interlayer dielectric 468, in operation 408, one or more vias 470 are etched through the interlayer dielectric 468, dielectric material 466, spacer layer 464, and dielectric material 332 to expose conductive material 440 (and / or the material of bridges 320, if the material of bridges 320 extends during bridge formation operation 206 and / or refill operation 207 as discussed above). The vias 470 may be aligned with one or more bridges 320 and disposed perpendicularly over such bridges. Although one via 470 is illustrated for each bridge 320 (e.g., 12 bridges in this example), it should be understood that due to the via-sharing nature of the bridges 320 and walls 305 in the corresponding rows, each word line row connected by a corresponding bridge (e.g., WR1, WR2, WR3, WR4, and WR5 in the illustrated embodiment, although there may be more or fewer rows) may require only one via.

[0090] Therefore, in an embodiment, each corresponding bridge connection row includes at least one hole. Additionally or alternatively, in an embodiment, each bridge connection row may include a number of holes less than or equal to the number of bridges 320, such as equal to or less than or about 90% of the number of holes of the bridges, such as less than or about 80% of the number of bridges in the corresponding row, such as less than or about 70%, such as less than or about 60%, such as less than or about 50%, such as less than or about 40%, such as less than or about 30%, such as less than or about 20%, such as less than or about 10%, provided that each bridge connection row contains at least one hole 470.

[0091] Furthermore, in embodiments, when the number of holes 470 is less than the number of bridges 320, the holes may be aligned in bit line rows (e.g., BR1, BR2, BR3, BR4, or BR5), or may be spaced apart in one or more of rows BR1-BR5 and WR1-WR5. For example, the first hole 470 may be located in WR5-BR1, the second hole in WR4-BR2, the third hole in WR3-BR3, the fourth hole in WR2-BR4, the fifth hole in WR1-BR5, and so on. However, as will be understood, any pattern or position may be used, such as a zigzag pattern between only two WR or BR rows, or other combinations thereof.

[0092] Nevertheless, in implementations, it may be desirable to space adjacent holes 470 in two or more BR or WR rows, as described in the examples above, in order to minimize the occurrence of short circuits. However, in implementations, it may be desirable for each bridge 320 to include one hole in order to further control hole dissipation.

[0093] In an embodiment, the aperture 470 may be self-aligned between adjacent second source / drain regions 456 in the corresponding bridge connection row. As shown, the second source / drain regions 456 can be used to align the aperture 470 with the bridge 320. However, it should be understood that in an embodiment, other methods for forming the aperture 470, as known in the art, may be used. For example, the aperture 470 may be formed using one or more methods for forming storage node contacts. That is, in an embodiment, a larger aperture than is required for contact may be formed, and an additional liner may be formed on the outside of the aperture, as an example only.

[0094] Although the hole is shown as having a circular cross-section, it should be understood that other cross-sectional shapes are possible. In an embodiment, the cross-sectional shape of the hole 470 may be selected based on the shape of the shallow trench isolation 308. Nevertheless, in an embodiment, the hole size and shape may be selected to remove all or most of the second dielectric material 332 from each respective shallow trench isolation 308 above the bridge 320 while keeping the protective pad 310 intact, or only a portion of the second dielectric material 332 may be removed. Regardless of the shape and size of the hole in the horizontal direction, the hole should have a height sufficient to expose the conductive material 440.

[0095] Nevertheless, after etching the via 470, in operation 409, the exposed conductive material 440 and / or the bridge 320 undergo a metallization process. In an embodiment, the metallization operation 409 may be a siliconization process, thereby forming a structure such as... Figure 5FThe main contact cover 472 is shown. For example, a metal layer may be applied over the conductive material 440 and / or the bridge 320 and exposed to the siliconization process. In embodiments, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, their metal-containing substances, their alloys, or combinations thereof. Therefore, the resulting main contact cover 472 may be a metallization layer of any one or more of the above metals and channel materials (such as silicon). In this example only, the cover layer 458 may be titanium silicide, molybdenum silicide, or a combination thereof.

[0096] After the main contact cover 472 is formed, in operation 410, a conductive metal shield 474 is formed in the hole 470 and above the interlayer dielectric 468, as shown. Figure 5G As shown in the figure. In embodiments, the conductive metal shielding element 474 may be one or more of cobalt (Co), copper (Cu), nickel (Ni), ruthenium (Ru), manganese (Mn), silver (Ag), gold (Au), platinum (Pt), iron (Fe), molybdenum (Mo), rhodium (Rh), titanium (Ti), tantalum (Ta), silicon (Si), tungsten (W), or combinations thereof. In one or more embodiments, the conductive metal shielding element 474 is one or more of titanium (Ti), copper (Cu), cobalt (Co), tungsten (W), ruthenium (Ru), or combinations thereof.

[0097] That is, by including a conductive metal shield 474 in the hole 470 and above the surface of the interlayer dielectric 468, which contacts the body contact cover 472, one or more bridges 320 can now be positioned for electrical contact with the body of the semiconductor structure 500. Therefore, one or more walls 305 / 448 no longer float, thereby reducing and / or completely eliminating the buoyancy effect attributable to the conductive metal shield 474 used as the body contact. For example, in an embodiment, a bias potential, such as zero voltage or a slightly negative voltage, can be applied to the conductive metal shield 474, thereby attracting the top plate 476 present in the conductive metal shield 474 and at least partially (if not completely) moving it out of any hole in the two or more walls 305.

[0098] However, due to the presence of conductive material (e.g., conductive metal shielding layer 474), the bit line contact must be isolated from the conductive metal shielding layer 474. Therefore, the operation 411 of forming the bit line contact includes connecting the bit line contact with... Figure 5H The conductive metal shielding layer 474 provides isolation. That is, as shown, operation 411 may include applying a second interlayer dielectric 478 over the conductive metal shielding layer 474. The second interlayer dielectric 478 may include any one or more of the dielectric materials discussed above. Figure 5HAs shown, the second interlayer dielectric 478 may be recessed to enter at least one bit line 462. After the recess is formed, the conductive metal shielding layer 474 may be horizontally recessed, and a plug dielectric material 482 is filled into the recess, thereby electrically isolating the recess 481 from the conductive metal shielding layer 474. The plug dielectric material 482 may be formed from any one or more of the dielectric and / or padding materials discussed above using any application technique. However, in this embodiment, the plug dielectric material 482 may be conformally filled into the recess. Nevertheless, as shown, the bottom of the plug 482 has been removed (e.g., “punched”) to expose the top 480 of one or more bit lines 462, while insulating the remaining portion of the recess from the conductive metal shielding layer 474.

[0099] See Figure 5I After the plug 482 is formed and its bottom is etched away, the bit line contact 484 can be formed by filling the recess 481 with one or more conductive materials. In embodiments, the bit line contact 484 can be formed of the same material as the bit line 462 or a different material. Therefore, in embodiments, the conductive material can be deposited using any suitable technique known in the art, such as one or more deposition or filling techniques discussed above. In some embodiments, the bit line contact 484 includes one or more of tungsten (W), ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), or molybdenum (Mo). In embodiments, the material of the bit line 462 is one or more of ruthenium or tungsten.

[0100] After forming bit line contacts 484, semiconductor structure 500 can re-enter a vertical cell DRAM array (such as 4F). 2 The semiconductor structure 500 follows the normal process flow of a DRAM array and undergoes one or more further processing steps. For example, the semiconductor structure 500 may undergo contact redistribution, bonding pad formation, and / or copper contact formation. Nevertheless, due to the shared vias between channels in the corresponding rows (e.g., rows WR1-WR5 parallel or coplanar with the word lines) and / or the connection of each row to the substrate body, the semiconductor structure may exhibit a significantly reduced or even eliminated floating body effect.

[0101] Regardless of whether the main contact is used, this technology can also provide the formation of more than one p-bridge. For example, Figure 6A The diagram is similar to Figure 3G The implementation method (e.g., after operation 206). However, Figure 6AThe diagram illustrates that the first and / or second recess operations 201 and / or 204 include etching the first dielectric material 306 to a height less than or about 50% of the trench height, such as less than or about 45%, such as less than or about 40%, such as less than or about 35%, such as less than or about 30%, such as less than or about 25%, such as less than or about 20%, such as less than or about 15%, such as less than or about 20%, or any range or value between thereof. However, in embodiments, the height may be greater than 0% of the trench height to prevent overlap with the source / drain regions and short circuits as discussed above, such as greater than or about 5%, such as greater than or about 10%, or any range or value between thereof.

[0102] That is, this technology surprisingly finds that by utilizing more than one p-bridge 320, vias (such as those formed by inter-band tunneling effects) can be prevented from accumulating in the center of the channel, thereby reducing the channel polarity and reducing the on-state current. In other words, by utilizing more than one p-bridge, such as one or more bridges adjacent to each source / drain region, a further reduction in gate-induced drain leakage can be exhibited, at least in part attributable to the location adjacent to the source / drain contacts. Therefore, in embodiments, such as those where a further reduction in word line voltage is desired, more than one p-bridge can be utilized, in addition to any other factors discussed above. However, it should be understood that in embodiments, any one or more of the methods and apparatuses discussed herein are suitable for reducing gate-induced leakage current and the floating body effect.

[0103] Nevertheless, such as Figure 6B As shown, in an embodiment, operation 207 may, as appropriate, include filling the p-bridge 320 with conductive material 340. The conductive material may be any material discussed above regarding conductive material 440, and may be integrated using any one or more of the methods discussed in operation 406. Regardless of the conductive material 340 and / or method used, a dielectric material, which may be the same as or different from the first dielectric material 306, may fill the remaining portion of the shallow trench isolation.

[0104] like Figure 6C As shown in the figure, similar to Figure 3G The dielectric material 306 can then be etched back to a second height lower than the first height, as discussed regarding operation 204. Exposed sidewalls 322 may be cleaned as needed, as discussed above regarding operation 205 and as... Figure 3F As shown in the image. Similar to... Figure 3G , Figure 6C The formation of the second p-type bridge 321 is shown. Depending on any one or more of the materials discussed above and the doping level, the second p-type bridge 321 can be formed from the same material as or a different material from the p-type bridge 320. Furthermore, although in Figure 6ATwo p-bridges are shown in the diagram. It should be clear that operations 204 to 207 can be repeated to form three or more p-bridges.

[0105] In any implementation, a p-bridge (such as a second p-bridge 321) may be formed adjacent to the first end 307 to be close to the second source / drain region. Therefore, in an implementation, at least the second p-bridge is formed in the shallow trench isolation 308 at a height greater than or about 60% of the trench height, such as greater than or about 65%, such as greater than or about 70%, such as greater than or about 75%, such as greater than or about 80%, such as greater than or about 85%, such as greater than or about 90%, or any range or value between therewith. However, in an implementation, the height may be less than 100% of the trench height to prevent overlap with the source / drain region and short circuits as discussed above, such as less than or about 95%, such as less than or about 90%, or any range or value between therewith.

[0106] Despite the chosen height, conductive materials, which may be the same as or different from conductive materials 340 and / or 440, may be formed above the second p-type bridge 321. Furthermore, similar to operation 207, dielectric materials, which may be the same as or different from the first dielectric material 306, may fill the remaining portion of the shallow trench isolation 308. After filling, structure 300 may undergo body contact formation as discussed above, or may be re-entered into a vertical cell DRAM array (such as 4F...). 2 The semiconductor structure 300 follows the normal process flow of a DRAM array and undergoes one or more further processing steps. For example, the semiconductor structure 300 may undergo contact redistribution, bonding pad formation, and / or copper contact formation. Nevertheless, due to the shared vias between channels in the respective rows, the semiconductor structure may exhibit a significantly reduced or even eliminated floating body effect.

[0107] It should be understood that the specific steps shown in the figures provide a method for forming a 4F according to various embodiments. 2 A specific method for DRAM arrays. Other sequences of steps may also be performed according to alternative implementations. For example, alternative implementations may perform the steps outlined above in a different order. Furthermore, the individual steps shown in the figures may include multiple sub-steps, which may be adapted to be performed in various sequences of the individual steps. In addition, additional steps may be added or removed depending on the specific application. Many variations, modifications, and substitutions also fall within the scope of this disclosure.

[0108] As used herein, the terms “about” or “approximately” or “substantially” may be interpreted as within the scope expected by a person of ordinary skill in the art in light of this specification.

[0109] In the above description, several specific details have been set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be apparent that some embodiments can be practiced without some of these specific details. In other instances, well-known structures and apparatuses are illustrated in block diagram form.

[0110] The above description provides only exemplary embodiments and is not intended to limit the scope, applicability, or construction of this disclosure. Rather, the above description of the various embodiments provides an enabling disclosure for implementing at least one embodiment. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the spirit and scope of some embodiments as set forth in the appended claims.

[0111] Specific details have been set forth in the foregoing description to provide a thorough understanding of this disclosure. However, it will be understood that implementations may be practiced without such specific details. For example, circuits, systems, networks, processes, and other components may be illustrated as components in the form of block diagrams so as not to obscure the implementation with unnecessary details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be illustrated without unnecessary details in order to avoid obscuring the implementation.

[0112] Furthermore, it should be noted that an independent implementation can be described as a process, which is depicted as a flowchart, flow diagram, data flow diagram, structure diagram, or block diagram. Although a flowchart can describe operations as a continuous process, many operations can be performed in parallel or simultaneously. Furthermore, the order of operations can be rearranged. A process can terminate when its operations are completed, but may have additional steps not included in the figures. A process can correspond to a method, function, program, subroutine, subroutine, etc. When a process corresponds to a function, its termination can correspond to the function returning to the calling function or the main function.

[0113] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying instructions and / or data. A code segment or machine-executable instruction can represent any combination of programs, functions, subroutines, programs, routines, subroutines, modules, software packages, classes, or instructions, data structures, or program statements. A code segment can be coupled to another code segment or hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., can be passed, forwarded, or transmitted by any suitable means, including memory sharing, message passing, symbol passing, network transmission, etc.

[0114] Furthermore, the implementation can be carried out through hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, program code or code segments for performing the necessary tasks can be stored in a machine-readable medium. The processor can then perform the necessary tasks.

[0115] In the above description, features are described with reference to specific embodiments thereof; however, it should be understood that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used independently or in combination. Furthermore, embodiments may be utilized in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the specification. The specification and drawings are therefore to be considered illustrative rather than restrictive.

[0116] Furthermore, for illustrative purposes, the methods are described in a specific order. It should be understood that in alternative embodiments, the methods may be performed in a different order than described. It should also be understood that the methods described above can be executed by hardware components or embodied in a sequence of machine-executable instructions that can be used to cause a machine (such as a general-purpose or special-purpose processor or logic circuit) to execute the methods using instruction programming. These machine-executable instructions may be stored on one or more machine-readable media, such as CD-ROMs or other types of optical discs, floppy disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic cards or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions. Alternatively, the methods may be executed by a combination of hardware and software.

Claims

1. A vertical cell dynamic random access memory (DRAM) array, the vertical cell dynamic random access memory (DRAM) array comprising: Multiple bit lines, the multiple bit lines being arranged in a first horizontal direction; Multiple character lines, wherein the multiple character lines are arranged in a second horizontal direction; Multiple channels extend in a direction substantially orthogonal to the vertical direction of the first horizontal direction and the second horizontal direction, such that the multiple bit lines intersect the source / drain regions of the multiple channels and the multiple word lines intersect the gate regions of the multiple channels; as well as p-doped bridge, the p-doped bridge extending between a first channel and a second channel of the plurality of channels, wherein the first channel is spaced apart from the second channel in a row extending in the second horizontal direction.

2. The vertical cell dynamic random access memory (DRAM) array of claim 1, wherein the p-doped bridge has a doping level greater than or about 1.6 times the doping level of the first channel and the second channel.

3. The vertical cell dynamic random access memory (DRAM) array of claim 1, wherein the vertical cell dynamic random access memory (DRAM) array further includes a shallow trench isolation defined between the first channel and the second channel, the shallow trench isolation having a height extending from the first end to the second end.

4. The vertical cell dynamic random access memory (DRAM) array of claim 3, wherein the p-doped bridge is disposed in the shallow trench isolation at about 20% to about 80% of the height of the shallow trench isolation.

5. The vertical cell dynamic random access memory (DRAM) array of claim 1, wherein the p-doped bridge is formed of crystalline silicon.

6. The vertical cell dynamic random access memory (DRAM) array of claim 1, wherein the vertical cell dynamic random access memory (DRAM) array further includes at least one third channel among the plurality of channels spaced apart from the second channel in the row extending in the second horizontal direction, wherein the second p-doped bridge extends between the second channel and the third channel.

7. The vertical cell dynamic random access memory (DRAM) array of claim 3, wherein the vertical cell dynamic random access memory (DRAM) array further includes body contacts electrically connected to the p-doped bridge.

8. The vertical cell dynamic random access memory (DRAM) array of claim 7, wherein the body contacts are connected to a bias voltage source and / or further include bit line contacts electrically connected to one or more of the plurality of bit lines, wherein the bit line contacts are electrically isolated from the body contacts.

9. The vertical cell dynamic random access memory (DRAM) array of claim 1, wherein the vertical cell dynamic random access memory (DRAM) array further includes a second p-doped bridge extending between the first channel of the plurality of channels and the second channel of the plurality of channels.

10. A vertical cell dynamic random access memory (DRAM) array, the vertical cell dynamic random access memory (DRAM) array comprising: Multiple bit lines, the multiple bit lines being arranged in a first horizontal direction; Multiple character lines, wherein the multiple character lines are arranged in a second horizontal direction; The first plurality of spaced-apart channels extend in a first row in the second horizontal direction; The second plurality of spaced-apart channels extend in a second row in the second horizontal direction, the second row being spaced apart from the first row; as well as Multiple p-doped bridges extend between adjacent channels in the first row and between adjacent channels in the second row; Each of the channels extends substantially orthogonally to the vertical direction of the first horizontal direction and the second horizontal direction, such that the plurality of bit lines intersect the source / drain regions of the plurality of channels and the plurality of word lines intersect the gate regions of the plurality of channels.

11. The vertical cell dynamic random access memory (DRAM) array of claim 10, wherein the vertical cell dynamic random access memory (DRAM) array further includes shallow trench isolation defined between adjacent channels in each row, the shallow trench isolation having a height extending from a first end to a second end.

12. The vertical cell dynamic random access memory (DRAM) array of claim 10, wherein the vertical cell dynamic random access memory (DRAM) array further includes a second shallow trench isolation between adjacent channels in the first row and the second row, and a gate formed along the outer surface of the second shallow trench isolation.

13. The vertical cell dynamic random access memory (DRAM) array of claim 11, wherein the vertical cell dynamic random access memory (DRAM) array further comprises conductive material covering each p-doped bridge.

14. The vertical cell dynamic random access memory (DRAM) array of claim 13, wherein the vertical cell dynamic random access memory (DRAM) array further includes at least a second plurality of p-doped bridges extending between adjacent channels in the first row and between adjacent channels in the second row.

15. A method for forming a vertical cell dynamic random access memory (DRAM) array, the method comprising: The substrate is etched to form one or more shallow trench isolations and a plurality of vertically extending channels, the channels having a first source / drain region at the second end of the vertically extending channels. Dielectric material is formed in one or more of the shallow trench isolations; The dielectric material is recessed into the first height of the one or more shallow trench isolations; Forming a protective liner in one or more shallow trench isolations; The protective liner with bottom perforation; The dielectric material is recessed into the one or more shallow trenches at a second height below the first height; p-doped bridges are formed in the one or more shallow trench isolations, wherein the p-doped bridges contact the first and second sidewalls of the one or more shallow trench isolations exposed by being recessed to the second height.

16. The method of claim 15, the method further comprising: filling the p-doped bridges in the one or more shallow trench isolations with dielectric material.

17. The method of claim 15, further comprising: forming a conductive material over the p-doped bridge.

18. The method of claim 17, the method comprising: epitaxially forming the p-doped bridge and depositing the conductive material over the p-doped bridge.

19. The method of claim 17, further comprising: etching a first hole in at least a portion of the one or more shallow trench isolations from the exposed surface of the vertical cell dynamic random access memory (DRAM) array to the conductive material in the one or more shallow trench isolations; metallizing the top surface of the conductive material; and forming a conductive metal shield in the hole and above the exposed surface of the vertical cell dynamic random access memory (DRAM) array.

20. The method of claim 19, further comprising: forming an interlayer dielectric over the conductive metal shield; etching a second via through the interlayer dielectric to a bit line formed over a second source / drain region formed at a first end of the vertically extending channel; and isolating the via from the conductive metal shield.

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