Simulation debugging system and method and computer readable storage medium

Abstract

The invention discloses a simulation debugging system and method and a computer readable storage medium, the simulation debugging system comprises a host and a hardware simulation acceleration platform, the host comprises a first high-speed serial interface subsystem, and the hardware simulation acceleration platform comprises a programmable logic device; the programmable logic device is used for receiving debugging information forwarded by a debugging and testing subsystem in the tested equipment; performing format conversion on each piece of debugging information to obtain each piece of debugging information after format conversion; coding each piece of debugging information after format conversion to obtain each piece of coded debugging information; each piece of coded debugging information is returned to the debugging and testing subsystem; the host is used for receiving each piece of coded debugging information sent by the debugging and testing subsystem through the second high-speed serial interface subsystem through the first high-speed serial interface subsystem; and decoding each piece of coded debugging information, and carrying out simulation debugging according to the obtained decoded debugging information. According to the method, the simulation debugging time is shortened, debugging information transmission of multiple devices is supported, and computing resources are saved.

Description

Technical Field

[0001] This invention relates to the field of simulation debugging technology, and in particular to a simulation debugging system, method, and computer-readable storage medium. Background Technology

[0002] During the design process, equipment requires system-level verification and simulation debugging of its functions, performance, and power consumption. The traditional simulation debugging process involves a hardware module (such as a CPU or a self-developed technology module) in the Device Under Test (DUT) generating debugging information during operation. The CPU formats this information into a string or binary data in serial communication format, encodes the formatted information, and then sends it to the host computer via serial port. The host computer receives the debugging information via serial port and displays it on a terminal or debugging tool for developers to analyze. Serial communication speeds are typically low and cannot meet the needs of large-scale simulation debugging. Serial communication requires CPU participation, consuming significant computing resources and impacting simulation performance. Furthermore, serial communication relies on CPU clock division, limiting simulation speed. The output of debugging information becomes a performance bottleneck, resulting in excessively long debugging times.

[0003] In summary, how to effectively solve the problems of failing to meet the needs of large-scale simulation debugging, consuming a large amount of computing resources, and having excessively long debugging time is an urgent problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a simulation debugging system that reduces simulation debugging time, supports debugging information transmission from multiple devices, and saves computing resources; another purpose of this invention is to provide a simulation debugging method and a computer-readable storage medium.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] A simulation debugging system includes a host and a hardware simulation acceleration platform. The host includes a first high-speed serial interface subsystem, and the hardware simulation acceleration platform includes a programmable logic device.

[0007] The programmable logic device is used to receive debugging information forwarded by the debugging subsystem in the device under test; convert the format of each debugging information to obtain the debugging information after format conversion; encode the debugging information after format conversion to obtain the debugging information after encoding; and return the debugging information after encoding to the debugging subsystem; wherein, each debugging information is the debugging information sent by each hardware module in the device under test to the debugging subsystem;

[0008] The host is configured to receive, through the first high-speed serial interface subsystem, each encoded debugging information sent by the debugging subsystem through the second high-speed serial interface subsystem; decode each encoded debugging information; and perform simulation debugging based on the obtained decoded debugging information.

[0009] In one specific embodiment of the present invention, the programmable logic device is specifically used to receive various debugging information forwarded by the debugging subsystem through a shared random access memory interface connected to the programmable logic device.

[0010] In one specific embodiment of the present invention, the programmable logic device is specifically used to receive various debugging information forwarded by the debugging subsystem through a double data rate interface connected to the programmable logic device.

[0011] In one specific embodiment of the present invention, the programmable logic device is specifically used to acquire the debugging level corresponding to each debugging information; determine the return priority corresponding to each debugging information according to the debugging level corresponding to each debugging information; and return the encoded debugging information corresponding to each debugging information to the debugging subsystem according to the return priority corresponding to each debugging information.

[0012] In one specific embodiment of the present invention, the method is specifically used to receive message packets sent by the debugging subsystem through the second high-speed serial interface subsystem via the first high-speed serial interface subsystem; and to decode the encoded debugging information in each message packet; wherein each message packet is a message packet obtained by the debugging subsystem assembling the encoded debugging information.

[0013] In one specific embodiment of the present invention, the host is specifically used to receive, through the first high-speed serial interface subsystem, message packets sent by the debugging subsystem through the second high-speed serial interface subsystem according to the packet transmission level; wherein, the packet transmission level is determined by the debugging subsystem assembling each encoded debugging information into a message packet according to the debugging level corresponding to each debugging information, and determining the packet transmission level corresponding to each message packet according to the debugging level of each debugging information contained in each message packet.

[0014] In one specific embodiment of the present invention, the host is further configured to parse the decoded debugging information and generate a debugging log based on the parsing result; wherein the parsing result includes at least the timestamp, hardware module identification information, debugging level, debugging status, and debugging content corresponding to each piece of debugging information.

[0015] A simulation debugging method, applied to programmable logic devices, includes:

[0016] Receive various debugging information sent by the debugging subsystem;

[0017] The debugging information is converted into different formats to obtain the debugging information after each format conversion.

[0018] Encode the debug information after each format conversion to obtain the encoded debug information;

[0019] The encoded debugging information is returned to the debugging subsystem, so that the debugging subsystem can send the encoded debugging information to the host for simulation debugging through the high-speed serial interface subsystem.

[0020] In one specific embodiment of the present invention, returning the encoded debugging information to the debugging subsystem includes:

[0021] Obtain the debugging level corresponding to each debugging information;

[0022] The return priority for each debugging message is determined based on its corresponding debugging level.

[0023] According to the return priority of each debugging information, the encoded debugging information corresponding to each debugging information is returned to the debugging subsystem.

[0024] A computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the simulation debugging method described above.

[0025] The simulation and debugging system provided by this invention includes a host and a hardware simulation acceleration platform. The host includes a first high-speed serial interface subsystem, and the hardware simulation acceleration platform includes a programmable logic device. The programmable logic device is used to receive debugging information forwarded by the debugging subsystem in the device under test; to convert the format of each debugging information to obtain debug information after format conversion; to encode the debug information after format conversion to obtain debug information after encoding; and to return the debug information after encoding to the debugging subsystem. Each debugging information is the debugging information sent to the device under test by each hardware module in the device under test. The host is used to receive the debug information after encoding sent by the debugging subsystem through a second high-speed serial interface subsystem via the first high-speed serial interface subsystem; to decode the debug information after encoding; and to perform simulation debugging based on the obtained decoded debug information.

[0026] The beneficial effects of this invention are as follows: by setting up high-speed serial interface subsystems in both the host and the device under test (DUT), and utilizing these subsystems for debugging information transmission, rapid data transmission of debugging information is achieved. The debugging information transmission channel between the host and DUT is separated from the main data channel, avoiding interference with normal business data transmission. By utilizing programmable logic devices (PLDs) for debugging information format conversion and encoding, no additional central processing unit (CPU) resources are required, saving computational resources. PLDs support multi-bit-width parallel data processing, efficiently completing the reading and writing of debugging information, reducing simulation debugging time. Debugging information transmission from multiple devices is supported.

[0027] Accordingly, the present invention also provides a simulation debugging method and a computer-readable storage medium corresponding to the above-mentioned simulation debugging system, which have the above-mentioned technical effects, and will not be elaborated here. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a structural block diagram of a simulation debugging system according to an embodiment of the present invention;

[0030] Figure 2 This is a flowchart illustrating another simulation debugging method in an embodiment of the present invention.

[0031] Figure 3 This is a structural block diagram of a simulation debugging device according to an embodiment of the present invention.

[0032] The attached figures are labeled as follows:

[0033] 1-Host, 11-First high-speed serial interface subsystem, 2-Hardware simulation acceleration platform, 21-Programmable logic device. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] See Figure 1 , Figure 1This is a structural block diagram of a simulation debugging system according to an embodiment of the present invention. The system may include a host 1 and a hardware simulation acceleration platform 2. The host 1 includes a first high-speed serial interface subsystem 11, and the hardware simulation acceleration platform 2 includes a programmable logic device 21.

[0036] Programmable logic device 21 is used to receive debugging information forwarded by the debugging subsystem in the device under test; convert the format of each debugging information to obtain the debugging information after format conversion; encode the debugging information after format conversion to obtain the debugging information after encoding; and return the debugging information after encoding to the debugging subsystem; wherein, each debugging information is the debugging information sent by each hardware module in the device under test to the debugging subsystem;

[0037] Host 1 is used to receive the encoded debugging information sent by the debugging subsystem through the second high-speed serial interface subsystem via the first high-speed serial interface subsystem 11; decode the encoded debugging information; and perform simulation debugging based on the decoded debugging information.

[0038] The simulation and debugging system provided in this embodiment of the invention includes a host 1 and a hardware simulation acceleration platform 2. The host 1 includes a first high-speed serial interface subsystem 11, and the hardware simulation acceleration platform 2 includes a programmable logic device 21, which can be a field-programmable gate array (FPGA). Each hardware module in the device under test (DUT) sends debugging information to the debugging subsystem, which forwards the debugging information to the programmable logic device 21. The programmable logic device 21 receives the debugging information forwarded by the debugging subsystem in the DUT, converts the format of each debugging information to obtain format-converted debugging information, encodes the format-converted debugging information to obtain encoded debugging information, and returns the encoded debugging information to the debugging subsystem.

[0039] The debugging subsystem sends each encoded debugging message to host 1 through the second high-speed serial interface subsystem. Host 1 receives each encoded debugging message through the first high-speed serial interface subsystem 11, decodes each encoded debugging message, and performs simulation debugging based on the obtained decoded debugging information. The host can pre-develop dedicated debugging tools or scripts to parse and display the debugging information in real time.

[0040] An efficient debugging information transmission channel is established between the host 1 and the device under test through the first high-speed serial interface subsystem 11 and the second high-speed serial interface subsystem, and is separated from the business data channel to avoid interference with normal business data transmission. The programmable logic device 21 realizes real-time storage and retrieval of debugging information, and performs format conversion and encoding of debugging information without occupying additional central processing unit resources, thus saving computing resources. Debugging information can quickly reach the host, facilitating real-time analysis and debugging.

[0041] It should be noted that the terms "first" and "second" in the first high-speed serial interface subsystem 11 and the second high-speed serial interface subsystem are only for distinguishing the high-speed serial interface subsystem in the host 1 from the high-speed serial interface subsystem in the device under test, and do not indicate any difference in size or order. The first high-speed serial interface subsystem 11 and the second high-speed serial interface subsystem can be configured as a high-speed peripheral component interconnect express (PMI) subsystem.

[0042] As can be seen from the above technical solution, by setting up high-speed serial interface subsystems in both the host and the device under test (DUT), and utilizing these subsystems for debugging information transmission, rapid data transmission of debugging information is achieved. The debugging information transmission channel between the host and DUT is separated from the main data channel, avoiding interference with normal business data transmission. By utilizing programmable logic devices (PLDs) for debugging information format conversion and encoding, no additional CPU resources are required, saving computational resources. PLDs support multi-bit-width parallel data processing, efficiently completing the reading and writing of debugging information, reducing simulation debugging time. Debugging information transmission from multiple devices is supported.

[0043] It should be noted that, based on the above embodiments, the present invention also provides corresponding improvements. In subsequent embodiments, steps identical or corresponding to those in the above embodiments can be referenced interchangeably, and their respective beneficial effects can also be referred to each other. These improvements will not be elaborated upon in the following improved embodiments.

[0044] In one specific embodiment of the present invention, the programmable logic device 21 is specifically used to receive various debugging information forwarded by the debugging subsystem through the shared random access memory interface connected to the programmable logic device 21.

[0045] The debugging subsystem forwards debugging information to the programmable logic device 21 via a shared random access memory interface connected to the programmable logic device 21. The programmable logic device 21 receives the debugging information. Low-latency, deterministic real-time communication is achieved through the shared random access memory interface, improving the efficiency of receiving debugging information.

[0046] In one specific embodiment of the present invention, the programmable logic device 21 is specifically used to receive various debugging information forwarded by the debugging subsystem through the double data rate interface connected to the programmable logic device 21.

[0047] The debugging subsystem forwards debugging information to the programmable logic device 21 via a double data rate interface connected to the programmable logic device 21. The programmable logic device 21 receives the debugging information. The double data rate interface enables high-capacity, high-bandwidth, and low-cost communication, thus supporting the simultaneous reception of debugging information from multiple devices.

[0048] In one specific embodiment of the present invention, the programmable logic device 21 is specifically used to obtain the debugging level corresponding to each debugging information; determine the return priority corresponding to each debugging information according to the debugging level corresponding to each debugging information; and return the encoded debugging information corresponding to each debugging information to the debugging subsystem according to the return priority corresponding to each debugging information.

[0049] After encoding the debug information, the programmable logic device 21 obtains the debug level corresponding to each debug information. Based on the debug level, it determines the return priority for each debug information; the higher the debug level, the higher the return priority. The encoded debug information corresponding to each debug information is then returned to the testing and debugging subsystem according to its respective return priority. By determining the return priority of each debug information based on its debug level and returning the encoded debug information to the testing and debugging subsystem according to its respective return priority, it ensures that debug information with higher priority is returned first, thus improving system stability.

[0050] As shown in Table 1, Table 1 is a sample table of debugging information formats.

[0051] Table 1

[0052]

[0053] In one specific embodiment of the present invention, the host 1 is specifically used to receive message packets sent by the debugging subsystem through the second high-speed serial interface subsystem via the first high-speed serial interface subsystem 11; and to decode the encoded debugging information in each message packet; wherein each message packet is a message packet obtained by the debugging subsystem assembling the encoded debugging information.

[0054] After the programmable logic device 21 returns the encoded debugging information to the debugging subsystem, the debugging subsystem assembles the encoded debugging information into message packets and sends these packets to the host 1 via the second high-speed serial interface subsystem. The host 1 receives the message packets via the first high-speed serial interface subsystem 11 and decodes the encoded debugging information within each packet. By packaging and transmitting multiple debugging messages, batch transmission mode is supported, improving transmission efficiency. Lightweight communication protocols can also be used to transmit debugging information, reducing protocol overhead.

[0055] In one specific embodiment of the present invention, the host 1 is specifically used to receive, through the first high-speed serial interface subsystem 11, message packets sent by the debugging subsystem through the second high-speed serial interface subsystem according to the information packet transmission level; wherein, the information packet transmission level is determined by the debugging subsystem assembling each encoded debugging information into each message packet according to the debugging level corresponding to each debugging information, and determining the information packet transmission level corresponding to each message packet according to the debugging level of each debugging information contained in each message packet.

[0056] The debugging subsystem assembles the encoded debugging information into message packets according to their respective debugging levels. Based on the debugging levels of the debugging information contained within each message packet, the transmission level of each message packet is determined. The debugging level of each debugging information can be used as the debugging level of its corresponding encoded debugging information. The encoded debugging information is then sorted according to its highest to lowest debugging level, resulting in a sorting result. Based on this sorting result, the encoded debugging information is assembled into message packets. Finally, the transmission level of each message packet is determined based on its position within the sorting result. By sorting the encoded debugging information according to its highest to lowest debugging level, the transmission level of each message packet can be quickly determined.

[0057] The debugging subsystem sends message packets to host 1 according to the packet transmission level through the second high-speed serial interface subsystem, and host 1 receives message packets through the first high-speed serial interface subsystem 11. By sending message packets to host 1 according to the packet transmission level, it ensures that debugging information with high priority is returned first, thus improving system stability.

[0058] In one specific embodiment of the present invention, the host 1 is further configured to parse the decoded debugging information and generate a debugging log based on the parsing result; wherein the parsing result includes at least the timestamp, hardware module identification information, debugging level, debugging status, and debugging content corresponding to each piece of debugging information.

[0059] After decoding and obtaining the decoded debugging information, host 1 parses the information to obtain the parsing results. These results include at least the timestamp, hardware module identifier, debugging level, debugging status, and debugging content for each piece of debugging information. Based on these results, a debugging log is generated for developers to analyze.

[0060] Corresponding to the system embodiments above, the present invention also provides a simulation debugging method, which can be referred to in conjunction with the simulation debugging system described above.

[0061] See Figure 2 , Figure 2 This is a flowchart illustrating another simulation and debugging method in an embodiment of the present invention, applied to a programmable logic device. The method may include the following steps.

[0062] S201: Receives various debugging information sent by the debugging subsystem.

[0063] S202: Convert the format of each debugging message to obtain the converted debugging message.

[0064] S203: Encode the debugging information after each format conversion to obtain the encoded debugging information.

[0065] S204: Return each encoded debugging information to the debugging subsystem, so that the debugging subsystem can send each encoded debugging information to the host for simulation debugging through the high-speed serial interface subsystem.

[0066] As can be seen from the above technical solution, by setting up high-speed serial interface subsystems in both the host and the device under test (DUT), and utilizing these subsystems for debugging information transmission, rapid data transmission of debugging information is achieved. The debugging information transmission channel between the host and DUT is separated from the main data channel, avoiding interference with normal business data transmission. By utilizing programmable logic devices (PLDs) for debugging information format conversion and encoding, no additional CPU resources are required, saving computational resources. PLDs support multi-bit-width parallel data processing, efficiently completing the reading and writing of debugging information, reducing simulation debugging time. Debugging information transmission from multiple devices is supported.

[0067] In one specific embodiment of the present invention, returning the encoded debugging information to the debugging subsystem may include the following steps:

[0068] Step 1: Obtain the debugging level corresponding to each debugging information;

[0069] Step 2: Determine the return priority for each debugging message based on its corresponding debugging level;

[0070] Step 3: According to the return priority of each debugging information, return the encoded debugging information corresponding to each debugging information to the debugging subsystem.

[0071] In one specific embodiment of the present invention, step S201 may include the following steps:

[0072] It receives debugging information forwarded by the debugging subsystem through the shared random access memory interface connected to the programmable logic device.

[0073] In one specific embodiment of the present invention, step S201 may include the following steps:

[0074] The system receives debugging information forwarded by the debugging subsystem through a double data rate interface connected to the programmable logic device.

[0075] In one specific embodiment of the present invention, the debugging subsystem sends the encoded debugging information to the host for simulation debugging through the high-speed serial interface subsystem, which may include the following steps:

[0076] Step 1: The debugging subsystem assembles the coded debugging information to obtain each message packet;

[0077] Step 2: The debugging subsystem sends each message packet to the host for simulation debugging through the second high-speed serial interface subsystem.

[0078] In one specific embodiment of the present invention, the debugging subsystem assembles the coded debugging information, which may include the following steps:

[0079] The debugging subsystem assembles each encoded debugging information into a message packet according to the debugging level corresponding to each debugging information, and determines the information packet transmission level corresponding to each message packet according to the debugging level of each debugging information contained in each message packet.

[0080] Correspondingly, the debugging subsystem sends each message packet to the host for simulation debugging through the second high-speed serial interface subsystem, which may include the following steps:

[0081] The debugging subsystem sends each message packet to the host for simulation debugging through the second high-speed serial interface subsystem according to the information packet transmission level.

[0082] Corresponding to the above system embodiments, the present invention also provides a simulation debugging device, which can be referred to in correspondence with the simulation debugging system described above.

[0083] See Figure 3 , Figure 3 This is a structural block diagram of a simulation debugging device according to an embodiment of the present invention, applied to a programmable logic device. The device may include:

[0084] The debugging information receiving unit 31 is used to receive various debugging information sent by the debugging subsystem;

[0085] The format conversion debugging information acquisition unit 32 is used to convert the format of each debugging information to obtain the format conversion debugging information;

[0086] The unit 33 for obtaining post-encoded debugging information is used to encode the post-encoded debugging information of each format conversion to obtain the post-encoded debugging information.

[0087] The simulation debugging unit 34 is used to return the encoded debugging information to the debugging subsystem, so that the debugging subsystem can send the encoded debugging information to the host for simulation debugging through the high-speed serial interface subsystem.

[0088] As can be seen from the above technical solution, by setting up high-speed serial interface subsystems in both the host and the device under test (DUT), and utilizing these subsystems for debugging information transmission, rapid data transmission of debugging information is achieved. The debugging information transmission channel between the host and DUT is separated from the main data channel, avoiding interference with normal business data transmission. By utilizing programmable logic devices (PLDs) for debugging information format conversion and encoding, no additional CPU resources are required, saving computational resources. PLDs support multi-bit-width parallel data processing, efficiently completing the reading and writing of debugging information, reducing simulation debugging time. Debugging information transmission from multiple devices is supported.

[0089] In one specific embodiment of the present invention, the simulation debugging unit 34 may include:

[0090] The debugging level acquisition subunit is used to obtain the debugging level corresponding to each debugging information.

[0091] The priority determination subunit is used to determine the return priority of each debugging information based on the debugging level corresponding to each debugging information.

[0092] The encoded debugging information return subunit is used to return the encoded debugging information corresponding to each debugging information to the debugging subsystem according to the return priority of each debugging information.

[0093] In one specific embodiment of the present invention, the debugging information receiving unit 31 is specifically a unit that receives various debugging information forwarded by the debugging subsystem through the shared random access memory interface connected to the programmable logic device.

[0094] In one specific embodiment of the present invention, the debugging information receiving unit 31 is specifically a unit that receives various debugging information forwarded by the debugging subsystem through a double data rate interface connected to the programmable logic device.

[0095] In one specific embodiment of the present invention, the simulation debugging unit 34 may include:

[0096] The message packet acquisition subunit is used by the debugging subsystem to assemble the encoded debugging information to obtain each message packet.

[0097] The first simulation debugging subunit is used by the debugging subsystem to send each message packet to the host for simulation debugging through the second high-speed serial interface subsystem.

[0098] In one specific embodiment of the present invention, the message packet acquisition subunit is specifically a unit in which the debugging subsystem assembles each encoded debugging information into a message packet according to the debugging level corresponding to each debugging information, and determines the packet transmission level corresponding to each message packet according to the debugging level of each debugging information contained in each message packet.

[0099] The second simulation and debugging subunit is used by the debugging subsystem to send each message packet to the host for simulation and debugging according to the information packet transmission level through the second high-speed serial interface subsystem.

[0100] Corresponding to the above method embodiments, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the following steps:

[0101] The system receives debugging information sent by the debugging subsystem; converts the format of each debugging information to obtain the converted debugging information; encodes the converted debugging information to obtain the encoded debugging information; and returns the encoded debugging information to the debugging subsystem so that the debugging subsystem can send the encoded debugging information to the host for simulation debugging through the high-speed serial interface subsystem.

[0102] The computer-readable storage medium may include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0103] For a description of the computer-readable storage medium provided by the present invention, please refer to the above method embodiments; the present invention will not be described in detail here.

[0104] Corresponding to the above method embodiments, the present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the aforementioned simulation debugging method.

[0105] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods and computer-readable storage media disclosed in the embodiments are described simply because they correspond to the systems disclosed in the embodiments; relevant details can be found in the method section.

[0106] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A simulation debugging system, comprising a host computer and a hardware simulation acceleration platform, characterized in that, The host includes a first high-speed serial interface subsystem, and the hardware simulation acceleration platform includes a programmable logic device. The programmable logic device is used to receive debugging information forwarded by the debugging subsystem in the device under test; and to convert the format of each debugging information to obtain the debugging information after format conversion. The debugging information after each format conversion is encoded to obtain each encoded debugging information; the encoded debugging information is returned to the debugging subsystem; wherein, each debugging information is the debugging information sent to the debugging subsystem by each hardware module in the device under test; The host is configured to receive, through the first high-speed serial interface subsystem, each encoded debugging information sent by the debugging subsystem through the second high-speed serial interface subsystem; decode each encoded debugging information; and perform simulation debugging based on the obtained decoded debugging information.

2. The simulation debugging system according to claim 1, characterized in that, The programmable logic device is specifically used to receive various debugging information forwarded by the debugging subsystem through a shared random access memory interface connected to the programmable logic device.

3. The simulation debugging system according to claim 1, characterized in that, The programmable logic device is specifically used to receive various debugging information forwarded by the debugging subsystem through a double data rate interface connected to the programmable logic device.

4. The simulation debugging system according to any one of claims 1 to 3, characterized in that, The programmable logic device is specifically used to acquire the debugging level corresponding to each debugging information; determine the return priority corresponding to each debugging information according to the debugging level corresponding to each debugging information; and return the encoded debugging information corresponding to each debugging information to the debugging subsystem according to the return priority corresponding to each debugging information.

5. The simulation debugging system according to claim 4, characterized in that, The host is specifically configured to receive message packets sent by the debugging subsystem through the second high-speed serial interface subsystem via the first high-speed serial interface subsystem; and to decode the encoded debugging information in each message packet; wherein each message packet is a message packet obtained by the debugging subsystem assembling the encoded debugging information.

6. The simulation debugging system according to claim 5, characterized in that, The host is specifically configured to receive, through the first high-speed serial interface subsystem, message packets sent by the debugging subsystem through the second high-speed serial interface subsystem according to the packet transmission level; wherein, the packet transmission level is determined by the debugging subsystem assembling each encoded debugging information into a message packet according to the debugging level corresponding to each debugging information, and determining the packet transmission level corresponding to each message packet based on the debugging level of each debugging information contained in each message packet.

7. The simulation debugging system according to claim 1, characterized in that, The host is also used to parse the decoded debugging information and generate a debugging log based on the parsing result; wherein the parsing result includes at least the timestamp, hardware module identification information, debugging level, debugging status, and debugging content corresponding to each piece of debugging information.

8. A simulation debugging method, characterized in that, Applied to programmable logic devices, including: Receive various debugging information sent by the debugging subsystem; The debugging information is converted into different formats to obtain the debugging information after each format conversion. Encode the debug information after each format conversion to obtain the encoded debug information; The encoded debugging information is returned to the debugging subsystem, so that the debugging subsystem can send the encoded debugging information to the host for simulation debugging through the high-speed serial interface subsystem.

9. The simulation debugging method according to claim 8, characterized in that, The encoded debugging information is returned to the debugging subsystem, including: Obtain the debugging level corresponding to each debugging information; The return priority for each debugging message is determined based on its corresponding debugging level. According to the return priority of each debugging information, the encoded debugging information corresponding to each debugging information is returned to the debugging subsystem.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the simulation debugging method as described in claim 8 or 9.

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